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Verification:
1) A.B = A + B
7404
7404
7404
A B A.B A.B A+
A B A B
B
0 0 0 1
0 0 1 1 1
0 1 0 1
0 1 1 0 1
1 0 0 1
1 0 0 1 1
1 1 1 0
1 1 0 0 0
2) A+B = A . B
7404
7404
7404
0 0 0 1 0 0 1 1 1
0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0
1 1 1 0 1 1 0 0 0
Theory:-
Theorem 1: The compliment of the product of two variables is equal to the
sum of the compliment of each variable. Thus according to De-Morgan’s
laws or De-Morgan's theorem if A and B are the two variables or Boolean
numbers. Then accordingly,
A.B = A + B
Theorem 2:-
The compliment of the sum of two variables is equal to the product of the
compliment of each variable. Thus according to De Morgan’s theorem if A
and B are the two variables then,
A+B = A . B
Given problem:
A B C D Y Y= f(A,B,C,D)=Σm(5,6,7,13,14,15)
0 0 0 0 0 Y= f(A,B,C,D)=ΠM(0,1,2,3,4,8,9,10,11,12)
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
K-map Simplification:
Procedure:
1. Verify that the gates are working.
2. Construct a truth table for the given problem.
3. Draw a Karnaugh Map corresponding to the given truth table.
4. Simplify the given Boolean expression manually using the Karnaugh Map.
A. Implementation Using Logic Gates:
5. Realize the simplified expression using logic gates.
6. Connect VCC and ground as shown in the pin diagram.
7. Make connections as per the logic gate diagram.
8. Apply the different combinations of input according to the truth tables.
Verify that the results are correct.
B. Implementation Using Universal Gates:
1. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic.
2. Realize the simplified Boolean expressions using only NAND gates, and
then using only NOR gates.
3. Connect the circuits according to the circuit diagrams, apply inputs
according to the truth table and verify the results.
Result:
Exercise:
1. Half Adder
Truth Table:
A B S C
0 0 0 0
0 1 1 0 S =A ⊕ B
C = A.B
1 0 1 0
1 1 0 1
Theory:
Half-Adder: A combinational logic circuit that performs the addition of two
data bits, A and B, is called a half-adder. Addition will result in two output
bits; one of which is the sum bit S, and the other is the carry bit, C. The
Boolean functions describing the half-adder are: S =A ⊕ B
C = A.B
Full-Adder: The half-adder does not take the carry bit from its previous
stage into account. This carry bit from its previous stage is called carry-in
bit. A combinational logic circuit that adds two data bits, A and B, and a
carry-in bit, Cin , is called a full-adder. The Boolean functions describing
the full-adder are:
S = A ⊕ B ⊕ Cin
C = A.B+ Cin (A ⊕ B)
2. Full Adder
Truth Table:
A B Cin S C
0 0 0 0 0
0 0 1 1 0 S = A ⊕ B ⊕ Cin
0 1 0 1 0
C = A.B + Cin (A ⊕ B)
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Procedure:
3. Half Subtractor
Truth Table:
A B D Br
0 0 0 0 D =A ⊕ B
0 1 1 1
Br = A.B
1 0 1 0
1 1 0 0
(i)
(ii) using logic gates
4. Full Subtractor
Truth Table:
A B Cin D Br
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1 D = A ⊕ B ⊕ Cin
1 0 0 1 0 Br= A’.B + A’.Cin + B.Cin
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Result:
Dept. of ECE, CIT, Gubbi Page 12
Digital Electronics Lab (15ECL38) 2017-18
1. 4-BIT
BIT BINARY ADDER
Circuit:
MSB LSB
INPUTS Cin
A3 A2 A1 A0
B3 B2 B1 B0
OUTPUT Cout S3 S2 S1 S0
Theory:
The Full adder can add single-digit
single digit binary numbers and carries. The
largest sum that can be obtained using a full adder is (11)2. Parallel adders
can add multiple-digit
digit numbers. If full adders are placed in parallel, we can
add two- or four-digit
digit numbers or any other size desired. Figure below uses
STANDARD SYMBOLS to show a parallel adder capable of adding
addi two digit
binary numbers. The addend would be input on the A inputs (A2 = MSD,
A1 = LSD), and the augend input on the B inputs (B2 = MSD, B1 = LSD).
To add four bits need four full adders arranged in parallel. IC 7483 is a 4-
4
bit parallel adder is used.
(i) 4 bit subtraction operation using 7483 for A>B and Cin=1
• 8 is realized at A3 A2 A1 A0 = 1000
• Output of X-OR
OR gate is 1’s complement = 1100
Therefore Cin = 1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1 Cout = 1 (Ignored)
(ii) 4 bit subtraction operation using 7483 for A<B and Cin=1
Example: 14 – 15 = -1 1 (1111)2
• 14 is realized at A3 A2 A1 A0 = 1110
Therefore Cin = 1
A3 A2 A1 A0 = 1 1 1 0
B3 B2 B1 B0 = 0 0 0 0
S3 S2 S1 S0 = 1 1 1 1
since the most significant bit of the result is 1, this is a negative number, so form the two's
complement of (1111)=-(0001)
(0001)2
Circuit:
Result:
4-BIT COMPARATOR:
Truth Table:
IC 7485
COMPARATORS
Aim: To realize One & Two Bit Comparator and study of 7485 magnitude
comparator.
Theory:
Result:
Exercise
A simple security system for two doors consists of a card reader and a
keypad. A person may open a particular door if he or she has a card
containing the corresponding code and enters an authorized code for that
card. The output from the card reader are as follows.
Action A B
No card inserted 0 0
Valid Code for Door 1 0 1
Valid Code for Door2 1 1
Invalid card code 1 0
To unlock a door, a person must hold down the proper keys on the keypad
and then insert the card in the reader. The authorized keypad codes for door
1 are 101 and 110, and the authorized keypad codes for door 2 are 101 and
011. If the card has an invalid code or if the wrong keypad code is entered,
the alarm will ring when card is inserted. If the correct keypad code is
entered, the corresponding door will be unlocked when the card is inserted.
A. 4:1 MULTIPLEXER
Truth Table:
Select Lines Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Components Required: IC 74153, IC 7404, 7432, 7411 and Patch Cords &
IC Trainer Kit.
Theory:
Multiplexers are very useful components in digital systems. They
transfer a large number of information units over a smaller number of
channels, (usually one channel) under the control of selection signals.
Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any
input to the output. Multiplexer is also called as data selector because the
output bit depends on the input data bit that is selected. The general
multiplexer circuit has 2n input signals, n control/select signals and 1
output signal.
Procedure:
1. The connection is made as shown in the diagram.
2. Here, S1 and S0 are the channel selection lines, I0, I1, I2, I3 are the
respective data lines of the channels and Y is the output.
3. Based on the selection lines one of the inputs will be selected at the output,
and thus the truth table is verified.
Truth table:
C B A Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Procedure:
1. For the given expression, a truth table is to be written.
2. An expression in SOP format is to be written.
3. The connection is made according to the obtained expression.
4. The truth table is verified for that particular expression.
Result:
Truth table:
C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 G1 1 1 1 1 1 1 1
0 0 1 1 G1 1 1 1 1 1 1
0 1 0 1 1 G1 1 1 1 1 1
0 1 1 1 1 1 G1 1 1 1 1
1 0 0 1 1 1 1 G1 1 1 1
1 0 1 1 1 1 1 1 G1 1 1
1 1 0 1 1 1 1 1 1 G1 1
1 1 1 1 1 1 1 1 1 1 G1
Theory:
A demultiplexer (or demux) is a device that takes a single input line and
routes it to one of several digital output lines. A demultiplexer of 2n outputs
has n select lines, which are used to select which output line to send the
input. A demultiplexer is also called a data distributor.
E1
E3
Truth table:
Select
Enable Output
Lines
E3 E2 E1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
1 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 0 X X X 1 1 1 1 1 1 1 1
0 0 1 0 0 0 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 0
Result:
1. SR FLIPFLOP:
Truth table:
Clk S R Q Q’ States
X 0 0 Q Q’ No Change
0 0 Q Q’ No Change
0 1 0 1 Reset
1 0 1 0 Set
1 1 - - Invalid
FLIP FLOPS
Aim: To realize the following Flip-flops using NAND gates:
A. Clocked SR Flip-flop
B. JK Flip-flop
Components required: IC 7410, IC7400
Theory:
A flip-flop is a circuit that has two stable states and can be used to
store state information. A flip-flop is a bistable multivibrator. The circuit
can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. It is the basic storage element in
sequential logic. Flip-flops and latches are a fundamental building block of
digital electronics systems used in computers, communications, and many
other types of systems.
A flip–flop is a “bit bucket”; it holds a single binary bit .Flip flops are
actually an application of logic gates. With the help of Boolean logic we can
create memory with them. Flip flops can also be considered as the most
basic idea of a Random Access Memory [RAM].
Procedure:
2. JK FLIPFLOP:
Clk J K Q Q’ States
X 0 0 Q Q’ No Change
0 0 Q Q’ No Change
0 1 0 1 Reset
1 0 1 0 Set
1 1 Q’ Q Toggle
Result:
Truth Table:
Serial
CLK Q3 Q2 Q1 Q0
I/P
1 D0=0 0 X X X
2 D1=1 1 0 X X
3 D2=1 1 1 0 X
4 D3=1 1 1 1 0=D0
5 X X 1 1 1=D1
6 X X X 1 1=D2
7 X X X X 1=D3
SHIFT REGISTERS
Aim: To study IC 7474, and the realization of SIPO, SISO, PISO, PIPO
operations using the same.
Theory:
Truth Table:
Serial
CLK Q3 Q2 Q1 Q0
I/P
1 1 1 X X X
2 0 0 1 X X
3 1 1 0 1 X
4 1 1 1 0 1
Truth Table:
Procedure:
Procedure:
D3 D2 D1 D0
Q0
Truth Table:
Procedure:
1. Connections are made as shown in the PISO circuit diagram.
2. Apply the 4-bit data at the parallel I/P pins D3, D2, D1, D0 and apply
single clock pulse to load the data to all 4 registers.
3. Now make all data bits as 0 and apply clock pulse one by one to get the
data bit by bit at the output line.
4. The data applied at the parallel input pins will shift and comes out
serially at the output line Q0.
NOTE: Here there is no Mode ‘M’ pin. It just indicates the status of loading
the data and shifting the data.
M – 1 indicates data loading operation.
M -- 0 indicates shifting operation.
Result:
Exercise:
S1 S0 Action
0 0 No change
0 1 Shift right 1 bit position
1 0 Shift left 1 bit position
1 1 Clear data
1. RING Counter:
Truth table
CLK QA QB QC QD
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0
6 0 1 0 0
2. JHONSON Counter:
Truth table
CLK QA QB QC QD
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0
9 1 0 0 0
10 1 1 0 0
Result:
1. MOD 10 Counter:
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Waveforms:
2. MOD 8 Counter:
Truth Table: Circuit diagram:
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
DECADE COUNTERS
Aim: To rig up Mod N counter using IC 7490.
Components required: IC7490,Patch cards, trainer kit ,etc.
Procedure:
1. Check all the components for their working.
2. Make connections as shown in the circuit diagram.
3. Clock pulses are applied one by one at the clock input and output is
observed at QA,QB ,QC and QD
4. Verify the Truth Table and observe the outputs.
Result:
Truth Table:
A B Cin S C
0 0 0 0 0
0 0 1 1 0 S = A ⊕ B ⊕ Cin
0 1 0 1 0
C = A.B + Cin (A ⊕ B)
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Result:
Circuit Diagram:
Truth Table:
Result:
IC PIN DETAILS
VIVA QUESTIONS
8. Define Literal.
Question Bank
3. Realize and verify the truth table of full adder basic gates only.
4. Realize and verify the truth table of a full Subtractor using basic gates
only.
9. Realize and verify 1:8 DEMUX and 3:8 decoder using IC 74138
10. Realize and verify the truth Table of JK Flip Flop using NAND gates
11. Realize and verify the truth Table of Clocked SR Flip Flop using
NAND gates
14. Realize a Modulo N counter using 7490, Write down the expected
functional table and verify its truth table and also display the
waveform.
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