Pre-Lab Tasks: (To be done before coming to the lab)

1. Write the Boolean expression of the following two functions. Simplify the
expression using algebraic manipulation and draw the logic diagram.
F (A, B, C) = ∑ (2, 3, 7)
G (A, B, C) = ∑ (4, 5, 7)
Solution:
F (x, y, z) = A’BC’+ A’BC +ABC
= Y(X’+AC)
G (x, y, z) = AB’C’+AB’C+ABC
= A (B’+ BC)
F = B(A’+C) G = A(B’+C)

2. Mention the number of literals and gates needed for implementing the above
function in hardware. (1 Mark)
Answer:
F function needs 3 gates :
1 AND gate, 1 OR gate, 1 NOT gate.

G function needs 3 gates:

1 AND gate, 1 OR gate, 1 NOT gate.

Lab Task 1:
Implement the Boolean functions in hardware you simplified in your Pre-Lab
Task. Make truth table and Schematic. Mention what and how many gates you
would be using? The following gates are available to you.
TRUTH TABLE:
F = B(A’+C):
A B C ~A ~A | C ~A|C &B
0 0 0 1 1 0
0 0 1 1 1 0
0 1 0 1 1 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1

SCHEMATIC:
TRUTH TABLE:
G = A(B’+C):
A B C ~B ~B | C ~B|C &A
0 0 0 1 1 0
0 0 1 1 1 0
0 1 0 0 0 0
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 1
1 1 0 0 0 0
1 1 1 0 1 1

SCHEMATIC:
Lab Task 2:
Write Verilog code for the minimized functions at gate-level and perform
simulation. Attach the relevant snapshots below.

VERILOG OF F- FUNCTION:
VERILOG OF G- FUNCTION: