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L1: 6.111 Course Overview
L1: 6.111 Course Overview
Acknowledgements:
Materials in this lecture are courtesy of the following sources and are used with
permission.
Rex Min
J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective.
Prentice Hall/Pearson, 2003.
Recommended Books
Logic Design:
Randy
Prerequisite
Prior digital design experience is NOT Required
6.004 is not a prerequisite!
Overview of Labs
Final Project
Open ended
Design presentation in class (% of the final grade for the inclass presentation)
Grading Policy
Approximate breakdown:
z
z
z
z
z
z
Quiz
3 Problem Sets
4 Lab exercises
Lab 1
Lab 2
Lab 3
Lab 4
Writing (Lab 2 revision- part of CIM requirement)
Participation (lecture, recitation, project presentations)
Final Project
10%
3%
9%
10%
7%
11%
10%
3%
37%
Collaboration
Discuss labs with anyone (staff, former students, other students, etc.)
Photograph of the
Babbage Difference Engine.
Image removed due to
copyright restrictions.
The Babbage
Difference Engine
(1834)
25,000 parts
cost: 17,470
The first digital systems were mechanical and used base10 representation.
OR
NOT
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
1
0
The
Vacuum
Tube
Lee de Forest, 1906
Claude Shannon
Digital
Electronics
Vacuum Tubes
Transistors
VLSI Circuits
ENIAC, 1946
First Transistor
Bell Labs, 1948
4004, 1971
UNIVAC, 1951
1900 adds/sec
500,000 adds/sec
2,000,000,000
adds/sec
10
Problem Statement
algorithm selection,
flowcharts, etc.
Behavioral Description
conversion to binary,
Booelan algebra
Hardware Implementation
Logic equations
Circuit schematics
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Problem Statement
algorithm selection,
flowcharts, etc.
Behavioral Description
software-like
programming
HDL Description
Verilog code
VHDL code
automated synthesis
Hardware Implementation
Programmable Logic
Custom ASICs
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Verilog
Commissioned in 1981 by
Department of Defense;
now an IEEE standard
Initially an interpreted
language for gate-level
simulation
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Dataflow Level
The flow of data through components is specified based on the idea of how
data is processed
Gate Level
Specified as wiring between logic gates
Not practical for large examples
Switch Level
Description in terms of switching (modeling a transistor)
No useful in general logic design we wont use it
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Verilog HDL
Misconceptions
The
Control
z
Functions
Logic
FSMs
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A/D
Memory
digitize
D/A
Analog
Outputs
(actuators, motors,
multimedia)
Control
synchronize
Digital Inputs
(peripherals,
buses, switches)
Sync.
Data
Processing
Digital
Outputs
(peripherals,
buses, lights)
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Peripheral
Interfaces
Audio/Video In
Memory Subsystem
Courtesy of Texas Instruments. Used with permission.
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Speed
Energy
commodity products
scientific computing,
simulation
portable applications
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OUT
IN
OUT
V(y)
V
OH
V(y)=V(x)
VM (Switching Threshold)
V OL
V OL
OH
VOH = f (VOL)
VOL = f (VOH)
VM = f (VM)
V(x)
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Capacitive coupling
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"1"
V
OH
V
IH
OUT
"0"
V
OL
OUT
V(y)
V
Slope = -1
OH
Undefined
Region
V
IL
IN
Slope = -1
VOL
V
VOH
V
OL IL VIH
V(x)
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Regenerative Property
A chain of inverters
v0
v1
v2
v3
v4
v5
out
v6
Simulated response
v3
f (v)
5
V (Volt)
v1
fin v(v)
v0
v1
21
v2
v0
in
v2
6
10
t (nsec)
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ModelSim (powerful front-end simulator for Verilog), Xilinx ISE (software for
Xilinx FPGAs), Office (Microsoft word, power point, etc.)
You can use WinSCP to transfer files between the lab PCs and the MIT server.
Use a USB flash drive (provided with your kit) to save your work
periodically
On MIT server use setup 6.111- setup 6.111 sources /mit/6.111/.attachrc
which attaches 6.111-nfs and sources /mit/6.111-nfs/.attachrc which
sets up your path and environment variables, etc.
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