IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO.

2, FEBRUARY 2010

463

An All-Digital Self-Calibration Method for a

Vernier-Based Time-to-Digital Converter
Rashid Rashidzadeh, Member, IEEE, Majid Ahmadi, Fellow, IEEE, and William C. Miller, Life Member, IEEE

AbstractThis paper presents a new calibration method for a

Vernier-based time-to-digital converter (TDC). In the proposed
method, delay lines in the TDC are configured as on-chip ring
oscillators for generating a sequence of time events. These time
events are applied to the TDC in the calibration mode, and then,
the probability distribution of output codes is determined. The
variations of the quantization step and the actual transfer characteristic representing the TDC are estimated through statistical
analysis of the output codes. The proposed method eliminates
the need for accurate external sources typically used for TDC
calibration. Simulation and experimental results using a fieldprogrammable gate array platform indicate that the method can
successfully be employed to calibrate high-resolution TDCs with
reasonable accuracy.
Index TermsCalibration, delay lines, phase-locked loop
(PLL), time-to-digital converter (TDC), Vernier delay line (VDL).

I. I NTRODUCTION
IME-TO-DIGITAL converters (TDCs) have been used
for a wide range of applications, such as laser distance
measurement, frequency synthesis, jitter measurement, and
evaluation of the timing performance of integrated circuits [1],
[2]. The performance and reliability of the results in these
applications strongly depends on the accuracy and resolution
of the TDC. With a proper TDC architecture [3][6] such as a
Vernier-based TDC, measurement resolution in the range of a
few tens of picoseconds can be achieved. To calibrate a TDC,
the performance parameters and the nonlinearity differences
between its building blocks are determined in the calibration
mode and then in the operation mode, correction techniques
are employed to reduce the measurement error. The mismatch
and nonidealities between the delay cells and interpolators
(flip-flops) in a TDC are the main sources of measurement
uncertainty. TDC calibration is generally performed by exciting the converter with a series of known time intervals and
correlating the outputs with the applied inputs. Statistical code
density test [7] is commonly used to calibrate a TDC. In this
method, an external reference clock is employed, and a large
number of time events are applied to the TDC to evaluate its
measurement uncertainty. On-chip timing oscillators are also

Manuscript received November 23, 2008; revised April 28, 2009. First
published September 22, 2009; current version published January 7, 2010.
The Associate Editor coordinating the review process for this paper was
Dr. Juha Kostamovaara.
The authors are with the Department of Electrical and Computer
Engineering, University of Windsor, Windsor, ON N9B 3P4, Canada
(e-mail: rashidza@uwindsor.ca).
Digital Object Identifier 10.1109/TIM.2009.2024699

used to generate time events for TDC calibration. However,

when the desired resolution falls below 10 ps, on-chip event
generators become less reliable. The accuracy of on-chip timing
generators, which are implemented using the same technology
process, is also limited by mismatch and process nonidealities.
Off-chip pulse generators can be employed for TDC calibration; however, the cost and complexity of the measurement
setup in this method limit its application. In this paper, a new
self-calibration method for Vernier-based TDCs is presented, in
which the need for precise external reference sources has been
eliminated. In the proposed scheme, the TDC delay lines are
configured as ring oscillators to provide timing events for calibration. The uncertainties of the time events generated by onchip oscillators are compensated through statistical methods.
The reuse of TDC circuitry in the proposed method reduces the
overall area overhead and power consumption of the calibration
scheme.
The rest of this paper is organized as follows. Section II
introduces TDC architectures and their measurement precision.
Section III introduces the dominant methods of TDC calibration
and their advantages and disadvantages. Section IV presents the
proposed method of calibration. Simulation and measurement
results are presented in Section V, and finally, conclusions are
summarized in Section VI.

II. TDC A RCHITECTURE

TDCs in integrated circuits are mainly implemented using
delay cells and flip-flops [8][12]. Delay cells are configured
as delay lines to produce a delayed version of the input signals,
and flip-flops are arranged as an arbitrator to compare signal
phases to quantize the input time interval. A conventional
TDC employs a single delay line containing several delay
cells to measure an input time interval. The resolution of the
measurement in this method is limited by one cell delay. To
overcome this limitation, two delay lines, as shown in Fig. 1,
can be employed to build a VDL-based TDC [13][15]. In
this architecture, the resolution is determined by the difference
between two propagation delay values, which can be much
shorter than the propagation delay of one delay element. In an
ideal case, a TDC is represented by a characteristic curve in
which the quantization step is constant over the entire range of
measurement, as shown in Fig. 2(a). Variation of quantization
step over the input dynamic range is the main source of measurement error in TDCs. Mismatch, noise, and random variations create delay differences between the delay cells. These
variations produce a nonlinearity error, which affect the size of

0018-9456/$26.00 2009 IEEE

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

464

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 2, FEBRUARY 2010

Fig. 1. Vernier delay line (VDL)-based TDC.

Fig. 2. TDC transfer characteristic. (a) Ideal with a quantization step of .

(b) Nonideal experiencing DNL.

the quantization step in different quantization levels. As a result,

the characteristic curve representing an actual TDC suffers from
a nonuniform quantization interval and takes different values
for each quantization level, as shown in Fig. 2(b). The deviation
of quantization steps in a TDC characteristic curve contributes
to both differential nonlinearity (DNL) and integral nonlinearity
(INL) errors [16].

III. TDC C ALIBRATION M ETHODS

To calibrate a TDC, first, the duration of each quantization level is determined. Then, the actual characteristic curve
representing the TDC is constructed based on the estimated
size of each quantization level. The measurement error of the
TDC is determined from its characteristic curve and compensated accordingly. Various TDC calibration methods have
been proposed in the literature; the dominant methods are
given here.
Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

Fig. 3. (a) Typical setup for direct calibration of an arbitrator. (b) Calibration
result for an arbitrator with a quantization step of = 4.

A. Direct Calibration
The concept of direct calibration is shown in Fig. 3, in which
two signals with a precise delay difference of Tin are externally
generated and applied to one stage of a Vernier-based TDC
containing two buffers with delays of 1 and 2 and a D flipflop. If the input time interval Tin is increased in small steps
over a sufficiently long interval of (T1 , +T1 ), the output of the
flip-flop generates a stream of 0s and 1s. Assuming an ideal
D flip-flop, the difference between the total number of 0s and
1s divided by two determines the size of the quantization step,
which is equal to = 2 1 , where 2 > 1 . The accuracy
of this calibration method is highly dependent on the size and
precision of .
B. Improved Direct Calibration Based on Added Noise
To ensure proper calibration of modern TDCs using the direct
calibration method, T has to be in the range of femtoseconds.

RASHIDZADEH et al.: ALL-DIGITAL SELF-CALIBRATION METHOD FOR VERNIER-BASED TDC

465

If a sequence of equally likely time events is applied to the

circuit shown in Fig. 4(b), the outputs of the flip-flops can be
represented by
Q1 = 1 and Q2 = 1

for Tin < 1

Q1 = 0 and Q2 = 1

for 1 < Tin < 1 + 2

Q1 = 0 and Q2 = 0

for Tin > 1 + 2 .

(1)

The output of the AND gate in Fig. 4(b) remains high for
all events falling in the range of 1 < Tin < 1 + 2 and
becomes zero for the rest of the events. The fraction of time
for which the output of the AND gate becomes high is equal to
2 /T1 , which repeats in each cycle of T2 . Therefore, the frequency of the AND gate output in Fig. 4(b) can be expressed by
fp =

2
f2 = 2 f1 f2 .
T1

(2)

From (2), the quantization step of 2 is determined through

the measurement of fp . To accurately calibrate a TDC with this
method, the reference signals of S1 and S2 have to be very low
jitter signals that are precisely aligned to generate accurate time
events. These requirements are difficult to achieve in practice.
Fig. 4. (a) Portion of a conventional VDL-based TDC. (b) Equivalent circuit
containing a single delay line with an added AND gate for calibration.

This requirement can be alleviated to some extend by adding

noise with a standard deviation of noise to T . Assuming that
the standard deviation of the TDC delay elements are much
lower than noise , the sum of T and the noise creates a set
of time events that follow Gaussian distribution with a mean
value of T and a standard deviation of noise . The addition
of noise in this method increases the standard deviation of
the quantization step and facilitates its measurement. Using
additive temporal noise, Levine and Roberts [17] reported TDC
calibration down to 5 ps. This method requires an on-chip noise
source with a relatively large standard deviation, which may not
be easy to implement.

D. Statistical Linearity Calibration

In [19], a statistical method of calibration is proposed, in
which an independent ring oscillator is used to generate a
sequence of equally likely time events within one period of a
reference clock. If this sequence of events is applied to a TDC,
it can be shown that the probability of hitting a specific code in
the TDC is proportional to the duration of the time that leads
to that particular code. Assuming the duration of Dc for code
c, the probability of hitting this code is equal to Pc = Dc /TR ,
where TR represents the period of the reference clock. For N
cycles of the event sequence applied to the TDC, code c is

expected n
c times, where nc is given by
n
c = N Pc =

C. Indirect Calibration
The differences between the quantization steps of a VDLbased TDC can be determined through an indirect calibration
method [18]. To illustrate this method, assume two periodic
signals of S1 and S2 with periods of T1 and T2 , where T2 is
slightly larger than T1 . The time difference between the rising
edges of S1 and S2 is incremented by = T2 T1 in every
cycle. If one cycle of S1 is observed over time, it can be seen
that the rising edges of S2 are uniformly distributed over that
particular cycle of S1 . It can be shown that it takes a total
number of N = T1 / cycles for a rising edge of S2 to sweep
one full cycle of S1 . The difference between the rising edges
of S1 and S2 can be considered as an input time interval that
extends by = T2 T1 in every cycle. Such a sequence of
time events includes a total number of N = T1 / distinct input
intervals. Fig. 4 shows a two-stage Vernier-based TDC and its
equivalent circuit in which two delay lines are replaced with a
single delay line where 1 = 12 11 and 2 = 22 21 .
Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

N Dc
.
TR

(3)

If the actual number of hits for code c is counted in a

calibration phase, the estimated duration of the code Dc can
be calculated from
Dc =

nc TR
N

(4)

where nc represents the actual number of hits. The estimated durations of the codes can be used to construct a
TDC characterization curve and calibrate the TDC accordingly. The simulation results reported in [19] indicate significant error reduction of more than five folds from 8 ps
RMS to 1.3 ps RMS for a VDL-based TDC in complementary
metaloxidesemiconductor 90-nm process. To implement this
calibration method, the frequencies of the on-chip oscillator and
the reference clock have to be adjusted to prevent coherency
between them. Coherency between these signals limits the number of time events and can adversely affect the uniformity of
the time events leading to inaccurate calibration. Even without

466

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 2, FEBRUARY 2010

events in (7) is given by

t = t(m + 1) t(m) = T1 mod T2 .

(8)

It can be shown that appropriate time events are not generated

for all periods of T1 and T2 . For instance, when T1 = N T2 for
all integer values of N , the time difference between the events
becomes zero.
An easy solution to this problem is to add extra delay cells
to the feedback path of the faster delay line to minimize the
delay difference between the two delay lines. As a result, when
the feedback paths are activated, the oscillators start running at
close frequencies. If the overall delay difference between the
two delay lines is reduced to /2 T1 , the difference between
successive time events generated by them is reduced to . Under
this condition, the time events are uniformly distributed over
one cycle of T2 and can be represented by
t(m) = m < T2 ,
Fig. 5. VDL-based TDC with feedback paths converting delay lines to ring
oscillators.

coherency between the oscillator and the reference clock, the

periods of these signals have to be carefully adjusted [20]
to ensure the generation of proper time events for calibration. In general, in addition to an on-chip oscillator, dedicated
circuitries are needed to properly control the period of the
oscillator to perform TDC calibration in this method.
IV. P ROPOSED M ETHOD OF TDC C ALIBRATION
The delay lines in the TDC can be reused in calibration mode
to generate necessary time events. As shown in Fig. 5, if the
feedback paths in a VDL-based TDC are added, the two delay
lines are converted to ring oscillators with different frequencies.
In the proposed method, first, the delay lines are configured
as ring oscillators to oscillate at close frequencies to generate
a set of time events with equal probabilities of occurrence.
Then, the output codes are recorded to estimate the size of each
quantization level. The frequencies of oscillation for the two
signals S1 and S2 generated by the ring oscillators in Fig. 5 are
given by
1
1
=
T1
2 n 1
1
1
=
f2 =
T2
2 n 2

f1 =

(5)
(6)

where T1 and T2 are the periods of S1 and S2 , respectively; n

is the number of delay cells in each delay line; and 1 and 2
represent one cell delay in the delay lines, respectively. For a
typical calibration case where f1 and f2 are not equal, if the
signals of S1 and S2 in Fig. 5 are observed, the time events can
be expressed by
t(m) = (T0 + mT1 ) mod T2

for m = 1, 2, . . . N

(7)

where T0 is the initial time difference between the rising edges

of S1 and S2 . The time difference between two successive
Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

m = 1, 2, . . . N.

(9)

The probability of the events occurring within the time interval

of 0 < t < T2 is linear and given by
P [t ] = t /T2 .

(10)

Therefore, if this sequence of time events is applied to a

monotonic TDC, the probability density of each output code
can be used to estimate the size of the corresponding quantization step. The sequence represented by (7) includes a set of
high-resolution deterministic events. Such events are difficult
to generate with on-chip ring oscillators that are known for
poor stability and high jitter. In most applications, jitter is undesirable and creates many problems. However, as shown here,
for the purpose of TDC calibration in the proposed method,
jitter is helpful and facilitates the generation of appropriate time
events. The sequence in (7) contains just m distinct events with
a grid spacing of that are equally distributed over T2 . For
ideal ring oscillators without jitter, the probability of events
between the specified grids is zero. As jitter increases, the
probability of the event between the grid positions increases
due to the displacement of the rising edges. If the effect of
jitter is taken into account, the locations of the grids cannot
accurately be determined. Instead, each grid position can be
represented by a Gaussian probability density function (pdf)
with a standard deviation of representing the RMS jitter of the
grid positions. The probability of hitting an event between the
grids can be calculated by superposition of all pdfs. For a total
of m grids with equal spacing of , the probability of hitting
time t between the grids follows normal distribution and can
be expressed by
m
2
1  (ti)
e 22
P (t) =
2 i=0

for 0 < t < T2 .

(11)

For a grid spacing of = , the probability of hitting time t

remains constant for all values of t with a slight variation of
0.018%. Thus, for a grid spacing of equal to or less than
the RMS jitter of the oscillators, all time events are given equal
chance to appear at the input.

RASHIDZADEH et al.: ALL-DIGITAL SELF-CALIBRATION METHOD FOR VERNIER-BASED TDC

Fig. 6.

467

(a) Sizes of the first quantization step 12 in 50 trials. (b) Distribution of 12 in 100 trials.

To calibrate a VDL-based TDC, a method that is similar to

the indirect calibration technique is adopted. First, the events
are applied to the TDC, and the distribution of zeros and ones
at the output of each flip-flop is determined. Then, the number
i
causing a transition from 1 and 0 between
of events N1,0
two consecutive flip-flops of i and i + 1 is counted. The
probability of observing these events in the entire sequence of
the events is determined from
i
P (i ) = N1,0
/Ntot

(12)

where Ntot is the total number of events in the event sequence.

Alternatively, the probability of P (i ) is estimated by
P (i ) = i /T2

(13)

where i is the duration of time that leads to logic high at

the output of Qi and logic low at the output of Qi+1 . From
(12) and (13), the width of i is determined. This procedure
is repeated N times, and the histograms of the density of the
codes are obtained for all TDC quantization levels; then, the
TDC characteristic curve is constructed.
V. S IMULATION AND E XPERIMENTAL R ESULTS
To verify the effectiveness of the proposed calibration
method, a 32-bit VDL-based TDC was implemented using an
Altera EPIC6T144C6 programmable logic device. To reduce
the delay difference between the delay lines in the calibration
mode, the building blocks were manually placed using the
Quartus II synthesis computer-aided design tool. In the calibration phase, the delay lines are configured as ring oscillators,
500 k samples of each TDC output were recorded through
an HP-1451A 20-MHz pattern input/output, and statistical
analysis was performed on a Sun Ultra 24 workstation. The
numbers of the samples with a transition between two consecutive quantization levels are determined, and the size of each
Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

Fig. 7. (a) Distribution curve of the first quantization step (12 ).

(b) PDF of 12 .

quantization step was estimated using the method described in

Section IV. Fig. 6(a) shows the estimated duration of the first
quantization step measured in different cycles of the time events
generated by the ring oscillators. It can be observed that the
estimated size of the quantization step varies from a minimum
of 75 ps up to a maximum of 80 ps. The histogram of the
estimated sizes in Fig. 6(b) shows that the distribution of the
measured step size has a maximum of 25 appearances at 77 ps.
To determine the pdf of the estimated sizes of the measured
quantization step, first, the distribution curve is obtained from
the histogram through a linear curve fitting. Then, the probabilities of the measured sizes are determined from their recorded
occurrence in 100 trials, and finally, the pdf is constructed, as
shown in Fig. 7. The mean value and standard deviation of the
quantization level obtained from the pdf are 77.5 and 2.5 ps,

468

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 2, FEBRUARY 2010

Fig. 8. (a) Quantization steps determined using the direct calibration method and the proposed calibration method. (b) Measurement error of the proposed
calibration method.

respectively. Fig. 8 shows the measured step sizes for all 32

levels of the TDC using direct calibration technique and the proposed method. The results of both methods are arranged from
the smallest value to the largest. The estimated quantization
steps obtained through simulation using the direct calibration
method have also been included for comparison. It can be
observed that the sizes of the quantization intervals change
from 75 to 92 ps, demonstrating a dynamic range of 17 ps.
The maximum error between the direct calibration method and
the proposed method is less than 8 ps. This amount of error
is expected and falls within a reasonable range of variations
since no external high-resolution reference source is employed
for calibration in this method. If the jitter of the external clock
in the direct calibration method is not compensated through
statistical methods, the measurement error produced by direct
calibration can exceed the error of the proposed method. To
measure the INL error of the implemented TDC, a straight line
is fitted to the data points of the quantization steps in such a way
that the distance between each quantization step and the line is
minimized. The INL with respect to the computed line, which is
commonly called the best-fit line, is shown in Fig. 9(a). It can be
observed that the peak-to-peak jitter without calibration is equal
to 75 ps. The measured RMS jitter before calibration exceeds
16.7 ps. A linearity calibration with uniformly distributed time
events, as shown in Fig. 9(b), reduces the jitter down to less
than 3.5 ps peak to peak (1.1 ps RMS). This remaining jitter
can be attributed to noise, inference, power supply ripples, and
other nonideal effects that have not been modeled.
VI. C ONCLUSION
A new method for the calibration of high-resolution on-chip
TDCs has been presented. It is shown how delay lines in a
VDL-based TDC can be used as ring oscillators to generate
Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

Fig. 9. (a) Linearity error without calibration. (b) Linearity error after
calibration.

a sequence of time events stimulating the TDC for calibration

purpose. The method uses statistical analysis techniques to estimate the variations of quantization steps over the measurement
range from TDC output codes in the calibration method. The
need for an external reference clock is eliminated, and the
area overhead of the calibration circuitry is minimized through
reuse of delay lines during the calibration phase. Simulation
and experimental results indicated that the proposed method
can effectively be used to calibrate VDL-based TDCs in the
range of a few picoseconds.

RASHIDZADEH et al.: ALL-DIGITAL SELF-CALIBRATION METHOD FOR VERNIER-BASED TDC

R EFERENCES
[1] K. Maatta and J. Kostamovaara, A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications, IEEE Trans.
Instrum. Meas., vol. 47, no. 2, pp. 521536, Apr. 1998.
[2] K. Cheng, S. Jiang, and Z. Chen, BIST for clock jitter measurements, in
Proc. IEEE Int. Symp. Circuits Syst., May 2528, 2003, pp. V-577V-580.
[3] D. Porat, Review of sub-nanosecond time-interval measurements, IEEE
Trans. Nucl. Sci., vol. NS-20, no. 10, pp. 3651, Oct. 1976.
[4] N. Abaskharoun, M. Hafed, and G. W. Roberts, Strategies for on-chip
sub-nanosecond signal capture and timing measurements, in Proc. IEEE
Int. Symp. Circuits Syst., May 2001, pp. 174177.
[5] S. Kleinfelder, T. J. Majors, K. A. Blumer, W. Farr, and B. Manor,
MTD132A new subnanosecond multi-hit CMOS time-to-digital converter, IEEE Trans. Nucl. Sci., vol. 38, no. 2, pp. 97101, Apr. 1991.
[6] F. Bigongiari, R. Roncella, R. Saletti, and P. Terreni, A 250-ps time
resolution CMOS multi-hit time-to-digital converter for nuclear physics
experiments, IEEE Trans. Nucl. Sci., vol. 46, no. 2, pp. 7377,
Apr. 1999.
[7] F. Baronti, L. Fanucci, D. Lunardini, R. Roncella, and R. Saletti,
On the differential nonlinearity of time-to-digital converters based on
delay-locked-loop delay lines, IEEE Trans. Nucl. Sci., vol. 48, no. 6,
pp. 24242431, Dec. 2001.
[8] P. Andreani, F. Bigongiari, R. Roncella, R. Saletti, P. Terreni,
A. Bigongiari, and M. Lippi, Multihit multichannel time-to-digital
converter with 1% differential nonlinearity and near optimal time
resolution, IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 650656,
Apr. 1998.
[9] M. J. Hsiao, J. R. Huang, and T. Y. Chang, A built-in parametric timing
measurement unit, IEEE Des. Test Comput., vol. 21, no. 4, pp. 322330,
Jul./Aug. 2004.
[10] P. Chen, L. Shen-Luan, and W. Jingshown, A CMOS pulse-shrinking
delay element for time interval measurement, IEEE Trans. Circuits
Syst. II, Analog Digit. Signal Process., vol. 47, no. 9, pp. 954958,
Sep. 2000.
[11] J. P. Jansson, A. Mantyniemi, and J. Kostamovaara, A CMOS time-todigital converter with better than 10 ps single-shot precision, IEEE J.
Solid-State Circuits, vol. 41, no. 6, pp. 12861296, Jun. 2006.
[12] B. K. Swann, B. J. Blalock, L. G. Clonts, D. M. Binkley, J. M. Rochelle,
E. Breeding, and K. M. Baldwin, A 100-ps time-resolution CMOS
time-to-digital converter for positron emission tomography imaging applications, IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 18391852,
Nov. 2004.
[13] R. Szplet, J. Kalisz, and R. Szymanowski, Interpolating time counter
with 100 ps resolution on a single FPGA device, IEEE Trans. Instrum.
Meas., vol. 49, no. 4, pp. 879883, Aug. 2000.
[14] E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, A low
power CMOS time-to-digital converter, IEEE J. Solid-State Circuits,
vol. 30, no. 9, pp. 984990, Sep. 1995.
[15] S. Tabatabaei and A. Ivanov, Embedded timing analysis: A soc infrastructure, IEEE Des. Test Comput., vol. 19, no. 3, pp. 2234,
May/Jun. 2002.
[16] R. Van De Plassche, CMOS Integrated Analog-to-Digital and Digital-toAnalog Converters, 2nd ed. Norwell, MA: Kluwer, 2003.
[17] P. M. Levine and G. W. Roberts, A high-resolution flash time-to-digital
converter and calibration scheme, in Proc. IEEE Int. Test Conf., 2004,
pp. 11481157.
[18] V. Gutnik and A. Chandrakasan, On-chip picosecond time measurement, in Proc. IEEE VLSI Circuits Dig. Tech. Papers, 2000, pp. 5253.
[19] J. Rivoir, Fully-digital time-to-digital converter for ATE with autonomous calibration, in Proc. IEEE Int. Test Conf., Oct. 2006, pp. 110.
[20] J. Rivoir, Statistical linearity calibration of time-to-digital converters
using a free-running ring oscillator, in Proc. 15th Asian Test Symp.,
Nov. 2006, pp. 4550.

Authorized licensd use limted to: IE Xplore. Downlade on May 13,20 at 1:4530 UTC from IE Xplore. Restricon aply.

469

Rashid Rashidzadeh (S04M07) received the

B.S.E.E. degree from Sharif University of Technology, Tehran, Iran, in 1989 and the M.A.Sc. and Ph.D.
degrees in electrical engineering from the University
of Windsor, Windsor, ON, Canada, in 2003 and 2007,
respectively.
He is currently with the Department of Electrical
and Computer Engineering, University of Windsor,
Windsor. His research interests include analog/radiofrequency (RF) integrated circuit design, built-in selftest for mixed-signal circuits, and RF identification.

Majid Ahmadi (S75M77SM84F02) received

the B.Sc. degree in electrical engineering from Sharif
University of Technology, Tehran, Iran, and the
Ph.D. degree in electrical engineering from Imperial
College, London University, London, U.K., in 1971
and 1977, respectively.
Since 1980, he has been with the Department of
Electrical and Computer Engineering, University of
Windsor, Windsor, ON, Canada, where he is currently a Professor and the Director of the Research
Center for Integrated Microsystems. He has coauthored the book Digital Filtering in 1-D and 2-Dimensions; Design and Applications (New York: Plennum, 1989) and has published more than 400 papers in
the areas of digital signal processing, pattern recognition and computer vision,
neural network architectures and applications, very large scale integration
circuits and testing and computer arithmetic. He is the Associate Editor for the
Journal of Pattern Recognition and the Regional Editor for the Journal of Circuits, Systems and Computers. His research interests include digital signal processing, microelectromechanical systems, machine vision, pattern recognition,
neural network architectures, and very large scale integration implementation.
Dr. Ahead is a Fellow of the Institution of Electrical Engineers (U.K.)
and The Institution of Engineering and Technology (U.K.). He was the IEEE
Circuits and Systems Society Representative on the Neural Network Council
and the Chair of the IEEE Circuits and Systems Neural Systems Applications
Technical Committee. He was the recipient of an Honorable Mention Award
from the Editorial Board of the Journal of Pattern Recognition in 1992 and
the Distinctive Contributed Paper Award from the Multiple-Valued Logic
Conference Technical Committee and the IEEE Computer Society in 2000.

William C. Miller (S57M60LM02) received

the B.S.E. degree from The University of Michigan,
Ann Arbor, and the M.A.Sc. and Ph.D. degrees from
the University of Waterloo, Waterloo, ON, Canada,
all in electrical engineering.
He is currently a Professor Emeritus with the
Department of Electrical and Computer Engineering,
University of Windsor, Windsor, ON, Canada. He is
currently a member of the Board of Directors of the
Canadian Microelectronics Corporation, Kingston,
ON, which is a nonprofit corporation delivering a
national research infrastructure support program to microsystems researchers
in universities across Canada. He is carrying out research in the design
of microelectromechanical systems (MEMS) devices for hearing instrument
applications as part of a research collaboration with the Gennum Corporation
of Burlington, ON. He has authored or coauthored more than 240 research
papers in refereed journal and conference proceedings. His research interests include electronics, digital signal processing, neural networks, microelectronics,
and MEMS.
Dr. Miller is a Registered Professional Engineer in the Province of Ontario,
Canada.