Session 3

NITK ECE DEPARTMENT

29 OCT 2015

2 ways to react to inputs

Polling

Interrupts

Interrupt Registers

PxIE : Each bit enables (1) or disables (0) the interrupt for that
particular pin

PxIES : Selects whether a pin will generate an interrupt on the

rising-edge (0) or the falling-edge (1)

PxIFG : Interrupt flag register indicating whether an interrupt has

occurred on a particular pin (if it experienced the transition)

Polling

Interrupts

Types of interrupts

System Reset Interrupts When triggered, these interrupts cause

a reset of the system

Non Maskable Interrupts These interrupts cannot be masked.

Typically these are fault handlers such as oscillator faults and
flash access violation which indicate a critical condition

Maskable Interrupts Most interrupts on the MSP430 fall into this

category. GPIO, timers and peripherals all generate interrupts
that can be masked by the GIE bit.

Functions to control
globalMSP430 interrupts

__enable_interrupt(); // Enable Global Interrupts by GIE = 1

__disable_interrupt(); // Disable Global Interrupts by GIE = 0

Functions to control MSP430 Low

Power Modes

__bis_SR_register_on_exit(x)

__bic_SR_register_on_exit(x)

MSP430Low Power Modes Bits

#define LPM0_bits
#define LPM1_bits
#define LPM2_bits
#define LPM3_bits
#define LPM4_bits
(SCG1+SCG0+OSCOFF+CPUOFF)
#define GIE

(CPUOFF)
(SCG0+CPUOFF)
(SCG1+CPUOFF)
(SCG1+SCG0+CPUOFF)

(0x0008)

Ex :
__bic_SR_register_on_exit(LPM0_bits | GIE); //Exits LPM0

and disables

GIE upon

exit

MSP430 Timer_A

A 16-bit counter

4 modes of operation Stop, Up, Continuous, Up/Down

3 capture/compare registers (CCRx)

2 interrupt vectors TACCR0 and TAIV

The timer register (TAR) can be read and written

and can generate an interrupt on overflow.

TIMER A Registers