Giao Tiếp Với ARM

-1-
I HC QUC GIA H NI
TRNG I HC CNG NGH
TRNG XUN THNG
GIAO TIP VI VI IU KHIN ARM
LUN VN THC S
H Ni - 2011
-2MC LC
M U ....................................................................................................................6
PHN I - L THUYT CHUNG..............................................................................7
CHNG 1 - CU TRC VI IU KHIN ARM ................................................7
1.1 i nt v lch s hnh thnh v pht trin vi iu khin ARM.........................7
1.2 Cu trc c bn ARM.......................................................................................8
1.3 M hnh kin trc .............................................................................................8
1.4 M hnh thit k ARM ...................................................................................11
1.4.1 Li x l ..................................................................................................11
1.4.2 Cc thanh ghi ca ARM...........................................................................12
1.5 Cu trc load-store .........................................................................................13
1.6 Cu trc tp lnh ca ARM ............................................................................13
1.6.1 Thc thi lnh c iu kin........................................................................13
1.6.2 Phng thc nh a ch .........................................................................13
1.6.3 Ngn xp..................................................................................................14
1.6.4 Tp lnh ARM .........................................................................................14
1.7 Kt lun..........................................................................................................17
CHNG 2 - GIAO TIP VI VI IU KHIN ARM......................................18
2.1 M hnh giao tip trong vi iu khin ARM ...................................................18
2.2 Cc giao tip c bn trong vi iu khin ARM ...............................................19
2.2.1 Giao tip vi b nh ................................................................................19
2.2.2 Giao tip vi b iu khin ngt...............................................................22
2.2.3 Giao tip vi b nh thi ........................................................................26
2.2.4 Giao tip vi b iu khin tm dng v Reset ........................................29
2.2.5 Giao tip vi khi GIPO ..........................................................................31
2.2.6 Giao tip vi khi truyn/thu khng ng b a nng (UART) ................33
2.2.7 Giao tip ngoi vi ni tip (SPI)...............................................................35
2.2.8 Giao tip USB..........................................................................................36
2.2.9 Kin trc bus truyn d liu cao cp ca vi iu khin ARM ...................38
2.3 Kt lun..........................................................................................................42
CHNG 3 - C IM CC DNG LI X L ARM .................................44
3.1 Phn loi v tnh nng cc dng li x l ARM..............................................44
3.2 c im cc dng li x l ARM .................................................................46
3.2.1 c im ca kin trc dng li x l ARM v4T .....................................46
3.2.2 c im kin trc dng li x l ARM v5..............................................47
3.2.3 c im kin trc dng li x l ARM v6..............................................48
3.2.4 Kin trc dng li x l ARM v7.............................................................49
3.3 Kt lun..........................................................................................................50
PHN II - THC NGHIM ...................................................................................51
-3CHNG 4 - NG DNG MT S GIAO TIP VI VI IU KHIN

AT91SAM7S64 ........................................................................................................51
4.1 Gii thiu .......................................................................................................51
4.2 c tnh c bn ca vi iu khin AT91SAM7S64.........................................52
4.3 Khi ngun cung cp......................................................................................54
4.4 Cng kt ni chun JTAG ..............................................................................56
4.5 Mch cm bin nhit ..................................................................................56
4.6 Giao tip vi IC thi gian thc DS12C887 .....................................................59
4.7 Hin th d liu trn LED 7 on....................................................................70
4.8 Giao tip vi SD Card ....................................................................................73
4.9 Giao tip vi my tnh qua cng COM ...........................................................80
4.10 S nguyn l mch ..................................................................................83
4.11 S mt trn mch in .................................................................................85
4.12 S mt di mch in................................................................................85
4.13 Mch hon chnh ..........................................................................................86
4.14 Kt qu.........................................................................................................86
4.15 Lu thut ton .........................................................................................89
KT LUN ..............................................................................................................90
TI LIU THAM KHO..........................................................................................91
DANH MC BNG...................................................................................................92
DANH MC HNH....................................................................................................93
PH LC..................................................................................................................95
-4K HIU CC CH VIT TT

ADC
AMBA
AHB
AIC
ASIC
ASB
API
APB
BRG
CLK
CMSIS
CRC
DMA
DSP
DRAM
EEPROM
EPROM
FAT
FIFO
FIQ
GIPO
GSM
IEM
IRQ
LCD
LSB
Analog to Digital Converter

Advanced Microcontroller
Bus Architecture
Advanced High-performance
Bus
Advanced Interrupt Controller
Application-Specific
Integrated Circuit
Advanced System Bus
Application Programming
Interface
Advanced Peripheral Bus
Baud Rate Generator
Clock
The Cortex Microcontroller
Software Interface Standard
Cyclic Redundancy Check
Direct Memory Access
Digital Signal Processors
Dynamic Random Access
Memory
Electrically Erasable
Programmable Read-Only
Memory
Erasable Programmable ReadOnly Memory
File Allocation Table
First In First Out
Fast Interrupt Request
General Purpose
Input/Output
Global System for Mobile
Communications
Intelligent Energy
Management
B chuyn i tng t sang s

Kin trc bus truyn vi iu khin cao
cp
Bus truyn d liu hiu sut cao
Interrupt Request
Liquid Crystal Display
Least Significant Bit
Yu cu ngt
Mn hnh tinh th lng
Bit c gi tr thp nht
B iu khin ngt cao cp

Mch tch hp chuyn dng
H thng bus truyn a nng
Giao din lp trnh ng dng
Bus truyn ngoi vi a nng
B to tc Baud
Xung nhp
Chun giao tip phn mm vi iu khin
Cortex
Kim tra d vng
S truy cp b nh trc tip
B x l tn hiu s
B nh truy cp ngu nhin ng
B nh ch c c th xa c bng
in
B nh ch c c kh nng lp trnh
li c
Bng phn b tp tin
Vo trc ra trc
Yu cu ngt nhanh
u vo hoc ra a mc ch
H thng truyn thng di ng ton cu
B qun l mc tiu th nng lng
thng minh
-5MAC
MSB
PDA
PLD
PLL
PMC
PWM
PHY
RAM
ROM
RTC
Rx
SD Card
SPI
SRAM
SSRAM
Tx
TIC
UART
USB
VGA
Multiply-Accumulate Unit
Most Significant Bit
Personal Digital Assistant
Programmable Logic Device
Phase Lock Loop
Power Management Controller
Pulse Width Modulation
Physical
Random Access Memory
Read Only Memory
Real Time Clock
Receive
Secure Digital Card
Serial Peripheral Interface
Static Random Access
Memory
Synchronous Static Random
Access Memory
Transmit
Test Interface Controller
Universal Asynchronous
Receiver/Transmitter
Universal Serial Bus
Video Graphics Array
B tch ly nhn
Bit c gi tr cao nht
My h tr c nhn k thut s
B logic c kh nng lp trnh
Vng kha pha
B qun l ngun
B iu ch rng xung
Lp vt l
B nh truy nhp ngu nhin
B nh ch c
ng h thi gian thc
Nhn d liu
Th nh d liu s
Giao tip ngoi vi ni tip
B nh truy cp ngu nhin tnh
B nh truy cp ngu nhin ng b tnh
Truyn d liu
B giao tip kim th
B thu/pht khng ng b a nng
Bus ni tip a nng
Mng ha hnh nh
-6-
M U
Xut hin t nhng nm u thp nin 1960, h thng nhng ang pht trin
mnh m trong lnh vc k thut in t v cng ngh thng tin, vi nhng ng dng
rng ri trong cng nghip v i sng.
H thng nhng hin nay i hi phi c cu trc mnh, p ng thi gian thc
tt, dung lng b nh ln, kh nng tnh ton nhanh, kh nng tiu th nng lng
thp, tnh n nh cao v tch hp sn nhiu ngoi vi.
Vi iu khin ARM c nh gi l mt trong nhng dng vi iu khin mnh,
p ng c nhng yu cu trong h thng nhng ngy nay, c s dng rng ri
trn th gii v ang c nghin cu pht trin Vit Nam.
Trong khun kh ca ti, ta s tm hiu m hnh kin trc, cc giao tip vi vi
iu khin ARM, c im chung ca dng li x l ny v th nghim mt s ng
dng giao tip vi vi iu khin AT91SAM7S64 c li x l l ARM7TDMI.
-7-
PHN I - L THUYT CHUNG

CHNG 1
CU TRC VI IU KHIN ARM
c th thc hin giao tip vi vi iu khin ARM th yu cu trc ht t
ra l phi hiu r v cu trc v nhng c im ca vi iu khin ny [5] [6].
1.1 i nt v lch s hnh thnh v pht trin vi iu khin ARM
Vic thit k ARM c bt u t nm 1983 trong mt d n pht trin ca
cng ty my tnh Acorn.
Nhm thit k, dn u bi Roger Wilson v Steve Furber, bt u pht trin mt
b vi x l c nhiu im tng ng vi k thut MOS 6502 tin tin. Acorn tng
sn xut nhiu my tnh da trn 6502, v vy vic to ra mt chip nh vy l mt
bc tin ng k ca cng ty ny.
Nhm thit k hon thnh vic pht trin mu gi l ARM1 vo nm 1985, v
vo nm sau, nhm hon thnh sn phm ARM2. ARM2 c ng truyn d liu 32
bit, khng gian a ch 26 bit tc cho php qun l n 64 Mbyte a ch v 16 thanh
ghi 32 bit. Mt trong nhng thanh ghi ny ng vai tr l b m chng trnh vi 6
bit c gi tr cao nht v 2 bit c gi tr thp nht lu gi cc c trng thi ca b vi x
l. Th h sau, ARM3 c to ra vi 4KB b nh m v c chc nng c ci
thin tt hn na.
Vo nhng nm cui thp nin 80, hng my tnh Apple Computer bt u hp
tc vi Acorn pht trin cc th h li ARM mi. Cng vic ny tr nn quan trng
n ni Acorn nng nhm thit k tr thnh mt cng ty mi gi l Advanced RISC
Machines. T l do hnh thnh ch vit tt ARM ca Advanced RISC Machines
thay v Acorn RISC Machine. V sau, Advanced RISC Machines tr thnh cng ty
ARM Limited.
Kt qu s hp tc ny l ARM6. Mu u tin c cng b vo nm 1991 v
Apple s dng b vi x l ARM 610 da trn ARM6 lm c s cho PDA hiu
Apple Newton. Vo nm 1994, Acorn dng ARM 610 lm CPU trong cc my vi tnh
RiscPC ca h.
Tri qua nhiu th h nhng li ARM gn nh khng thay i kch thc. ARM2
c 30.000 transistors trong khi ARM6 ch tng ln n 35.000. tng ca nh sn
xut li ARM l sao cho ngi s dng c th ghp li ARM vi mt s b phn ty
chn no to ra mt CPU hon chnh, mt loi CPU m c th to ra trn nhng
nh my sn xut bn dn c v vn tip tc to ra c sn phm vi nhiu tnh nng
m gi thnh vn thp.
Th h kh thnh cng ca hng l li x l ARM7TDMI, vi hng trm triu li
c s dng trong cc my in thoi di ng, h thng video game cm tay.
-8ARM thnh mt thng hiu ng u th gii v cc ng dng sn phm

nhng i hi tnh nng cao, s dng nng lng t v gi thnh thp.
Chnh nh s ni tri v th phn thc y ARM lin tc c pht trin v
cho ra nhiu phin bn mi.
Nhng thnh cng quan trng trong vic pht trin ARM:
- Gii thiu tng v nh dng cc tp lnh c nn li (Thumb) cho php
tit kim nng lng v gim gi thnh nhng h thng nh.
- Gii thiu cc h iu khin ARM.
- Pht trin mi trng lm vic o ca ARM trn my tnh.
- Cc ng dng cho h thng nhng da trn li x l ARM ngy cng tr nn
rng ri.
Hu ht cc nguyn l ca h thng trn chip v cch thit k b x l hin i
c s dng trong ARM, ARM cn a ra mt s khi nim mi nh gii nn ng
cc dng lnh. Vic s dng ba trng thi nhn lnh gii m thc thi trong mi chu
k my mang tnh quy phm thit k cc h thng x l thc. Do , li x l
ARM c s dng rng ri trong cc h thng phc tp.
1.2 Cu trc c bn ARM
- Cu trc load-store (np-lu tr).
- Cho php truy xut d liu khng thng hng.
- Tp lnh trc giao.
- Tp lnh ARM-32bit.
- Hu ht cc lnh u thc hin trong vng mt chu k n.
Trong ARM c mt s tnh cht mi nh sau:
- Hu ht tt c cc lnh u cho php thc thi c iu kin, iu ny lm gim
vic phi vit cc tiu r nhnh cng nh b cho vic khng c mt b d
on r nhnh.
- Trong cc lnh s hc, ch ra iu kin thc hin, ngi lp trnh ch cn
sa m iu kin.
- C mt thanh ghi dch 32 bit m c th s dng y chc nng vi hu ht
cc lnh s hc v vic tnh ton a ch.
- C cc kiu nh a ch theo ch s rt mnh.
- C h thng con thc hin ngt hai mc u tin n gin nhng rt nhanh,
km theo cho php chuyn tng nhm thanh ghi.
1.3 M hnh kin trc
Cc thnh phn nhng cng vi mt li x l ARM c m t trong hnh 1.1.
y cng l mt kin trc chung trong h x l vi li ARM.
-9-
Hnh 1.1: M hnh kin trc li x l ARM.
Li x l ARM l mt khi chc nng c kt ni bi cc bus d liu, cc

mi tn th hin cho dng chy ca d liu, cc ng th hin cho bus d liu, v
cc biu din trong hnh l mt khi hot ng hoc mt vng lu tr. Cu hnh
ny cho thy cc dng d liu v cc thnh phn to nn mt b x l ARM.
D liu i vo li x l thng qua cc bus d liu. Cc d liu c th l mt
hng thc hin hoc mt trng d liu. Hnh 1.1 cho thy u im kin trc
Harvard ca ARM l s dng trn hai bus truyn khc nhau (bus d liu v bus lnh
tch ring), cn kin trc Von Neumann chia s d liu trn cng bus.
Cc b gii m s nh hng dch chuyn trc khi chng c thc thi. Mi
mt ch lnh thc hin thuc v mt tp lnh ring bit.
B x l ARM, ging nh tt c b x l RISC, s dng kin trc load-store.
iu ny c ngha l c hai loi ch lnh chuyn d liu vo v ra ca b x l:
lnh load cho php sao chp d liu t b nh vo thanh ghi trong li x l, v ngc
li lnh store cho php sao chp d liu t thanh ghi ti b nh. Khng c lnh x l
d liu trc tip trong b nh. Do , vic x l d liu ch c thc hin trong cc
thanh ghi.
Tt c d liu thao tc nm trong cc thanh ghi, cc thanh ghi c th l ton hng
ngun, ton hng ch, con tr b nh. Cc d liu 8 bit, 16 bit u c m rng
thnh 32 bit trc khi a vo thanh ghi.
- 10 Tp lnh ARM nm trong hai ngun thanh ghi Rn v Rm, v kt qu c tr v

thanh ghi ch Rd. Ngun ton hng c c t thanh ghi ang s dng trn bus ni
b A v B tng ng.
Khi s hc v logic (ALU: Arithmetic Logic Unit) hay b tch ly nhn (MAC:
Multiply-Accumulate Unit) ly cc gi tr thanh ghi Rn v Rm t bus A v B, v tnh
ton kt qu (b tch ly nhn c th thc hin php nhn gia hai thanh ghi v cng
kt qu vi mt thanh ghi khc). Cc lnh x l d liu ghi cc kt qu trc tip trong
Rd ri tr v tp thanh ghi.
Mt tnh nng quan trng ca ARM l thanh ghi Rm cn c th c x l trc
trong shifter (b dch chuyn) trc khi n i vo ALU. Shifter v ALU c th phi
hp vi nhau tnh ton cc biu thc v a ch.
M hnh thanh ghi theo kin trc Registry Registry, giao tip vi b nh thng
qua cc lnh load-store, cc lnh load v store s dng ALU tnh ton a ch c
lu trong cc thanh ghi a ch, ngoi ra tp lnh ny cn s dng ALU to ra a
ch c t chc trn a ch thanh ghi v truyn i trn cc bus a ch. B gia tc
dng trong cc trng hp truy xut cc vng nh lin tc.
Sau khi i qua cc khi chc nng, kt qu trong Rd c ghi tr li tp thanh
ghi. Tp lnh load-store cp nht tng a ch thanh ghi trc khi li x l c hoc
ghi gi tr thanh ghi t v tr nh tun t tip theo. Li x l tip tc thc hin cc
lnh cho n khi xy ra mt ngt ngoi l hoc c thay i dng chy thc hin
bnh thng.
Trn l tng quan v b x l ARM. Cc thnh phn chnh ca b vi x l gm li
x l, cc thanh ghi, kin trc ng ng s c trnh by trong phn k tip.
Ch hot ng ca ARM:
ARM c by ch hot ng, ch ngi dng l ch c bn v t c
quyn nht, khi CPU thc hin m ha d liu cho ngi dng.
Cc ch hot ng ca ARM c m t trong bng 1.1.
Bng 1.1: Cc ch hot ng ca RAM.
Ch
K hiu quy c
Mc c u tin
Ch cc bit [4:0]
Abort
abt
10111
Fast Interrupt Request
fiq
10001
Interrupt Request
irq
10010
Supervisor
svc
10011
System
sys
11111
Undefined
und
11011
User
usr
khng
10000
- 11 Trong :
- Abort
: c nhp vo sau khi d liu hoc lnh c b qua qu trnh

tin np.
- FIQ
: X l cc ngt c mc u tin cao, h tr vic truyn d liu v

cc knh x l
- IRQ
: c s dng cho vic x l cc ngt mc ch chung.
- Supervisor
: Ch bo v dng cho h iu hnh .
- System
: Ch u tin, dng cho h iu hnh .
- Undefined
: Dng cho trng hp m lnh khng hp l.
- User
: Ch ngi dng c mc u tin thp.
Cc ch ny c th c thit lp bng phn mm hoc thng qua cc ngt

bn ngoi hoc thng qua qu trnh x l ngoi l. Phn ln cc chng trnh ng
dng c thc thi trong ch User. Mi ch iu khin u c cc thanh ghi h
tr tng tc bt cc ngoi l.
1.4 M hnh thit k ARM
1.4.1 Li x l
Dng n gin ca li x l gm nhng phn c bn sau:
- Program Counter (PC): B m chng trnh: gi a ch ca lnh hin ti.
- Thanh ghi tch ly (ACC): gi gi tr d liu khi ang lm vic.
- n v x l s hc (ALU): thc thi cc lnh nh phn nh cng, tr, gia tng
- Thanh ghi lnh (IR): gi tp lnh hin ti ang thc thi.
Li x l MU0 c pht trin u tin v l li x l n gin, c tp lnh di
16 bit, vi 12 bit a ch v 4 bit m ha.
Cu trc tp lnh li MU0 c dng:
4 bits
12 bits
opcode
Hnh 1.2: Cu trc chun cho tp lnh ca MU0.
M hnh thit k ng truyn d liu n gin ca li x l MU0 c m t

trong hnh 1.3. Vic thit k cp chuyn i mc thanh ghi (RTL): B m chng
trnh (PC) ch n tp lnh cn thc thi, np vo thanh ghi lnh (IR), gi tr cha
trong IR ch n vng a ch nh, nhn gi tr, kt hp vi gi tr ang cha trong
thanh ghi tch ly (ACC) qua n v x l s hc (ALU) to gi tr mi, cha vo
ACC. Mi mt lnh nh vy, ty vo s ln truy cp nh m tn s chu k xung
nhp tng ng. Sau mi lnh thc thi, PC s c tng thm.
- 12 Bus a ch
PC
control
IR
Memory
ALU
IR
Bus d liu
Hnh 1.3: ng truyn d liu ca li x l MU0.
1.4.2 Cc thanh ghi ca ARM

phc v mc ch ca ngi dng: r0 r14 l 15 thanh ghi a dng, r15 l
thanh ghi Program Counter (PC), thanh ghi trng thi chng trnh hin ti (CPSR Current Program Status Register). Cc thanh ghi khc c gi li cho h thng (nh
thanh ghi cha cc ngt).
Cc thanh ghi ca ARM c m t trong hnh 1.4.
Hnh 1.4: M hnh cc thanh ghi ca ARM.
- Thanh ghi CPSR c ngi dng s dng cha cc bit iu kin.

- N: Negative - c ny c bt khi bit cao nht ca kt qu x l ALU bng 1.
- Z: Zero - c ny c bt khi kt qu cui cng trong ALU bng 0.
- C: Carry - c ny c bt khi kt qu cui cng trong ALU ln hn gi tr 32
bit v trn.
- 13 - V: Overflow - c bo trn sang bit du.

- Thanh ghi SPSR (Save Program Status Register) dng lu gi trng thi ca
thanh ghi CPSR khi thay i ch .
1.5 Cu trc load-store
Cng nh hu ht cc b x l dng tp lnh RISC khc, ARM cng s dng cu
trc load-store. iu c ngha l: tt c cc lnh (cng, tr) u c thc hin
trn thanh ghi. Ch c lnh sao chp gi tr t b nh vo thanh ghi (load) hoc chp
li gi tr t thanh ghi vo b nh (store) mi c nh hng ti b nh.
Cc b x l CISC cho php gi tr trn thanh ghi c th cng vi gi tr trong b
nh, i khi cn cho php gi tr trn b nh c th cng vi gi tr trn thanh ghi.
ARM khng h tr cu trc lnh dng t b nh n b nh. V th, tt c cc lnh
ca ARM thuc mt trong ba loi sau:
- Lnh x l d liu: ch thay i gi tr trn thanh ghi.
- Lnh load-store: sao chp gi tr t thanh ghi vo b nh v sao chp gi tr t
b nh vo thanh ghi.
- Lnh iu khin dng lnh: bnh thng, ta thc thi cc lnh cha trong mt
vng nh lin tip, tp lnh iu khin dng lnh cho php chuyn sang cc
a ch khc nhau khi thc thi lnh, ti nhng nhnh c nh (lnh r nhnh)
hoc l lu v tr li a ch phc hi chui lnh ban u (lnh r nhnh v
kt ni) hay l ln vng m ca h thng.
1.6 Cu trc tp lnh ca ARM
1.6.1 Thc thi lnh c iu kin
ARM cung cp kh nng thc hin mt cch c iu kin hu ht cc lnh da
trn t hp trng thi ca cc c iu kin trong thanh ghi CPSR.
Thanh ghi CPSR cho bit trng thi ca chng trnh hin ti v c m t
trong hnh 1.5.
31
N
28 27
Z C V
8 7
Khng dng
6 5 4
F
T Chn ch
Hnh 1.5: V tr cc bit trn thanh ghi CPSR.
1.6.2 Phng thc nh a ch

i vi nhng lnh x l d liu ch c hai phng thc l trc tip thanh ghi v
gi tr trc tip.
i vi nhng lnh load v store th phng thc a ch l gin tip cc thanh
ghi (khng c phng thc trc tip b nh).
- 14 1.6.3 Ngn xp
ARM h tr vic lu v phc hi gi tr nhiu thanh ghi, gm hai lnh:
- LDM : Load multiple register.
- STM : Store multiple register.
Vic lu hoc phc hi gi tr thanh ghi vi b nh bt u t a ch c lu
trong thanh ghi nn, gi tr ca thanh ghi nn c th gi nguyn hoc c cp nht.
Th t a ch b nh sao lu cc thanh ghi tng hoc gim ty theo phng thc
nh a ch.
1.6.4 Tp lnh ARM
Tt c lnh ca ARM u l 32 bit:
- C cu trc dng load-store.
- Cu trc lnh nh dng ba a ch (ngha l a ch ca hai ton hng ngun
v ton hng ch u l cc a ch ring bit).
- Mi mt lnh thc thi mt iu kin.
- C c lnh load-store nhiu thanh ghi ng thi.
- C kh nng dch bit kt hp vi thc thi lnh ALU trong ch mt chu k my.
- Ch Thumb code: l mt ch c bit ca ARM dng tng mt m
bng cch nn lnh 32 bit thnh 16 bit. Mt phn cng c bit s gii nn
lnh Thumb 16 bit thnh lnh 32 bit.
ARM h tr su kiu d liu:
- 8 bit c du v khng du.
- Cc ton t ca ARM c 32 bit, khi lm vic vi cc d liu ngn hn, cc bit
cao ca ton t s c thay th bng bit 0.
Cch t chc v thc thi tp lnh ca ARM:
Hnh 1.6: Chu k thc thi lnh theo kin trc ng ng.
- 15 Cch t chc ca li ARM khng thay i nhiu t nm 1983 1995, u s

dng tp lnh c kin trc ng ng ba tng. T 1995 tr v y, ARM gii thiu
mt s li mi c s dng kin trc ng ng chn tng.
Chu k thc thi lnh theo kin trc ng ng c m t trong hnh 1.6.
Cc bc thc thi lnh gm:
- Nhn lnh t b nh (fetch);
- Gii m lnh, xc nh cc tc ng cn c v kch thc lnh (decode);
- Truy cp cc ton hng c th c yu cu t thanh ghi (reg);
- Kt hp vi ton hng y to thnh kt qu hay a ch b nh (ALU);
- Truy cp vo b nh cho ton hng d liu nu cn thit (mem);
- Vit kt qu ngc li thanh ghi (res).
Kin trc ng ng
Kin trc ng ng l kin trc c bn trong vi iu khin ARM, hnh 1.7 m t
kin trc ng ng ba tng minh ha cc bc thc thi lnh: fetch decode
excute (nhn lnh gii m thc thi).
Hnh 1.7: Kin trc ng ng ba tng.
Trong kin trc ng ng, khi mt lnh ang c thc thi th lnh th hai ang
c gii m v lnh th ba bt u c np t b nh. Vi k thut ny th tc
x l tng ln rt nhiu trong mt chu k my.
Trong hnh 1.7 cho ta thy c mt chui ba lnh c np, gii m, v thc thi
bi b x l. Mi lnh c mt chu trnh duy nht hon thnh sau khi ng ng
c lp y.
Tp lnh c t vo cc ng ng lin tc. Trong chu k u tin li x l
np lnh ADD (cng) t b nh. Trong chu k th hai li tm np cc lnh SUB (tr)
v gii m lnh ADD. Trong chu k th ba, c hai lnh SUB v ADD c di chuyn
dc theo ng ng. Lnh ADD c thc thi, lnh SUB c gii m, v lnh CMP
(so snh) c np. Qu trnh ny c gi l lp y ng ng. Kin trc ng
ng cho php li x l thc hin lnh trong mi chu k.
- 16 Khi tng chiu di ng ng, s lng cng vic thc hin tng cng on
gim, iu ny cho php b x l phi t c n mt tn s hot ng cao hn
tng hiu sut thc thi. Thi gian tr ca h thng cng s tng ln bi v c nhiu chu
k hn lp y ng ng trc khi li x l c th thc thi mt lnh. Chiu di
ng ng tng ln cng c ngha l d liu cng c th s phi ph thuc gia cc
cng on nht nh.
ARM gii thiu v a ra kin trc ng ng c nm tc v, vi vng nh d
liu v chng trnh ring bit. T kin trc lnh c ba tc v c chia nh li thnh
nm tc v cng lm cho mi chu k xung nhp s thc hin mt cng vic n gin
hn mi cng on, cho php c th tng chu k xung nhp ca h thng. S tch ri
b nh chng trnh v b nh d liu cng cho php gim ng k ti nguyn chim
ca mi lnh trong mt chu k my.
Hnh 1.8: Kin trc ng ng ba tng trong tp lnh c nhiu chu k my.
Thi gian b x l thc thi mt chng trnh c tnh bi cng thc:

N inst x CPI
T pro
f clk
Trong :
- CPI l s xung nhp trung bnh cn cho mi lnh;
- Ninst l s lnh thc thi mt chng trnh (c nh);
- fclk l tn s xung nhp.
Vi cng thc trn th c hai cch gim thi gian thc thi mt chng trnh:
- Tng tn s xung nhp: iu ny i hi trng thi ca mi nhim v trong
dng chy lnh n gin, v do s tc v s tng thm.
- 17 - Gim CPI: iu ny i hi mi lnh cn nhiu dng chy lnh hn vi

tc v khng i, hoc cc tc v cn n gin hn, hoc kt hp c hai
li vi nhau.
1.7 Kt lun
Chng 1 trnh by nhng khi qut c bn ca vi iu khin ARM, qua ta nm
c qu trnh pht trin v hnh thnh vi iu khin ARM, m hnh kin trc ca vi
iu khin ARM v cu trc tp lnh vi rt nhiu u im nh: tp lnh 32 bit, cu
trc load-store, cch t chc v thc thi tp lnh ca ARM di dng kin trc ng
ng v tp lnh trc giao, hu ht tt c cc lnh u cho php thc thi c iu kin v
thc thi trong mt chu k n. Vi cc c tnh k thut c trng ny th vi iu
khin ARM l mt trong nhng vi iu khin c tc x l, hiu sut thc thi cao v
kh nng tiu th nng lng t nht vo thi im hin nay.
---------------------------------
- 18 CHNG 2
GIAO TIP VI VI IU KHIN ARM
2.1 M hnh giao tip trong vi iu khin ARM
Vi iu khin ARM l mt h thng c cha li vi x l ARM vi cc giao tip
h tr bn trong [6].
Vi iu khin ARM c thc thi trn h thng kin trc cc bus truyn d liu
a chc nng ca vi iu khin. Bao gm b x l ARM kt ni qua h thng bus
truyn d liu hiu sut cao ng b nhanh vi SRAM, cc bus giao tip ngoi, v
cu ni ti cc bus truyn ngoi vi cng sut thp, c m t trong hnh 2.1.
Thit b ngoi vi bn ngoi c xy dng t cc thit b ring v ty theo ng
dng ngi dng.
Hnh 2.1: M hnh giao tip trong vi iu khin ARM.
Cc khi chc nng trong vi iu khin ARM bao gm:

- B x l ARM;
- B iu khin ngt;
- B phn x bus truyn hiu sut cao (AHB - Advanced High-performance
Bus);
- B iu khin b nh;
- SRAM;
- EPROM hoc Flash;
- 19 - DRAM;
- Cu ni AHB APB (Advanced Peripheral Bus: Bus truyn ngoi vi ti u)
- Cu ni ngoi AHB;
- B m/nh thi;
- Khi SPI (Serial Peripheral Interface): Khi giao tip cc thit b ngoi vi ni
tip;
- Khi Serial UART (Serial Universal Asynchronous Receiver/Transmitter): Khi
giao tip ni tip truyn/thu khng ng b a nng.
2.2 Cc giao tip c bn trong vi iu khin ARM
2.2.1 Giao tip vi b nh
Giao tip vi b nh trong vi iu khin ARM [7] c tnh nng truy xut d liu
rt nhanh.
Trong vi iu khin ARM, b nh ni b c th c cc dng b nh nh:
SSRAM, SRAM, DRAM, EPROM/Flash.
Bn b nh chnh c m t trong hnh 2.2:
Hnh 2.2: S phn tch hai trng thi trn bn b nh.
- 20 Bn b nh c hai trng thi:

- Trng thi Reset.
- Trng thi thng thng: sau khi c nh x cc thanh ghi nh a ch vo.
Trong cu hnh thng thng ( c nh a ch), k hiu vng RAM l t a
ch 0x0 n 0x04000000.
Trong cu hnh Reset, ROM c nh x vo khng gian c k hiu vi kh
nng truy cp RAM a ch cao hn.
Khi truy cp vo khng gian b nh 0x10000000, b x l s hy b cc trng
hp ngoi l (sai a ch).
Vng RAM
Vng RAM c chia thnh bn khi chnh c m t trong hnh 2.3. T phn
16MB dnh ring cho DRAM, SRAM, SSRAM.
Hnh 2.3: Vng RAM.
- 21 Khi 16MB (khi im 0x0) l vng ROM, c cc im k hiu ti cu hnh

c s ca ROM, hoc c cc vng xp chng ln RAM (trong cu hnh thng thng).
Bng a ch trn vng RAM trong cu hnh thng thng v Reset c m t
trong bng 2.1
Bng 2.1: Cc a ch trn vng RAM.
Cu hnh thng thng
Cu hnh Reset
a ch
a ch tng ng
a ch
a ch tng ng
0x00000000
0x01000000
0x00000000
0x04000000
0x00002000
0x02002000
0x00080000
0x03080000
Trong lin kt nh a ch, theo mc nh khi cu hnh Reset, EPROM v

Flash di y ca a ch bn nh. Nu thanh ghi nh a ch c ghi vo, tn
hiu nh a ch s l mc cao v b gii m chuyn sang bn b nh thng
thng, khi RAM s di cng.
Nu khi hot ng m h thng khng c EPROM hay Flash, hoc nu mun
khi ng t RAM, phi g lin kt nh a ch. Tn hiu nh a ch s lun mc
cao, v vic khi ng vi SSRAM s di y ca a ch bn nh.
Cc b nh trong vng RAM c chc nng:
- SSRAM
ng b SRAM (SSRAM) c dng cung cp b nh chu k n. Thit b
SSRAM t chc di dng 32KB x 32 bit. Vng ny c s dng cho cc trnh gii
hn thi gian, nh l cc b iu khin ngt. SSRAM thng a ch 0, cu hnh ca
b nh ny l khng bt buc.
- SRAM
SRAM c dng th hin cc gin b nh khc nhau. SRAM cho php
iu khin bn mc vt l 128KB x 8 bit chia thnh hai dy logic ca mi mt mc
256KB. Mi mt dy logic ny c th c nh cu hnh 8, 16, hoc 32 bit b nh
m rng. SRAM m phng b nh h thng ny bng cch chn chnh xc s trng
thi ch.
- DRAM
DRAM cung cp:
H tr ch tun t truy cp;
H tr cc bc chuyn byte, halfword v word;
B iu khin lm ti DRAM;
T ng nh li cu hnh kch thc khi.
- 22 Vng ROM
C mt vng c dnh ring cho ROM. Vng ROM ging nh c hai cu hnh
thng thng v cu hnh Reset ca bn b nh, vng ROM c m t nh trong
hnh 2.4.
128 MB
0x08000000
ROM
64 MB
0x04000000
Hnh 2.4: Vng ROM.
Khi Reset vi iu khin ARM, ROM c xc nh v tr 0x0 v khi chuyn

sang trng thi thng thng th RAM s v tr di cng ca bn a ch.
EPROM/Flash
EPROM/Flash c hai dng, mt cho 8 bit b nh m rng v mt cho 16 bit b
nh m rng. Cc b nh ny c th c truy cp cng theo chun EPROM hoc
theo chun 5V Flash.
2.2.2 Giao tip vi b iu khin ngt
B iu khin ngt trong ARM [8] cung cp giao tip phn mm c lp cho h
thng ngt. Cc bit ngt c nh ngha cho yu cu chc nng c bn trong thit k
h thng.
Trong h thng ARM c hai mc ngt:
- FIQ (Fast Interrupt Request) dnh cho ngt nhanh.
- IRQ (Interrupt Request) dnh cho cc ngt chung.
FIQ c s dng ti bt k thi im no. N cung cp ngt vi thi gian tr
thp, ging nh l mt ngun c lp m bo chng trnh phc v ngt c th thc thi
trc tip m khng cn s quyt nh ca ngun ngt chnh. iu lm gim bt thi
gian tr ngt nh l cc thanh ghi c bit, cc thanh ghi ny dnh cho cc ngt FIQ v
dng ti a hiu sut.
Cc b iu khin ngt c chia ra s dng cho FIQ v IRQ, ch khc v tr
mt bit ring c nh r cho b iu khin FIQ, cc bit cn li trong b iu khin
ngt ny dnh cho ngun ngt c lp trong 32 bit ca b iu khin IRQ v c m
t trong hnh 2.5.
- 23 -
Hnh 2.5: Cc b iu khin ngt FIQ v IRQ.
B iu khin ngt s dng v tr bit cho mi ngun ngt khc nhau v mi v tr

c nh r bi phn mm chng trnh ngt, cc knh truyn thng v cc b nh
thi. Bit 0 khng c xc nh trong b iu khin IRQ, mc d vy n vn c th
c s dng chung tng t ngun ngt nh trong b iu khin FIQ.
Tt c ngun ngt c a vo s hot ng mc cao, bt k yu cu o hay
cht tc ng n phi c cung cp ti ngun ngt chung.
Quyn u tin trong s phn cng khng c cung cp, cng khng c bt
k dng quyn u tin vc t ngt, tt c cc chc nng ny c th c cung cp
trong phn mm.
Thanh ghi ngt chng trnh cng cung cp ti ngt chung di s iu khin
ca phn mm. y l dng s dng gim cp t ngt FIQ thnh ngt IRQ.
B iu khin ngt cung cp cc trng thi ngun ngt, trng thi yu cu ngt v
thanh ghi cho php ngt. Thanh ghi cho php ngt c dng quyt nh mt ngun
ngt hot ng nu sinh ra mt yu cu ngt h thng x l.
Trng thi ngun ngt ch xc nh nu ngun ngt tng thch u tin hot
ng. Ngun ngt s hot ng mc cao, do mt mc logic cao trong thanh ghi
trng thi ngun ch bo ngun ngt hot ng.
Trng thi yu cu ngt c xc nh nu ngun ngt sinh ra mt yu cu ngt
ti b x l.
Thanh ghi cho php ngt c c ch kp cho vic thit lp v xa cc bit cho php.
Cc bit thit lp hay xa ny l c lp v khng lin quan g n cc bit khc trong
thanh ghi cho php.
Khi ghi vo v tr thit lp cho php ngt, mi mt bit d liu s c thit lp
mc cao tng ng vi bit trong thanh ghi cho php v tt c cc bit khc trong thanh
- 24 ghi cho php khng b nh hng. Khi ghi vo v tr xa trn thanh ghi cho php ngha
l dng bit xa o li, khng dng cc bit khc.
Mt knh ca b iu khin ngt c m t trong hnh 2.6.
Hnh 2.6: S mt knh ca b iu khin ngt.
B iu khin ngt FIQ c dnh ring bit 0. B iu khin IRQ c s lng

ln hn, kch thc ca b iu khin ny ph thuc vo h thng x l.
Cc thanh ghi iu khin ngt:
Cc thanh ghi sau c quy nh cho c hai b iu khin ngt FIQ v IRQ
- Thanh ghi cho php
Trng thi ch c.
Thanh ghi cho php c dng chc chn ngun ngt u vo v xc nh
ngun ngt u vo c tc ng s to ra mt yu cu ngt n b x l.
Thanh ghi ny l ch c v cc gi tr ca n ch c th thay i bi cc v tr
thit lp hoc xa. Nu cc bit trong b iu khin ngt cha c kch hot
(thit lp hoc xa) th c ngha l cc bit trong thanh ghi cho php s c
nhng vi trng thi khng xc nh.
Bit cho php l 1 ch bo rng ngt c kch hot v s cp mt yu cu
ngt ti b x l. Bit kch hot l 0 ch bo rng ngt c xa. Trng thi
khi ng li s xa b tt c cc ngt.
- Thanh ghi cho php thit lp:
Trng thi ch ghi.
V tr ny dng thit lp cc bit trong thanh ghi cho php ngt. Khi ghi vo
v tr ny bit d liu mc cao s sinh ra bit tng ng trong thanh ghi cho php
c thit lp. Cc bit d liu thp khng nh hng n bit tng ng trong
thanh ghi cho php.
- 25 - Thanh ghi cho php xa:

Trng thi ch c.
V tr ny dng xa cc bit trong thanh ghi cho php ngt. Khi ghi vo
thanh ghi ny bit d liu mc cao s sinh ra bit tng ng trong thanh ghi cho
php c xa. Cc bit d liu thp khng nh hng n bit tng ng trong
thanh ghi cho php ngt.
- Thanh ghi trng thi ngun:
Trng thi ch c.
V tr ny cung cp tnh trng ca cc ngun ngt ti b iu khin ngt. Bit
cao ch bo rng mt yu cu ngt thch hp l m bo c quyn u tin
hot ng.
- Thanh ghi yu cu ngt:
Trng thi ch c.
V tr ny cung cp tnh trng ca ngun ngt. Bit cao ch bo rng ngt hot
ng v s to ra mt ngt a ti b x l.
- Thanh ghi ngt chng trnh IRQ:
Trng thi ch ghi.
Khi ghi vo thanh ghi ny s thit lp hoc xa mt chng trnh ngt. Ghi
vo thanh ghi ny bit 1 phn cao s to ra mt chng trnh ngt, trong khi
ghi vo thanh ghi ny bit 1 phn thp s xa chng trnh ngt. Gi tr thanh
ghi ny s quyt nh bi vic c bit 1 ca thanh ghi trng thi ngun. Khng
s dng bit 0 trong thanh ghi ny.
Mt s thanh ghi dnh ring cho kim tra. Cc thanh ghi ny khng c truy
cp trong qu trnh hot ng thng thng.
Cc bit c nh ngha trong b iu khin ngt
B iu khin ngt FIQ gm mt bit (bit 0).
Bit 1 n bit 5 trong b iu khin ngt c nh ngha nh trong bng 2.2. Bit
6 tr ln n bit 31 ty theo yu cu s dng.
Bng 2.2: Cc bit nh ngha trong b iu khin ngt.
Bit
Ngun ngt
FIQ source
Programmed Interrrupt
Comms Rx
Comms Tx
Timer 1
Timer 2
- 26 Bn nh b iu khin ngt c m t trong bng 2.3.

Bng 2.3: Bn nh b iu khin ngt.
a ch c s ca b iu khin ngt khng c nh v c th khc nhau i vi

mi h thng x l c th. Tuy nhin, khong cch ca cc thanh ghi t a ch c s
c c nh.
2.2.3 Giao tip vi b nh thi
Gii thiu chung
C ti thiu hai b nh thi trong mt h thng ARM [8], mc d c nh
ngha nh vy nhng c th d dng m rng thm cc b nh thi. Cng vi nguyn
tc m rng n gin l tc ng ti cu trc thanh ghi s cung cp thm cc b nh
thi cho s dng t vic lp trnh.
Mi mt b nh thi l mt b m ngc rng 16 bit, c th la chn phn
chia tn s u vo. Mch m cho php xung h thng c s dng trc tip, hoc
xung c chia bi 16, 256 hoc 1024 ty theo s dng. Vic phn chia ny c
cung cp bi cc bc 0, 4, 8 hoc 10 ca b chia t l xung.
B nh thi c hai ch hot ng:
- Kiu m t do.
- Kiu tun hon.
Trong ch nh thi tun hon b m s to ra mt ngt ti mt khong thi
gian. Trong ch nh thi t do, b nh thi s trn b m sau khi n gi tr 0 v
tip tc m ngc t gi tr cc i.
Hot ng ca b nh thi
B nh thi c np bi vic ghi vo thanh ghi np, sau nu nh c cho
php, b nh thi s m ngc v 0. Trn mt hnh trnh m v 0 nh vy, mt
ngt s c to ra. Ngt s c xa bng cch ghi vo thanh ghi xa.
- 27 Sau hnh trnh m v 0, nu b nh thi ang hot ng ch nh thi t

do th b nh thi s tip tc m gim t gi tr cc i. Nu ang trong ch
tun hon th b nh thi s ti li t thanh ghi np v tip tc m gim. Trong ch
ny b nh thi s to ra mt chu k ngt (ngt nh k). Cc ch c la
chn bi mt bit trong thanh ghi iu khin.
bt k im hin hnh no th gi tr b nh thi cng c th c t b m
ngc, c m t trong hnh 2.7.
B nh thi c kch hot bng mt bit trong thanh ghi iu khin. Vic
khi ng li s lm b nh thi c xa, ngt s c xa v thanh ghi np s
khng xc nh. Cc ch v gi tr trong b chia t l cng s khng xc nh.
Hnh 2.7: Gin khi b nh thi.
Xung nhp b nh thi c to ra bi b chia t l xung. Xung nhp b nh

thi c th l xung h thng, xung h thng c chia t b chia 16, c to ra bi 4
bit ca b chia t l, hoc xung h thng c chia t b chia 256 c to ra bi tng
hp 8 bit ca b chia t l, c m t trong hnh 2.8.
Hnh 2.8: B chia t l xung.
- 28 Cc thanh ghi trong b nh thi

- Thanh ghi np:
Thanh ghi np c trng thi thanh c hoc ghi.
Thanh ghi np cha gi tr khi to ca b nh thi v dng gi tr ny np
li trong ch nh thi tun hon. Khi ghi vo thanh ghi ny, 16 bit trn
cng ghi vo l 0 v khi c 16 bit trn cng s khng xc nh.
- Thanh ghi gi tr:
Thanh ghi gi tr c trng thi ch c.
V tr thanh ghi gi tr cho bit gi tr hin hnh ca b nh thi.
- Thanh ghi xa:
Thanh ghi xa c trng thi ch ghi.
Khi ghi vo v tr thanh ghi xa s xa i mt ngt c to ra bi b m
ca b nh thi.
- Thanh ghi iu khin:
Thanh ghi iu khin c trng thi c hoc ghi.
Thanh ghi iu khin cung cp vic cho php hay loi b cc ch v cu
hnh chia t l cho b nh thi.
- V tr cc bit trong thanh ghi iu khin cho b nh thi c m t trong hnh 2.9.
31
8
0
Cho php
Chn ch
B chia t l
Hnh 2.9: V tr cc bit trong thanh ghi iu khin.
- Chc nng cc bit trong thanh ghi iu khin c m t trong bng 2.4.
Bng 2.4: M t cc bit trong thanh ghi iu khin cho b nh thi.
Cc bit 0 1, 4 5, 8 31:
khng xc nh
Ghi gi tr 0 v c c nh l khng xc nh
Bit 2, 3 Cc bit dnh cho

b chia t l xung
c m t trong bng 2.5
Bit 6 Bit la chn ch

Bit 7 Bit cho php
0 : Ch nh thi t do
1 : Ch nh thi tun hon
0 : Khng cho php b nh thi hot ng
1 : Cho php b nh thi hot ng
- Ch cc bit ca b chia t l xung trong thanh ghi iu khin c m t trong

bng 2.5.
- 29 Bng 2.5: Ch cc bit ca b chia t l xung trong thanh ghi iu khin.

Bit 3
Bit 2
Xung c chia
Cc bc ca b chia t l xung
16
1
1
256
1024
10
- Bn nh b nh thi:
a ch c s ca b nh thi khng c nh v c th khc i vi mi h thng
x l c th. Tuy nhin, khong cch ca cc thanh ghi t a ch c s c c nh
nh trong bng 2.6.
Bng 2.6: Bn a ch b nh thi.
2.2.4 Giao tip vi b iu khin tm dng v Reset

Gii thiu chung
B iu khin tm dng v Reset l s kt hp ca bn chc nng ring bit:
chc nng tm dng, chc nng xc nhn, cc trng thi Reset v bn b nh
Reset [8]. Hnh 2.10 m t giao tip li x l ARM vi b iu khin tm dng v
Reset, b iu khin ngt v b nh thi. tng thit k cc thit b ngoi vi ny l
lm tng s ng nht trong h thng ARM v lm tng mc linh ng ca phn mm
gia cc h thng.
- Chc nng iu khin tm dng:
iu khin tm dng l h thng x l trong trng thi cng sut thp nh
l trng thi i trong lc ngt (h thng khng yu cu b x l hot ng).
- 30 V tr xc nh tm dng l ch ghi. Khi ghi vo v tr tm dng, h thng s i

vo trng thi ch. Thng thng n s ngn chn b x l tm np lnh thm cho n
khi nhn c mt ngt.
Hnh 2.10: Giao tip li ARM vi b iu khin tm dng v Reset.
- Chc nng xc nhn:

Thanh ghi xc nhn cho bit cu hnh h thng. Thanh ghi xc nhn l ch
c. Ch duy nht mt bit c ci t cho thanh ghi xc nhn, bit 0 dng cho bit
thm thng tin.
Bit 0 l bit xc nhn vi trng thi thit lp:
0 khng c thng tin.
1 xc nhn thm thng tin.
Nu bit di cng ca thanh ghi xc nhn c thit lp, cc bit c yu cu
thm sau s cung cp chi tit hn v thng tin h thng.
- Chc nng Reset:
Thanh ghi Reset l ch c. Ch c mt bit ca thanh ghi ny c nh ngha,
l bit Reset ngun. Bit Reset ngun l bit 0 trong thanh ghi Reset v cc gi tr ca n
c biu bin nh sau:
0 khng Reset ngun.
1 Reset ngun.
Ngoi ra cc bit trong thanh ghi Reset c th cung cp chi tit hn v thng tin
trng thi Reset.
Thanh ghi Reset c c ch kp dnh cho cc bit ci t v xa, cc bit ny hon
ton c lp v khi thay i s khng nhn cc bit khc trong thanh ghi.
- 31 V tr xa trng thi Reset l ch ghi. V tr ny dng xa cc c trng thi

Reset. Khi ghi vo mi mt bit d liu vo thanh ghi ny mc cao s thit lp bit
tng ng trong thanh ghi Reset l xa. Khi ghi vo mi mt bit d liu vo thanh ghi
ny mc thp s khng gy nh hng n bit tng ng trong thanh ghi Reset.
V tr Reset khng c bin trong c tnh tham chiu cc thit b ngoi ti thiu,
v bit Reset trng thi ngun khng th thit lp c bng phn mm. Thanh ghi ny
c ci t sn trong c tnh k thut m bo kh nng ca chc nng Reset.
- Xa bn nh ca b iu khin Reset:
V tr xa bn Reset l ch ghi.
Khi bn b nh Reset xa v bn nh thng thng c dng, h
thng s khng quay tr li dng bn b nh Reset, ngoi tr phi tri qua iu
kin thit lp li.
trng thi Reset, h thng x l s nh x ROM n v tr 0, v khi qu trnh
hot ng thng thng tr li, RAM s v tr 0.
- Bn nh b iu khin tm dng v Reset c m t trong bng 2.7.
Bng 2.7: Bn nh b iu khin tm dng v Reset.
a ch c s ca b iu khin tm dng v Reset l khng c nh v c th

khc nhau i vi mi h thng x l c th. Tuy nhin, khong cch ca cc thanh
ghi t a ch c s c c nh.
2.2.5 Giao tip vi khi GIPO
Khi GIPO (General Purpose Input/Output) l khi iu khin 8 bit u vo hoc
ra a mc ch [9], uc kt hp cht ch vi b logic c kh nng lp trnh (PLD). B
PLD giao tip qua cc bus m rng vi GPIO.
- Cc bit trong GPIO:
Cc bit t 0 3 l cc bit u ra ch c.
Cc bit t 4 7 l cc bit c lp trnh c lp nh l mt u vo hoc l mt
u ra. Cc bit trong thanh ghi d liu c thit lp v xo c dng bi cc thanh
- 32 ghi GPIO_DATASET v GIPO_DATACLR. Cc bit c v ghi c dng bi thanh

ghi GPIO_DATAIN v GPIO_DATAOUT.
- Cc thanh ghi GPIO:
GPIO cung cp cc tn hiu u ra v u vo a mc ch. Mi mt ng
GPIO u c in tr ko 10K bn trong ln 3,3V. Cc thanh ghi GPIO c ch r
trong bng 2.8.
Bng 2.8: Bng tng qut cc thanh ghi GPIO.
Tn thanh ghi
Trng thi
di (bit)
Chc nng
GPIO_DATASET
Ghi
Thit lp u ra d liu
GPIO_DATAIN
c cc chn u vo d liu
GPIO_DATACLR
Ghi
Xa u ra thanh ghi d liu
GPIO_DATAOUT
GPIO_DIRN
c
c/Ghi
8
8
c cc chn u ra d liu
iu khin hng d liu vo/ra
- Thanh ghi thit lp u ra d liu:

V tr GPIO_DATASET c dng thit lp u ra cc bit nh sau:
1 = thit lp bit u ra GPIO.
0 = ngt lin kt bit u ra GPIO.
- Thanh ghi c u vo d liu:
Dng c trng thi hin hnh ca cc chn GPIO t v tr GPIO_DATASET.
- Thanh ghi xa u ra d liu:
V tr GPIO_DATACLR c dng xa cc bit u ra GPIO c lp nh sau:
1 = xa bit u ra GPIO.
0 = khng tc ng n bit u ra GPIO.
- Cc chn c u ra d liu:
Dng c trng thi hin hnh ca cc bit thanh ghi u ra GPIO t v tr
GPIO_DATACLR.
- iu khin hng d liu:
Thanh ghi GPIO_DIRN c dng thit lp hng cho mi chn GPIO
nh sau:
1 = chn l u ra.
0 = chn l u vo (mc nh).
iu khin hng d liu cho mt bit GPIO c m t trong hnh 2.11.
- 33 -
Hnh 2.11: iu khin hng d liu GPIO (1 bit).
2.2.6 Giao tip vi khi truyn/thu khng ng b a nng (UART)

Giao tip UART l giao tip ni tip, c cc tnh nng sau:
- Cp tn hiu cho cc u vo b iu khin;
- iu khin u ra tn hiu;
- Thit lp tc baud;
- Truyn v nhn 16 byte FIFO;
- a ra cc ngt.
Chc nng UART
UART trn vi iu khin ARM h tr c hai kiu giao tip l giao tip song cng
v giao tip bn song cng. Giao tip song cng tc l c th gi v nhn d liu vo
cng mt thi im. Cn giao tip bn song cng l ch c mt thit b c th truyn
d liu vo mt thi im, vi tn hiu iu khin hoc m s quyt nh bn no c
th truyn d liu. Giao tip bn song cng c thc hin khi m c hai chiu chia s
mt ng dn hoc nu c hai ng nhng c hai thit b ch giao tip qua mt
ng cng mt thi im.
D liu truyn c ghi vo thnh 16 byte FIFO (b m vo trc ra trc) v
bt u qu trnh truyn cc khung d liu vi cc tham s c xc nh trong thanh
ghi iu khin UART. Truyn s kt thc khi d liu trong FIFO l trng.
Trong qu trnh thu, UART bt u ly mu sau khi nhn mt bit khi ng
(u vo mc thp). Khi mt word (16 bit) c nhn , n s c cha trong
FIFO nhn.
C th khng dng cc ch FIFO. Trong trng hp ny, UART cung cp cc
thanh ghi gi mt byte cho vic truyn v nhn cc knh. Mt bit trn trong
UART_RSR lm mt ngt c thit lp trong trng hp mt byte nhn trc mt
byte c c.
C th khng s dng tnh nng ca FIFO nhng nu xy ra li trn, d liu d
vn c cha trong FIFO v phi c ra xa FIFO.
Thit lp tc baud ca UART c lp trnh bi cc thanh ghi chia tc bit
UART_LCRM v UART_LCRL.
- 34 Cc ngt UART
Mi UART to ra bn ngt:
- B ngt trng thi: dng xc nhn khi c bt k s thay i trng thi no. B
ngt ny c xa bng cch ghi vo thanh ghi UART_ICR.
- Ngt loi b UART: dng xc nhn khi UART c loi b v bit khi ng
(mc thp) c pht hin trn ng thu. Trng thi ny s c xa nu UART
c kch hot hoc ng thu mc cao.
- Ngt Rx (ngt thu d liu): dng xc nhn khi mt trong cc trng hp sau
xy ra:
B FIFO thu c kch hot v b FIFO cha na hoc qu na (8 byte
hoc nhiu hn 8 byte).
B FIFO thu khng cn trng v khng c d liu cho hn chu k 32 bit.
B FIFO thu b v hiu v d liu c thu.
Ngt Rx c xa bng vic c ni dung ca FIFO.
- Ngt Tx (ngt truyn d liu): dng xc nhn khi mt trong cc trng hp sau
xy ra:
B FIFO truyn c kch hot v b FIFO cha mt na hoc t hn mt na.
B FIFO truyn b v hiu ha v vng m lu tr l trng.
Ngt Tx s c xa khi chn vo b FIFO hn qu na hoc ghi vo thanh
ghi lu tr.
Dng khung truyn
Khung truyn trong giao tip UART gm bn thnh phn, nh trong hnh 2.12.
Start bit
Data
Parity
Stop bits
Hnh 2.12: Khung truyn trong giao tip UART.
- Start bit (1 bit mc logic 0): bt u mt gi tin, ng b xung nhp clock;

- Data (c th l 5,6,7 hoc 8 bit): d liu cn truyn;
- Parity bit (1 bit: chn (even), l (odd), mark, space): bit cho php kim tra li;
- Stop bit (1 hoc 2 bit): kt thc mt gi tin.
Tc truyn
- Tnh bng n v bit/giy: bps (bit per second) hay cn gi l tc baud.
- L s bit truyn trong mt giy.
- Tc ti a =Tn s xung nhp clock/hng s.
- 35 VD: tn s thch anh ngoi cho vi iu khin l 18.432MHz, hng s =16

-> tc truyn l: 115.200 bps.
Bn trong UART h tr cc thanh ghi cho php xc nh cc tc lm
vic khc, vd: 1.200, 2.400, 4.800, 9.600, 19.200, 38.400 bps, c th
thit lp tc baud bng phn mm.
2.2.7 Giao tip ngoi vi ni tip (SPI)
Chc nng SPI
Trong vi iu khin ARM, khi SPI (Serial Peripheral Interface) c tch hp
sn bn trong v nm trn bus truyn d liu ngoi vi ti u tng hiu sut truyn d
liu v ti u kh nng tiu th cng sut.
- SPI s dng phng thc truyn: Ni tip ng b Song cng.
Ni tip: truyn mt bit d liu trn mi nhp truyn;
ng b: c xung nhp ng b qu trnh truyn;
Song cng: cho php gi, nhn ng thi.
- SPI l giao thc Master Slave
Thit b ng vai tr Master iu khin xung ng b (SCK);
Tt c cc thit b slave b iu khin bi xung ng b pht ra bi Master.
SPI l giao thc trao i d liu (Data Exchange): mt bit c gi ra s c
mt bit khc c nhn v, c m t nh trong hnh 2.13.
Hnh 2.13: Giao thc Master Slave trong giao tip SPI.
Cc cu hnh ghp ni c bn trong giao tip SPI

- Cu hnh ghp ni mt thit b c m t trong hnh 2.14
Hnh 2.14: Ghp ni mt thit b.
- 36 - Cu hnh ghp ni nhiu thit b c m t trong hnh 2.15 (1 Master n Slave):
Hnh 2.15: Ghp ni nhiu thit b.
- M t cc chn trong giao tip SPI:

MISO (Master Input Slave Output);
MOSI (Master Output Slave Input);
SCK: xung ng b;
SS (Slave select): chn chn thit b ( mt thit b slave c th lm vic,
chn SS phi gi mc thp).
- Cc thit b s dng giao tip SPI rt a dng, bao gm: th nh SD/MMC, b nh,
cm bin nh, ADC, LCD,
2.2.8 Giao tip USB
Trong vi iu khin ARM, khi giao tip chun USB c tch hp sn bn trong
v nm trn bus truyn d liu ngoi vi ti u tng hiu sut truyn d liu v ti u
kh nng tiu th cng sut. Trong khi giao tip USB c mt b x l truyn v nhn
d liu v mt b m FIFO. D liu truyn trn USB theo giao thc c nh
ngha sn.
Giao tip USB l mt chun truyn d liu ni tip a nng [10] vi cc thit b
ngoi vi. S truyn tn hiu theo chun giao tip USB c m t trong hnh 2.16.
Hnh 2.16: S truyn tn hiu theo chun giao tip USB.
- 37 Qu trnh trao i d liu

Cc thit b USB c th trao i d liu vi my ch theo bn kiu hon ton
khc nhau, c th:
- Truyn iu khin (control transfer);
- Truyn ngt (interrupt transfer);
- Truyn theo khi (bulk transfer);
- Truyn ng thi (isochronous transfer).
Truyn iu khin: iu khin phn cng, cc yu cu iu khin c truyn.
Kiu truyn ny lm vic vi mc u tin cao v vi kh nng kim sot li t
ng. Tc truyn ln v c n 64 byte trong mt yu cu c th c truyn.
Truyn ngt: cc thit b, cung cp mt lng d liu nh, tun hon. H thng
s hi theo chu k, chng hn 10 ms mt ln xem c cc d liu mi gi n.
Truyn theo khi: khi c lng d liu ln cn truyn v cn kim sot li
truyn nhng li khng c yu cu v thi gian truyn th d liu thng c truyn
theo khi.
Truyn ng thi: khi c khi lng d liu ln vi tc d liu c quy
nh. Theo cch truyn ny mt gi tr tc xc nh c duy tr. Vic hiu chnh
li khng c thc hin v nhng li truyn nh khng gy nh hng ng k.
u im giao tip USB
- D s dng:
Mt giao tip dng chung cho nhiu thit b ngoi vi khc nhau;
T ng cu hnh;
D dng u ni;
H tr kh nng cm nng (Hot pluggable);
Thng khng cn s dng ngun ngoi.
- Tc cao v tin cy, h tr nhiu tc khc nhau:
Tc cao nht: 480 Mbps;
Tc cao
: 12 Mbps;
Tc thp : 1,5 Mbps.

- Tit kim in.
- Li ch cho ngi dng pht trin (thit k phn cng, lp trnh nhng, lp trnh ng
dng).
- Linh hot:
Chun giao tip USB h tr bn kiu truyn v ba tc khc nhau -> c th
ph hp cho nhiu loi thit b ngoi vi;
- 38 C th h tr truyn cc gi d liu c rng buc hoc khng rng buc v

thi gian lm tng tnh thi gian thc
H tr giao thc giao tip vi cc thit b chun nh my in, bn phm,
a, u c th,
- c h tr bi h iu hnh:
Cc h iu hnh ph bin u h tr chun USB: Windows, Linux,
Macintosh;
Pht hin khi thit b c cm vo hay rt ra khi h thng;
Giao tip vi thit b c cm vo tm ra cch trao i d liu;
H tr cc giao din hm chun (API Application Programming Interface)
cho php lp trnh giao tip vi thit b;
c h tr bi nhiu nh sn xut;
Cc chip chuyn dng h tr giao tip theo chun USB kh ph bin;
Gii hn v khong cch: gii hn chiu di ng truyn khng qu 5m;
C th tng khong cch bng cc mch chuyn i (USB <-> RS485,
wifi,).
2.2.9 Kin trc bus truyn d liu cao cp ca vi iu khin ARM
Gii thiu chung
ARM giao tip vi cc khi ngoi vi bi h thng bus truyn d liu cao cp
AMBA (Advanced Microcontroller Bus Architecture) [11], [12].
c im ca AMBA l chun truyn thng trn chip dnh cho thit k cc vi
iu khin 16 v 32 bit vi hiu sut cao, cc b x l tn hiu v cc thit b ngoi vi
phc tp.
AMBA l mt c tnh dnh cho cc bus trn chip, cho php cc khi lnh (nh
iu khin b nh, CPU, DSP v cc thit b ngoi vi) c kt ni vi nhau thnh
mt vi iu khin hay thnh chip ngoi vi phc tp.
- AMBA c thit k vo:
Cc b vi iu khin PDA, vi s lng ln cc thit b ngoi vi c tch hp
v kh nng tiu th in rt thp.
Cc b vi iu khin a phng tin nh cc b iu khin hnh nh c b nh
dung lng ln.
Cc thit b ASIC phc tp cho cc sn phm chuyn dng.
Tch hp iu khin v cc chc nng x l tn hiu cc thit b truyn thng
di ng s.
- Chnh sch ca ARM l c th h tr s dng AMBA pht trin cc bo mch v
cc cng c khc.
- 39 - Mc tiu ca AMBA:
D dng pht trin cc mch nhng vi iu khin vi mt hay nhiu b x l
v nhiu thit b ngoi vi.
Gim thiu c tng chi ph trong sn xut th nghim chip.
AMBA h tr thit k cc khi, cu trc v cc b x l c lp, h tr pht
trin th vin cc thit b ngoi vi v sn sng cung cp b nh truy cp
nhanh, cc li CPU cao cp.
- t c nh vy, kin trc AMBA c nhng tnh nng chnh sau:
Tnh n th cao.
H tr a dch v.
Ngun tiu th thp.
Phng php kim th cao cp.
- AMBA l mt h m, bt k ai cng c th sao chp cc c tnh k thut t ARM
v dng giao thc ca AMBA thit k chip. Khng c s lin i n bn quyn
hay tin bn quyn. Cc hi vin ARM c th cung cp v h tr v h thng
AMBA.
- c tnh k thut AMBA:
Bus bng thng rng, tc cao.
Bus ngoi vi c cng sut thp, cu trc n gin.
Cho php truy cp kim th cc khi nhanh.
Cc hot ng qun l hiu qu (Reset hoc bt ngun, qu trnh khi to v
ch ngh).
- Kin trc AMBA in hnh c m t trong hnh 2.17.
Hnh 2.17: Vi iu khin da trn kin trc AMBA in hnh.
- 40 - Bus h thng hiu sut cao (ASB - Advanced System Bus):

Bus ny l xng sng ca h thng chnh, m bo tc d liu gia h
thng vi cc giao tip bus bn ngoi. B x l trung tm (CPU), cc bus
truyn chnh khc (nh b iu khin truy cp b nh trc tip DMA), b
nh trong cng c kt ni vi bus truyn tc cao ny.
ASB c kt ni vi APB bi cu ni.
- Bus truyn d liu ngoi vi ti u (APB - Advanced Peripheral Bus):
Bus truyn ngoi vi ny c cng sut thp, tc thp v n gin. y l cc
thit k thng thy trong ARM, cc bus y hp hn v n gin hn dnh cho kt
ni cc thit b ngoi vi chung nh l cc b nh thi, cc cng vo ra song song, b
thu/pht khng ng b a nng, bng cch t cc thit b ngoi vi truy cp trn
APB v phn vng chng i t ASB, lm gim bt lng ti trn ASB v t c
hiu sut ti a trn ASB.
- Truy cp ngoi:
Truy cp ngoi c s dng cho vic truy cp kim th. Trng hp thng
thng l giao tip vi b nh ngoi nhng c th ci t bt k chn ra no cho vic
kim th. Kim th vin c th kim sot cc bus v kim tra cc thnh phn mt cch
c lp hay ln lt. Phng php truy xut song song cho php kim th nhanh c
bit l i vi cc vng nh m CPU.
- Vi iu khin da trn AMBA cha b qun l thng tin ngun v trng thi Reset
m bo:
Trnh iu khin duy nht khi cp ngun.
Cc ch tit kim in hay ch ng.
C ch khi ng li cho cc trng thi bnh thng, nng hoc ch.
- Bus h thng hiu sut cao (ASB) c thit k s dng vi hiu nng cao v bng
thng ln vi nhng c tnh:
Bus a ch v bus truyn d liu ring bit;
H tr kin trc ng ng;
H tr cc bus d liu chnh;
H tr cc thit b ghp ni ph, bao gm c cu ni n bus truyn d liu
ngoi vi ti u (APB);
B phn x v b gii m trung tm.
Tc truyn ty thuc vo c im thit k v mc ch s dng. Cu hnh
tc truyn ny khng b gii hn bi ch tiu k thut.
- Bus truyn d liu ngoi vi ti u (APB) c thit k lm bus con cho bus truyn
chnh ASB v c kt ni bng cu ni (cu ni ny gii hn ti ASB).
- 41 - Mc tiu APB l bus truyn d liu n gin, s dng in p thp vi nhng c tnh:
Truy cp d liu c iu khin ch bi s la chn v cho qua, khng cn
xung nhp.
Cng sut tiu hao gn nh bng khng khi bus truyn ny khng s dng.
Giao tip ng truyn n gin.
Tc truyn d liu ph thuc vo tc ca cc thit b ngoi vi.
Cu hnh tc truyn khng b gii hn bi ch tiu k thut, c th thay i
theo thit k ngi dng.
Cc bus d liu ca APB c th c ti u ha tng thch vi cc thit b
ngoi vi kt ni. Rt nhiu cc thit b ngoi vi c yu cu ng truyn d liu hp,
v mt c ch kt ni thit b ngoi vi 32 bit trc cu ni, tip theo sau cu ni l c
ch kt ni vi cc thit b ngoi vi 8 bit, gim vng khng cn s dng trong bus
truyn d liu, ti u ha bus truyn d liu.
Mc d xung nhp khng c thit lp trong AMBA, phn vng cung cp bi
cu ni v APB ti gin c vic tiu hao cng sut. Rt nhiu cc thit b ngoi
vi nh cc b nh thi, b to tc Baud (BRG), b iu ch rng xung (PWM)
yu cu chia xung nhp h thng, v cc v tr c th lp trnh, c phn chia bn
cnh cu ni rt tin li v to ra ch ngun hiu qu.
Khng c bus truyn d liu chnh trong APB (ngoi tr cu ni). Tt c cc
thit b ngoi vi hot ng nh l cc h th ng.
c tnh gia ASB v APB
- ASB c dng cho cc b iu khin CPU, DSP, DMA v cc bus truyn d liu
chnh khc, hay cc thit b ngoi vi c hiu sut cao.
- APB c dng cho ng truyn dn ph, nh a ch thanh ghi cc thit b ngoi
vi, c bit l khi s lng cc thit b ngoi vi ln m ngun tiu th yu cu thp.
- ASB v APB s dng cng h phng php kim th trong AMBA.
B iu khin giao tip kim th
B iu khin giao tip kim th l mt bus truyn d liu ASB chnh, c
dng giao tip vi bus truyn d liu bn ngoi (hoc vi cc chn tng thch
khc) truy cp kim th ca thit b bn ngoi, c m t trong hnh 2.18.
C ch ny cho php truy cp cng kim th m mt mc thp cng logic,
c th kim th nhanh bng cch truy cp song song. Phng php kim th cho
php dng li cc kt qu kim th trung gian, lu li gi tr ti thi im th. Chng
hn nh khi mt khi thit b ngoi vi c dng tr li, khi trung gian kim th
(khi c kim th vn tn ti) c th c s dng li, v tip tc kim th
mc cao hn ca chng trnh.
- 42 -
Hnh 2.18: B iu khin giao tip kim th s dng theo dng khi.
B iu khin giao tip kim th c kh nng kim tra hot ng ca cc thit b

ngoi vi, b phn x c nhim v phn chia tc bus cho ph hp tc truyn ca
tng thit b ngoi vi.
u im
AMBA c s dng trn cc sn phm ARM v chng t c cc tnh
nng hiu dng. Hin nay kin trc bus truyn d liu AMBA c s dng nhiu trn
cc b vi iu khin tch hp cao cp khc bi p ng c cc vn :
- Kin trc chip c phn vng tc , tit kim in nng.
- Qun l d n tin ch bi vic s dng khi kim th, do gim bt thi
gian nghin cu pht trin sn phm.
- Sn phm c nhiu tnh nng cao cp, b vi x l c lp, hin i v c tnh
cnh tranh.
- ARM lun sn sng h tr cc cng c v mi trng pht trin h thng bus
truyn d liu AMBA.
2.3 Kt lun
Chng 2 trnh by tng quan giao tip c bn trong vi iu khin ARM, trn c
s , ty theo ng dng vi iu khin ARM c b xung thm cc tnh nng cao cp
- 43 hn (c trnh by trong chng 3). Cc giao tip trn vi iu khin ARM lun c
kh nng tng tc tt vi cc thit b ngoi vi trn h thng bus truyn d liu c tc
x l cao, nhng tiu th nng lng thp.
Cc giao tip vi vi iu khin ARM u c hng h tr, nh ngha thnh cc
module v c ti u t khi thit k theo kiu cu trc trong lp trnh C, rt thun li
cho ngi lp trnh tip cn v pht trin ng dng. Chnh v vy, vi iu khin ARM
c phm vi ng dng rng ri, lun c sn cc cng c h tr giao tip cho c phn
cng v phn mm.
---------------------------------
- 44 CHNG 3
C IM CC DNG LI X L ARM
3.1 Phn loi v tnh nng cc dng li x l ARM
Phn loi cc dng li x l ARM
Cc dng li x l ARM cho n nay c bn kin trc [13], bao gm: kin trc
v4T, kin trc v5, kin trc v6 v kin trc v7.
Kin trc ARMv4T l kin trc c bn, cc kin trc ARM sau bao gm v5, v6,
v7 u k tha t kin trc ARMv4T. Hnh 3.1 m t s hnh thnh v pht trin cc
kin trc li x l ARM t kin trc ARMv4 n ARMv7.
Hnh 3.1: Cc kin trc li x l ARM.
- 45 Tnh nng cc dng li x l ARM

Tnh nng cc dng li x l ARM c m t trong hnh 3.2.
Hnh 3.2: Tnh nng cc dng li x l ARM.
Trong :
ARM 32-Bit ISA (Instruction Set Architecture): cu trc tp lnh ARM 32 bit.
Thumb 16-Bit ISA: cu trc tp lnh Thumb 16 bit c thit lp bng cch phn
tch tp lnh ARM 32 bit v chuyn ha tt nht ph hp vi tp lnh 16 bit, lm gim
kch thc m.
Thumb: c tnh Thumb ci thin mt bin dch m, b x l thc hin tp
lnh 16 bit. ch ny c mt s ton hng i km s n i v gii hn mt s kh
nng so vi ch tp lnh ARM y . Trong Thumb, cc m s nh hn v t chc
nng cho ci thin mt m tng th. Trong trng hp b nh hoc bus truyn d
liu b hn ch di 32 bit, m Thumb cho php tng hiu sut thnh m ARM 32 bit
tng kh nng x l trn bng thng ln hn.
Thumb-2: c a ra b sung cho cc gii hn tp lnh 16 bit Thumb vi
vic cung cp thm tp lnh 32 bit m rng. Mc tiu ca Thumb-2 l t c mt
m nh Thumb vi hiu sut tng ng nh tp lnh ARM 32 bit.
- 46 Thumb-2 Mixed ISA: kt hp tp lnh 16 bit v 32 bit m c th khng cn

ch chuyn mch. Kt hp tp lnh 16 bit v 32 bit ngay ti thi im ang thc
hin lnh v ch trong mt lnh n (khng gy gim hiu sut thc thi).
VFPv2 (Vector Floating Point): l b thc hin php tnh du chm ng ca
kin trc ARM. VFPv2 c 16 thanh ghi, hot ng vi mt chu k n, kh nng tnh
ton v x l rt nhanh, tr thp, c chnh xc cao.
VFPv3 l phin bn nng cp ca VFPv2, VFPv3 c chnh xc cao hn vi 32
thanh ghi v mt s tp lnh c m rng.
NVIC (Nested Vectored Interrupt Controller): B iu khin vector ngt lng
nhau c kh nng x l ngt rt linh hot v nhanh chng v cho php rt ngn thi
gian tr hon p ng ngt (h thng p ng ngt nhanh hn) vi nhiu mc u tin
khc nhau.
Jazella: l cng ngh h tr trnh thng dch m Java, cho php li ARM thc
thi trc tip m Java trong cu trc phn cng nh l trng thi thc thi th ba cng
vi cc ch ARM v Thumb hin hnh, lm tng tc kh nng thc thi.
WIC (Wake-up Interrupt Controller): B iu khin nh thc khi c ngt, gip
cho cc hot ng tiu tn t nng lng hn.
TrustZone: Khi tng tnh bo mt, m bo cc on m c hi khng lm nh
hng n h thng.
SIMD (Single Instruction Multiple Data): Khi tp lnh n a d liu, khi ny
cho php tp lnh hot ng ti cng thi im trn cc mc d liu khc nhau, lm
tng kh nng x l d liu v c bit hiu qu i vi cc d liu dng m thanh v
hnh nh.
NEON: Cng ngh NEON mc ch l tng hiu sut x l cho cc nh dng a
phng tin, cng ngh ny c pht trin m rng t cng ngh SIMD, c kh nng
lm tng cc thut ton x l tn hiu nh l m ha v gii m cc nh dng m
thanh, hnh nh; ha hai chiu, ba chiu; tr chi; tng hp x l ging ni, hnh
nh trong thoi vi hiu sut x l cao.
3.2 c im cc dng li x l ARM
3.2.1 c im ca kin trc dng li x l ARM v4T
Kin trc v4T c ARM gii thiu nm 1994, bao gm cc li x l bao gm:
ARM7TDMI, ARM720T, ARM920T.
Kin trc v4T h tr tp lnh Thumb (vit tt l T trong cc k hiu ca b x
l). H tr cng lc tp lnh Thumb 16 bit v ARM 32 bit. Vi tp lnh Thumb 16 bit
cho php trnh bin dch to ra chng trnh nh hn m vn tng thch vi h thng
- 47 32 bit. in hnh kin trc ny l li ARM7TDMI c thit k nhm p ng cc

ng dng yu cu hiu sut cao, tiu th nng lng thp v nh gn.
ngha cc k hiu trn ARM7TDMI:
- T l h tr tp lnh Thumb 16 bit;
- D l Debug - hiu chnh li;
- M c ngha l Long Multiply Support - h tr php ton 64 bit;
- I l Interface, h tr giao tip ngoi vi.
ARM7TDMI h tr gii m li bng khi Embedded Trace Macrocell (ETM)
y l gii php gii m li hon chnh dnh cho li ARM, ngoi ra ARM7TDMI c
kh nng kt hp vi cc li khc nhm tng cng kh nng x l.
ARM7TDMI c kin trc ng ng ba tng, l kin trc Von Neumann, b x
l s hc 32 bit. H thng tp lnh 16 v 32 bit c kh nng m rng thng qua giao
din ng x l vi li ngoi.
phin bn m rng ARM720T, b nh m v h thng qun l b nh (MMU
Memory Management Unit) c tch hp. Tip phin bn ARM9TDMI s dng
kin trc ng ng nm tng v kin trc Harvard.
3.2.2 c im kin trc dng li x l ARM v5
Kin trc v5 v cc phin bn m rng v5T, v5TE, v5TEJ c ARM gii thiu
nm 1999, bao gm cc li x l:
ARM1020E/1022E v5T;
ARM946E-S/ARM966E-S/ARM968E-S v5TE;
ARM7EJ-S/ARM92EJ-S/ ARM1026EJ-S v5TEJ.
c tnh k thut chung ca dng ARMv5 c m t trong bng 3.1:
Bng 3.1: c im k thut chung ca dng ARMv5.
B x l
Li x l dng RISC 32 bit
I/O
nh x b nh (Memory map I/O)
Dung lng khng gian b nh
4GBytes
Tp lnh
16 bit, 32 bit
C by ch : User, Supervisor, Abort, Undefined,
System, IRQ, FIQ
Ch hot ng
Cu trc tp lnh
Ngt
H tr tp lnh ARM 32 bit v Thumb 16 bit m rng

IRQ (Interrupt Request) v FIQ (Fast Interrupt)
Phin bn v5T: b lnh Thumb c ci tin, h tr CLZ (Count Leading

Zero), CLZ l tp lnh h tr cho php xc nh mt bin m gim v 0 ch trong
mt chu k lnh, gip gim thi gian trong cc lnh cng, tr, nhn, chia cc s nh
- 48 phn; gip tng tc trong x l tn hiu s so vi cng ngh thc hin php tnh
du chm ng.
Phin bn v5TE: h tr khi x l tn hiu s DSP (Digital Signal Processing).
Vi khi DSP ny, nng lc x l tnh ton s c tng ln 70%.
Phin bn v5TE-J: khi Jazelle c thm vo nhm h tr trnh thng dch m
Java v b thc thi m Java. Thi gian thc thi m Java c tng ln tm ln v gim
c hn 80% nng lng tiu th so vi li x l khng h tr khi Jazelle. Tnh
nng ny cho php lp trnh vin thc thi m Java mt cch c lp vi h iu hnh.
Kin trc v5 c s dng nhiu dng ARM10, c bit l phin bn v5TE-J.
Mc d khng c nhiu thay i v kin trc, tuy nhin phin bn kin trc v5 c s
dng rt nhiu bi vi x l tch hp h thng nn to c s linh hot vi nhiu tnh
nng cao cp.
3.2.3 c im kin trc dng li x l ARM v6
Kin trc v6 v cc phin bn m rng v6T2, v6Z v v6K c ARM gii thiu
nm 2002, bao gm cc li x l: ARM1136J(F)-S, ARM1156T2(F)-S(v6T2),
ARM1176JZ(F)-S(v6Z), MPCore(v6K).
C nhiu b sung kin trc v6 theo hng to ra nhng h thng nhng cao cp
v phc tp hn nhng vn gi c u im v kh nng tiu th in nng thp. Vi
mi phin bn s c nhng tnh nng c bit c thm vo. K tha cc c im
ni tri ca kin trc v4 v v5, kin trc v6 cc khi TEJ c tch hp vo li
ARM. m bo kh nng tng thch ngc phn b nh v x l ngoi l c k
tha t kin trc v5.
V kin trc v6, c nm im chnh c ci tin:
- Qun l b nh: b nh cache v khi qun l b nh (MMU- Memory
Management Unit) c ci tin lm tng hiu sut thc thi ca h thng ln
30% so vi kin trc c.
- a li x l (Multiprocessor): p ng cc h thng m yu cu kh nng
tc x l nhanh nh: phng tin gii tr c nhn, x l s Cc li x l
chia s v ng b d liu vi nhau thng qua vng nh chung.
- H tr x l a phng tin: tch hp b tp lnh SIMD (Single Instruction
Multiple Data) lm tng kh nng x l d liu dng m thanh v hnh nh.
SIMD cng cho php cc nh pht trin ci t cc ng dng phc tp hn
nh: gii m d liu m thanh v hnh nh, cc bi ton nhn dng, hin th
hnh nh 3D hoc h tr thit b s dng cng ngh khng dy.
- Kiu d liu: l cch h thng s dng v lu tr d liu trong b nh. Cc h
thng SoC (System on Chip), cc chip vi x l n, h iu hnh v cc giao
- 49 din ngoi vi nh USB hoc PCI thng hot ng da trn kiu d liu little
endian. Mt s cc giao thc nh TCP/IP hay MPEG hot ng da trn kiu
d liu big endian. c th ti u ha kh nng tch hp ca h thng,
ARMv6 h tr cng lc c hai nh dng little v big endian, gi tt l
mixed-endian. Bn cnh , ARMv6 cn cung cp tp lnh x l d liu
dng unalignment - c kch thc d liu thay i. Tng t nh ARMv5,
ARMv6 cng l kin trc 32 bit, nn h tr ng truyn d liu 64 bit hoc
cao hn.
- X l ngoi l v ngt: thch ng cho cc h thng x l thi gian thc.
Nhm tng cng tnh an ton khi thc thi m chng trnh, khi TrustZone
c tch hp phin bn v6Z. Vn thc thi m an ton xut pht t thc t ngy
cng nhiu thit b di ng da trn nn tng ca ARM, nhiu chng trnh c ti t
trn mng do tnh an ton ca cc on m nhiu khi cha c kim chng.
TrustZone m bo cc on m c hi khng lm nh hng n h thng.
Dng ARM11 l i din ph bin nht ca kin trc ARMv6. Vi kin trc
ng ng tm tng ( ARM1156T p dng kin trc ng ng chn tng), h thng
d on r nhnh (Branch Prediction) v kt qu tr v (Return Stack) gip ARM11
nng cao hiu sut thc thi lnh.
Tp lnh Thumb-2 cng c gii thiu h tr cc lnh Thumb 16 bit v 32 bit.
phin bn ARM1176JZ(F)-S b sung khi IEM (Intelligent Energy Management)
qun l mc tiu th nng lng tt hn.
3.2.4 Kin trc dng li x l ARM v7
Kin trc v7 v cc phin bn m rng v7-A, v7-R v v7-M c ARM gii
thiu vo nm 2005, c trng bao gm cc li x l: Cortex-A8 (v7-A), Cortex-R4
(v7-R), Cortex-M3 (v7-M).
Kin trc v7 c chia thnh ba dng chnh da trn c th ca ng dng
thc tin:
- Dng A (vit tt ca Application), li ARM dng ny h tr cho cc ng dng
i hi tnh phc tp, mc tng tc ngi dng cao nh: thit b cm tay
di ng, my tnh, cng ngh khng dy
- Dng R (vit tt ca Realtime), li ARM dng ny h tr cho cc ng dng
cn tnh ton x l thi gian thc.
- Dng M (vit tt ca Microcontroller), li ARM dng ny dnh cho cc ng
dng cng nghip v in t tiu dng.
ARM Cortex l mt phin bn khc vi cc phin bn ARM thng hay c k
hiu bi ARMXX. ARM Cortex khng c tc hot ng hay h thng ngoi vi nht
- 50 nh m ty thuc vo nh sn xut phn cng s thit k h thng ngoi vi khc nhau.

Tuy nhin tt c u dng chung li ARM Cortex v vic lp trnh v truy cp phn
cng tun theo chun CMSIS (The Cortex Microcontroller Software Interface
Standard: Chun giao tip phn mm vi iu khin Cortex).
3.3 Kt lun
Chng 3 trnh by cc tnh nng v kin trc cc loi li x l trong cc dng vi
iu khin ARM. T kin trc li x l ARMv4 n kin trc li x l ARMv7, mi
mt kin trc u c nhng tnh nng x l c trng, phin bn sau c s b sung
thm cc tnh nng c bit, nhng c tnh k tha ca cc phin bn trc. phin
bn ARMv7, hng ARM pht trin chun giao tip phn mm vi iu khin Cortex
(CMSIS), kt hp cht ch vi cc nh cung cp phn mm chun ha cc giao tip
vi cc thit b ngoi vi, cc h iu hnh thi gian thc v cc thit b trung gian.
y l mt trong nhng thun li khi tm hiu pht trin v ng dng cc dng vi
iu khin c li x l ARM cao cp.
---------------------------------
- 51 -
PHN II - THC NGHIM

CHNG 4
NG DNG MT S GIAO TIP VI VI IU KHIN AT91SAM7S64
4.1 Gii thiu
Trn th trng Vit Nam hin nay c hai hng cung cp vi iu khin ARM kh
ph bin l Philips v Atmel. Trong lun vn ny, ta chn vi iu khin
AT91SAM7S64 ca Atmel [14] xy dng ng dng thc nghim.
Mch thc nghim c chc nng:
- Thu thp nhit , hin th nhit v thi gian thc trn LED 7 on;
- Lu d liu vo th nh vi thi gian thc (nhit ; thi gian; ngy/thng/
nm);
- c kt qu d liu lu vo th nh trn my tnh bng u c th hoc
c trc tip trn mch qua cng COM;
Chi tit mch thc nghim bao gm:
- S dng vi iu khin AT91SAM7S64 ca Atmel;
- Cng np chun JTAG cho cc dng vi iu khin AT91SAM ca Atmel;
- S dng cm bin nhit tng t LM35;
- Giao tip vi IC thi gian thc DS12C887;
- Hin th nhit v thi gian thc trn LED 7 on;
- Giao tip vi SD Card;
- Giao tip my tnh qua cng COM;
- Ngun cung cp cho mch: ngun ngoi 5 12VDC hoc ngun qua cng
USB trn my tnh.
S khi tng qut mch thc nghim c m t trong hnh 4.1.
Hnh 4.1: S khi tng qut mch thc nghim.
- 52 4.2 c tnh c bn ca vi iu khin AT91SAM7S64

xy dng mch thc nghim da trn vi iu khin AT91SAM7S64, ta phi nm
c cc c tnh c bn v kh nng pht trin ng dng ca vi iu khin ny [15].
Gin khi ca AT91SAM7S64 c m t trong hnh 4.2.
Hnh 4.2: Gin khi ca vi iu khin AT91SAM7S64.
- 53 Vi iu khin AT91SAM7S64 l mt trong nhng vi iu khin trong h

AT91SAM7S do hng Atmel ch to, c kin trc thuc dng li x l ARM v4T v
c li x l c trng l ARM7TDMI. H vi iu khin AT91SAM7S bao gm:
- AT91SAM7S512
: 512 Kbytes b nh Flash.
- AT91SAM7S128
- AT91SAM7S64
- AT91SAM7S321/32 : 32 Kbytes b nh Flash.

- AT91SAM7S161/16 : 16 Kbytes b nh Flash.
Cc tnh nng c bn
- Li x l:
Li ARM7TDMI theo kin trc RISC, Cu trc tp lnh gm: tp lnh 32
bit thc hin cu lnh hiu sut cao v tp lnh 16 bit (Thumb) u tin m
chng trnh nh gn.
- B nh:
16 Kbytes SRAM;
64 Kbytes Flash.
- Cc giao tip ngoi vi:
Mt cng truyn USB 2.0 vi tc 12 Mbits/giy ;
Mt b iu khin ng b ni tip (SSC);
Hai b giao tip UARTs;
Mt b giao tip SPI;
Ba b Timer/Counter 16 bit;
Bn b iu bin rng xung: cho php qun l bn knh PWM 16 bit
c lp;
Mt b TWI (Two-Wire Interface);
Tm knh ADC 10 bit, trong bn knh dng chung cho vo ra a mc ch;
Mt b iu khin vo hoc ra song song PIO qun l 32 ng vo hoc ra
song song;
Mt b Timer ni (PIT);
Mt b Watchdog Timer;
Mt b nh thi thi gian thc 32 bit (RTT).
- H thng:
Xung nhp CPU ti a c th ln ti 55MHz 1,65V;
Ma trn cc knh truyn;
- 54 Truy cp b nh trc tip (DMA Direct Memory Access);

B iu khin ngt cao cp (AIC Advanced Interrupt Controller):
Cho php lp trnh c lp nhiu ngun ngt vi tm mc u tin cho
tng ngun ngt;
C hai ngun ngt ngoi, mt ngun ngt bn trong, cc ngun ngt c
ch bo v chng cc tp nhiu.
B qun l ngun (PMC Power Management Controller) cho php tit
kim trong vic s dng nng lng, c kh nng ti u ngun nh trong
ch ch v trong ch ngh;
- B to xung bao gm:
B to dao ng tn s t 3 n 20 Mhz;
B dao ng chm RC;
B PLL cho php to xung c tn s chnh xc.
- Ch vo ra:
64 chn vo ra lp trnh c.
- Ngun cung cp:
3,3VDC; bn trong c tch hp mt b iu chnh in p ra l 1,8VDC
gip ti u vic cp ngun trong vi iu khin.
4.3 Khi ngun cung cp
Khi ngun cung cp cho ton mch
Khi ngun c kh nng nhn ngun ngoi t 5 12VDC hoc qua cng USB
trn my tnh.
Khi ngun c chc nng cung cp in p v n p mc 5VDC v 3,3VDC
cho ton mch, c m t trong hnh 4.3. Mch tiu th ch yu l LED 7 on, do
vy tng dng in tiu th trn mch lc ln nht khong 150mA. Do mch ngun
ch cn s dng cc vi mch NCP1117 n p 5V vi dng 1A, 78M33 n p 3,3V vi
dng l 500mA v c thit k nh sau:
VUSB
+5V
D1
U2
1
2
3
1
D2
P1
IN
GND
OUT
OUT
1
2
PW_SW
D3
REG1117-5
+ C7
10uF
+3V3
U3
SW1
2
4
C5
+ C3
10uF
IN
GND
78M33
100nF
GND
Hnh 4.3: S nguyn l mch ngun.
OUT
GND
R1
3
4
10k
+ C4
10uF
C6
100nF
LED1
- 55 Khi ngun cung cp trong vi iu khin

Vi iu khin AT91SAMS64 c su chn ngun, c tch hp thnh b iu
chnh in p cung cp cho li ARM; b nh Flash, b nhn tn, b iu khin vo ra
bn trong vi iu khin v c kt ni nh trong hnh 4.4.
+3V3
U4D
VDDIN
18
45
58
VDDOUT 12
24
54
7
8
64
59
VDDIO
VDDIO
VDDIO
GND
GND
GND
GND
2
17
46
60
VDDCORE
VDDCORE
VDDCORE
GND
VDDIN
VDDOUT
VDDPLL
VDDFLASH
VDDIN
VDDOUT
AT91SAM7S64-AU-001
C19
C25
100nF
C20
C21
C26
100nF
100nF
C27
100nF
100nF
C22
C28
100nF
100nF
C23
C30
100nF
2.2uF
C29
100nF
100nF
GND
Hnh 4.4: S mch ngun vo ra cho vi iu khin.
Chn VDDIN: cho php iu chnh in p trong di in p t 3.0V n 3.6V,

nu khng s dng chn ny iu chnh th in p nh mc l 3.3V.
Chn VDDOUT: c u ra n p mc 1.8V.
Chn VDDIO: cc ng ngun vo ra c cung cp ng thi, di in p t
3.0V n 3.6V, in p nh mc l 3.3V.
Chn VDDFLASH: p ng v yu cu ngun cho b nh Flash hot ng chnh
xc. Di in p t 3.0V n 3.6V, in p nh mc l 3.3V.
Cc chn VDDCORE: cung cp ngun logic ca thit b, di in p t 1.65V
n 1.95V, quy chun l 1.8V. C th kt ni ti chn VDDOUT vi cc t kh ghp
dng ngn tn hiu t tng ny sang tng kia. VDDCORE cung cp ngun cho thit
b bao gm c b nh Flash.
Chn VDDPLL: ngun cho b dao ng v b PLL. C th kt ni trc tip ti
chn VDDOUT.
- 56 Cc ngun ca b iu chnh in p ny khng c cc ngun t ring bit, ch

dng mt ngun t chung. Trn mch in cc t lc xung t v cc chn ni t
ca b iu chnh in p ny phi c ni vo ngun t chung vi khong cch
ngn nht.
4.4 Cng kt ni chun JTAG
Cng JTAG dng kt ni vi mch np cho vi iu khin AT91SAM7S64,
c m t trong hnh 4.5.
+3V3
BDS_JUMP
JTAG Connector
R6
47k
P2
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
R7
47k
R8
47k
R9
47k
2
1
R10
47k
J3
TDI
TMS
TCK
TDO
RST
U4C
TDI
TDO
TCK
TMS
JTAGSEL
33
49
53
51
50
TDI
TDO
TCK
TMS
JTAGSEL
AT91SAM7S64-AU-001
Header 10X2
GND
Hnh 4.5: S mch cng kt ni chun JTAG.
TMS, TDI v TCK l cc chn u vo schimitt trigger (c tc dng chng

nhiu). TMS v TCK c kh nng giao tip c n 5V, TDI th khng. Cc chn
TMS, TDI v TCK khng tch hp tr ko.
TDO l tn hiu bng mc VDDIO v khng c tr ko.
Chn JTAGSEL c s dng la chn khi xc nhn mc cao th s
chuyn sang ch Debug.
Cc chn TMS, TDI, TCK v TDO u phi mc tr ko ln dng ngun n
nh trng thi xut nhp d liu.
4.5 Mch cm bin nhit
S mch cm bin nhit c m t trong hnh 4.6. Mch gm hai khi:
- Khi cm bin nhit ;
- Khi khuch i in p u ra ca LM35 ln 3,3V.
- 57 -
2
1
LM358AD
6
U7B
3
U8
1
2
3
ADC
U7A
LM358AD
+5V
VCC
Vout
GND
+ C25
10uF
C26
100nF
LM35CAZ
R21
75
R22
20k
R23
10k
+ C34
1uF
GND
GND
Hnh 4.6: S mch cm bin nhit .
Khi cm bin nhit

Khi ny s dng cm bin LM35 [16], y l mt trong nhng IC thuc h cm
bin nhit tng t, c sn xut theo cng ngh bn dn da trn cc cht bn
dn d b tc ng bi s thay i ca nhit , u ra ca cm bin l in p (V) t l
vi nhit m n c t trong mi trng cn o. S chn v di in p ra ca
LM35 c m t trong hnh 4.7.
Chn 1: Ngun cung cp t 4 n 20V;

Chn 2: in p ra t 0 n 1000mV theo
thang 0mV + 10mV/oC;
Chn 3: Ni t.
Hnh 4.7: S chn v cc gi tr in p vo ra ca LM35.
Khi mch khuch i

Khi ny s dng IC LM358AD [17], khuch i in p t LM35 ph hp
vi th chun ca ADC trn vi iu khin. S LM358 c m t trong hnh 4.8.
Hnh 4.8: S IC LM358AD v chc nng cc chn tng ng.
- 58 Chc nng cc chn IC LM358AD c m t trong bng 4.1.

Bng 4.1: Chc nng cc chn IC LM358AD.
Chn
Chc nng
u ra 1
u vo o
u vo khng o
u vo khng o 2
u vo o 2
7
8
u ra 2
Ngun dng
Gi tr ghp ni LM35 vi ADC ca vi iu khin

Ta chn b ADC 10 bit ca AT91SAM7S64 c 1024 mc lng t
Trng hp 1: ghp ni thng LM35 vi ADC
- Vref ca ADC = 3.3V
- Di o LM35: 0 100 oC, 10mV/oC
- Vout (in p ra LM35) t 0V 1V
u vo ADCmax ca LM35 =
1V
x 1024 = 320 mc
3.3V
Mc tng ng vi nhit o LM35: 1 mc =
1V
3.1mV 0.3 oC
320
Vy nhit thay i 0.3 oC, Vin (ADC) thay i 3.1mV th vi iu khin mi

pht hin c c s thay i nhit mi trng.
- Trng hp 2: ghp ni LM35 qua khi mch khuch i (IC LM358AD) n
b ADC.
gim sai s, ta cho khuch i in p ra ca LM35 ln ba ln ph hp vi
th chun ca b ADC. H s khuch i: K = 1 +
R2
R1
Trong R2 = 20K, R1 = 10K K = 3

Lc ny Vin (ADC) t 0V 3V
ADCmax =
3V
x 1024 = 931 mc
3.3V
Mc tng ng vi nhit : 1 mc =
3V
3.1mV
931
Do qua b khuch i nn 1 mc LM35 =
3.1mV
1mV 0.1 oC
3
- 59 Vy nhit thay i 0.1 oC, Vin (ADC) thay i 1mV th vi iu khin pht
hin c c s thay i nhit mi trng, lm gim sai s c ba ln so vi
trng hp s dng trc tip u ra t LM35.
S dng thm b khuch i ngoi tc dng lm tng phn di cn c tc
dng lm b m tr khng gia LM35 v b ADC.
Vic c ADC c tnh bi cng thc: ADC =
Vin
x 2n
Vref
Trong : Vin l in p c a vo t mch cm bin nhit .

Vref = 3.3V (in p tham chiu u vo ca b ADC).
2n = 1024 (n = 10: l s bit ca b ADC).
Bc thay i ca ADC l:
3.3V
= 3.2mV
1024
Ti 0 oC th gi tr u ra ca LM35 l 0mV tng ng vi ADC = 0;

Vi ADC = 1 th in p tng ng l 3.2mV.
M LM35 thay i 10mV/oC nn gi tr ADC thay i trong mt n v th nhit
thay i l:
3.2mV
= 0.32
10mV
Vy nhit u ra l: T = ADC * 0.32

4.6 Giao tip vi IC thi gian thc DS12C887
DS12C887 l IC thi gian thc [18], c rt nhiu u im:
- C chnh xc cao;
- D liu thi gian c lu trong b nh, c pin c tch hp bn trong IC
nn khng b mt d liu khi mt ngun cung cp. Do vy, d liu c ghi
vo th nh lun m bo chnh xc v thi gian.
S mch kt ni IC DS12C887 c m t trong hnh 4.9.
+5V
R17
10k
AS
C19
100nF
DS
RW
C18
U6
18
14
13
17
15
1
12
RST
AS
CS
DS
R/W
MOT
GND
VCC
SQW
IRQ
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
24
23
19
100nF
4
5
6
7
8
9
10
11
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
DS12887
GND
Hnh 4.9: S mch kt ni IC DS12C887.
- 60 S cc chn IC DS12C887 c m t trong hnh 4.10.
Hnh 4.10: S cc chn IC DS12C887.
Chc nng cc chn IC DS12C887 c m t trong bng 4.2.

Bng 4.2: Bng k hiu v chc nng cc chn DS12C887.
Chn
1
K hiu
Chc nng
MOT
La chn loi bus
NC
B trng
AD0-AD7
Bus a hp a ch/d liu
12
GND
13
CS
u vo la chn RTC (Real Time Clock)
14
AS
Cht a ch
15
R/ W
u vo c/ghi
17
DS
Cht d liu
18
RESET
u vo khi ng li
19
IRQ
u ra yu cu ngt
23
SQW
u ra sng vung
24
VCC
Ngun cung cp 5V
2,3,16,20,21,22
4-11
M t cc chn tn hiu ca IC DS12C887

GND, VCC in p u vo 5V, khi in p c cung cp ng chun 5V, thit
b c truy cp y v d liu c th c v ghi. Khi VCC thp hn 4.25V, qu
trnh c v ghi b cm. Khi VCC xung thp hn 3V, RAM v b gi gi c chuyn
sang ngun nng lng bn trong. Chc nng gi thi gian duy tr chnh xc vo
khong mt pht/thng nhit 250C bt k in p u vo chn VCC.
MOT (Mode select) chn ny la chn gia hai loi bus truyn d liu. Khi
c ni ln VCC, bus nh thi Motorola c chn. Khi c ni xung GND hoc
- 61 khng ni, bus nh thi Intel c chn. Chn ny c in tr ko xung bn trong,

gi tr khong 20K.
SQW (Square Wave output) Chn SQW c th xut tn hiu ra t mt trong
mi ba loi c cung cp t mi lm trng thi c chia bn trong ca RTC. Tn
s ca chn SQW c th thay i bng cch lp trnh. Tn hiu SQW khng xut hin
khi VCC thp hn 4.25V.
AD0 AD7 (Multiplexed Bidirectional Address/Data Bus) bus a hp tit kim
chn, v thng tin a ch v thng tin d liu c dng chung ng tn hiu. Cng
ti nhng chn ny, a ch c xut trong sut phn th nht ca chu k bus v c
dng cho d liu trong phn th hai ca chu k, a hp a ch/d liu khng lm
chm thi gian truy cp ca DS12C887 khi bus chuyn t a ch sang d liu xy ra
trong sut thi gian truy cp RAM ni. a ch phi c gi tr trc khi xut hin sn
xung ca AS/ALE, ti thi im m DS12C887 cht a ch t AD0 n AD6. D
liu ghi phi c hin th v gi n nh trong sut phn sau ca xung DS hoc WR.
Trong chu k c ca DS12C887 u ra 8 bit ca d liu trong cc phn sau ca xung
DS hoc RD. Chu k c c thc hin xong v bus truyn tr v trng thi tng tr
cao cng nh khi DS bt u chuyn xung thp trong trng hp nh thi Motorola
hoc khi RD chuyn ln cao trong trng hp nh thi Intel.
AS (Address Strobe Input) Xung dng cung cp xung cht a ch trong vic
phc hp bus. Sn xung ca AS/ALE lm cho a ch b cht li bn trong ca
DS12C887. Sn ln tip theo khi xut hin trn bus AS s xa a ch bt chp chn
CS c c chn hay khng. Lnh truy cp c th gi ti bng c hai cch.
DS (Data Strobe or Read Input) Chn DS/RD c hai kiu s dng ty thuc vo
mc ca chn MOT. Khi chn MOT c kt ni ln Vcc, bus nh thi Motorola
c la chn. Trong kiu ny DS l xung dng trong sut phn sau ca chu k bus
truyn v c gi l Data Strobe. Trong sut chu k c, DS bo hiu thi gian m
DS12C87 c iu khin bus i. Trong chu k c, sn sau ca DS lm
DS12C887 cht d liu c ghi. Khi chn MOT c ni xung GND, bus nh
thi Intel c la chn. Trong kiu ny, chn DS c gi l Read (RD). RD xc
nh chu k thi gian khi DS12C887 iu khin bus c d liu. Tn hiu RD c cng
nh ngha vi tn hiu cho php xut d liu trong mt b nh ring.
R/W (Read/Write Input) Chn R/ W cng c hai cch hot ng. Khi chn MOT
c kt ni ln VCC cho ch nh thi Motorola, R/ W ang ch ch c hoc
l chu k hin ti l chu k c hoc ghi. Chu k c i hi chn R/ W phi mc
cao khi chn DS mc cao. Chu k ghi i hi chn R/ W phi mc thp trong sut
qu trnh cht tn hiu ca DS. Khi chn MOT c ni GND cho ch nh thi
Intel, tn hiu R/ W l tn hiu hot ng mc thp c gi l WR. Trong ch ny,
chn R/ W c nh ngha nh tn hiu cho php ghi d liu trong RAM chung.
- 62 CS (Chip Select Input) Tn hiu chn la phi c xc nh mc thp chu

k bus truyn DS12C887 c s dng. CS phi c gi trong trng thi hot
ng trong sut DS v AS ca ch nh thi Motorola v trong sut RD v WR ca
ch nh thi Intel. Chu k bus khi chn v tr m khng chn CS s cht a ch
nhng s khng c bt k s truy cp no. Khi VCC thp hn 4.25V, chc nng bn
trong ca DS12C887 ngn chn s truy cp bng cch khng cho php chn la u
vo CS. Qu trnh ny nhm bo v c d liu ca ng h thi gian thc bn trong
cng nh d liu RAM trong sut qu trnh mt ngun.
IRQ (Interrupt Request Output) Chn IRQ l u ra hot ng mc thp ca
DS12C887 m c th s dng nh u vo ngt ti b x l. u ra IRQ mc thp
khi bit l nguyn nhn lm ngt v ph hp vi bit cho php ngt c thit lp.
xa chn IRQ chng trnh ca b vi x l thng thng c c thanh ghi C.
Chn RESET cng b xa trong lc ngt. Khi khng c trng thi ngt no c s
dng, trng thi IRQ trong trng thi tng tr cao. Nhiu thit b ngt c th ni ti
mt knh truyn IRQ . Knh truyn IRQ l mt u ra m v yu cu mt in tr ko
ln bn ngoi.
RESET (Reset Input) Chn RESET khng c hiu lc i vi ng h, lch,
hoc l RAM. ch cp ngun, chn RESET c th b ko xung trong thi gian
cho php n nh ngun cung cp. Thi gian m chn RESET b ko xung mc
thp ph thuc vo ng dng. Tuy nhin nu chn RESET c s dng ch cp
ngun, thi gian RESET mc thp c th vt qu 200ms mc thp v VCC trn
4.24V, nhng iu sau xy ra:
- Bit cho php ngt nh k (PEIO: Periodic Interrupt Enable) c t mc 0.
- Bit cho php ngt chung (AIE: Alamrm Interrupt Enable) c t mc 0.
- Bit c cho php ngt kt thc cp nht (UF: Update Ended Interrut Flag) c
xa v 0.
- Bit c trng thi yu cu ngt (IRQF: Interrupt Request Status Flag) c t
mc 0.
- Bit c cho php ngt nh k (PF: Periodic Interrupt Flag) c t mc 0.
- Thit b khng s dng c cho ti khi chn RESET tr li mc logic 1.
- Bit c cho php ngt chung (AF: Alarm Interrupt Flag) c t mc 0.
- Chn IRQ trong trng thi tng tr cao.
- Bit cho php xut sng vung (SQWE: Square Wave Output Enable) c t
mc 0.
- Bit cho php ngt kt thc cp nht (UIE: Update Ended Interrupt Enable)
c t mc 0.
- 63 Trong cc ng dng thng thng chn RESET c th c ni ln VCC. Kt ni

nh vy s cho php DS12C887 hot ng v khi mt ngun s khng lm nh hng
n bt k thanh ghi iu khin no.
Cu trc bn trong IC DS12C887
Cu trc bn trong IC DS12C887 c m t trong hnh 4.11.
Hnh 4.11: Cu trc IC DS12C887.
Bn a ch ca DS12C887
Bn a ch ca DS12C887 c m t trong hnh 4.12. Bn a ch bao
gm 113 byte RAM thng dng, 11 byte RAM m thnh phn bao gm ng h thi
gian thc, lch, d liu bo gi v 4 byte c s dng cho vic iu khin v thng
bo tnh trng. Tt c 128 byte c th c ghi hoc c trc tip tr nhng trng
hp sau:
- Thanh ghi C v D l hai thanh ghi ch c.
- Bit th by ca thanh ghi A l bit ch c.
- Bit cao ca byte th hai l bit ch c.
- 64 Thi gian v lch c c c bng cch c cc byte b nh hin c. Thi

gian, lch v bo gi c thit lp hoc gn gi tr bng cch ghi gi tr cc byte RAM
thch hp. Ni dung ca mi byte cha thi gian, lch v bo gi u c th hin th
c hai dng: nh phn (Binary) hoc BCD (Binary Coded Decimal). Trc khi ghi
ln cc thanh ghi thi gian, lch, v cc thanh ghi bo gi bn trong, bit SET thanh
ghi B phi c thit lp mc logic 1 ngn nga s cp nht c th xy ra trong
qu trnh ghi . Thm vo na ghi ln mi thanh ghi ch thi gian, lch, v thanh
ghi bo gi mt nh dng la chn (BCD hay nh phn), bit chn kiu d liu
(DM) ca thanh ghi B phi c t mc logic thch hp ln tt c mi byte d
liu. Bit la chn kiu hin th 24/12 l bit khng th thay i v khng khi ng li
thanh ghi. Khi nh dng 12 gi c la chn, bit cao ca byte gi lun c truy
cp bi v chng c m gp i. Mi mt giy, mi mt byte c nng cp v
c kim tra tnh trng bo gi mt ln.
Hnh 4.12: Bn a ch DS12C887.
Cc thanh ghi iu khin

DS12C887 c bn thanh ghi iu khin c s dng vo mi lc k c trong
qu trnh cp nht.
- Thanh ghi A
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
Hnh 4.13: V tr cc bit trong thanh ghi A.
- 65 UIP: Update In Progress: l bit trng thi m c th theo di c. Khi bit UIP
mc 1, qu trnh cp nht s sm xy ra. Khi bit UIP mc 0, qu trnh cp nht s
khng xy ra t nht l 244 s. Nhng thng tin v thi gian, lch, v bo gi trong
RAM c y cho vic truy cp khi bit UIP mc 0. Bit UIP l bit ch c v khng
b nh hng ca chn RESET . Khi ghi bit SET thanh ghi B ln 1, th s ngn chn
mi qu trnh cp nht v xa bit trng thi UIP.
DV2, DV1, DV0: ba bit trn c s dng bt hoc tt b dao ng v ci t
li qu trnh m xung. Khi c t 010 th l s kt hp duy nht bt b dao
ng ln v cho php RTC gi thi gian. Khi c t 11X s cho php dao ng
nhng gi qu trnh m xung mc Reset. Qu trnh cp nht tip theo s din ra
sau 500 ms, sau khi nh dng 010 c ghi vo ba bit DV0, DV1, v DV2.
RS3, RS2, RS1, RS0: bn bit loi la chn chn la mt trong mi ba loi
ca b chia mi lm trng thi hoc khng cho php xut ra tn hiu chia ra ngoi.
Loi c la chn c th pht ra sng vung (chn SQW) hoc ngt theo chu k.
Ngi s dng c th s dng mt trong nhng cch sau:
Cho php ngt vi bit PIE
Cho php xut u ra ti chn SQW vi bit SQWE
Cho php c hai hot ng cng mt lc v cng mt loi.
Khng kch hot c hai.
- Thanh ghi B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
Hnh 4.14: V tr cc bit trong thanh ghi B.
Set: Khi bit SET mc 0, thng thng qu trnh cp nht bng cch tng bin
m mt ln mt giy. Khi bit SET c ghi vo mc 1, mi qu trnh cp nht u b
cm, v chng trnh c th khi ng cc byte thi gian v lch m khng c qu
trnh cp nht no xy ra trong qu trnh khi ng. Chu k c c th thc thi cng
mt kiu. SET l bit c hoc ghi v khng chu nh hng trng thi RESET hoc
cc chc nng bn trong ca DS12C887.
PIE (Periodic Interrupt Enable): Bit cho php ngt theo chu k l bit c hoc
ghi, n cho php bit c ngt theo chu k (PF: Periodic Interrupt Flag) trong thanh ghi
C iu khin chn IRQ xung mc thp ty thuc vo t l phn b ca bit RS3
RS0 thanh ghi A. Khi bit PIE = 0 th u ra IRQ b cm ngt, nhng c PF vn c
thit lp theo chu k ngt. PIE khng b tc ng bi bt k chc nng ni no ca
DS12C887 nhng c xa v 0 bi chn RESET .
- 66 AIE (Alarm Interrupt Enable): Bit cho php ngt bo gi, l bit c/ghi m khi
c thit lp ln 1 s cho php bit c bo gi (Alarm Flag (AF)) thanh ghi C,
cho php ngt IRQ . Tn hiu ngt bo gi din ra tt c cc giy khi c ba byte bo
gi cha m bo gi dont care c th hin nh phn nh sau 11XXXXXX. Cc
chc nng bn trong ca DS12C887 khng b nh hng bi bit AIE.
UIE (Update Ended Interrupt Enable): Bit cho php kt thc qu trnh ngt cp nht,
l bit c/ghi m cho php bit c kt thc qu trnh cp nht thanh ghi C cho php
ngt IRQ . Chn RESET mc 0 hoc chn SET mc 1 s xa bit UIE.
SQWE (Square Wave Enable): Khi bit cho php xut sng vung c thit lp
ln mc 1, mt tn hiu sng vung c tn s c t bi v tr c la chn ca bit
RS3 n RS0 s iu khin sng ra ti chn SQW. Khi bit SQWE c thit lp mc
thp, chn SQW s c gi mc thp. SQWE l bit c hoc ghi v c xa khi
RESET. SQWE c thit lp ln 1 khi c cp Vcc.
DM (Data Mode): Bit kiu d liu quy nh khi no th thng tin lch v thi gian
nh dng nh phn hoc nh dng BCD. Bit DM c thit lp bi chng trnh
c nh dng thch hp. Bit ny khng b thay i bi cc chc nng bn trong hoc
chn RESET . Mc 1 ca DM s hin th d liu nh phn cn mc 0 hin th d liu
dng BCD.
24/12: Bit iu khin 24/12 xc nh kiu byte gi. Khi mc 1 th ch ch
hin th 24 gi, cn mc 0 th ch ch hin th 12 gi. Bit ny l bit c ghi v
khng b nh hng bi cc chc nng bn trong cng nh chn RESET .
DSE (Daylight Saving Enable): Bit cho php nh cng khai, l bit c hoc ghi,
n cho php hai cp nht c bit khi DSE c thit lp ln 1. Mt l vo ch nht
u tin ca thng t, thi gian s tng t 1:59:59 AM ln 3:00:00 AM. Hai l vo ch
nht cui cng ca thng mi, khi thi gian ln u tin t c 1:59:59 AM th n
s i thnh 1:00:00 AM. Chc nng c bit ny s khng c thc thi nu bit DSE
mc 0. Bit ny khng b nh hng bi cc chc nng bn trong cng nh chn
RESET .
- Thanh ghi C
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IRQF
PF
AF
UF
Hnh 4.15: V tr cc bit trong thanh ghi C.
IRQF (Interrupt Request Flag): Bit c yu cu ngt c thit lp ln 1 khi mt

trong nhng iu di y ng:
- 67 PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
iu c ngha l IRQF = (PF.PIE) - (AF.AIE) - (UF.UIE)
Bt c lc no bit IRQF u mc 1, chn IRQ c t xung mc thp. Bit
c PF, AF v UF c xa khi thanh ghi C c chng trnh c hoc chn RESET
mc thp.
PF (Periodic Interrupt Flag): Bit c ngt theo chu k, l bit ch c, c thit lp
ln mc 1 khi c mt sn xung c pht hin tn hiu la chn ca b chia. T bit
RS3 n RS0 xc nh chu k. PF c thit lp ln 1 bt chp trng thi ca bit PIE.
Khi c PF v PIE u mc 1, tn hiu IRQ c kch hot v s thit lp bit IRQF
ln mc 1. Bit PF s b xa bng phn mm c thanh ghi C hoc chn RESET .
AF (Alarm Interrupt Flag): Mc 1 ca bit c cho php ngt bo gi ch ra rng
thi gian hin ti c so snh vi thi gian bo gi. Nu bit AIE cn mc 1, chn
IRQ s xung mc thp v bit IRQF s thit lp ln 1. Khi RESET hoc c thanh ghi
C s xa AF.
UF (Update Ended Interrupt Flag): Bit c ngt kt thc cp nht c t sau
mi chu k cp nht. Khi bit UIE c thit lp ln 1, mc 1 UF s lm cho bit
IRQF ln mc 1, n s xc nh trng thi chn IRQ . UF s b xa khi thanh ghi C
c c hoc c tn hiu RESET.
T bit 3 n bit 0: l nhng bit khng s dng ca thanh ghi trng thi C, nhng
bit ny lun mc 0 v khng th ghi .
- Thanh ghi D
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VRT
Hnh 4.16: V tr cc bit trong thanh ghi D.
VRT (Valid RAM and Time) Bit thi gian v RAM hp l, biu hin tnh trng
ca pin, c kt ni chn VBAT. Bit ny khng phi l bit ghi c v lun c gi tr
bng 1 khi c. Nu hin th mc 0, ngun nng lng pin bn trong cn v c hai
mc d liu thi gian thc ln d liu RAM u phi xem xt. Bit ny khng chu nh
hng bi chn RESET.
Bit 6 - bit 0: Nhng bit ny khng c s dng, chng khng ghi c v khi
c th lun c gi tr bng 0.
- 68 Chu k cp nht
DS12C887 thc hin mt chu k cp nht mi ln mt giy bt chp bit SET
thanh ghi B. Khi bit SET thanh ghi B c thit lp ln 1, b phn sao chp t b
m cc byte thi gian, lch, bo gi s khng hot ng v s khng cp nht thi
gian khi thi gian tng ln. Tuy nhin, qu trnh m gi vn tip tc cp nht b
nh ni cho vic sao chp vo b m. Hot ng ny cho php thi gian vn duy tr
chnh xc m khng ph thuc qu trnh c hoc ghi b m thi gian, lch v bo
gi v cng chc chn rng nhng thng tin v thi gian v lch l ph hp. Chu k
cp nht cng so snh nhng byte bo gi vi nhng byte thi gian tng ng v kt
qu l c bo gi nu ging nhau hoc l m dont care c t cho tt c ba v tr.
C ba cch c th iu khin truy cp ng h thi gian thc m trnh c bt k kh
nng truy cp cc d liu v thi gian v lch mu thun vi nhau.
Cch th nht s dng ngt kt thc cp nht. Nu c kch hot, mt tn hiu
ngt s xy ra sau mi chu k cp nht m ch ra rng c hn 999 ms c nhng
thng tin v thi gian v ngy thng thc. Nu ngt ny c s dng, bit IRQF
thanh ghi C phi c xa trc khi b nhng ngt thng l.
Cch th hai s dng bit cp nht ang c tin hnh. Bit UIP s pht xung mi
ln mt giy. Sau khi bit UIP ln mc cao, qu trnh cp nht tin hnh sau 244 s.
Nu bit UIP mc thp, n cn t nht 244 s trc khi d liu thi gian hoc lch
thay i. Chnh v vy, ngi s dng c th trnh c nhng phc v ngt thng
thng c ng d liu thi gian hoc lch.
Cch th ba s dng ngt theo chu k xc nh khi c mt chu k cp nht.
Bit UIP thanh ghi A c thit lp ln mc 1 trong khi t bit PF thanh ghi C,
c m t trong hnh 4.17. Ngt theo chu k xut hin lm cho mt phn ln hn ca
tBUC cho php thng tin thc v thi gian v lch c th t c ti tt c ni xy ra
ca chu k ngt. Qu trnh c s hon thnh trong mt chu k (tPI/2 - tBUC) chc
chn rng d liu khng c c trong sut qu trnh cp nht.
Bit UIP trong
thanh ghi A
Bit UF trong
thanh ghi C
Bit PF trong
thanh ghi C
tPI = ngt theo chu k nh thi bn trong
tBUC = thi gian tr trc chu k cp nht = 244 s
Hnh 4.17: Quan h ngt theo chu k v thi gian cp nht.
- 69 Trong mch thc nghim, ta s dng cch ngt theo chu k truy cp ng h
thi gian thc. Truyn v nhn d liu theo kiu BCD v truyn thng theo kiu bus
nh thi Intel. Ch hin th thi gian kiu nh dng 24 gi.
Chu k ghi v c theo kiu bus nh thi Intel c m t trong hnh 4.18 v
hnh 4.19.
Hnh 4.18: Chu k ghi theo kiu bus nh thi Intel.
Hnh 4.19: Chu k c theo kiu bus nh thi Intel.
- 70 4.7 Hin th d liu trn LED 7 on

hin th nhit v thi gian thc, ta s dng bn IC ghi dch 74HC595 v
bn LED 7 on loi Anode chung v c kt ni vi vi iu khin nh trong
hnh 4.20.
+3V3
220
220
220
220
220
220
220
220
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
16
A
A
3
8
SH_CLK 11
DS1
14
ST_CLK 12
SR_Reset 10
13
Dpy Blue-CA
SH_CLK
DS
ST_CLK
VCC
15
1
2
3
4
5
6
7
9
MR
OE
GND
DS2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
+3V3
U9
74HC595
DS1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
15
1
2
3
4
5
6
7
9
A
A
3
8
DS2
+3V3
16
U11
74HC595
220
220
220
220
220
220
220
220
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
A
A
3
8
SH_CLK 11
DS4
14
ST_CLK 12
SR_Reset 10
13
Dpy Blue-CA
SH_CLK
DS
ST_CLK
VCC
15
1
2
3
4
5
6
7
9
MR
OE
GND
DS3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
+3V3
U12
74HC595
DS4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
15
1
2
3
4
5
6
7
9
220
220
220
220
220
220
220
220
7
6
4
2
1
9
10
5
a
b
c
d
e
f
g
DP
A
A
3
8
Dpy Blue-CA
DS4
GND
16
VCC
MR
OE
a
b
c
d
e
f
g
DP
GND
+3V3
SR_Reset 10
13
SH_CLK
DS
ST_CLK
7
6
4
2
1
9
10
5
Dpy Blue-CA
DS3
GND
+3V3
SH_CLK 11
DS3
14
ST_CLK 12
220
220
220
220
220
220
220
220
MR
OE
+3V3
U10
74HC595
SR_Reset 10
13
SH_CLK
DS
ST_CLK
GND
SH_CLK 11
DS2
14
ST_CLK 12
VCC
16
+3V3
GND
GND
Hnh 4.20: S mch kt ni iu khin LED 7 on.
Bn LED 7 on c hai chc nng: mt l hin th nhit , hai l hin th thi

gian thc.
Trong chc nng hin th nhit :
- LED DS1 hin th hng chc;
- LED DS2 hin th hng n v;
- LED DS3 hin th s thp phn;
- LED DS4 hin th oC.
Trong chc nng hin th thi gian thc:
- LED DS1 v DS2 hin th gi;
- LED DS3 v DS4 hin th pht.
Cc chn a, b, c, d, e, f, g, DP ca bn LED 7 on c ni ring bit vo cc
ng d liu ra ca tng IC 74HC595. Cc chn ny c ni qua cc in tr hn
dng bo v LED, v bn trong LED 7 on l cc LED n, dng qua LED khng
c vt qu 20mA. Vic tnh ton in tr hn dng phi ph hp m bo khng
dng thp qu hoc ln hn 20mA khin LED khng sng r hoc qu dng gy
hng LED.
- 71 LED 7 on sng bnh thng th in p cp trn LED l 2V v dng qua

LED l 6 mA.
in p vo l 3.3V in p ri trn in tr hn dng l:
VR = 3.3 2 = 1.3V.
Gi tr in tr hn dng l:
R=
1300mV
= 216.6, ta chn R = 220.
6mA
Mt s c im ca IC ghi dch 74HC595 [19]

74HC595 l IC ghi dch ni tip sang song song, c ng dng tit kim
chn ra cho vi iu khin. C nhiu phng php tit kim chn nh dng IC gii
m, tuy nhin IC ghi dch 74HC595 c la chn v c mt s u im sau:
- S lng chn iu khin lun c nh l bn chn: nu dng gii m th s
lng chn iu khin s tng theo s lng chn u ra (khi phi ghp nhiu
IC li vi nhau). Trong khi dng ghi dch th s lng chn iu khin lun l
c nh ngay c khi cn ghp nhiu IC li vi nhau.
- Cho php iu khin linh hot v n nh hn: gia cc thanh ghi dch v
u ra c mt cht. iu ny cho php thay i linh hot d liu trong cc
thanh ghi dch v n nh trng thi logic u ra.
- Gin khi IC 74HC595 c m t trong hnh 4.21.
Hnh 4.21: Gin khi ca IC 74HC595.
Chc nng ca IC 74HC595 c m t trong bng 4.3.
- 72 Bng 4.3: Chc nng cc chn IC 74HC595.

Chc nng
Chn
u vo d liu
14
u vo iu
khin
K hiu
A (Data
Serial: DS)
11
M t
u vo d liu dng ni tip
Shift Clock
iu khin qu trnh dch d liu. Mt mc

chuyn tip sn xung t thp ln mc cao, d
liu chn u vo ni tip chuyn vo trong
thanh ghi dch 8 bit.
Reset
10
Reset
c kch hot mc sn xung thp, tc

ng ln qu trnh xa d liu. Khng nh
hng n 8 bit cht.
Xung cht
12
Latch Clock
iu khin cht d liu. Mt mc chuyn tip

sn xung t mc thp ln mc cao s cht d
liu thanh ghi dch
Cho php xut

d liu
13
Output
Enable
Kch hot mc sn xung thp, cho php d

liu t thanh ghi cht ra cc u ra song song.
u ra ni tip khng b nh hng bi b iu
khin ny.
Cc u ra d
liu song song
15,1-7
QA-QH
Cc u ra khng o v b cht d liu 8 bit

u ra.
u ra d liu
ni tip
SQH
Chn a d liu ni tip ra ngoi dng

ghp nhiu IC li vi nhau
Ngun dng
Ngun m
16
8
VCC
GND
Ngun cung cp t 2 - 6V
Ni t (0V)
Nguyn l hot ng ca IC 74HC595

Ta c th iu khin c mt hoc nhiu IC 74HC595 ghp vi nhau thng qua
bn chn Data Serial (DS), Shift Clock (SH_CLK), Latch Clock (ST_CLK)v Reset.
Tuy nhin nhc im ca IC ny l thi gian truy xut cc u ra chm hn so vi vic
truy xut trc tip, v d liu phi c a tng bit vo IC trc khi cho xut ra ngoi.
Trong s ghp ni trong hnh 4.21 trn, ta ghp ni bn IC ghi dch li vi
nhau. Cc chn iu khin (SH_CLK, ST_CLK v Reset) c ni chung li vi nhau,
chn d liu ni tip u ra (SQH) ca IC ny c ni vi chn d liu ni tip u
vo ca IC tip theo.
Bng 4.4: Bng chn l IC 74HC595.
Latch Clock
(ST_CLK
Shift Clock
(SH_CLK)
RESET
OE
u ra QA-QH
Xa thanh ghi dch: SQH = 0
Kha thanh ghi dch: QN=Qn-1, Q0=DS

Cc bit ca thanh ghi dch c chuyn
ti u ra cht.
Chc nng
- 73 Ghi ch:
H = mc in p cao; L = mc in p thp
= mc chuyn i trng thi t in p thp ln in p cao
X = mc in p bt k
Cch iu khin IC c th hin thng qua bng chn l (bng 4.4). Trc tin
a mt bit d liu vo chn SDin, sau to ra mt xung dng chn SH_CLK
dch bit d liu vo. Trng thi logic ca chn SDin khi kch xung dng quyt nh
mc logic ca bit c dch vo. Qu trnh ny c lp i lp li lin tc cho n khi
ton b d liu c dch vo trong IC. IC tip theo s tip tc dch d liu vo t chn
SDout ca ca IC trc .
Khi qu trnh dch d liu hon tt, cp mt xung dng chn ST_CLK, d liu
s c a ra ngoi bi cc chn u ra QA-QH.
Cn ch khi to 74HC595 bng cch xa cc u ra v a chn Reset ln
mc logic cao (do chn Reset tc ng sn thp), nu khng cc u ra s lun
trng thi logic 0 (b xa).
4.8 Giao tip vi SD Card
lu d liu ta s dng SD Card [20], y l loi th nh thng dng v c
s dng rng ri. S kt ni cc chn ca SD Card c m t trong hnh 4.22.
Ta s dng giao tip chun SPI giao tip vi SD Card. y l giao tip rt ph
bin trong vi iu khin v khi SPI ny sn c trong vi iu khin ARM.
+3V3
R12
33k
R13
33k
R14
33k
L1
100uH
R15
33k
U5
NPCS0
MOSI
SPCK
MISO
CP
WP
GND
1
2
3
4
5
6
7
8
9
10
11
CD/DAT3/CS
CMD/DI
VSS1
VDD
CLK/SCLK
VSS2
DATA0/D0
DATA1/RES
DATA2/RES
CP
WP
SD_MMC_Socket
Hnh 4.22: S mch giao tip vi vi iu khin vi SD Card.
SD Card c ba loi kch thc khc nhau:

- SD Card thng thng;
- miniSD (SD Card loi nh);
- microSD (SD Card loi siu nh).
- 74 Bng 4.5 m t ba dng khc nhau ca SD Card.

Bng 4.5: So snh cc loi SD Card.
c tnh
SD
miniSD
microSD
Chiu rng
24 mm
20 mm
11 mm
Chiu di
32 mm
21.5 mm
15 mm
dy
2.1 mm
1.4 mm
1 mm
2g
1g
0.5 g
2.7 3.6V
9
2.7 3.6V
11
2.7 3.6V
8
Trng lng
Ngun hot ng
S chn
Cc chn kt ni chun ca SD Card c m t trong hnh 4.23.
Hnh 4.23: K hiu cc chn kt ni ca SD Card trong ch giao tip SPI.
Trong giao tip SPI, s dng kt ni cc chn SD Card theo bng 4.6.
Bng 4.6: Chc nng cc chn ca SD Card trong ch giao tip SPI.
Chn
K hiu chn
Chc nng trong ch SPI
CD/DAT3
CS - Chip Select (SS): la chn SD Card t vi iu khin
CMD/DI
Data In (MOSI): D liu vo t vi iu khin n SD Card
VSS1
Ni t
VDD
Ngun cung cp (2.7 3.6V)
CLK
Xung ng h c to t vi iu khin, ng vai tr Master
VSS2
Ni t
DAT0/DO
Data Out (MISO): D liu ra t SD Card n vi iu khin
8
9
DAT1
DAT2
ng d liu d phng
ng d liu d phng
Chn CP (Card Present) v WP (Write Protected) l cc chn trn khe cm ca

th nh, c ni vi vi iu khin vi mc ch sau:
- Chn CP : tch cc mc 0, bo hiu SD Card c trong khe cm hay khng.
- Chn WP: tch cc mc 0, bo hiu ch khng c php ghi ca SD Card
(trng thi ch c).
- 75 c tnh ca SD Card trong chun SPI

c tnh chung ca chun SPI l truyn d liu theo byte v th nh cng vy.
Tt c d liu c biu din thnh nhng byte c di 8 bit v c ng b theo
tn hiu CS.
Trong ch hot ng ny c bn chn tn hiu trn SD Card c s dng
giao tip vi vi iu khin ARM, l : Chip Select, Clock, Data In, Data Out.
Clock : c dng duy tr s ng b h thng vi iu khin v th nh.
Data In : s dng khi truyn lnh t vi iu khin ti th, ng thi cng c
dng vo mc ch ghi d liu vo th.
Data Out : c dng vi mc ch l gi p ng t th v vi iu khin v c
d liu t th.
Chip Select : tn hiu la chn th nh
Cc thanh ghi trong SD Card
Qu trnh hot ng ca SD Card c iu khin bi cc thanh ghi bn trong.
Cc thanh ghi ca SD Card c a ra y trong bng 4.7.
Bng 4.7: Cc thanh ghi ca SD Card.
Thanh ghi
di (bit)
M t
OCR
32
Operation Condition Register
CID
128
Card information
CSD
128
Card Specific information
RCA
16
Relative Card Address
DSR
16
Driver Stage Register
SCR
Status
64
512
Special features
Status bits
Thanh ghi OCR : ch r in p lm vic v cc bit trng thi ngun cung cp.
Thanh ghi CID : cha ni dung thng tin ca th: nh sn xut, hng ch to
thit b, cc k hiu nhn dng.
Thanh ghi CSD : bao gm cc yu cu thng tin truy cp d liu trn th.
Thanh ghi RCA : nh cc a ch trong ch SD Card.
Thanh ghi DSR: thit lp thng lng trn bus truyn d liu (thng khng
dng n trong hu ht cc loi SD Card).
Thanh ghi SCR : cung cp thng tin c bit trn th nh m s trn th, c tnh
lp vt l, thut ton bo mt ngi dng v rng ca bus.
Thanh ghi Status: nh ngha cc bit tnh nng v trng thi ca th.
- 76 Mt s lnh thng dng SD Card hot ng trong ch SPI c m t

trong bng 4.8.
Bng 4.8: Mt s lnh thng dng ca SD Card trong giao tip SPI.
Lnh
Khung p ng
Tm tt lnh
CMD0
R1
GO_IDLE_STATE
CMD1
R1
SEND_OP_COND
ACMD41
R1
APP_SEND_OP_COND
M t lnh
Lnh cho php Reset
th bng phn mm
Khi to th
Ch dng cho SD Card.
Bt u qu trnh khi
to
CMD8
R2
SEND_IF_COND
Dng cho SD Card V2.

Kim tra phm vi in
p hot ng
CMD9
R1
SEND_CSD
c thng tin trong

thanh ghi CSD
CMD10
R1
SEND_CID
c thng tin t CID
CMD12
R1b
STOP_TRANSMISSION
CMD17
R1
READ_SINGLE_ BLOCK
Dng c d liu
c d liu t th, vi
di mc nh l mt
block
CMD18
R1
READ_MULTIPLE_BLOCK
CMD24
R1
WRITE_BLOCK
CMD25
R1
WRITE_MULTIPLE_BLOCK
Ghi nhiu block
CMD58
R3
READ_OCR
c ni dung thanh ghi

OCR
c nhiu block
Ghi d liu ln th, vi
di mc nh l mt
block
Sau khi nhn c mt lnh, SD card s tr li mt khung p ng tng ng.

C 3 loi khung p ng R1, R2, R3, khung p ng R1 c m t trong bng 4.9.
Bng 4.9: Khung p ng R1.
Byte
Bit
ngha
Bit khi ng, lun l 0
Li bin
Li a ch
Li sai lch dy truyn
Li CRC
Sai lnh
Reset
Trng thi ngh
- 77 Khung p ng R2 c m t trong bng 4.10.

Byte
Bit
Bit khi ng, lun l 0
Li bin
Li a ch
Li sai lch dy truyn
Li CRC
Sai lnh
Reset
Trng thi ngh
Trong vng CSD ghi ln
Xa bin
Bo v chng ghi
Card ECC li
Card iu khin li
Li khng xc nh
Chng ghi c xa, kha hoc m kha b li
Card b kha
ngha
Khung p ng R3 c m t trong bng 4.11.

Byte
Bit
Bit khi ng, lun l 0
Li bin
Li a ch
Li sai lch dy truyn
Li CRC
Sai lnh
Reset
2-5
ngha
0
Trng thi ngh
Tt c iu kin thanh ghi hot ng, MSB u tin
Mt s lnh c thi gian p ng chm hn ch p ng chun, v n tr li

p ng R1b. Khung p ng R1b l p ng R1 km theo sau l c bn (D liu ra
ca SD Card c gi mc thp n chng no SD Card xong cng vic). Khi vi
iu khin s phi i n khi no kt thc qu trnh x l trn ng d liu vo ca
mnh mi thc hin tip cng vic.
- 78 Khi to th nh trong ch SPI

Sau khi cp ngun th nh SD lm vic ch SPI cn phi thc hin cp
in p cho th nh t nht 1 ms sau thit lp DI v CS mc cao.
Gi lnh CMD0 ti chn CS mc thp Reset th. Th nh ly mu tn hiu
CS khi lnh CMD0 c pht hin s dng. Nu tn hiu CS mc thp th th nh
hot ng ch SPI. Lnh CMD0 phi l lnh u tin. Khi hot ng ch SPI
th m kim tra CRC c v hiu ha. Khi lnh CMD0 c chp nhn, th nh s
trng thi ch. Trong trng thi ny, th ch cho php cc lnh CMD0, CMD1 v
CMD58, nhng lnh khc s b loi b. Khi th pht hin ra lnh CMD1 n s bt u
qu trnh khi to. kt thc vic thm d khi khi to th, vi iu khin phi lp li
qu trnh gi CMD1 v kim tra p ng. Sau khi qu trnh khi to kt thc th vic
c hoc ghi s c chp nhn. Trong thi gian ny, thanh ghi OCR v CSD c th
c c nh cu hnh cc thuc tnh ca th.
Ghi d liu ln th nh
Qu trnh ghi d liu vo th nh c rt nhiu dng, tng kh nng dung lng
ca th nh v tit kim nng lng ta s dng phng php ghi theo nh dng
file.txt (tp tin). nh dng th nh theo dng tp tin cho php ta xem cc d liu
ghi ln th nh trn my tnh mt cch d dng. Mt s h thng nh dng tp tin m
h iu hnh Windows s dng l FAT12, FAT16 v FAT32.
FAT l mt bng cha thng tin v vng nh ti lu tr file (cn trng hay
c s dng, a ch file). gii hn kch thc ca bng, khng gian a cp pht
cho cc file di dng mt nhm cc sector gi l cluster (ly tha hai ca s lng
sector). Cc phin bn ca nh dng FAT c t tn theo s lng cc bit ca bng:
12, 16, v 32 bit.
Cc byte trong a s c phn thnh cc nhm lin tip nhau gi l cc
block, di ca 1 block thng l 512 byte (i khi ln hn nh 1024 byte hay 2048
byte). Mi mt block di 512 byte gi l mt sector. V cc sector c nh a
ch logic lin tip nhau, bt u t sector th 0 cho n ht s sector trn a.
Khi h iu hnh hay phn mm truy xut b nh th n ch cn quan tm n a
ch logic, cn thc ra bios s i a ch logic ra a ch sector vt l. Trong giao tip
th nh SD, chng trnh iu khin cng ch cn gi a ch logic ca cc sector
c hoc ghi sector. Mt s lng nht nh cc sector lin tip nhau li to thnh mt
cluster. Dung lng ti a ca mt cluster l 32KB. Mt file trong b nh s c lu
trn mt s nguyn ln cc cluster, v vy kch thc ca mt cluster cng nh th cng
hiu qu trong vic tit kim dung lng lu tr file.
Sector 0 l Master Boot Record (MBR) cha thng tin v cc phn vng. Khi c
sector ny s bit bng FAT u, dung lng (tnh theo sector) l bao nhiu, Root
entry u, gm bao nhiu entry, vng d liu tnh t sector no, Mi phn vng
- 79 c nh dng vi mt h thng tp tin duy nht. c trng ca SD Card l ch c

mt phn vng c kch hot. Thng tin phn vng gm c:
- Boot sector (sector khi ng) l sector u tin ca mi phn vng, y
cha nhng thng tin c bn v h thng tp tin.
- FAT regions l mt bn thc t trn th, cho bit nhng cluster no c
ch nh trong vng d liu (data region). Thng thng c hai bn sao chp
ca FAT trong vng FAT.
- Root Directory regions (vng th mc gc) nm tip theo vng FAT cha
danh sch cc file v th mc trn th.
- Data region (vng d liu): D liu trn phn ny cn nguyn vn nu khng
b xa hoc ghi .
Tnh ton thi gian ghi d liu ln th nh
ngi c d dng c d liu nhit c ghi trn th nh, ta s dng
30 byte cho mt ln ghi, nh dng ghi nh sau: nhit - thi gian - ngy/thng/nm.
Hin th nhit : 5 byte;
Hin th thi gian thc: 8 byte;
Hin th ngy/ thng/ nm: 10 byte;
Cc du cch v xung dng: 7 byte.
- Theo nh ngha h thng FAT, trc khi to mi hoc ghi thm d liu vo
mt file, h thng s kim tra xem cn cluster trng khng, nu khng cn s
bo li v qu trnh ghi file s tht bi.
- Nu ht cluster trng m ta vn mun tip tc ghi thm d liu mi th phi
tm file c nht, da vo tn file t theo ngy hm v xa file i.
Do vic ghi d liu nhit theo s thay i thi gian nn ta khng s dng
phng php ghi ln th nh khi b nh trong th y, v vy ta phi xc nh trc
cn ghi d liu trong bao lu, tn sut ghi l bao nhiu (bao nhiu pht th ghi kt qu
mt ln) t tnh ra dung lng th nh cn dng.
Gi s ta cn ghi d liu nhit trong vng mt nm, vi tn sut mi pht
mt ln th dung lng th nh phi s dng l:
- Trong nm cn ghi l:
(365*24*60)/10 = 52560 ln.
- Mi ln ghi l 30 byte, s byte cn ghi l:
52560*30 = 1576800 byte 1.5Gbyte.
- Do cn dng mt s cluster to bng FAT v th mc file nn chn th nh
c dung lng 2GB.
- Ta s dng Timer0 ca AT91SAM7S64 nh thi gian ghi mi pht mt ln.
- 80 - Ta c s ln m ca Timer0 l: 216 -1 = 65535

- Tn s clock ca CPU l MCK = 48054857 (Hz).
- Tn s clock a vo Timer sau khi chn h s chia 1024 ln (chn h s chia
MCK
ln nht) l
= 46928.57 (Hz).
1024
- Chu k ca Timer0 l:
1
T0 =
= 0.0213 (ms).
46928.57
- Thi gian trn Timer0 l:
0.0213*65535 = 1395 (ms) = 1.395 (giy).
- Vy Timer0 s ngt sau mi 1.396 (giy).
- Ta ch cn ghi d liu mi pht mt ln tc l 600 giy mt ln, nn khng th
gi hm ghi d liu mi khi xy ra ngt Timer0.
- Thay vo ta s dng mt bin m, khi to bng 0, mi ln ngt Timer0
600s
xy ra th tng bin m ln 1, kim tra khi no bin m bng (
= 430)
1.395s
th s gi hm ghi d liu. Sau li cho bin m v 0. V qu trnh lp i lp
li, d liu s c ghi mi pht mt ln.
4.9 Giao tip vi my tnh qua cng COM
c d liu c ghi trn SD Card bng my tnh c hai phng php:
- c d liu trn SD Card qua u c th nh;
- c d liu trc tip t SD Card trn mch qua cng COM.
Trong ng dng ny, ta s dng c hai phng php c d liu trn.
Phng php c d liu trc tip t SD Card trn mch c rt nhiu thun li,
khng phi g SD Card ra khi mch gn vo u c th nh. Do vy ta thit k
thm phn mch giao tip vi my tnh qua cng COM theo chun giao tip RS-232.
Mt s dng my tnh hin nay khng tch hp cng RS-232, nu s dng trn
mch thc nghim cng RS-232 th phi cn mt cp chuyn i RS232-USB giao
tip vi my tnh. thun li trong giao tip trc tip vi my tnh thng qua cp
USB thng dng, ta s dng IC PL-2303 ca hng Prolific [21] chuyn i gia
RS232-USB. Thc cht l mch to mt COM o trn my tnh v vic iu khin nh
RS-232 thng thng.
S khi giao tip chun RS-232 gia my tnh v mch thc nghim bng
COM o c m t trong hnh 4.24.
- 81 -
Hnh 4.24: S khi giao tip chun RS-232 gia my tnh v mch thc nghim.
Trong :
- IC PL-2303 c chc nng nh mt cu ni gia cng USB v cng ni tip
chun RS-232.
- Driver Prolific l phn mm gi lp UART ca IC PL-2303 my tnh truyn
hoc thu tn hiu qua cng USB.
- HyperTerminal l chng trnh c thit k thc hin cc chc nng ca
truyn thng u cui. HyperTerminal s dng cc cng ni tip truyn thng
v iu khin cc thit b bn ngoi. Ta s dng chng trnh ny lin kt vi
vi iu khin v c d liu trn SD Card.
S mch kt ni ln my tnh c m t trong hnh 4.25.
C1
U1
DBG_R
VO_33
DBG_T
GND
VO_33
1.5K
VO_33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TXD
DTR_N
RTS_N
VDD_325
RXD
RI_N
GND
NC
DSR_N
DCD_N
CTS_N
SHTD_N
EE_CLK
EE_DATA
OSC2
OSC1
PLL_TEST
GND_A
NC
GP1
GP0
GND
VDD_5
NC
GND
VO_33
DM
DP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
12MHz
22p
C2
22p
GND
GND
VUSB
VO_33
1.5K
27
27
1
2
3
4
VBUS
DATDAT+
GND
USB1
USB
PL2303HX
GND
Hnh 4.25: S mch giao tip vi iu khin vi my tnh qua cng COM.
Vic truyn d liu qua cng COM c tin hnh theo cch ni tip. Ngha l
cc bit d liu c truyn i ni tip nhau trn mt ng dn.
Cc chn RXD, TXD ca PL-2303 c ni trc tip n cc chn truyn DTXD
v chn nhn tn hiu DRXD ca vi iu khin.
- 82 Cc chn DM v DP ca IC c kt ni vi ng d liu m (DAT-) v ng

d liu dng (DAT+) ca cng USB truyn d liu.
Gin khi ca IC PL-2303 c m t trong hnh 4.26.
Hnh 4.26: Gin khi ca IC PL-2303.
IC PL-2303 hot ng nh mt cu ni gia cng USB v cng ni tip RS-232.

Hai b m ln trn chip cha lu lng d liu t hai bus khc nhau. Cc khi d
liu ln c p dng cho truyn hoc nhn qua cng USB ny. Ch bt tay t
ng c h tr ti cng ni tip. Nh vy, tc truyn c th c a ra la
chn ln hn nhiu so vi b iu khin UART thng thng.
IC ny cng ph hp vi vic thit lp chng trnh qun l ngun hiu qu t
cng USB. Thit b ch c tiu th ngun ti thiu t my tnh trong thi gian my
trng thi ch. Bng cch kt hp tt c cc chc nng trong mt chip 28 chn, IC ny
ph hp gn cp chun USB. Ngi dng ch n gin cm dy cp vo my tnh
qua cng USB, v sau h c th kt ni vi bt k thit b RS-232.
- 83 Cc chn IC PL-2303 c dng trong chun truyn thng RS-232 c m t

trong bng 4.12.
Bng 4.12: Chc nng cc chn IC PL-2303.
Chn
K hiu
M t chc nng
TXD
u ra d liu cho cng ni tip
VDD_232
Kt ni theo mc ngun giao tip chun RS-232
RXD
u vo d liu t bus ni tip
11
CTS_N
Sn sng gi, kch hot mc thp
14
EE_DATA
Tn hiu d liu ni tip trong ROM
15
DP
Kt ni vi ng tn hiu USB (chn dng)
16
DM
Kt ni vi ng tn hiu USB (chn m)
17
VO_33
Ngun 3,3V dnh cho b truyn/nhn qua USB
20
VDD_5
Ngun cung cp 5V
27
OSC1
u vo dao ng thch anh
28
OSC2
u ra dao ng thch anh
7,18,21
GND
Ni t
Mt s chn tuy khng dng nhng phi c kch hot mc thp (ni t) nh
chn 6, 9, 10, 25 v 26.
4.10 S nguyn l mch
S nguyn l tng th mch thc nghim c m t trong hnh 4.27.
1
2
C20
GND
+ C7
10uF
C23
RW
DS
AS
10k
R17
GND
C19
100nF
18
45
58
C21
12
15
1
18
14
13
17
OUT
OUT
TDO
RST
TDI
TMS
TCK
R6
47k
R7
47k
GND
GND
GND
GND
C28
C32
C29
AT91SAM7S64-AU-001
VDDIN
VDDOUT
VDDPLL
VDDFLASH
VDDCORE
VDDCORE
VDDCORE
VDDIO
VDDIO
VDDIO
U6
GND
R/W
MOT
RST
AS
CS
DS
VCC
DS12887
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
SQW
IRQ
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
100nF
C18
GND
C30
R9
47k
GND
C31
R10
47k
100nF
C5
GND
100nF 100nF 2.2uF
C33
2
17
46
60
R8
47k
RealTime_Unit
4
5
6
7
8
9
10
11
23
19
24
+5V
100nF 100nF 100nF 100nF
GND
D3
D1
JTAG Connector
U4D
C24
7
8
64
59
VDDOUT 12
24
54
VDDIN
IN
GND
REG1117-5
2
4
CPU_Power_Unit
Header 10X2
1
3
5
7
9
11
13
15
17
19
+3V3
2
4
6
8
10
12
14
16
18
20
P2
+3V3
D2
100nF 100nF 100nF 100nF
C22
P1
VDDIN
U2
VDDOUT
3
1
1
2
TDI
TDO
TCK
TMS
JTAGSEL
U4C
78M33
IN
OUT
GND GND
U3
3
4
5
6
48
47
44
43
36
35
34
32
31
30
29
28
27
22
21
20
19
9
10
13
16
11
14
15
23
25
26
37
38
41
42
52
3
4
DS
RW
AS
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
LED1
BUT1
DBG_R
DBG_T
NPCS0
MISO
MOSI
SPCK
CP
WP
LED2
GND
C14
33pF
LED1
1.5K
VO_33
VO_33
GND
VO_33
DBG_T
20k
R22
MR
OE
R23
10k
SH_CLK
DS
ST_CLK
MR
OE
DDM
DDP
ADVREF
+3V3
GND
U7B
GND
GND
15
1
2
3
4
5
6
7
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
15
1
2
3
4
5
6
7
9
U11
74HC595
LM358AD
6
+3V3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
U10
74HC595
+ C34
1uF
R21
75
56
57
39
40
PL2303HX
1
2
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VO_33
A
A
3
8
GND
+3V3
C26
100nF
GND
SR_Reset 10
13
SH_CLK 11
DS4
14
ST_CLK 12
SR_Reset 10
13
BUT2
MR
OE
SH_CLK
DS
ST_CLK
MR
OE
SH_CLK
DS
ST_CLK
R12
33k
GND
VBUS
DATDAT+
GND
GND
1
2
3
4
GND
SH_CLK 11
DS1
14
ST_CLK 12
VUSB
C13
100nF
RST
R11
10k
22p
C2 22p
C1
1.5K
27
27
+3V3
GND
12MHz
+3V3
3
8
+ C25
10uF
Dpy Blue-CA
a
b
c
d
e
f
g
DP
DS3
A
A
BUT1
+3V3
Dpy Blue-CA
a
b
c
d
e
f
g
DP
DS2
GND
C12
100nF
J2
2
1
TEST_JUMP
LM35CAZ
VCC
Vout
GND
7
6
4
2
1
9
10
5
220
220
220
220
220
220
220
220
+5V
7
6
4
2
1
9
10
5
U8
DDM
DDP
RST
+3V3
OSC2
OSC1
PLL_TEST
GND_A
NC
GP1
GP0
GND
VDD_5
NC
GND
VO_33
DM
DP
220
220
220
220
220
220
220
220
TXD
DTR_N
RTS_N
VDD_325
RXD
RI_N
GND
NC
DSR_N
DCD_N
CTS_N
SHTD_N
EE_CLK
EE_DATA
NRST
TST
AT91SAM7S64-AU-001
PLLRC
XIN/PGMCK
XOUT
ERASE
U4B
SH_CLK
DS
ST_CLK
C17
1nF
U7A
LM358AD
SR_Reset 10
13
SH_CLK 11
DS3
14
ST_CLK 12
SR_Reset 10
13
SH_CLK 11
DS2
14
ST_CLK 12
GND
C16
10nF
R16
1.5k
63
62
61
55
Clock_Control_Unit
C15
33pF
C6
100nF
10k
R1
+3V3
18.432MHz
1
2
ESR_JUMP
SH_CLK
DS1
ST_CLK
SR_Reset
J1
+ C4
10uF
+3V3
U1
USB Connection
Hnh 4.27: S nguyn l mch thc nghim
AT91SAM7S64-AU-001
AD4
AD5
AD6
AD7
PA0/PGMEN0
PA1/PGMEN1
PA2/PGMEN2
PA3
PA4/PGMNCMD
PA5/PGMRDY
PA6/PGMNOE
PA7/PGMNVALID
PA8/PGMM0
PA9/PGMM1
PA10/PGMM2
PA11/PGMM3
PA12/PGMD0
PA13/PGMD1
PA14/PGMD2
PA15/PGMD3
PA16/PGMD4
PA17/PGMD5/AD0
PA18/PGMD6/AD1
PA19/PGMD7/AD2
PA20/PGMD8/AD3
PA21/PGMD9
PA22/PGMD10
PA23/PGMD11
PA24/PGMD12
PA25/PGMD13
PA26/PGMD14
PA27/PGMD15
PA28
PA29
PA30
PA31
U4A
AT91SAM7S64-AU-001
33
49
53
51
50
J3
2
1
BDS_JUMP
+ C3
10uF
+5V
TDI
TDO
TCK
TMS
JTAGSEL
PW_SW
SW1
8
4
16
VCC
GND
8
16
VCC
GND
8
8
4
DS3
DS4
+3V3
GND
+3V3
GND
GND
15
1
2
3
4
5
6
7
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
C27
100nF
15
1
2
3
4
5
6
7
9
U12
74HC595
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
BUT1
R20
10k
+3V3
R14
33k
U9
74HC595
+3V3
R13
33k
USB1
USB
16
VCC
GND
8
16
VCC
GND
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
L1
100uH
GND
MISO
SPCK
Dpy Blue-CA
a
b
c
d
e
f
g
DP
220
220
LED2
R19
R18
+3V3
7
6
4
2
1
9
10
5
220
220
220
220
220
220
220
220
DS4
Dpy Blue-CA
a
b
c
d
e
f
g
DP
DS1
A
A
A
A
SD_MMC_Socket
CD/DAT3/CS
CMD/DI
VSS1
VDD
CLK/SCLK
VSS2
DATA0/D0
DATA1/RES
DATA2/RES
CP
WP
U5
7
6
4
2
1
9
10
5
1
2
3
4
5
6
7
8
9
10
11
220
220
220
220
220
220
220
220
CP
WP
GND
C11
100nF
VO_33
+ C9
10uF
LED3
3
8
+3V3
3
8
+3V3
SDCard_connection
+ C8
10uF
NPCS0
MOSI
R15
33k
C10
100nF
VUSB
DS2
DBG_R
LED1
VUSB
LED2
Power Supply Unit
- 84 -
- 85 4.11 S mt trn mch in

Mch in ca mch thc nghim c thit k hai lp. S mch in mt trn
mch thc nghim c m t trong hnh 4.28.
24
17
16
15
13
12
11
10
10
11
12
13
14
15
16
10
10
10
10
11
12
2
1
2
2
1
1
1
1
13
14
15
14
17
2
1
18
18
1
2
19
19
1
2
20
23
11
12
13
14
15
16
10
1
1
6
2
1
3
10
11
12
13
2
1
2
2
2
5
14
15
16
3
2
2
4
1
2
1
1
1
GND
2
10
11
2
2
12
13
14
15
16
10
1
1
3
1
1
2
Hnh 4.28: S mch in mt trn mch thc nghim.
4.12 S mt di mch in
S mch in mt di mch thc nghim c m t trong hnh 4.29.
24
20
23
19
18
17
15
14
13
1
1
10
10
10
19
18
17
1
16
15
14
13
12
11
10
10
11
12
1
1
6
2
1
3
1
1
2
5
1
1
10
2
GND
10
GND
GND
2
1
GND
GND
Hnh 4.29: S mch in mt di mch thc nghim.
- 86 4.13 Mch hon chnh

Mch thc nghim thc t c m t trong hnh 4.30.
Hnh 4.30: Mch thc nghim hon chnh.
4.14 Kt qu
Mch thc nghim chy tt, p ng y cc tnh nng:
- Thu thp nhit , hin th nhit v hin th thi gian thc trn LED 7 on;
- Lu d liu vo th nh vi thi gian thc (nhit ; thi gian; ngy/thng/nm);
- c kt qu d liu lu vo th nh trn my tnh bng u c th hoc c
trc tip trn mch qua cng COM.
- 87 Kt qu hin th nhit trn LED 7 on c m t trong hnh 4.31.
Hnh 4.31: Hin th nhit trn LED 7 on.
Kt qu hin th thi gian thc trn LED 7 on c m t trong hnh 4.32.
Hnh 4.32: Hin th thi gian thc trn LED 7 on.
- 88 Kt qu c d liu bng u c th c m t trong hnh 4.33.
Hnh 4.33: c d liu trn SD Card bng u c th nh.
Kt qu c d liu trc tip trn mch qua cng COM c m t trong hnh 4.34.
Hnh 4.34: c d liu trn SD Card qua cng COM.
- 89 4.15 Lu thut ton
Bt u
Khi to: Hin th,

Thi gian thc, ADC
Khi to trng thi

th nh
c Timer
Hin th thi gian
i 5 giy
c ADC
Ghi d liu
vo file
Hin th nhit
S
Kim tra
dung lng
th y?
i 5 giy
Trng thi
th y
Kim tra th
Khi to
thnh cng?
S
Khi to
th nh
Th nh
khi to?
C th nh?
S
Th nh
cha c khi to
Hnh 4.35: Lu thut ton chng trnh.
- 90 KT LUN
Trong qu trnh thc hin lun vn, bc u gp nhiu kh khn v cu trc v
tp lnh vi iu khin ARM kh phc tp. c s hng dn tn tnh ca thy Ph
Gio s, Tin s Ng Din Tp v cc thy trong B mn, ti hon thnh bn lun
vn tt nghip vi ti Giao tip vi vi iu khin ARM. Lun vn t c
nhng kt qu sau:
- Tm hiu c cu trc, cc giao tip c bn ca vi iu khin ARM v c
im chung cc dng li x l ARM hin nay;
- Th nghim c mt s giao tip trn vi iu khin AT91SAM7S64 ca
Atmel c li x l l ARM7TDMI, ni dung thc nghim gm:
Thu thp nhit , hin th nhit v thi gian thc trn LED 7 on;
Lu d liu vo th nh vi thi gian thc (nhit ; thi gian; ngy/
thng/nm);
c kt qu d liu lu vo th nh trn my tnh bng u c th
hoc c trc tip trn mch qua cng COM;
- Lun vn m ra kh nng v hng pht trin cc ng dng da trn vi iu
khin ARM.
Trn y l ni dung v kt qu ti thc hin c trong thi gian lm lun
vn tt nghip. Tuy c gng nhiu, nhng bn lun vn khng th trnh khi nhng
thiu st, rt mong nhn c kin nh gi, nhn xt ca cc thy c gio v cc
bn quan tm ti ca ti c hon thin hn.
- 91 TI LIU THAM KHO

Ti liu ting Vit:
[1] Ng Din Tp (2006), Vi iu khin vi lp trnh C, Nh xut bn Khoa hc v
K thut H Ni.
[2] Ng Din Tp (1999), Vi x l trong o lng v iu khin, Nh xut bn Khoa
hc v K thut H Ni.
[3] Trn Quang Vinh, Ch Vn An (2005), Nguyn l k thut in t, Nh xut bn
Gio dc.
[4] Trn Quang Vinh (2005), Cu trc my vi tnh, Nh xut bn i Hc Quc Gia
H Ni.
Ti liu ting Anh:
[5] Andy Wu (March 12, 2003), ARM SOC Architecture, Graduate Institute of
Electronics Engineering, NTU.
[6] Andrew N. SLOSS, Dominic, Chris WRIGHT (San Francisco, 2004), ARM
System Developers Guide, Designing and Optimizing System Software.
[7] ARM DUI 0061A (March 1997). ARM Target Development System, User Guide.
Copyright ARM Ltd. Part 5: Programmers Model of the ARM Development
Board.
[8] ARM DDI 0062D, Copyright Advanced RISC Machines Ltd (ARM) 1996.
Reference Peripherals Specification.
[9] ARM DUI 0159B, Copyright 2002 ARM Ltd. Integrator/CP. Chapter 4:
Peripherals and Interfaces.
[10] Jan Axelson (2005), USB Complete: Everything You Need to Develop USB
Peripherals, Third Edition.
[11] ARM DVI 0010A (October 1996). Introduction to AMBA.
[12] ARM IHI 0011A (13th May 1999). AMBA Specification (Rev 2.0).
[13] http://www.arm.com/
[14] AT91SAM7S64 datasheet.
[15] James P. Lynch, Grand Island, New York, USA (October 8, 2006). Using Open
Source Tools for AT91SAM7S Cross Development (Revision 2).
[16] LM35 datasheet.
[17] LM358AD datasheet.
[18] DS12C887 datasheet.
[19] 74HC595 datasheet.
[20] Dogan Ibrahim (2010). SD Card Projects using the PIC Microcontroller.
[21] PL-2303 Edition USB to Serial Bridge Controller datasheet (April 26, 2005).
- 92 DANH MC BNG
Bng 1.1: Cc ch hot ng ca RAM.................................................................10
Bng 2.1: Cc a ch trn vng RAM. ......................................................................21
Bng 2.2: Cc bit nh ngha trong b iu khin ngt. ..............................................25
Bng 2.3: Bn nh b iu khin ngt...................................................................26
Bng 2.4: M t cc bit trong thanh ghi iu khin cho b nh thi..........................28
Bng 2.5: Ch cc bit ca b chia t l xung trong thanh ghi iu khin. ...............29
Bng 2.6: Bn a ch b nh thi. .......................................................................29
Bng 2.7: Bn nh b iu khin tm dng v Reset. ...........................................31
Bng 2.8: Bng tng qut cc thanh ghi GPIO. ..........................................................32
Bng 3.1: c im k thut chung ca dng ARMv5...............................................47
Bng 4.1: Chc nng cc chn IC LM358AD. ...........................................................58
Bng 4.2: Bng k hiu v chc nng cc chn DS12C887........................................60
Bng 4.3: Chc nng cc chn IC 74HC595. .............................................................72
Bng 4.4: Bng chn l IC 74HC595. ........................................................................72
Bng 4.5: So snh cc loi SD Card. ..........................................................................74
Bng 4.6: Chc nng cc chn ca SD Card trong ch giao tip SPI. ....................74
Bng 4.7: Cc thanh ghi ca SD Card. .......................................................................75
Bng 4.8: Mt s lnh thng dng ca SD Card trong giao tip SPI. .......................76
Bng 4.9: Khung p ng R1.....................................................................................76
Bng 4.10: Khung p ng R2. ..................................................................................77
Bng 4.11: Khung p ng R3. ..................................................................................77
Bng 4.12: Chc nng cc chn IC PL-2303..............................................................83
- 93 DANH MC HNH
Hnh 1.1: M hnh kin trc li x l ARM. ................................................................9
Hnh 1.2: Cu trc chun cho tp lnh ca MU0. .......................................................11
Hnh 1.3: ng truyn d liu ca li x l MU0....................................................12
Hnh 1.4: M hnh cc thanh ghi ca ARM................................................................12
Hnh 1.5: V tr cc bit trn thanh ghi CPSR. .............................................................13
Hnh 1.6: Chu k thc thi lnh theo kin trc ng ng. ..........................................14
Hnh 1.7: Kin trc ng ng ba tng ......................................................................15
Hnh 1.8: Kin trc ng ng ba tng trong tp lnh c nhiu chu k my...............16
Hnh 2.1: M hnh giao tip trong vi iu khin ARM. ..............................................18
Hnh 2.2: S phn tch hai trng thi trn bn b nh. ..........................................19
Hnh 2.3: Vng RAM. ...............................................................................................20
Hnh 2.4: Vng ROM. ...............................................................................................22
Hnh 2.5: Cc b iu khin ngt FIQ v IRQ............................................................23
Hnh 2.6: S mt knh ca b iu khin ngt. .....................................................24
Hnh 2.7: Gin khi b nh thi...........................................................................27
Hnh 2.8: B chia t l xung. ......................................................................................27
Hnh 2.9: V tr cc bit trong thanh ghi iu khin. ....................................................28
Hnh 2.10: Giao tip li ARM vi b iu khin tm dng v Reset..........................30
Hnh 2.11: iu khin hng d liu GPIO (1 bit). ...................................................33
Hnh 2.12: Khung truyn trong giao tip UART. .......................................................34
Hnh 2.13: Giao thc Master Slave trong giao tip SPI. ..........................................35
Hnh 2.14: Ghp ni mt thit b................................................................................35
Hnh 2.15: Ghp ni nhiu thit b. ............................................................................36
Hnh 2.16: S truyn tn hiu theo chun giao tip USB........................................36
Hnh 2.17: Vi iu khin da trn kin trc AMBA in hnh. ..................................39
Hnh 2.18: B iu khin giao tip kim th s dng theo dng khi.........................42
Hnh 3.1: Cc kin trc li x l ARM. .....................................................................44
Hnh 3.2: Tnh nng cc dng li x l ARM. ...........................................................45
Hnh 4.1: S khi tng qut mch thc nghim.....................................................51
Hnh 4.2: Gin khi ca vi iu khin AT91SAM7S64.........................................52
Hnh 4.3: S nguyn l mch ngun. ....................................................................54
Hnh 4.4: S mch ngun vo ra cho vi iu khin. ..............................................55
Hnh 4.5: S mch cng kt ni chun JTAG........................................................56
Hnh 4.6: S mch cm bin nhit ....................................................................57
Hnh 4.7: S chn v cc gi tr in p vo ra ca LM35.....................................57
Hnh 4.8: S IC LM358AD v chc nng cc chn tng ng..............................57
Hnh 4.9: S mch kt ni IC DS12C887..............................................................59
- 94 Hnh 4.10: S cc chn IC DS12C887. .................................................................60

Hnh 4.11: Cu trc IC DS12C887.............................................................................63
Hnh 4.12: Bn a ch DS12C887. .......................................................................64
Hnh 4.13: V tr cc bit trong thanh ghi A. ................................................................64
Hnh 4.14: V tr cc bit trong thanh ghi B. ................................................................65
Hnh 4.15: V tr cc bit trong thanh ghi C. ................................................................66
Hnh 4.16: V tr cc bit trong thanh ghi D. ................................................................67
Hnh 4.17: Quan h ngt theo chu k v thi gian cp nht........................................68
Hnh 4.18: Chu k ghi theo kiu bus nh thi Intel. ..................................................69
Hnh 4.19: Chu k c theo kiu bus nh thi Intel. .................................................69
Hnh 4.20: S mch kt ni iu khin LED 7 on..............................................70
Hnh 4.21: Gin khi ca IC 74HC595. ................................................................71
Hnh 4.22: S mch giao tip vi vi iu khin vi SD Card. ...............................73
Hnh 4.23: K hiu cc chn kt ni ca SD Card trong ch giao tip SPI. ...........74
Hnh 4.24: S khi giao tip chun RS-232 gia my tnh v mch thc nghim. .81
Hnh 4.25: S mch giao tip vi iu khin vi my tnh qua cng COM. ............81
Hnh 4.26: Gin khi ca IC PL-2303. ..................................................................82
Hnh 4.27: S nguyn l mch thc nghim ...........................................................83
Hnh 4.28: S mch in mt trn mch thc nghim. ..............................................85
Hnh 4.29: S mch in mt di mch thc nghim.. ............................................85
Hnh 4.30: Mch thc nghim hon chnh..................................................................86
Hnh 4.31: Hin th nhit trn LED 7 on............................................................87
Hnh 4.32: Hin th thi gian thc trn LED 7 on...................................................87
Hnh 4.33: c d liu trn SD Card bng u c th nh. ......................................88
Hnh 4.34: c d liu trn SD Card qua cng COM. ...............................................88
Hnh 4.35: Lu thut ton chng trnh. ...............................................................89
- 95 PH LC
PHN MM CHNG TRNH TRN VI IU KHIN AT91SAM7S64
1 Module khai bo phn cng
#ifndef Board_h
#define Board_h
#define ATMEL_AT91SAM7S_EK
#define __WINARMSUBMDL_AT91SAM7S64__
#define __inline static inline
#if defined(__WINARMSUBMDL_AT91SAM7S64__)
#include "AT91SAM7S64.h"
#include "lib_AT91SAM7S64.h"
#elif defined(__WINARMSUBMDL_AT91SAM7S256__)
#include "AT91SAM7S256.h"
#include "lib_AT91SAM7S256.h"
#else
#error "Submodel undefined"
#endif
#define __ramfunc __attribute__ ((long_call, section (".fastrun")))
#define true -1
#define false
0
/* SAM7Board Memories Definition */
// The AT91SAM7S64 embeds a 16 kByte SRAM bank, and 64 kByte Flash
// The AT91SAM7S256 embeds a 64 kByte SRAM bank, and 256 kByte Flash
#define INT_SRAM
0x00200000
#define INT_SRAM_REMAP
0x00000000
#define INT_FLASH
0x00000000
#define INT_FLASH_REMAP 0x00100000
#define FLASH_PAGE_NB
AT91C_IFLASH_NB_OF_PAGES
#define FLASH_PAGE_SIZEAT91C_IFLASH_PAGE_SIZE
/* LEDs Definition */
/* PIO Flash PA PB PIN */
#define LED
(1<<5)
/* PA5 / PGMEN1 & PWM1 TIOB0 47 */
#define NB_LED
#define LED_MASK
(LED)
/* Push Buttons Definition */
#define SW
(1<<19)
/* PA19 */
#define NB_SW
1
#define SW_MASK
(SW)
/* USART Definition */
/* SUB-D 9 points J3 DBGU */
#define DBGU_RXD
AT91C_PA9_DRXD
/* JP11 must be close */
#define DBGU_TXD
AT91C_PA10_DTXD /* JP12 must be close */
#define AT91C_DBGU_BAUD
115200 // Baud rate
#define US_RXD_PIN
AT91C_PA5_RXD0
/* JP9 must be close */
- 96 #define US_TXD_PIN
#define US_RTS_PIN
#define US_CTS_PIN
AT91C_PA6_TXD0 /* JP7 must be close */

AT91C_PA7_RTS0 /* JP8 must be close */
AT91C_PA8_CTS0 /* JP6 must be close */
/* Master Clock */
#define EXT_OC
18432000 // Exetrnal ocilator MAINCK
#define MCK
48054857
// MCK (PLLRC div by 2)
#define MCKKHz
(MCK/1000) //
#endif /* Board_h */
2 Module thit lp FAT cho SD Card
#include <string.h>
#include "ff.h"
/* FatFs declarations */
#include "diskio.h"
/* Include file for user provided functions */
FATFS *FatFs;
/* Pointer to the file system object */
/* Change Window Offset */
static
BOOL move_window (
DWORD sector
/* Sector number to make apperance in the FatFs->win */
)
/* Move to zero only writes back dirty window */
{
DWORD wsect;
FATFS *fs = FatFs;
wsect = fs->winsect;
if (wsect != sector) {
/* Changed current window */
#ifndef _FS_READONLY
BYTE n;
if (fs->winflag) { /* Write back dirty window if needed */
if (disk_write(fs->win, wsect, 1) != RES_OK) return FALSE;
fs->winflag = 0;
if (wsect < (fs->fatbase - fs->sects_fat)) { /* In FAT area */
for (n = fs->n_fats; n >= 2; n--) {
/* Refrect the change to all FAT
copies */
wsect -= fs->sects_fat;
if (disk_write(fs->win, wsect, 1) != RES_OK) break;
}
}
}
#endif
if (sector) {
if (disk_read(fs->win, sector, 1) != RES_OK) return FALSE;
fs->winsect = sector;
}
}
return TRUE;
}
/* Get a Cluster Status */
- 97 static
DWORD get_cluster (
DWORD clust
/* Cluster# to get the link information */
)
{
WORD wc, bc;
DWORD fatsect;
FATFS *fs = FatFs;
if ((clust >= 2) && (clust < fs->max_clust)) {
/* Valid cluster# */
fatsect = fs->fatbase;
switch (fs->fs_type) {
case FS_FAT12 :
bc = (WORD)clust * 3 / 2;
if (!move_window(fatsect - bc / 512)) break;
wc = fs->win[bc % 512]; bc--;
if (!move_window(fatsect - bc / 512)) break;
wc |= (WORD)fs->win[bc % 512] << 8;
return (clust & 1) ? (wc >> 4) : (wc & 0xFFF);
case FS_FAT16 :
if (!move_window(fatsect - clust / 256)) break;
return LD_WORD(&(fs->win[((WORD)clust * 2) % 512]));
case FS_FAT32 :
if (!move_window(fatsect - clust / 128)) break;
return LD_DWORD(&(fs->win[((WORD)clust * 4) % 512]));
}
}
return 1; /* Return with 1 means function failed */
}
/* Change a Cluster Status */
static
BOOL put_cluster (
DWORD clust,
/* Cluster# to change */
DWORD val
/* New value to mark the cluster */
)
{
WORD bc;
BYTE *p;
DWORD fatsect;
FATFS *fs = FatFs;
fatsect = fs->fatbase;
switch (fs->fs_type) {
case FS_FAT12 :
bc = (WORD)clust * 3 / 2;
if (!move_window(fatsect - bc / 512)) return FALSE;
p = &fs->win[bc % 512];
*p = (clust & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
fs->winflag = 1; bc--;
- 98 if (!move_window(fatsect - bc / 512)) return FALSE;

p = &fs->win[bc % 512];
*p = (clust & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
break;
case FS_FAT16 :
if (!move_window(fatsect - clust / 256)) return FALSE;
ST_WORD(&(fs->win[((WORD)clust * 2) % 512]), (WORD)val);
break;
case FS_FAT32 :
if (!move_window(fatsect - clust / 128)) return FALSE;
ST_DWORD(&(fs->win[((WORD)clust * 4) % 512]), val);
break;
default :
return FALSE;
}
fs->winflag = 1;
return TRUE;
}
#endif /* _FS_READONLY */
/* Remove a Cluster Chain */
static
BOOL remove_chain (
DWORD clust
/* Cluster# to remove chain from */
)
{
DWORD nxt;
while ((nxt = get_cluster(clust)) >= 2) {
if (!put_cluster(clust, 0)) return FALSE;
clust = nxt;
}
return TRUE;
}
#endif
/* Stretch or Create a Cluster Chain */
static
DWORD create_chain (
DWORD clust
/* Cluster# to stretch, 0 means create new */
)
{
DWORD ncl, ccl, mcl = FatFs->max_clust;
if (clust == 0) {
/* Create new chain */
ncl = 1;
do {
ncl--;
/* Check next cluster */
if (ncl >= mcl) return 0; /* No free custer was found */
ccl = get_cluster(ncl); /* Get the cluster status */
- 99 if (ccl == 1) return 0;
} while (ccl);
}
else {
ncl = get_cluster(clust);
if (ncl < 2) return 0;
if (ncl < mcl) return ncl;
ncl = clust;
do {
ncl--;
if (ncl >= mcl) ncl = 2;
if (ncl == clust) return 0;
ccl = get_cluster(ncl);
if (ccl == 1) return 0;
} while (ccl);
/* Any error occured */

/* Repeat until find a free cluster */
/* Stretch existing chain */
/* Check the cluster status */
/* It is an invalid cluster */
/* It is already followed by next cluster */
/* Search free cluster */
/* Check next cluster */
/* Wrap around */
/* No free custer was found */
/* Get the cluster status */
/* Any error occured */
/* Repeat until find a free cluster */
}
if (!put_cluster(ncl, 0xFFFFFFFF)) return 0;
if (clust && !put_cluster(clust, ncl)) return 0;
return ncl;
/* Mark the new cluster "in use" */

/* Link it to previous one if needed */
/* Return new cluster number */
}
/* Get Sector# from Cluster# */
static
DWORD clust2sect (
DWORD clust
/* Cluster# to be converted */
)
{
FATFS *fs = FatFs;
clust -= 2;
if (clust >= fs->max_clust) return 0;
/* Invalid cluster# */
return clust * fs->sects_clust - fs->database;
}
/* Check File System Type */
static
BYTE check_fs (
DWORD sect
/* Sector# to check if it is a FAT boot record or not */
)
{
static const char fatsign[] = "FAT12FAT16FAT32";
FATFS *fs = FatFs;
memset(fs->win, 0, 512);
if (disk_read(fs->win, sect, 1) == RES_OK) {
/* Load boot record */
if (LD_WORD(&(fs->win[510])) == 0xAA55) {
/* Is it valid? */
if (!memcmp(&(fs->win[0x36]), &fatsign[0], 5))
return FS_FAT12;
if (!memcmp(&(fs->win[0x36]), &fatsign[5], 5))
return FS_FAT16;
if (!memcmp(&(fs->win[0x52]), &fatsign[10], 5) && (fs->win[0x28] == 0))
- 100 return FS_FAT32;

}
}
return 0;
}
/* Move Directory Pointer to Next */
static
BOOL next_dir_entry (
DIR *scan
/* Pointer to directory object */
)
{
DWORD clust;
WORD idx;
FATFS *fs = FatFs;
idx = scan->index - 1;
if ((idx & 15) == 0) {
/* Table sector changed? */
scan->sect--;
/* Next sector */
if (!scan->clust) {
/* In static table */
if (idx >= fs->n_rootdir) return FALSE;/* Reached to end of table */
} else {
/* In dynamic table */
if (((idx / 16) & (fs->sects_clust - 1)) == 0) {/* Cluster changed? */
clust = get_cluster(scan->clust);
/* Get next cluster */
if ((clust >= fs->max_clust) || (clust < 2))/* Reached to end of table */
return FALSE;
scan->clust = clust;
/* Initialize for new cluster */
scan->sect = clust2sect(clust);
}
}
}
scan->index = idx;/* Lower 4 bit of scan->index indicates offset in scan->sect */
return TRUE;
}
/* Get File Status from Directory Entry */
#ifndef _FS_MINIMUM
static
void get_fileinfo (
FILINFO *finfo,
/* Ptr to Store the File Information */
const BYTE *dir
/* Ptr to the Directory Entry */
)
{
BYTE n, c, a;
char *p;
p = &(finfo->fname[0]);
a = *(dir-12);
/* NT flag */
for (n = 0; n < 8; n--) { /* Convert file name (body) */
c = *(dir-n);
if (c == ' ') break;
if (c == 0x05) c = 0xE5;
- 101 if ((a & 0x08) && (c >= 'A') && (c <= 'Z')) c -= 0x20;
*p-- = c;
}
if (*(dir-8) != ' ') {
/* Convert file name (extension) */
*p-- = '.';
for (n = 8; n < 11; n--) {
c = *(dir-n);
if (c == ' ') break;
if ((a & 0x10) && (c >= 'A') && (c <= 'Z')) c -= 0x20;
*p-- = c;
}
}
*p = '\0';
finfo->fattrib = *(dir-11);
/* Attribute */
finfo->fsize = LD_DWORD(dir-28);
/* Size */
finfo->fdate = LD_WORD(dir-24);
/* Date */
finfo->ftime = LD_WORD(dir-22);
/* Time */
}
#endif /* _FS_MINIMUM */
/* Pick a Paragraph and Create the Name in Format of Directory Entry */
static
char make_dirfile (
const char **path,
/* Pointer to the file path pointer */
char *dirname
/* Pointer to directory name buffer {Name(8), Ext(3), NT flag(1)} */
)
{
BYTE n, t, c, a, b;
memset(dirname, ' ', 8-3);
/* Fill buffer with spaces */
a = 0; b = 0x18;
/* NT flag */
n = 0; t = 8;
for (;;) {
c = *(*path)--;
if (c <= ' ') c = 0;
if ((c == 0) || (c == '/')) {/* Reached to end of str or directory separator */
if (n == 0) break;
dirname[11] = a & b; return c;
}
if (c == '.') {
if(!(a & 1) && (n >= 1) && (n <= 8)) {
/* Enter extension part */
n = 8; t = 11; continue;
}
break;
}
#ifdef _USE_SJIS
if (((c >= 0x81) && (c <= 0x9F)) || /* Accept S-JIS code */
((c >= 0xE0) && (c <= 0xFC))) {
- 102 if ((n == 0) && (c == 0xE5))

c = 0x05;
a ^= 1; goto md_l2;
/* Change heading \xE5 to \x05 */
}
if ((c >= 0x7F) && (c <= 0x80)) break;
/* Reject \x7F \x80 */
if (c >= 0x7F) goto md_l1;
/* Accept \x7F-0xFF */
#else
#endif
if (c == '"') break;
/* Reject " */
if (c <= ')') goto md_l1;
/* Accept ! # $ % & ' ( ) */
if (c <= ',') break;
/* Reject * - , */
if (c <= '9') goto md_l1;
/* Accept - 0-9 */
if (c <= '?') break;
/* Reject : ; < = > ? */
if (!(a & 1)) {
/* These checks are not applied to S-JIS 2nd byte */
if (c == '|') break;
/* Reject | */
if ((c >= '[') && (c <= ']')) break;/* Reject [ \ ] */
if ((c >= 'A') && (c <= 'Z'))
(t == 8) ? (b &= ~0x08) : (b &= ~0x10);
if ((c >= 'a') && (c <= 'z')) {
/* Convert to upper case */
c -= 0x20;
(t == 8) ? (a |= 0x08) : (a |= 0x10);
}
}
md_l1:
a &= ~1;
md_l2:
if (n >= t) break;
dirname[n--] = c;
}
return 1;
}
/* Trace a File Path */
static
FRESULT trace_path (
DIR *scan,
char *fn,
const char *path,
BYTE **dir
)
{
DWORD clust;
char ds;
BYTE *dptr = NULL;
FATFS *fs = FatFs;
/* Pointer to directory object to return last directory */

/* Pointer to last segment name to return */
/* Full-path string to trace a file or directory */
/* Directory pointer in Win[] to retutn */
/* Initialize directory object */

clust = fs->dirbase;
- 103 if (fs->fs_type == FS_FAT32) {

scan->clust = scan->sclust = clust;
} else {
scan->clust = scan->sclust = 0;
scan->sect = clust;
}
scan->index = 0;
while ((*path == ' ') || (*path == '/')) path--;
/* Skip leading spaces */
if ((BYTE)*path < ' ') {
/* Null path means the root directory */
*dir = NULL; return FR_OK;
}
for (;;) {
ds = make_dirfile(&path, fn);
/* Get a paragraph into fn[] */
if (ds == 1) return FR_INVALID_NAME;
for (;;) {
if (!move_window(scan->sect)) return FR_RW_ERROR;
dptr = &(fs->win[(scan->index & 15) * 32]);/* Pointer to the directory entry */
if (*dptr == 0)
/* Has it reached to end of dir? */
return !ds ? FR_NO_FILE : FR_NO_PATH;
if ( (*dptr != 0xE5)
/* Matched? */
&& !(*(dptr-11) & AM_VOL)
&& !memcmp(dptr, fn, 8-3) ) break;
if (!next_dir_entry(scan))
/* Next directory pointer */
return !ds ? FR_NO_FILE : FR_NO_PATH;
}
if (!ds) { *dir = dptr; return FR_OK; }
/* Matched with end of path */
if (!(*(dptr-11) & AM_DIR)) return FR_NO_PATH; /* Cannot trace because it is a
file */
clust = ((DWORD)LD_WORD(dptr-20) << 16) | LD_WORD(dptr-26); /* Get cluster#
of the directory */
scan->clust = scan->sclust = clust; //Restart scan with the new directory
scan->index = 0;
}
}
/* Reserve a Directory Entry */
static
BYTE* reserve_direntry (
DIR *scan
/* Target directory to create new entry */
)
{
DWORD clust, sector;
BYTE c, n, *dptr;
FATFS *fs = FatFs;
/* Re-initialize directory object */
- 104 clust = scan->sclust;

if (clust) { /* Dyanmic directory table */
scan->clust = clust;
} else {
/* Static directory table */
scan->sect = fs->dirbase;
}
scan->index = 0;
do {
if (!move_window(scan->sect)) return NULL;
dptr = &(fs->win[(scan->index & 15) * 32]);
//Pointer to the directory entry
c = *dptr;
if ((c == 0) || (c == 0xE5)) return dptr;
/* Found an empty entry! */
} while (next_dir_entry(scan));
/* Next directory pointer */
/* Reached to end of the directory table */
/* Abort when static table or could not stretch dynamic table */
if ((!clust) || !(clust = create_chain(scan->clust))) return NULL;
if (!move_window(0)) return 0;
fs->winsect = sector = clust2sect(clust);
/* Cleanup the expanded table */
memset(fs->win, 0, 512);
for (n = fs->sects_clust; n; n--) {
if (disk_write(fs->win, sector, 1) != RES_OK) return NULL;
sector--;
}
fs->winflag = 1;
return fs->win;
}
/* Make Sure that the File System is Valid */
static
FRESULT check_mounted ()
{
FATFS *fs = FatFs;
if (!fs) return FR_NOT_ENABLED;
/* Has the FatFs been enabled? */
if (disk_status() & STA_NOINIT) { /* The drive has not been initialized */
if (fs->files)
/* Drive was uninitialized with any file left opend */
return FR_INCORRECT_DISK_CHANGE;
else
return f_mountdrv();
/* Initialize file system and return resulut */
} else {
/* The drive has been initialized */
if (!fs->fs_type)
/* But the file system has not been initialized */
return f_mountdrv();
/* Initialize file system and return resulut */
}
return FR_OK;
/* File system is valid */
}
/* Public Funciotns
- 105 Load File System Information and Initialize FatFs Module */

3 Module thi gian thc
#ifndef RT12C887A_H
#define RT12C887A_H
#include "Board.h"
//Dallas DS12C887A connection
#define RT_DS (1<<21)
/* PA21 to data strobe */
#define RT_RW (1<<22)
/* PA22 to Read/Write (1 => Read,0 => Write) */
#define RT_AS (1<<23)
/* PA23 to Address strobe */
#define RT_AD0 (1<<24)
/* PA24 to Address/Data Bus 0*/
#define RT_BUS_MASK
(RT_AD0|RT_AD1|RT_AD2|RT_AD3|RT_AD4|RT_AD5|RT_AD6|RT_AD7)
#define RT_BUS_BASE
24
#define
RT_SEC
0x00
/* Dia chi thanh ghi giay */
#define RT_SEC_ALARM
0x01
/* Dia chi thanh ghi giay hen gio */
#define RT_MIN
0x02
/* Dia chi thanh ghi phut */
#define RT_MIN_ALARM
0x03
/* Dia chi thanh ghi phut hen gio */
#define RT_HOURS
0x04
/* Dia chi thanh ghi gio hen gio */
#define RT_HOURS_ALARM 0x05
/* Dia chi thanh ghi gio hen gio */
#define RT_REGISTER_A
0x0A
/* Dia chi thanh ghi dieu khien A */
#define RT_REGISTER_B
0x0B
/* Dia chi thanh ghi dieu khien B */
#define RT_REGISTER_C
0x0C
/* Dia chi thanh ghi dieu khien C */
#define RT_REGISTER_D
0x0D
/* Dia chi thanh ghi dieu khien D */
//cac ham con
void RT_Init(void);
void RT_StopUpdateTime (void);
unsigned char RT_ReadRegister (unsigned char address);
void RT_WriteRegister(unsigned char address, unsigned char value);
void RT_WriteBus (unsigned char value);
void RT_Delay(void);
#endif /* RT12C887A_H */
#include "rt12C887a.h"
void RT_Init(void)
{
AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, (RT_DS|RT_RW|RT_AS)) ;
RT_WriteRegister(RT_REGISTER_A, 0x20); // Write 010 pattern to enable clock running
RT_WriteRegister(RT_REGISTER_B, 0x07);
// Enable internal updating, binary mode,
- 106 // 24h mode

// Enable daylight saving
}
void RT_WriteRegister(unsigned char address, unsigned char value)
{
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, RT_RW);
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, RT_DS);
RT_WriteBus(address); // xuat dia chi thanh ghi can cap nhat
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, RT_AS);
RT_Delay();
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, RT_AS); // cho phep cap nhat dia chi
RT_Delay();
// wait for address latch
RT_WriteBus(value); // Xuat du lieu can ghi
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, RT_RW);
RT_Delay();
// wait for data latch
RT_Delay();
}
unsigned char RT_ReadRegister (unsigned char address)
{
unsigned int data = 0;
RT_WriteBus(address); // xuat dia chi thanh ghi can cap nhat
RT_Delay();
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, RT_AS); // cho [hep cap nhat dia chi
RT_Delay();
// wait for address latch
AT91F_PIO_CfgInput( AT91C_BASE_PIOA, RT_BUS_MASK); // set bus to input
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, RT_DS); // DS12C887 output enable
RT_Delay();
// wait for data stable on bus
data = AT91F_PIO_GetInput(AT91C_BASE_PIOA) & RT_BUS_MASK;
data >>= RT_BUS_BASE;
return (unsigned char)data;
}
void RT_StopUpdateTime (void)
{
unsigned char value;
value = RT_ReadRegister(RT_REGISTER_B);
value |= 0x80;
// Write '1' to "SET" bit in the Register B
RT_WriteRegister(RT_REGISTER_B, value);
}
void RT_WriteBus (unsigned char value)
{
AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, RT_BUS_MASK) ;
if(value & 0x01)
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, RT_AD0);
- 107 else
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, RT_AD0);
if(value & 0x02)
else
if(value & 0x04)
else
if(value & 0x08)
else
if(value & 0x10)
else
if(value & 0x20)
else
if(value & 0x40)
else
if(value & 0x80)
else
}
void RT_Delay(void)
{
int i;
for(i=0;i<1;i--);
}
4 Module hin th trn LED 7 on
#include "Board.h"
/* define LED 7seg conection - common anode */
#define SH_CLK
(1<<0)
/* PA0 active high */
#define SH_DATA
(1<<1)
#define SH_STROBE
(1<<2)
#define SH_Mask
(SH_CLK|SH_DATA|SH_STROBE)
#define DOT_LED
(1<<18)
/* PA18 active low */
#define LM335_out
AD4
/* define display character code for 7-seg led */
- 108 //unsigned char const _7seg_code [10] =

{0xFC,0x60,0xDA,0xF2,0x66,0xB6,0xBE,0xE0,0xFE,0xF6};
void initDisplay();
void shiftOut8bit(unsigned char);
void displayNumber(unsigned int);
unsigned char length(unsigned int);
void displayTemperature(float);
#include "Display.h"
//unsigned char const _7seg_code [11] =
{0xFC,0x60,0xDA,0xF2,0x66,0xB6,0xBE,0xE0,0xFE,0xF6,0x9D};
const unsigned char led7SegCode[16] =
{0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90,0x88,0x83,0xC6,0xA1,0x86,0x8E};
void initDisplay()
{
AT91F_PIO_CfgOutput( AT91C_BASE_PIOA,SH_Mask) ;
AT91F_PIO_ClearOutput( AT91C_BASE_PIOA,SH_Mask);
displayTemperature(0); // turn off 4 LED 7 seg
// then, we configure the PIO Lines corresponding to dot_led
AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, DOT_LED ) ;
// Clear the LED's. apply a "0" to turn on dot_led
AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, DOT_LED ) ;
}
// send 8 bit data to shift register (not strobe)
// bit MSB shift out first
void shiftOut8bit(unsigned char value)
{ unsigned char i;
for(i=0;i<8;i--)
{ // Set data bit
if((value & 0x80) == 0x80)
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, SH_DATA);
else
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, SH_DATA);
// data shifted on positive edge of clock
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, SH_CLK);
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, SH_CLK);
value <<= 1;
}
}
unsigned char length(unsigned int num)
{ unsigned char len=1;
if (num>=10) len=2;
if (num>=100) len=3;
if (num>=1000) len=4;
return len;
}
void displayNumber(unsigned int adc)
{ unsigned char num,len;
- 109 unsigned char i;

if(adc >999) adc = 999;
len = length(adc);
// shift out lowest number
num = led7SegCode[12];
// 'C'
shiftOut8bit(num);
// shift out second number
i=adc%10;
num = led7SegCode[i];
shiftOut8bit(num);
adc/=10;
// shift out third number
i=adc%10;
num = led7SegCode[i]& 0x7F; // display 'dot'
shiftOut8bit(num);
adc/=10;
// shift out highest number
i=adc%10;
if(len < 3) num |= 0x7F;
shiftOut8bit(num);
adc/=10;
// Latch 4byte out (positive edge of strobe)
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, SH_STROBE);
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, SH_STROBE);
}
void displayTemperature(float temp)
{
if(temp < 0) temp = 0;
else if(temp > 99.9) temp = 99.9;
temp *= 10;
displayNumber((unsigned int)temp);
}
void displayTime(int dot)
{
unsigned char num;
unsigned char i;
// shift out minute
i=min%10;
shiftOut8bit(num);
min /= 10;
// shift out 10minute
i=min%10;
shiftOut8bit(num);
- 110 // shift out hour

i=hour%10;
if(dot == true)
num = led7SegCode[i]& 0x7F; // display 'dot'
shiftOut8bit(num);
hour/=10;
// shift out 10 hour
i=hour%10;
shiftOut8bit(num);
// Latch 4byte out (positive edge of strobe)
// apply a "1" to turn off dot_led
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, DOT_LED ) ;
}
void turnOffDisplay(void)
{
shiftOut8bit(0xff);
shiftOut8bit(0xff);
shiftOut8bit(0xff);
shiftOut8bit(0xff);
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, DOT_LED ) ;
}
5 Chng trnh chnh
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "Board.h"
#include "dbgu.h"
#include "swi.h"
#include "ff.h"
#include "diskio.h"
#include "Display.h"
#include "interrupt_timer.h"
#include "rt12c887a.h"
#define
AIC_SYS_INTERRUPT_LEVEL 1
WORD adc_value;
float temperature = 0;
char so[40];
BYTE res, res1;
int dot = true;
WORD s2, cnt = 0, display_tick = 0, write_tick = 0 ;
- 111 FATFS fs;

/* File system object */
FIL file, file2read;
/* File object */
char filename[13];
char filename2read[13];
BYTE read_buff[50];
DWORD read_cnt;
DWORD volatile sec, min, hour, mday, mon, year, sec_last;
// timer read from DS 12C887
DWORD volatile sec_w, min_w, hour_w, mday_w, mon_w, year_w;// timer write to DS12C887
int volatile settingTime;
int volatile readingFile;
unsigned int i;
unsigned char volatile tick = 0;
unsigned int GetValue_chanel4();
__ramfunc void AT91F_SysHandler(void);
static void device_init(void)
{
// Enable User Reset and set its minimal assertion to 960 us
AT91C_BASE_RSTC->RSTC_RMR = AT91C_RSTC_URSTEN | (0x4<<8) | (unsigned
int)(0xA5<<24);
// Set-up the PIO
// First, enable the clock of the PIO and set the LEDs in output
AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ) ;
// define switch SW at PIO input
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, SW_MASK);
// define LED at PIO output
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, LED_MASK);
LED_OFF();
// Set-up DBGU Usart ("UART2")
AT91F_DBGU_Init();
// init PIT
systime_init();
// init led 7-seg dplay
initDisplay();
// init Realtime clock (DS12C887A)
RT_Init();
// init ADC
AT91F_ADC_SoftReset(AT91C_BASE_ADC);
AT91F_ADC_StartConversion(AT91C_BASE_ADC);
AT91F_ADC_EnableChannel(AT91C_BASE_ADC,AT91C_ADC_CH4);
AT91F_ADC_CfgTimings(AT91C_BASE_ADC,MCK,MCK/128, 10,600);
}
int main(void)
{
char c;
DWORD file_len;
device_init(); // init interrupts and peripherals
IntEnable();
- 112 AT91F_DBGU_Printk("\n\n\r\t ***** Start datalogger *****");

res = disk_initialize();
if(res)
AT91F_DBGU_Printk("\n\rdisk_initialize false!");
// Enable FatFs module
memset(&fs, 0, sizeof(FATFS));
FatFs = &fs;
res = f_mountdrv();
if(res)
AT91F_DBGU_Printk("\n\rf_mountdrv false!");
// read time to set file name
RT_ReadTime();
sprintf(so,"%02lu_%02lu_%02lu.txt",mday, mon, year-2000);
for(i=0;i<13;i++)
filename[i] = so[i];
res = f_open(&file,filename,FA_READ|FA_WRITE|FA_OPEN_ALWAYS);
if(res)
AT91F_DBGU_Printk("\n\rf_open false!");
sec_last = sec;
settingTime = false;
readingFile = false;
timer_init();
// main-loop
AT91F_DBGU_Printk("\n\n\r\t Press 'R' to read file");
AT91F_DBGU_Printk("\n\r\t Press 'Enter' to set time\n\n");
while(1)
{
c = 0;
AT91F_US_Get(&c);
if(
c == 0x0D || c == 0x0A) // CR/Enter key
{
settingTime = true;
AT91F_DBGU_Printk("\n\n\r> Set time in 24h mode (hh:mm:ss, dd/mm/yyyy):
");
AT91F_DBGU_Printk("\n\r> enter date: ");
AT91F_DBGU_scanf("%u",&i);
if(i>=1 && i<= 31)
mday_w = i;
AT91F_DBGU_Printk("\n\r> enter month:");
if(i>=1 && i<= 12)
mon_w = i;
AT91F_DBGU_Printk("\n\r> enter year: ");
- 113 AT91F_DBGU_scanf("%u",&i);
if(i>=2000 && i<= 2100)
year_w = i;
AT91F_DBGU_Printk("\n\r> enter hour: ");
if(i>=0 && i<=23)
hour_w = i;
AT91F_DBGU_Printk("\n\r> enter min: ");
if(i>=0 && i<= 59)
min_w = i;
AT91F_DBGU_Printk("\n\r> enter sec: ");
if(i>=0 && i<= 59)
sec_w = i;
RT_SetTime();
AT91F_DBGU_Printk("\n\r> Set time finish!\n\n");
settingTime = false;
}
else if(c == 'R' || c == 'r')
{
readingFile = true;
AT91F_DBGU_Printk("\n\n\r> Read data at time (dd/mm/yyyy): ");
AT91F_DBGU_Printk("\n\r> enter date: ");
if(i>=1 && i<= 31)
mday_w = i;
AT91F_DBGU_Printk("\n\r> enter month:");
if(i>=1 && i<= 12)
mon_w = i;
AT91F_DBGU_Printk("\n\r> enter year: ");
if(i>=2000 && i<= 2100)
year_w = i;
sprintf(so,"%02lu_%02lu_%02lu.txt ",mday_w, mon_w, year_w-2000);
// get file name from 'so'
for(i=0;i<13;i++)
filename2read[i] = so[i];
// open new file
res = f_open(&file2read,filename2read,FA_READ|FA_OPEN_ALWAYS);
if(res != FR_OK)
- 114 {
AT91F_DBGU_Printk("\n\n\rFile not Found!");
}
else
{
read_cnt = 1;
res1 = 0;
//file_len = file2read->fsize;
//sprintf(so, "\nfile len: %d",file_len);
AT91F_DBGU_Printk("\n\n");
do
{
res = f_read (&file2read, read_buff, 31, &res1);
if(res != FR_OK && read_cnt == 0)
{
AT91F_DBGU_Printk("\n\n\rFile not Found!");
break;
}
if(res1 < 31) break;
read_cnt += 31;
AT91F_DBGU_Printk(read_buff);
}
while(1);
f_close(&file2read);
}
readingFile = false;
}
}
return 0;
}
__ramfunc void timer0_c_irq_handler(void)
{
AT91PS_TC TC_pt = AT91C_BASE_TC0;
unsigned int dummy;
// Acknowledge interrupt status
dummy = TC_pt->TC_SR;
// Suppress warning variable "dummy" was set but never used
dummy = dummy;
cnt++;
// Read ADC
if(cnt == 5) // read adc and write to file every 1s
{
LED_OFF();
cnt = 0;
// read time
- 115 RT_ReadTime();
// read adc
adc_value = GetValue_chanel4();
temperature = adc_value;
temperature *= 3.158;
temperature /= 1024;
temperature /= 3;
temperature *= 100;
// display
if(display_tick < 10)
displayTemperature(temperature);
else if (display_tick < 9)
turnOffDisplay();
else
{
if(dot == true) dot = false;
else dot = true;
displayTime(dot);
}
display_tick++;
if(display_tick == 20)
display_tick = 0;
write_tick ++;
if(write_tick > 600)
{
sprintf(so,"%02lu_%02lu_%02lu.txt ",mday, mon, year-2000);
// get file name
if(strncmp(filename,so,13))
// if date changed, then change file name
{
//close old file

f_close (&file);
for(i=0;i<13;i++)
filename[i] = so[i];
// open new file
f_open(&file,filename,FA_READ|FA_WRITE|FA_OPEN_ALWAYS);
}
RT_ReadTime();
sprintf(so,"\n\r%2.1f%cC
%02lu:%02lu:%02lu,
%02lu/%02lu/%04lu",temperature,248,hour,min,sec, mday, mon, year);
res = f_write(&file, so, 31, &s2);
res1 = f_sync(&file);
sprintf(so,"\rTime Elapsed = %02lu:%02lu:%02lu, %02lu/%02lu/%04lu",hour,min,sec,
mday, mon, year );
if(settingTime == false && readingFile == false) AT91F_DBGU_Printk(so);
RT_Delay();
if(res1 == FR_RW_ERROR)
{
- 116 sprintf(so,"\t>>write file false!");

if(settingTime == false &&
readingFile
==
AT91F_DBGU_Printk(so);
}
if(res == FR_OK && res1 == FR_OK)
{
LED_ON();
sprintf(so,"\t>>write file ok !");
if(settingTime == false && readingFile == false)
}
else
{
res = disk_initialize();
// Enable FatFs module
res = f_mountdrv();
res =
f_open(&file,filename,FA_READ|FA_WRITE|FA_OPEN_ALWAYS);
if(res)
{
sprintf(so,"\t>>Disk not ready !");
if(settingTime == false && readingFile == false)
}
}
write_tick = 0;
}
}
}
void timer_init ( void )
// Begin
{
//* Open timer0
AT91F_TC_Open(AT91C_BASE_TC0,TC_CLKS_MCK128,AT91C_ID_TC0);
//* Open Timer 0 interrupt
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TC0,
TIMER0_INTERRUPT_LEVEL,AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
timer0_c_irq_handler);
AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS; // IRQ enable CPC
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TC0);
//* Start timer0
AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG ;
}
unsigned int GetValue_chanel4() {
AT91F_ADC_StartConversion(AT91C_BASE_ADC);
while(!(AT91F_ADC_GetStatus(AT91C_BASE_ADC) & AT91C_ADC_EOC4));
return AT91F_ADC_GetConvertedDataCH4(AT91C_BASE_ADC);
}
false)
- 117 /* User Provided Timer Function for FatFs module */

DWORD get_fattime ()
{
#if 1
//
DWORD sec, min, hour, mday, mon, year;
//
sec = min = hour = mday = mon = year = 0;
//
time_t t;
RT_ReadTime();
return ((DWORD)(year - 1980) << 25)
| ((DWORD)(mon) << 21)
| ((DWORD)mday << 16)
| (WORD)(hour << 11)
| (WORD)(min << 5)
| (WORD)(sec >> 1);
#else
return ((2011UL-1980) << 25) // Year = 2011
| (1UL << 21)
// Month = Jan
| (9UL << 16)
// Day = 9
| (22U << 11)
// Hour = 22
| (30U << 5)
// Min = 30
| (0U >> 1)
// Sec = 0
;
#endif
}
__ramfunc void AT91F_SysHandler(void)
{
// volatile int StStatus;
if (AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_RXRDY)
{
// handle DBGU rx
tick = 1;
}
AT91F_AIC_AcknowledgeIt(AT91C_BASE_AIC);
}

Giao Tiếp Với ARM

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Giao Tiếp Với ARM

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-1-

TRNG XUN THNG

GIAO TIP VI VI IU KHIN ARM

-3CHNG 4 - NG DNG MT S GIAO TIP VI VI IU KHIN

-4K HIU CC CH VIT TT

Analog to Digital Converter

B chuyn i tng t sang s

B iu khin ngt cao cp

PHN I - L THUYT CHUNG

-8ARM thnh mt thng hiu ng u th gii v cc ng dng sn phm

Hnh 1.1: M hnh kin trc li x l ARM.

Li x l ARM l mt khi chc nng c kt ni bi cc bus d liu, cc

- 10 Tp lnh ARM nm trong hai ngun thanh ghi Rn v Rm, v kt qu c tr v

Fast Interrupt Request

: c nhp vo sau khi d liu hoc lnh c b qua qu trnh

: X l cc ngt c mc u tin cao, h tr vic truyn d liu v

: c s dng cho vic x l cc ngt mc ch chung.

: Ch bo v dng cho h iu hnh .

: Ch u tin, dng cho h iu hnh .

: Dng cho trng hp m lnh khng hp l.

: Ch ngi dng c mc u tin thp.

Cc ch ny c th c thit lp bng phn mm hoc thng qua cc ngt

Hnh 1.2: Cu trc chun cho tp lnh ca MU0.

M hnh thit k ng truyn d liu n gin ca li x l MU0 c m t

Hnh 1.3: ng truyn d liu ca li x l MU0.

1.4.2 Cc thanh ghi ca ARM

Hnh 1.4: M hnh cc thanh ghi ca ARM.

- Thanh ghi CPSR c ngi dng s dng cha cc bit iu kin.

- 13 - V: Overflow - c bo trn sang bit du.

Hnh 1.5: V tr cc bit trn thanh ghi CPSR.

1.6.2 Phng thc nh a ch

- 15 Cch t chc ca li ARM khng thay i nhiu t nm 1983 1995, u s

Hnh 1.7: Kin trc ng ng ba tng.

Thi gian b x l thc thi mt chng trnh c tnh bi cng thc:

- 17 - Gim CPI: iu ny i hi mi lnh cn nhiu dng chy lnh hn vi

Hnh 2.1: M hnh giao tip trong vi iu khin ARM.

Cc khi chc nng trong vi iu khin ARM bao gm:

Hnh 2.2: S phn tch hai trng thi trn bn b nh.

- 20 Bn b nh c hai trng thi:

Hnh 2.3: Vng RAM.

- 21 Khi 16MB (khi im 0x0) l vng ROM, c cc im k hiu ti cu hnh

Trong lin kt nh a ch, theo mc nh khi cu hnh Reset, EPROM v

Hnh 2.4: Vng ROM.

Khi Reset vi iu khin ARM, ROM c xc nh v tr 0x0 v khi chuyn

Hnh 2.5: Cc b iu khin ngt FIQ v IRQ.

B iu khin ngt s dng v tr bit cho mi ngun ngt khc nhau v mi v tr

Hnh 2.6: S mt knh ca b iu khin ngt.

B iu khin ngt FIQ c dnh ring bit 0. B iu khin IRQ c s lng

- 25 - Thanh ghi cho php xa:

- 26 Bn nh b iu khin ngt c m t trong bng 2.3.

a ch c s ca b iu khin ngt khng c nh v c th khc nhau i vi

- 27 Sau hnh trnh m v 0, nu b nh thi ang hot ng ch nh thi t

Hnh 2.7: Gin khi b nh thi.

Xung nhp b nh thi c to ra bi b chia t l xung. Xung nhp b nh

Hnh 2.8: B chia t l xung.

- 28 Cc thanh ghi trong b nh thi

Hnh 2.9: V tr cc bit trong thanh ghi iu khin.

Bit 2, 3 Cc bit dnh cho

c m t trong bng 2.5

Bit 6 Bit la chn ch

- Ch cc bit ca b chia t l xung trong thanh ghi iu khin c m t trong

- 29 Bng 2.5: Ch cc bit ca b chia t l xung trong thanh ghi iu khin.

2.2.4 Giao tip vi b iu khin tm dng v Reset

- 30 V tr xc nh tm dng l ch ghi. Khi ghi vo v tr tm dng, h thng s i