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MemoryTimingAnalysis

MemoryRead/Writetimingcycles
The most important timing parameter to be considered in choosing a memory device is the
access time. The maximum time delay from an address input to a data output is longer than
the delay between a chip enable and a data output, and consequently the former timing
figure is normally considered to be the access time. The access time for commonly used
RAMs varies from 50 to 500 ns.
For a read operation, once the output data are valid, the address input cannot be changed
immediately to start another read operation. This is because the device needs a certain
amount of time, called read recovery time, to complete its internal operations before the
next memory operation. The sum of the access time and read recovery time is the memory
read cycle time. This is the time needed between the start of a read operation and the start
of the next memory cycle.
The memory write cycle time can be similarly defined and may be different from the read
cycle time. The Figure below illustrates the timing of a memory read cycle. The address is
applied at point A, which is the beginning of the read cycle, and must be held stable during
the entire cycle. In order to reduce the access time, the chip enable input should be applied
before point B. The data output becomes valid after point C and remains valid as long as the
address and chip enable inputs hold.
The R/W control input is not shown in the timing diagram for the read cycle, but should
remain high throughout the entire cycle.

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A typical write cycle is shown in Figure above. In addition to the address and chip enable
inputs, an active low write pulse on the R/W line and the data to be stored must be applied
during the write cvcle. The timing of data input is less restrictive and can be satisfied simply
by holding the data input stable during the entire cycle. However, the application of the
write pulse has two critical timing parameters: the address setup time and the write pulse
width. The address setup time is the time required for the address to stabilize and is the
time that must elapse before the write pulse can be applied.
In the Figure above, the address setup time is the time interval between points A and B. The
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write pulse width defines the amount of time that the write input must remain active low.
The write cycle time is the time interval between points A and D and is the sum of address
setup time, write pulse width, and write recovery time.
It is important to note that the access time and cycle time discussed in this section are the
minimum timing requirements for the memory devices themselves. The access time and cycle
time for the memory system as a whole are considerably longer because of the delays
resulting from the I/O control logic, system bus logic, and memory interface logic.

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