HWBOOK

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Visit Cable City at <http://www.cablecity.com>
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by Joakim gren
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Created and maintained by Joakim gren.
Welcome to the Hardware Book. Your electronic reference guide.
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This is the PDF (Adobe Acrobat) version. It's converted from HTML to PDF so the result may
sometimes look a bit strange. Please let me know if you find any major visual errors.
You will find the online version and the latest PDF version at HwB
<http://www.blackdown.org/~hwb/hwb.html>.
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Current version 1.3 BETA.

Converted from HTML 1997-11-23.
Pinouts for connectors, buses etc.

Too many? These are the most common.
How to build serial cables and many other cables.
How to build adapters.
Misc circuits (active filters etc).
Misc information (encyclopaedia).
Misc tables with info. (AWG..)
Download a WinHelp or HTML version for offline viewing.
Subscribe to the HwB Newsletter! Info about updates etc.
Information I am currently looking for.
Who did this? And why?
Send your comments to the author.
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Connectors
Connectors Top 10
Cables
Adapters
Circuits
Misc
Tables
Download
HwB-News
Wanted
About
Comment
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Contents:
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The Hardware Book is freely distributable but is copyrighted to Joakim gren. It may not be modified and re-distributed without the authors permission.
The Hardware Book
Note: This PDF file may NOT be sold in printed form.

(C) Joakim gren 1996,1997
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Connector Menu
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What does the information that is listed for each connector mean? See the tutorial.
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- ISA - (Technical)
- EISA - (Technical)
- PCI - (Technical)
- VESA LocalBus (VLB) - (Technical)
- CompactPCI - (Technical)
- IndustrialPCI
- SmallPCI
- Miniature Card - (Technical)
- NuBus
- NuBus 90
- Zorro II
- Zorro II/III
- CPU-port (A1200)
- Ramex (A1000)
- Video Expansion (Amiga)
- CD32 Expansion
- CardBus
- PC Card
- PC Card ATA
- PCMCIA
- CompactFlash
- C-bus II
- SSFDC
- PC-104
- Unibus
Buses:
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Chapter 1
Serial In/Out:
- RS-232
- Serial (PC 9)
- Serial (PC 25)
- Serial (Amiga 1000)
- Serial (Amiga)
- Serial (MSX)
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- Serial (Printer)
- Mouse (PS/2)
- Serial (15)
- DEC Dual RS-232
- Macintosh RS-422
- RS-422
- Macintosh Serial
- C64 RS232 User Port
- DEC DLV11-J Serial
- Cisco Console Port
- RocketPort Serialport
- CoCo Serial Printer
- Conrad Electronics MM3610D
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Parallel In/Out:
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Misc In/Out:
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- Parallel (PC)
- Parallel (Amiga)
- Parallel (Amiga 1000)
- ECP Parallel - (Technical)
- Centronics Printer
- MSX Parallel
- Parallel (Olivetti M10)
- Amstrad CPC6128 Printer Port
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- Universal Serial Bus (USB) - (Technical)

- BeBox GeekPort
- C64/C16/C116/+4 Serial I/O
- Atari ACSI DMA
Video:
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- VGA (VESA DDC)

- VGA (15)
- VGA (9)
- CGA
- EGA
- PGA
- MDA (Hercules)
- VESA Feature
- Macintosh Video
- Amiga Video
- RF Monitor (Amiga 1000)
- CDTV Video Slot
- PlayStation A/V
- Commodore 1084 & 1084S (Analog)
- Commodore 1084 & 1084S (Digital)
- Commodore 1084d & 1084dS
- Atari Jaguar A/V
- SNES Video
- NeoGeo Audio/Video
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Chapter 1: Connector Menu
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- Amstrad CPC6128 Monitor

- Amstrad CPC6128 Plus Monitor
- Atari ST Monitor
- Sun Video
- ZX Spectrum 128 RGB
- 3b1-7300 Video
- CM-8/CoCo RGB
- AT&T 53D410
- AT&T 6300 Taxan Monitor
- AT&T PC6300
- Vic 20 Video
- C64 Audio/Video
- C65 Video
- C128 RGBI
- C128/C64C Video
- C16/C116/+4
- CBM 1902A
- Spectravideo SVI318/328 Audio/Video
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Keyboards:
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- PC Gameport
- PC Gameport+MIDI
- Amiga Mouse/Joy
- C64 Control Port
- C16/C116/+4 Joystick
- MSX Joystick
- SGI Mouse (Model 021-0004-002)
- Macintosh Mouse
- Atari Mouse/Joy
- Atari Enhanced Joystick
- Atari 2600 Joystick
- Amstrad Digital/Joystick
- NeoGeo Joystick
Joysticks/Mice:
- Keyboard (5 PC)
- Keyboard (6 PC)
- Keyboard (XT)
- Keyboard (5 Amiga)
- Keyboard (6 Amiga)
- Keyboard (Amiga CD32)
- Macintosh Keyboard
- AT&T 6300 Keyboard
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Diskdrives:
- Internal Diskdrive
- 8" Floppy Diskdrive
- External Diskdrive (Amiga)
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- SCSI Internal (Single-ended)

- SCSI Internal (Differential)
- SCSI External Centronics 50 (Single-ended)
- SCSI External Centronics 50 (Differential)
- SCSI-II External Hi D-Sub Connector (Single-ended)
- SCSI-II External Hi D-Sub Connector (Differential)
- SCSI External D-Sub (Future Domain)
- SCSI External D-Sub (PC/Amiga/Mac)
- Novell and Procomp External SCSI
- IDE Internal
- ATA Internal
- ATA (44) Internal
- ESDI
- ST506/412
- Paravision SX-1 External IDE
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Harddrives:
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Misc data storage:
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- Mitsumi CD-ROM
- Panasonic CD-ROM
- Sony CD-ROM
- C64 Cassette
- C16/C116/+4 Cassette
- CoCo Cassette
- MSX Cassette
- Spectravideo SVI318/328 Cassette
- Amstrad CPC6128 Tape
Memories:
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- 30 pin SIMM
- 72 pin SIMM
- 72 pin ECC SIMM
- 72 pin SO DIMM
- 144 pin SO DIMM
- 168 pin DRAM DIMM (Unbuffered)
- 168 pin SDRAM DIMM (Unbuffered)
- CDTV Memory Card
- SmartCard AFNOR
- SmartCard ISO 7816-2
- SmartCard ISO
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- MSX External Diskdrive

- Amstrad CPC6128 Diskdrive 2
- Amstrad CPC6128 Plus External Diskdrive
- Macintosh External Drive
- Atari Floppy Port
Home audio/video:
- SCART
- S-Video
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PC motherboards:
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- 5.25" Power
- 3.5" Power
- Motherboard Power
- Turbo LED
- AT Backup Battery
- AT LED/Keylock
- PC-Speaker
- Motherboard IrDA
- Motherboard CPU Cooling fan
Networking:
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- Ethernet 10Base-T & 100Base-T

- Ethernet 100Base-T4
- AUI
Cartridge/Expansion:
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- Atari 2600 Cartridge

- Atari 5200 Expansion
- Atari 7800 Expansion
- Atari Cartridge Port
- GameBoy Cartridge
- MSX Expansion
- Vic 20 Memory Expansion
- C64 Cartridge
- C64 User Port
- C128 Expansion Bus
- C16/+4 Expansion Bus
- +4 User Port
- CDTV Diagnostic Slot
- CDTV Expansion Slot
- PC-Engine Cartridge
- SNES Cartridge
- TG-16 Cartridge
- ZX Spectrum AY-3-8912
- ZX Spectrum ULA
- Spectravideo SVI318/328 Expansion Bus
- Spectravideo SVI318/328 Game Cartridge
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- DIN Audio
- 3.5 mm Mono Telephone plug
- 3.5 mm Stereo Telephone plug
- 6.25 mm Mono Telephone plug
- 6.25 mm Stereo Telephone plug
Misc:
- MIDI Out
- MIDI In
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- Minuteman UPS
- C64 Power Supply Connector
- Amstrad CPC6128 Stereo Connector
Last updated 1997-11-17.
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Connector Tutorial
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Short tutorial
First at each page there a short heading describing what the connector is.
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Pictures of the connectors
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After that there is at each page there is one or more pictures of the connectors. Sometimes
there is some question marks only. This means that I don't know what kind of connector it is
or how it looks.
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(At the computer)
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There may be some pictures I haven't drawn yet. I illustrate this with the following advanced
picture:
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(At the computer)
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(At the videocard)
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Normally are one or more pictures. These are seen from the front, and NOT the soldside.
Holes (female connectors usually) are darkened. Look at the example below. The first is
a female connector and the second is a male. The texts insde parentheses will tell you at
which kind of the device it will look like that.
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(At the monitor cable)
Texts describing the connectors
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Below the pictures there is texts that describes the connectors. Including the name of the
physical connector.
5 PIN DIN 180 (DIN41524) at the computer.
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Heading
Pin table
The pin table is perhaps the information you are looking for. Should be simple to read.
Contains mostly the following three columns; Pin, Name & Description.
Pin
1
2
3
4
5
Name
CLOCK
GND
DATA
VCC
n/c
Description
Key Clock
GND
Key Data
+5 VDC
Not connected
Contributor & Source
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Connector Tutorial
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All persons that helped me or sent me information about the connector will be listed here.
The source of the information is perhaps a book or another site. I must admit that I am bad
at writing the source, but I will try to fill in these in the future.
Contributor: Joakim gren
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Source: Amiga 4000 User's Guide from Commodore
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Example:
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ISA Connector
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ISA
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(At the card)
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(At the computer)
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Description
I/O channel check; active low=parity error
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
I/O Channel ready, pulled low to lengthen memory cycles
Address enable; active high when DMA controls bus
Address bit 19
Address bit 18
Address bit 17
Address bit 16
Address bit 15
Address bit 14
Address bit 13
Address bit 12
Address bit 11
Address bit 10
Address bit 9
Address bit 8
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
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Name
Dir
/I/O CH CK
D7
D6
D5
D4
D3
D2
D1
D0
I/O CH RDY
AEN
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
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Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
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62+36 PIN EDGE CONNECTOR MALE at the card.

62+36 PIN EDGE CONNECTOR FEMALE at the computer.
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ISA=Industry Standard Architecture
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10
ISA Connector
A0
GND
RESET
+5V
IRQ2
-5VDC
DRQ2
-12VDC
/NOWS
+12VDC
GND
/SMEMW
/SMEMR
/IOW
/IOR
/DACK3
DRQ3
/DACK1
DRQ1
/REFRESH
CLOCK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
/DACK2
T/C
ALE
+5V
OSC
GND
Address bit 0
Ground
Active high to reset or initialize system logic
+5 VDC
Interrupt Request 2
-5 VDC
DMA Request 2
-12 VDC
No WaitState
+12 VDC
Ground
System Memory Write
System Memory Read
I/O Write
I/O Read
DMA Acknowledge 3
DMA Request 3
DMA Acknowledge 1
DMA Request 1
Refresh
System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
Interrupt Request 7
Interrupt Request 6
Interrupt Request 5
Interrupt Request 4
Interrupt Request 3
DMA Acknowledge 2
Terminal count; pulses high when DMA term. count reached
Address Latch Enable
+5 VDC
High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
Ground
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
D2
D3
D4
D5
D6
D7
D8
D9
SBHE
LA23
LA22
LA21
LA20
LA18
LA17
LA16
/MEMR
/MEMW
SD08
SD09
SD10
SD11
SD12
SD13
SD14
SD15
/MEMCS16
/IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
/DACK0
DRQ0
System bus high enable (data available on SD8-15)

Address bit 23
Address bit 22
Address bit 21
Address bit 20
Address bit 19
Address bit 18
Address bit 17
Memory Read (Active on all memory read cycles)
Memory Write (Active on all memory write cycles)
Data bit 8
Data bit 9
Data bit 10
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Memory 16-bit chip select (1 wait, 16-bit memory cycle)
I/O 16-bit chip select (1 wait, 16-bit I/O cycle)
Interrupt Request 10
DMA Acknowledge 0
DMA Request 0
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A31
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
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DMA Acknowledge 5
DMA Request 5
DMA Acknowledge 6
DMA Request 6
DMA Acknowledge 7
DMA Request 7
/DACK5
DRQ5
/DACK6
DRQ6
/DACK7
DRQ7
+5 V
/MASTER
GND
Used with DRQ to gain control of system

Ground
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D10
D11
D12
D13
D14
D15
D16
D17
D18
ISA Connector
Note: Direction is Motherboard relative ISA-Cards.
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Note: B8 was /CARD SLCDTD on the XT. Card selected, activated by cards in XT's slot J8
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Contributor: Joakim gren , Rob Gill <gillr@mailcity.com>
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Sources: IBM PC/AT Technical Reference, pages 1-25 through 1-37

Sources: comp.sys.ibm.pc.hardware.* FAQ Part 4
<ftp://rtfm.mit.edu/pub/usenet/news.answers/pc-hardware-faq/part1>, maintained by Ralph Valentino
<ralf@alum.wpi.edu>
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Please send any comments to Joakim gren.
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12
ISA (Tech) Connector
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This file is designed to give a basic overview of the bus found in most IBM clone computers,
often referred to as the XT or AT bus. The AT version of the bus is upwardly compatible,
which means that cards designed to work on an XT bus will work on an AT bus. This bus
was produced for many years without any formal standard. In recent years, a more formal
standard called the ISA bus (Industry Standard Architecture) has been created, with an
extension called the EISA (Extended ISA) bus also now as a standard. The EISA bus
extensions will not be detailed here.
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This file is not intended to be a thorough coverage of the standard. It is for informational
purposes only, and is intended to give designers and hobbyists sufficient information to
design their own XT and AT compatible cards.
Physical Design:
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ISA cards can be either 8-bit or 16-bit. 8-bit cards only uses the first 62 pins and 16-bit cards
uses all 98 pins. Some 8-bit cards uses some of the 16-bit extension pins to get more
interrupts.
16-bit card:
(At the card)
(At the computer)
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8-bit card:
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ISA (Technical)
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(At the card)
(At the computer)
Signal Descriptions:
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+5, -5, +12, -12
Power supplies. -5 is often not implemented.
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AEN
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Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O
device from responding to the I/O command lines during a DMA transfer. When AEN is
active, the DMA Controller has control of the address bus as the memory and I/O read/write
command lines.
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BALE
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BCLK
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Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The
address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle.
Memory devices should latch the LA bus on the falling edge of BALE. Some references refer
to this signal as Buffered Address Latch Enable, or just Address Latch Enable (ALE). The
Buffered-Address Latch Enable is used to latch SA0-19 on the falling edge. This signal is
forced high during DMA cycles.
Bus Clock, 33% Duty Cycle. Frequency Varies. 4.77 to 8 MHz typical. 8.3 MHz is specified
as the maximum, but many systems allow this clock to be set to 12 MHz and higher.
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DACKx
DMA Acknowledge. The active-low DMA Acknowledge 0 to 3 and 5 to 7 are the

corresponding acknowledge signals for DRQ 0-3, 5-7.
DRQx
DMA Request. These signals are asynchronous channel requests used by I/O channel
devices to gain DMA service. DMA request channels 0-3 are for 8-bit data transfer. DAM
request channels 5-7 are for 16-bit data transfer. DMA request channel 4 is used internally
on the system board. DMA requests should be held high until the corresponding DACK line
goes active. DMA requests are serviced in the following priority sequence:
High: DRQ 0, 1, 2, 3, 5, 6, 7 Lowest
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IOCS16
I/O CH CK
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Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC,
externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3
of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach
the cpu. The I/O Channel Check is an active-low signal which indicates that a parity error
exists in a device on the I/O channel.
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I/O CH RDY
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Channel Ready. Setting this low prevents the default ready timer from timing out. The slave
device may then set it high again when it is ready to end the bus cycle. Holding this line low
for too long (15 microseconds, typical) can prevent RAM refresh cycles on some systems.
This signal is called IOCHRDY (I/O Channel Ready) by some references. CHRDY and
NOWS should not be used simultaneously. This may cause problems with some bus
controllers. This signal is pulled low by a memory or I/O device to lengthen memory or I/O
read/write cycles. It should only be held low for a minimum of 2.5 microseconds.
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IOR
The I/O Read is an active-low signal which instructs the I/O device to drive its data onto the
data bus, SD0-SD15.
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IOW
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The I/O Write is an active-low signal which instructs the I/O device to read data from the
data bus, SD0-SD15.
IRQx
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Interrupt Request. IRQ2 has the highest priority. IRQ 10-15 are only available on AT
machines, and are higher priority than IRQ 3-7. The Interrupt Request signals which indicate
I/O service attention. They are prioritized in the following sequence: Highest IRQ 9(2),10,11,
12,14,3,4,5,6,7
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LAxx
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Latchable Address lines. Combine with the lower address lines to form a 24 bit address
space (16 MB) These unlatched address signals give the system up to 16 MB of address
ability. The are valid when "BALE" is high.
MASTER
16 bit bus master. Generated by the ISA bus master when initiating a bus cycle. This
active-low signal is used in conjunction with a DRQ line by a processor on the I/O channel to
gain control of the system. The I/O processor first issues a DRQ, and upon receiving the
corresponding DACK, the I/O processor may assert MASTER, which will allow it to control
the system address, data and control lines. This signal should not be asserted for more than
15 microseconds, or system memory may be corrupted du to the lack of memory refresh
activity.
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I/O size 16. Generated by a 16 bit slave when addressed by a bus master. The active-low
I/O Chip Select 16 indicates that the current transfer is a 1 wait state, 16 bit I/O cycle. Open
Collector.
MEMCS16
The active-low Memory Chip Select 16 indicates that the current data transfer is a 1 wait
state, 16 bit data memory cycle.
MEMR
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The Memory Read is an active-low signal which instructs memory devices to drive data onto
the data bus SD0-SD15. This signal is active on all memory read cycles.
The Memory Write is an active-low signal which instructs memory devices to store data
present on the data bus SD0-SD15. This signal is active on all memory write cycles.
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NOWS
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No Wait State. Used to shorten the number of wait states generated by the default ready
timer. This causes the bus cycle to end more quickly, since wait states will not be inserted.
Most systems will ignore NOWS if CHRDY is active (low). However, this may cause
problems with some bus controllers, and both signals should not be active simultaneously.
OSC
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Oscillator, 14.31818 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by
3 to provide the 4.77 MHz cpu clock of early PCs, and divided by 12 to produce the 1.19
MHz system clock. Some references have placed this signal as low as 1 MHz (possibly
referencing the system clock), but most modern systems use 14.318 MHz.
This frequency (14.318 MHz) is four times the television colorburst frequency. Refresh
timing on many PC's is based on OSC/18, or approximately one refresh cycle every 15
microseconds. Many modern motherboards allow this rate to be changed, which frees up
some bus cycles for use by software, but also can cause memory errors if the system RAM
cannot handle the slower refresh rates.
REFRESH
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Refresh. Generated when the refresh logic is bus master. This active-low signal is used to
indicate a memory refresh cycle is in progress. An ISA device acting as bus master may also
use this signal to initiate a refresh cycle.
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RESET
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A
This signal goes low when the machine is powered up. Driving it low will force a system
reset. This signal goes high to reset the system during powerup, low line-voltage or
hardware reset. ??????????????
SA0-SA19
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System Address Lines, tri-state. The System Address lines run from bit 0 to bit 19. They are
latched on to the falling edge of "BALE".
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SBHE
System Bus High Enable, tristate. Indicates a 16 bit data transfer. The System Bus High
Enable indicates high byte transfer is occurring on the data bus SD8-SD15. This may also
indicate an 8 bit transfer using the upper half of the bus data (if an odd address is present).
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MEMW
SD0-SD16
System Data lines, or Standard Data Lines. They are bidrectional and tri-state. On most
systems, the data lines float high when not driven. These 16 lines provide for data transfer
between the processor, memory and I/O devices.
SMEMR
System Memory Read Command line. Indicates a memory read in the lower 1 MB area. This
System Memory Read is an active-low signal which instructs memory devices to drive data
onto the data bus SD0-SD15. This signal is active only when the memory address is within
the lowest 1MB of memory address space.
BETA RELEASE
16
SMEMW
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T/C
Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.
Terminal Count provides a pulse when the terminal count for any DMA channel is reached.
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8 Bit Memory or I/O Transfer Timing Diagram (4 wait states

shown)
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|___| |__| |___| |___| |___| |__
W1
W2
W3
W4
___|
|___|
BALE
_______|
AEN
__________________________________________________
SA0-SA19
______________________________________
---------<______________________________________>-
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BCLK
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|_______________________________________
___________________________________
---------<___________________________________>----
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SD0-SD7
(WRITE)
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_____________
_____
Command Line
|______________________________|
(IORC,IOWC,
SMRDC, or SMWTC)
_____
SD0-SD7
---------------------------------------<_____>---(READ)
Note: W1 through W4 indicate wait cycles.
YB
BALE is placed high, and the address is latched on the SA bus. The slave device may safely
sample the address during the falling edge of BALE, and the address on the SA bus remains
valid until the end of the transfer cycle. Note that AEN remains low throughout the entire
transfer cycle.
AR
The command line is then pulled low (IORC or IOWC for I/O commands, SMRDSC or
SMWTC for memory commands, read and write respectively). For write operations, the data
remains on the SD bus for the remainder of the transfer cycle. For read operations, the data
must be valid on the falling edge of the last cycle.
PR
EL
IM
IN
System Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.
The System Memory Write is an active-low signal which instructs memory devices to store
data preset on the data bus SD0-SD15. This signal is active only when the memory address
is within the lowest 1MB of memory address space.
NOWS is sampled at the midpoint of each wait cycle. If it is low, the transfer cycle terminates
without further wait states. CHRDY is sampled during the first half of the clock cycle. If it is
low, further wait cycles will be inserted.
The default for 8 bit transfers is 4 wait states. Some computers allow the number of default
wait states to be changed.
16 Bit Memory or I/O Transfer Timing Diagram (1 wait state

shown)
__
__
__
__
__
__
BETA RELEASE
17
BCLK
___|
|___|
|__|
|___|
|___|
|_
AEN [2]
__________________________________________
LA17-LA23
_____________
-------<_____________>-[1]-----------------
BALE
______________|
|________________________
________________
_______
|__________________|
RI
SBHE
ST
__________________
---------------<__________________>-------
SA0-SA19
____________________
|____|
* * [4]
_________________
DI
_________________
M16
___________
|_____________|
*
RE
IO16 [3]
_________________
FO
____
---------------------------<____>--------______________
-----------------<______________>---------
OT
SD0-SD7
(WRITE)
___________
|____________|
Command Line
(IORC,IOWC,
MRDC, or MWTC)
SD0-SD7
(READ)
BU
__
TIO
N.
|___|
.N
An asterisk (*) denotes the point where the signal is sampled.
ET
A
[1] The portion of the address on the LA bus for the NEXT cycle may now be placed on the
bus. This is used so that cards may begin decoding the address early. Address pipelining
must be active.
[2] AEN remains low throughout the entire transfer cycle, indicating that a normal (non-DMA)
transfer is occurring.
YB
[3] Some bus controllers sample this signal during the same clock cycle as M16, instead of
during the first wait state, as shown above. In this case, IO16 needs to be pulled low as soon
as the address is decoded, which is before the I/O command lines are active.
AR
[4] M16 is sampled a second time, in case the adapter card did not active the signal in time
for the first sample (usually because the memory device is not monitoring the LA bus for
early address information, or is waiting for the falling edge of BALE).
16 bit transfers follow the same basic timing as 8 bit transfers. A valid address may appear
on the LA bus prior to the beginning of the transfer cycle. Unlike the SA bus, the LA bus is
not latched, and is not valid for the entire transfer cycle (on most computers). The LA bus
should be latched on the falling edge of BALE. Note that on some systems, the LA bus
signals will follow the same timing as the SA bus. On either type of system, a valid address
is present on the falling edge of BALE.
PR
EL
IM
IN
I/O adapter cards do not need to monitor the LA bus or BALE, since I/O addresses are
always within the address space of the SA bus.
SBHE will be pulled low by the system board, and the adapter card must respond with IO16
or M16 at the appropriate time, or else the transfer will be split into two separate 8 bit
transfers. Many systems expect IO16 or M16 before the command lines are valid. This
requires that IO16 or M16 be pulled low as soon as the address is decoded (before it is
known whether the cycle is I/O or Memory). If the system is starting a memory cycle, it will
ignore IO16 (and vice-versa for I/O cycles and M16).
18
BETA RELEASE
TIO
N.
BU
The default for 16 bit transfers is 1 wait state. This may be shortened or lengthened in the
same manner as 8 bit transfers, via NOWS and CHRDY. Many systems only allow 16 bit
memory devices (and not I/O devices) to transfer using 0 wait states (NOWS has no effect
on 16 bit I/O cycles).
RI
SMRDC/SMWTC follow the same timing as MRDC/MWTC respectively when the address is
within the lower 1 MB. If the address is not within the lower 1 MB boundary,
SMRDC/SMWTC will remain high during the entire cycle.
DI
ST
It is also possible for an 8 bit bus cycle to use the upper portion of the bus. In this case, the
timing will be similar to a 16 bit cycle, but an odd address will be present on the bus. This
means that the bus is transferring 8 bits using the upper data bits (SD8-SD15).
RE
Shortening or Lengthening the bus cycle:
BCLK
W
W
W
W
_
__
__
__
__
__
__
__
__
__
__
__
|__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__| |__
FO
|--Transfer 1-----|----Transfer 2---------|----Transfer 3---|

BALE
__
__
|______________|
__
|____________________|
OT
________|
SBHE
_________
__
|______________|
_______________________
.N
|__________________|__________________|
SA0-SA19
ET
A
_________________ _____________________ _________________

----------<_________________><_____________________><_________________>
IO16
___________
___
YB
|_____________|
*
___________________________
|_____________|
*
CHRDY
________________________________
_______________________________
AR
|______|
*
[1]
NOWS
______________________________________________________
PR
EL
IM
IN
For read operations, the data is sampled on the rising edge of the last clock cycle. For write
operations, valid data appears on the bus before the end of the cycle, as shown in the timing
diagram. While the timing diagram indicates that the data needs to be sampled on the rising
clock, on most systems it remains valid for the entire clock cycle.
_____
IORC
______________
|__________|
* [2]
_______
|_________|
_______
|_______________|
____
|_________|
SD0-SD15
____
____
____
--------------------<____>------------------<____>------------<____>--*
*
*
An asterisk (*) denotes the point where the signal is sampled.

W=Wait Cycle
BETA RELEASE
19
TIO
N.
This timing diagram shows three different transfer cycles. The first is a 16 bit standard I/O
read. This is followed by an almost identical 16 bit I/O read, with one wait state inserted. The
I/O device pulls CHRDY low to indicate that it is not ready to complete the transfer (see [1]).
This inserts a wait cycle, and CHRDY is again sampled. At this second sample, the I/O
device has completed its operation and released CHRDY, and the bus cycle now terminates.
The third cycle is an 8 bit transfer, which is shortened to 1 wait state (the default is 4) by the
use of NOWS.
BU
I/O Port Addresses
ST
RI
Note: Only the first 10 address lines are decoded for I/O operations. This limits the I/O
address space to address 3FF (hex) and lower. Some systems allow for 16 bit I/O address
space, but may be limited due to some I/O cards only decoding 10 of these 16 bits.
AR
YB
ET
A
.N
OT
FO
RE
DI
Port (hex) Port Assignments

000-00F DMA Controller
010-01F DMA Controller (PS/2)
020-02F Master Programmable Interrupt Controller (PIC)
030-03F Slave PIC
040-05F Programmable Interval Timer (PIT)
060-06F Keyboard Controller
070-071 Real Time Clock
080-083 DMA Page Register
090-097 Programmable Option Select (PS/2)
0A0-0AF PIC #2
0C0-0CF DMAC #2
0E0-0EF reserved
0F0-0FF Math coprocessor, PCJr Disk Controller
100-10F Programmable Option Select (PS/2)
110-16F AVAILABLE
170-17F Hard Drive 1 (AT)
180-1EF AVAILABLE
1F0-1FF Hard Drive 0 (AT)
200-20F Game Adapter
210-217 Expansion Card Ports
220-26F AVAILABLE
278-27F Parallel Port 3
280-2A1 AVAILABLE
2A2-2A3 clock
2B0-2DF EGA/Video
2E2-2E3 Data Acquisition Adapter (AT)
2E8-2EF Serial Port COM4
2F0-2F7 Reserved
2F8-2FF Serial Port COM2
300-31F Prototype Adapter, Periscope Hardware Debugger
320-32F AVAILABLE
330-33F Reserved for XT/370
340-35F AVAILABLE
360-36F Network
370-377 Floppy Disk Controller
378-37F Parallel Port 2
380-38F SDLC Adapter
390-39F Cluster Adapter
3A0-3AF reserved
3B0-3BF Monochrome Adapter
3BC-3BF Parallel Port 1
3C0-3CF EGA/VGA
3D0-3DF Color Graphics Adapter
3E0-3EF Serial Port COM3
3F0-3F7 Floppy Disk Controller
PR
EL
IM
IN
BETA RELEASE
20
3F8-3FF Serial Port COM1
TIO
N.
Soundblaster cards usually use I/O ports 220-22F.

Data acquisition cards frequently use 300-31F.
RI
BU
The ISA bus uses two DMA controllers (DMAC) cascaded together. The slave DMAC
connects to the master DMAC via DMA channel 4 (channel 0 on the master DMAC). The
slave therefore gains control of the bus through the master DMAC. On the ISA bus, the
DMAC is programmed to use fixed priority (channel 0 always has the highest priority), which
means that channel 0-4 from the slave have the highest priority (since they connect to the
master channel 0), followed by channels 5-7 (which are channel 1-3 on the master).
DI
ST
The DMAC can be programmed for read transfers (data is read from memory and written to
the I/O device), write transfers (data is read from the I/O device and written to memory), or
verify transfers (neither a read or a write - this was used by DMA CH0 for DRAM refresh on
early PCs).
RE
Before a DMA transfer can take place, the DMA Controller (DMAC) must be programmed.
This is done by writing the start address and the number of bytes to transfer (called the
transfer count) and the direction of the transfer to the DMAC. After the DMAC has been
programmed, the device may activate the appropriate DMA request (DRQx) line.
FO
Slave DMA Controller
AR
YB
ET
A
.N
OT
I/O Port
0000 DMA CH0 Memory Address Register
Contains the lower 16 bits of the memory address, written as two consecutive bytes.
0001 DMA CH0 Transfer Count
Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
0008 DMAC Status/Control Register
Status (I/O read) bits 0-3: Terminal Count, CH 0-3
- bits 4-7: Request CH0-3
Control (write)
- bit 0: Mem to mem enable (1 = enabled)
- bit 1: ch0 address hold enable (1 = enabled)
- bit 2: controller disable (1 = disabled)
- bit 3: timing (0 = normal, 1 = compressed)
- bit 4: priority (0 = fixed, 1 = rotating)
- bit 5: write selection (0 = late, 1 = extended)
- bit 6: DRQx sense asserted (0 = high, 1 = low)
- bit 7: DAKn sense asserted (0 = low, 1 = high)
0009 Software DRQn Request
- bits 0-1: channel select (CH0-3)
- bit 2: request bit (0 = reset, 1 = set)
000A DMA mask register
- bit 2: mask bit (0 = reset, 1 = set)
000B DMA Mode Register
- bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
- bit 4: Auto init (0 = disabled, 1 = enabled)
- bit 5: Address (0 = increment, 1 = decrement)
- bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer
mode, 11 = cascade mode
21
PR
EL
IM
IN
DMA Read and Write
BETA RELEASE
ST
RI
BU
TIO
N.
000C DMA Clear Byte Pointer

Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data
transfers into and out of the DMAC for hi/low byte sequencing.
000D DMA Master Clear (Hardware Reset)
000E DMA Reset Mask Register - clears the mask register
000F DMA Mask Register
- bits 0-3: mask bits for CH0-3 (0 = not masked, 1 = masked)
0081 DMA CH2 Page Register (address bits A16-A23)
0082 DMA CH3 Page Register
008A DMA CH7 Page Register
008B DMA CH5 Page Register
DI
Master DMA Controller
AR
YB
ET
A
.N
OT
FO
RE
I/O
Port
00C0 DMA CH4 Memory Address Register
Contains the lower 16 bits of the memory address, written as two consecutive bytes.
00C2 DMA CH4 Transfer Count
Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
00C6 DMA CH5 Transfer Count
00CA DMA CH6 Transfer Count
00CC DMA CH7 Memory Address Register
00CE DMA CH7 Transfer Count
00D0 DMAC Status/Control Register
Status (I/O read) bits 0-3: Terminal Count, CH 4-7
- bits 4-7: Request CH4-7
Control (write)- bit 0: Mem to mem enable (1 = enabled)
- bit 1: ch0 address hold enable (1 = enabled)
- bit 2: controller disable (1 = disabled)
- bit 3: timing (0 = normal, 1 = compressed)
- bit 4: priority (0 = fixed, 1 = rotating)
- bit 5: write selection (0 = late, 1 = extended)
- bit 6: DRQx sense asserted (0 = high, 1 = low)
- bit 7: DAKn sense asserted (0 = low, 1 = high)
00D2 Software DRQn Request
- bit 2: request bit (0 = reset, 1 = set)
00D4 DMA mask register
- bit 2: mask bit (0 = reset, 1 = set)
00D6 DMA Mode Register
- bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
- bit 4: Auto init (0 = disabled, 1 = enabled)
- bit 5: Address (0 = increment, 1 = decrement)
- bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer
mode, 11 = cascade mode
00D8 DMA Clear Byte Pointer
Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data
transfers into and out of the DMAC for hi/low byte sequencing.
00DA DMA Master Clear (Hardware Reset)
00DC DMA Reset Mask Register - clears the mask register
00DE DMA Mask Register
- bits 0-3: mask bits for CH4-7 (0 = not masked, 1 = masked)
PR
EL
IM
IN
BETA RELEASE
22
TIO
N.
The DMAC is programmed for transfer. The DMA device requests a transfer by driving the
appropriate DRQ line high. The DMAC responds by asserting AEN and acknowledges the
DMA request through the appropriate DAK line. The I/O and memory command lines are
also asserted. When the DMA device sees the DAK signal, it drops the DRQ line.
__
___|
__
|___|
__
|___|
__
|__|
_______
DRQx
_|
__
|___|
__
|___|
|___
RE
BCLK
DI
ST
RI
BU
The DMAC places the memory address on the SA bus (at the same time as the command
lines are asserted), and the device either reads from or writes to memory, depending on the
type of transfer. The transfer count is incremented, and the address
incremented/decremented. DAK is de-asserted. The cpu now once again has control of the
bus, and continues execution until the I/O device is once again ready for transfer. The DMA
device repeats the procedure, driving DRQ high and waiting for DAK, then transferring data.
This continues for a number of cycles equal to the transfer count. When this has been
completed, the DMAC signals the cpu that the DMA transfer is complete via the TC (terminal
count) signal.
|___________________________________
______________________________
____|
_______
DAKx
OT
____________________________
-------<____________________________>------____________
.N
___________
Command Line
(IORC, MRDC)
|___________________|
ET
A
_____________
----------------------<_____________>------____________________________
-------<____________________________>-------
YB
SD0-SD7
(WRITE)
________
|___________________________|
SA0-SA15
SD0-SD7
(READ)
|________
FO
AEN
Block Transfer Mode
AR
The DMAC is programmed for transfer. The device attempting DMA transfer drives the
appropriate DRQ line high. The motherboard responds by driving AEN high and DAK low.
This indicates that the DMA device is now the bus master. In response to the DAK signal,
the DMA device drops DRQ. The DMAC places the address for DMA transfer on the
address bus. Both the memory and I/O command lines are asserted (since DMA involves
both an I/O and a memory device). AEN prevents I/O devices from responding to the I/O
command lines, which would not result in proper operation since the I/O lines are active, but
a memory address is on the address bus. The data transfer is now done (memory read or
write), and the DMAC increments/decrements the address and begins another cycle. This
continues for a number of cycles equal to the DMAC transfer count. When this has been
completed, the terminal count signal (TC) is generated by the DMAC to inform the cpu that
the DMA transfer has been completed.
PR
EL
IM
IN
Single Transfer Mode
Note: Block transfer must be used carefully. The bus cannot be used for other things (like
RAM refresh) while block mode transfers are being done.
Demand Transfer Mode
BETA RELEASE
23
BU
TIO
N.
The DMAC is programmed for transfer. The device attempting DMA transfer drives the
appropriate DRQ line high. The motherboard responds by driving AEN high and DAK low.
This indicates that the DMA device is now the bus master. Unlike single transfer and block
transfer, the DMA device does not drop DRQ in response to DAK. The DMA device transfers
data in the same manner as for block transfers. The DMAC will continue to generate DMA
cycles as long as the I/O device asserts DRQ. When the I/O device is unable to continue the
transfer (if it no longer had data ready to transfer, for example), it drops DRQ and the cpu
once again has control of the bus. Control is returned to the DMAC by once again asserting
DRQ. This continues until the terminal count has been reached, and the TC signal informs
the cpu that the transfer has been completed.
ST
DI
OT
FO
RE
InterruptDescription
2
Parity Error, Mem Refresh
8
8253 Channel 0 (System Timer)
9
Keyboard
A
Cascade from slave PIC
B
COM2
C
COM1
D
LPT2
E
Floppy Drive Controller
F
LPT1
F
Real Time Clock
F
Redirection to IRQ2
F
Reserved
F
Reserved
F
Mouse Interface
F
Coprocessor
F
Hard Drive Controller
F
Reserved
.N
Name
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
RI
Interrupts on the ISA bus
IRQ0,1,2,8, and 13 are not available on the ISA bus.
YB
ET
A
The IBM PC and XT had only a single 8259 interrupt controller. The AT and later machines
have a second interrupt controller, and the two are used in a master/slave combination.
IRQ2 and IRQ9 are the same pin on most ISA systems. Interrupts on most systems may be
either edge triggered or level triggered. The default is usually edge triggered, and active high
(low to high transition). The interrupt level must be held high until the first interrupt
acknowledge cycle (two interrupt acknowledge bus cycles are generated in response to an
interrupt request).
AR
The software aspects of interrupts and interrupt handlers is intentionally omitted from this
document, due to the numerous syntactical differences in software tools and the fact that
adequate documentation of this topic is usually provided with developement software.
Bus Mastering:
PR
EL
IM
IN
An ISA device may take control of the bus, but this must be done with caution. There are no
safety mechanisms involved, and so it is easily possible to crash the entire system by
incorrectly taking control of the bus. For example, most systems require bus cycles for
DRAM refresh. If the ISA bus master does not relinquish control of the bus or generate its
own DRAM refresh cycles every 15 microseconds, the system RAM can become corrupted.
The ISA adapter card can generate refresh cycles without relinquishing control of the bus by
asserting REFRESH. MRDC can be then monitored to determine when the refresh cycle
ends.
To take control of the bus, the device first asserts its DRQ line. The DMAC sends a hold
request to the cpu, and when the DMAC receives a hold acknowledge, it asserts the
appropriate DAK line corresponding to the DRQ line asserted. The device is now the bus
master. AEN is asserted, so if the device wishes to access I/O devices, it must assert
MASTER16 to release AEN. Control of the bus is returned to the system board by releasing
BETA RELEASE
24
DRQ.
TIO
N.
BU
Sources: Mark Sokos ISA page <http://www.gl.umbc.edu/~msokos1/isa.txt>

Sources: "ISA System Architecture, 3rd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40996-8
Sources: "Eisa System Architecture, 2nd Edition" by Tom Shanley and Don Anderson ISBN 0-201-40995-X
Sources: "Microcomputer Busses" by R.M. Cram ISBN 0-12-196155-9
Sources: HelpPC v2.10 Quick Reference Utility, by David Jurgens
Sources: ZIDA 80486 Mother Board User's Manual, OPTi 486, 82C495sx
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
PR
EL
IM
IN
Contributor: Joakim gren, Niklas Edmundsson <nikke@ing.umu.se> , Mark Sokos <msokos1@gl.umbc.edu> ,

Pieter Hollants <fxmts205@rz.uni-frankfurt.de>
BETA RELEASE
25
EISA Connector
TIO
N.
EISA
DI
ST
RI
BU
+---------------------------------------------+
|
(component side)
|
|
|
|___________ ISA-16bit __
ISA-8bit
__|
||||||||||| ||||||||||||||||||| A1(front)/B1(back)
| | | | |
| | | | | | | | | EISA: E1(front)/F1(back)
C1/D1
G1/H1
A,C,E,G=Component Side
A,B,F,H=Sold Side
RE
(At the computer)

62+38 PIN EDGE CONNECTOR at the computer.
Name
CMD#
START#
EXRDY
EX32#
GND
KEY
EX16#
SLBURST#
MSBURST#
W/R#
GND
RES
RES
RES
GND
KEY
BE1#
LA31#
GND
LA30#
LA28#
LA27#
LA25#
GND
KEY
LA15
LA13
LA12
LA11
GND
LA9
Description
Command Phase
Start Phase
EISA Ready
EISA Slave Size 32
Ground
Access Key
EISA Slave Size 16
Slave Burst
Master Burst
Write/Read
Ground
Reserved
Reserved
Reserved
Ground
Access Key
Byte Enable 1
Latchable Addressline 31
Ground
Ground
Access Key
Ground
F1
F2
F3
F4
F5
GND
+5V
+5V
-----
Ground
+5 VDC
+5 VDC
AR
YB
ET
A
.N
OT
FO
Pin
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
PR
EL
IM
IN
EISA=Extended Industry Standard Architecture.

Developed by Compaq, AST, Zenith, Tandy...
BETA RELEASE
26
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
TIO
N.
Ground
Ground
Access Key
Data 17
Data 19
Data 20
Data 22
Ground
Data 25
Data 26
Data 28
Access Key
Ground
Data 30
Data 31
Master Request
BU
LA7
GND
LA4
LA3
GND
KEY
D17
D19
D20
D22
GND
D25
D26
D28
KEY
GND
D30
D31
MREQx
RI
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
AR
YB
ET
A
.N
OT
FO
+12 VDC
Memory/Input-Output
Lock bus
Reserved
Ground
Reserved
Byte Enable 3
Access Key
Byte Enable 2
Byte Enable 0
Ground
+5 VDC
Ground
Access Key
+5 VDC
+5 VDC
Ground
ST
Access Key
DI
KEY
----+12V
M/IO#
LOCK#
RES
GND
RES
BE3#
KEY
BE2#
BE0#
GND
+5V
LA29#
GND
LA26#
LA24#
KEY
LA16
LA14
+5V
+5V
GND
LA10
EISA Connector
RE
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
PR
EL
IM
IN
LA8
LA6
LA5
+5V
LA2
KEY
D16
D18
GND
D21
D23
D24
GND
+5 VDC
Access Key
Data 16
Data 18
Ground
Data 21
Data 23
Data 24
Ground
BETA RELEASE
27
D27
KEY
D29
+5V
+5V
MAKx
Data 27
Access Key
Data 29
+5 VDC
+5 VDC
Master Acknowledge
TIO
N.
H14
H15
H16
H17
H18
H19
EISA Connector
Contributor: Joakim gren, Mark Sokos <msokos1@gl.umbc.edu>
RI
BU
Sources: Mark Sokos EISA page <http://www.gl.umbc.edu/~msokos1/eisa.txt>

Sources: "Eisa System Architecture, 2nd Edition" by Tom Shanley and Don Anderson, ISBN 0-201-40995-X
Sources: comp.sys.ibm.pc.hardware.* FAQ Part 4
<ralf@alum.wpi.edu>
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
PR
EL
IM
IN
BETA RELEASE
28
EISA (Technical)
This file is intended to provide a basic functional overview of the EISA Bus, so that hobbyists
and amateurs can design their own EISA compatible cards.
BU
It is not intended to provide complete coverage of the EISA standard.
ST
RI
EISA is an acronym for Extended Industry Standard Architecture. It is an extension of the

ISA architecture, which is a standardized version of the bus originally developed by IBM for
their PC computers. EISA is upwardly compatible, which means that cards originally
designed for the 8 bit IBM bus (often referred to as the XT bus) and cards designed for the
16 bit bus (referred to as the AT bus, and also as the ISA bus), will work in an EISA slot.
EISA specific cards will not work in an AT or an XT slot.
RE
DI
The EISA connector uses multiple rows of connectors. The upper row is the same as a
regular ISA slot, and the lower row contains the EISA extension. The slot is keyed so that
ISA cards cannot be inserted to the point where they connect with the EISA signals.
Signal Descriptions
+5, -5, +12, -12
FO
Power supplies. -5 is often not implemented.
AEN
OT
Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O
device from responding to the I/O command lines during a DMA transfer.
BALE
ET
A
.N
Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The
address on the SA bus is valid from the falling edge of BALE to the end of the bus cycle.
Memory devices should latch the LA bus on the falling edge of BALE.
BCLK
YB
Bus Clock, 33% Duty Cycle. Frequency Varies. 8.33 MHz is specified as the maximum, but
many systems allow this clock to be set to 10 MHz and higher.
BE(x)
CHCHK
AR
Byte Enable. Indicates to the slave device which bytes on the data bus contain valid data. A
16 bit transfer would assert BE0 and BE1, for example, but not BE2 or BE3.
Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC,
externally to the processor (of course). Bit 7 of port 70(hex) (enable NMI interrupts) and bit 3
of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach
the cpu.
PR
EL
IM
IN
This section is currently based solely on the work by Mark Sokos.
TIO
N.
EISA (Tech) Connector
CHRDY
Channel Ready. Setting this low prevents the default ready timer from timing out. The slave
device may then set it high again when it is ready to end the bus cycle. Holding this line low
for too long can cause problems on some systems. CHRDY and NOWS should not be used
simultaneously. This may cause problems with some bus controllers.
CMD
BETA RELEASE
29
TIO
N.
Command Phase. This signal indicates that the current bus cycle is in the command phase.
After the start phase (see START), the data is transferred during the CMD phase. CMD
remains asserted from the falling edge of START until the end of the bus cycle.
System Data lines. They are bidrectional and tri-state.
BU
DAKx
DMA Acknowledge.
RI
DRQx
ST
DMA Request.
EX16
RE
DI
EISA Slave Size 16. This is used by the slave device to inform the bus master that it is
capable of 16 bit transfers.
EX32
EISA Slave Size 32. This is used by the slave device to inform the bus master that it is
capable of 32 bit transfers.
FO
EXRDY
EISA Ready. If this signal is asserted, the cycle will end on the next rising edge of BCLK.
The slave device drives this signal low to insert wait states.
OT
IO16
.N
I/O size 16. Generated by a 16 bit slave when addressed by a bus master.
I/O Read Command line.
IOWC
I/O Write Command line.
YB
IRQx
ET
A
IORC
Interrupt Request. IRQ2 has the highest priority.
AR
LAxx
Latchable Address lines.
LOCK
PR
EL
IM
IN
SD0-SD16
Asserting this signal prevents other bus masters from requesting control of the bus.
MAKx
Master Acknowledge for slot x: Indicates that the bus master request (MREQx) has been
granted.
MASTER16
16 bit bus master. Generated by the ISA bus master when initiating a bus cycle.
M/IO
BETA RELEASE
30
TIO
N.
Memory/Input-Output. This is used to indicate whether the current bus cycle is a memory or
an I/O operation.
M16
BU
MRDC
Memory Read Command line.
RI
MREQx
ST
Master Request for Slot x: This is a slot specific request for the device to become the bus
master.
MSBURST
RE
DI
Master Burst. The bus master asserts this signal in response to SLBURST. This tells the
slave device that the bus master is also capable of burst cycles.
MWTC
Memory Write Command line.
NOWS
OT
FO
No Wait State. Used to shorten the number of wait states generated by the default ready
timer. This causes the bus cycle to end more quickly, since wait states will not be inserted.
Most systems will ignore NOWS if CHRDY is active (low). However, this may cause
problems with some bus controllers, and both signals should not be active simultaneously.
OSC
.N
Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies.
ET
A
REFRESH
Refresh. Generated when the refresh logic is bus master.
RESDRV
YB
This signal goes low when the machine is powered up. Driving it low will force a system
reset.
SA0-SA19
SBHE
AR
System Address Lines, tri-state.
PR
EL
IM
IN
Memory Access, 16 bit
System Bus High Enable, tristate. Indicates a 16 bit data transfer.
SLBURST
Slave Burst. The slave device uses this to indicate that it is capable of burst cycles. The bus
master will respond with MSBURST if it is also capable of burst cycles.
SMRDC
Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area.
SMWTC
Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area.
BETA RELEASE
31
START
TIO
N.
TC
BU
Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete.
W/R
ST
RI
Write or Read. Used to indicate if the current bus cycle is a read or a write operation.
Sources: Mark Sokos EISA page <http://www.gl.umbc.edu/~msokos1/eisa.txt>
Sources: "Eisa System Architecture, 2nd Edition" by Tom Shanley and Don Anderson, ISBN 0-201-40995-X
AR
YB
ET
A
.N
OT
FO
RE
DI
PR
EL
IM
IN
Start Phase. This signal is low when the current bus cycle is in the start phase. Address and
M/IO signals are decoded during this phase. Data is transferred during the command phase
(indicated by CMD).
BETA RELEASE
32
PCI Connector
TIO
N.
PCI
RE
DI
ST
RI
BU
PCI Universal Card 32/64 bit

---------------------------------------------------------------|
PCI
Component Side (side B)
|
|
|
|
|
|
optional
|
|
____
mandatory 32-bit pins
64-bit pins _____|
|___|
|||||||--|||||||||||||||||--|||||||--||||||||||||||
^
^ ^
^ ^
^ ^
^
b01
b11 b14
b49 b52 b62 b63
b94
PCI 5V Card 32/64 bit
|
optional
|
|
____
64-bit pins _____|
|___|
||||||||||||||||||||||||||--|||||||--||||||||||||||
PCI 3.3V Card 32/64 bit
|
optional
|
|
____
64-bit pins _____|
|___|
|||||||--||||||||||||||||||||||||||--||||||||||||||
FO
(At the computer)

Universal Description
Test Logic Reset
+12 VDC
Test Mde Select
Test Data Input
+5 VDC
Interrupt A
Interrupt C
+5 VDC
Reserved VDC
+3.3V Signal Rail +V I/O (+5 V or +3.3 V)
Reserved VDC
(OPEN) (OPEN)
Ground or Open (Key)
(OPEN) (OPEN)
Reserved VDC
Reset
Grant PCI use
Ground
Reserved VDC
Address/Data 30
+3.3 VDC
Address/Data 28
Address/Data 26
Ground
Address/Data 24
Initialization Device Select
+3.3 VDC
Address/Data 22
Address/Data 20
Ground
Address/Data 18
ET
A
.N
OT
+3.3V
YB
+5V
TRST
+12V
TMS
TDI
+5V
INTA
INTC
+5V
RESV01
+5V
RESV03
GND03
GND05
RESV05
RESET
+5V
GNT
GND08
RESV06
AD30
+3.3V01
AD28
AD26
GND10
AD24
IDSEL
+3.3V03
AD22
AD20
GND12
AD18
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
PR
EL
IM
IN
PCI=Peripheral Component Interconnect
BETA RELEASE
33
Address/Data 16
+3.3 VDC
Address or Data phase
Ground
Target Ready
Ground
Stop Transfer Cycle
+3.3 VDC
Snoop Done
Snoop Backoff
Ground
Parity
Address/Data 15
+3.3 VDC
Address/Data 13
Address/Data 11
Ground
Address/Data 9
Command, Byte Enable 0
+3.3 VDC
Address/Data 6
Address/Data 4
Ground
Address/Data 2
Address/Data 0
Signal Rail +V I/O (+5 V or +3.3 V)
Request 64 bit ???
+5 VDC
+5 VDC
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
GND
C/BE[7]#
C/BE[5]#
+5V
+3.3V
PAR64
AD62
GND
AD60
AD58
GND
AD56
AD54
+5V
+3.3V
AD52
AD50
GND
AD48
AD46
GND
AD44
AD42
+5V
+3.3V
AD40
AD38
GND
AD36
AD34
GND
AD32
RES
Ground
Parity 64 ???
Address/Data 62
Ground
Address/Data 60
Address/Data 58
Ground
Address/Data 56
Address/Data 54
Address/Data 52
Address/Data 50
Ground
Address/Data 48
Address/Data 46
Ground
Address/Data 44
Address/Data 42
Address/Data 40
Address/Data 38
Ground
Address/Data 36
Address/Data 34
Ground
Address/Data 32
Reserved
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
BU
AD16
+3.3V05
FRAME
GND14
TRDY
GND15
STOP
+3.3V07
SDONE
SBO
GND17
PAR
AD15
+3.3V10
AD13
AD11
GND19
AD9
C/BE0
+3.3V11
AD6
AD4
GND21
AD2
AD0
+5V
+3.3V
REQ64
VCC11
VCC13
TIO
N.
PCI Connector
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
PR
EL
IM
IN
BETA RELEASE
34
OT
FO
RE
DI
ST
RI
BU
-12 VDC
Test Clock
Ground
Test Data Output
+5 VDC
+5 VDC
Interrupt B
Interrupt D
Reserved
+V I/O (+5 V or +3.3 V)
??
(OPEN) (OPEN)
(OPEN) (OPEN)
Reserved VDC
Reset
Clock
Ground
Request
Address/Data 31
Address/Data 29
Ground
Address/Data 27
Address/Data 25
+3.3VDC
Address/Data 23
Ground
Address/Data 21
Address/Data 19
+3.3 VDC
Address/Data 17
Ground
Initiator Ready
+3.3 VDC
Device Select
Ground
Lock bus
Parity Error
+3.3 VDC
System Error
+3.3 VDC
Address/Data 14
Ground
Address/Data 12
Address/Data 10
Ground
GND
(OPEN)
GND
(OPEN)
Address/Data 8
Address/Data 7
+3.3 VDC
Address/Data 5
Address/Data 3
Ground
.N
-12V
TCK
GND
TDO
+5V
+5V
INTB
INTD
PRSNT1
RES
PRSNT2
GND
GND
RES
GND
CLK
GND
REQ
+5V
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2
GND13
IRDY
+3.3V06
DEVSEL
GND16
LOCK
PERR
+3.3V08
SERR
+3.3V09
C/BE1
AD14
GND18
AD12
AD10
GND20
(OPEN)
(OPEN)
AD8
AD7
+3.3V12
AD5
AD3
GND22
ET
A
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
TIO
N.
Ground
Reserved
YB
GND
RES
AR
A93
A94
PCI Connector
PR
EL
IM
IN
BETA RELEASE
35
RE
DI
ST
RI
BU
Reserved
Ground
Ground
Address/Data 63
Address/Data 61
Address/Data 59
Address/Data 57
Ground
Address/Data 55
Address/Data 53
Ground
Address/Data 51
Address/Data 49
Address/Data 47
Address/Data 45
Ground
Address/Data 43
Address/Data 41
Ground
Address/Data 39
Address/Data 37
Address/Data 35
Address/Data 33
Ground
Reserved
Reserved
Ground
FO
RES
GND
C/BE[6]#
C/BE[4]#
GND
AD63
AD61
+5V
+3.3V
AD59
AD57
GND
AD55
AD53
GND
AD51
AD49
+5V
+3.3V
AD47
AD45
GND
AD43
AD41
GND
AD39
AD37
+5V
+3.3V
AD35
AD33
GND
RES
RES
GND
OT
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
TIO
N.
Address/Data 1
+5 VDC
Acknowledge 64 bit ???
+5 VDC
+5 VDC
.N
AD1
VCC08
ACK64
VCC10
VCC12
ET
A
B58
B59
B60
B61
B62
PCI Connector
YB
Notes: Pin 63-94 exists only on 64 bit PCI implementations.

+V I/O is 3.3V on 3.3V boards, 5V on 5V boards, and define signal rails on the Universal
board.
Source: ?
AR
Contributor: Joakim gren, Phil Toms <ptoms@m4.com>
PR
EL
IM
IN
BETA RELEASE
36
PCI (Technical)
ST
RI
BU
This file is not intended to be a thorough coverage of the PCI standard. It is for informational
purposes only, and is intended to give designers and hobbyists an overview of the bus so
that they might be able to design their own PCI cards. Thus, I/O operations are explained in
the most detail, while memory operations, which will usually not be dealt with by an I/O card,
are only briefly explained. Hobbyists are also warned that, due to the higher clock speeds
involved, PCI cards are more difficult to design than ISA cards or cards for other slower
busses. Many companies are now making PCI prototyping cards, and, for those fortunate
enough to have access to FPGA programmers, companies like Xilinx are offering PCI
compliant designs which you can use as a starting point for your own projects.
For a copy of the full PCI standard, contact:
RE
DI
PCI Special Interest Group (SIG)

PO Box 14070
Portland, OR 97214
1-800-433-5177
1-503-797-4207
FO
AD(x)
Address/Data Lines.
OT
CLK
Clock. 33 MHz maximum.
.N
C/BE(x)
ET
A
Command, Byte Enable.
FRAME
Used to indicate whether the cycle is an address phase or a data phase.
YB
DEVSEL
Device Select.
AR
IDSEL
INT(x)
PR
EL
IM
IN
TIO
N.
PCI (Tech) Connector
Interrupt
IRDY
Initiator Ready
LOCK
Used to manage resource locks on the PCI bus.
REQ
Request. Requests a PCI transfer.
BETA RELEASE
37
GNT
TIO
N.
Grant. indicates that permission to use PCI is granted.
Parity. Used for AD0-31 and C/BE0-3.
BU
PERR
Parity Error.
RI
RST
ST
Reset.
SBO
DI
Snoop Backoff.
RE
SDONE
Snoop Done.
SERR
FO
System Error. Indicates an address parity error for special cycles or a system error.
STOP
OT
Asserted by Target. Requests the master to stop the current transfer cycle.
TCK
.N
Test Clock
TDI
ET
A
Test Data Input
TDO
TMS
TRDY
Target Ready
AR
Test Mode Select
YB
Test Data Output
PR
EL
IM
IN
PAR
TRST
Test Logic Reset
The PCI bus treats all transfers as a burst operation. Each cycle begins with an address
phase followed by one or more data phases. Data phases may repeat indefinitely, but are
limited by a timer that defines the maximum amount of time that the PCI device may control
the bus. This timer is set by the CPU as part of the configuration space. Each device has its
own timer (see the Latency Timer in the configuration space).
The same lines are used for address and data. The command lines are also used for byte
enable lines. This is done to reduce the overall number of pins on the PCI connector.
The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address
phase.
BETA RELEASE
38
ST
RI
BU
TIO
N.
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
reserved
reserved
Memory Read
Memory Write
reserved
reserved
Configuration Read
Configuration Write
Multiple Memory Read
Dual Address Cycle
Memory-Read Line
Memory Write and Invalidate
DI
C/BE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
RE
The three basic types of transfers are I/O, Memory, and Configuration.
___
___|
___
|___|
___
|___|
FO
___
CLK
|___|
_______
___
|___|
___
|___|
|___
_________
|_________________________________|
OT
FRAME
PCI timing diagrams:
______ _______ ______ ______ ______

-------<______><_______><______><______><______>--Address Data1
Data2
Data3
Data4
C/BE
______ _______________________________
-------<______><_______________________________>--Command
Byte Enable Signals
____________
IRDY
ET
A
.N
AD
___
|_________________________________|
_____________
___
|________________________________|
YB
TRDY
______________
___
|_______________________________|
AR
DEVSEL
PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of
CLK.
PR
EL
IM
IN
___
CLK
___|
[1]
|___|
___
___
|___|
[2]
[3]
___
___
___
___
|___|
|___|
|___|
|___|
|__
___
|___|
_______
FRAME
_________
|________________________________________________|
AD
A
B
C
______
______________ ______ _____________
-------<______>---------<______________><______><_____________>--Address
Data1
Data2
Data3
C/BE
______ ______________________________________________
-------<______><______________________________________________>--Command
Byte Enable Signals
BETA RELEASE
39

Wait
_____
IRDY
|__________________________________|
Wait
______________________
|_______|
___
|_______________________|
______________
___
|______________________________________________|
BU
DEVSEL
RI
PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points
labelled A, B, and C.
ST
Bus Cycles:
Interrupt Acknowledge (0000)
Description
Processor Shutdown
Processor Halt
x86 Specific Code
Reserved
FO
AD15-AD0
0x0000
0x0001
0x0002
0x0003 to 0xFFFF
Special Cycle (0001)
RE
DI
The interrupt controller automatically recognizes and reacts to the INTA (interrupt
acknowledge) command. In the data phase, it transfers the interrupt vector to the AD lines.
OT
I/O Read (0010) and I/O Write (0011)
ET
A
.N
Input/Output device read or write operation. The AD lines contain a byte address (AD0 and
AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of address
space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O space, which
is further limited by some ISA cards that may also be installed in the machine (many ISA
cards only decode the lower 10 bits of address space, and thus mirror themselves
throughout the 16 bit I/O space). This limit assumes that the machine supports ISA or EISA
slots in addition to PCI slots.
YB
The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and
0x0CFC (Data). The address port must be written first.
Memory Read (0110) and Memory Write (0111)
AR
A read or write to the system memory space. The AD lines contain a doubleword address.
AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which
bytes are valid.
Configuration Read (1010) and Configuration Write (1011)
PR
EL
IM
IN
TRDY
Wait
______
___
|_______|
TIO
N.
____________
A read or write to the PCI device configuration space, which is 256 bytes in length. It is
accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword
address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the
remaining AD lines are not used.
Address
Bit 32
16
15
00
04
08
0C
10-24
28
2C
30
Unit ID
| Manufacturer ID
Status
| Command
Class Code
| Revision
BIST | Header | Latency | CLS
Base Address Register
Reserved
Reserved
Expansion ROM Base Address
BETA RELEASE
40

Reserved
Reserved
MaxLat|MnGNT
| INT-pin | INT-line
available for PCI unit
TIO
N.
34
38
3C
40-FF
BU
This is an extension of the memory read bus cycle. It is used to read large blocks of memory
without caching, which is beneficial for long sequential memory accesses.
Dual Address Cycle (1101)
DI
ST
RI
Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical
address exists. The least significant portion of the address is placed on the AD lines first,
followed by the most significant 32 bits. The second address cycle also contains the
command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O
address space, although this is not available on Intel based PCs due to limitations of the
CPU.
RE
Memory-Read Line (1110)
This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a
cache line. It is more efficient than normal memory read bursts for a long series of sequential
memory accesses.
FO
Memory Write and Invalidate (1111)
Bus Arbitration:
.N
This section is under construction.
OT
This indicates that a minimum of one cache line is to be transferred. This allows main
memory to be updated, saving a cache write-back cycle.
PCI BIOS:
ET
A
This section is under construction.
YB
Sources: Mark Sokos PCI page <http://www.gl.umbc.edu/~msokos1/pci.txt>

Sources: "Inside the PCI Local Bus" by Guy W. Kendall, Byte, February 1994 v 19 p. 177-180
Sources: "The Indispensible PC Hardware Book" by Hans-Peter Messmer, ISBN 0-201-8769-3
AR
PR
EL
IM
IN
Multiple Memory Read (1100)
BETA RELEASE
41
VESA LocalBus (VLB) Connector
TIO
N.
VESA LocalBus (VLB)
BU
RI
ST
DI
RE
(At the
FO
card)
(At the computer)
ET
A
.N
Description
Data 1
Data 3
Ground
Data 5
Data 7
Data 9
Data 11
Data 13
Data 15
Ground
Data 17
+5 VDC
Data 19
Data 21
Data 23
Data 25
Ground
Data 27
Data 2
Data 31
Address 30
Address 28
Address 26
Ground
Address 24
Address 22
+5 VDC
Address 20
YB
Name
D1
D3
GND
D5
D7
D9
D11
D13
D15
GND
D17
Vcc
D19
D21
D23
D25
GND
D27
D29
D31
A30
A28
A26
GND
A24
A22
VCC
A20
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
OT
58 PIN EDGE CONNECTOR MALE at the card.

58 PIN EDGE CONNECTOR FEMALE at the computer.
PR
EL
IM
IN
VLB=VESA Local Bus.

VESA=Video Electronics Standards Association.
BETA RELEASE
42
A18
A16
A14
A12
A10
A8
GND
A6
A4
WBACK#
BE0#
VCC
BE1#
BE2#
GND
BE3#
ADS#
Address 18
Address 16
Address 14
Address 12
Address 10
Address 8
Ground
Address 6
Address 4
Write Back
Byte Enable 0
+5 VDC
Byte Enable 1
Byte Enable 2
Ground
Byte Enable 3
Address Strobe
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
LRDY#
LDEV
LREQ
GND
LGNT
VCC
ID2
ID3
ID4
LKEN#
LEADS#
Local Ready
Local Device
Local Request
Ground
Local Grant
+5 VDC
Identification 2
Identification 3
Identification 4
Local Enable Address Strobe
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
D0
D2
D4
D6
D8
GND
D10
D12
VCC
D14
D16
D18
D20
GND
D22
D24
D26
D28
D30
VCC
A31
GND
A29
A27
A25
A23
A21
A19
GND
A17
Data 0
Data 2
Data 4
Data 6
Data 8
Ground
Data 10
Data 12
+5 VDC
Data 14
Data 16
Data 18
Data 20
Ground
Data 22
Data 24
Data 26
Data 28
Data 30
+5 VDC
Address 31
Ground
Address 29
Address 27
Address 25
Address 23
Address 21
Address 19
Ground
Address 17
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
BU
TIO
N.
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
PR
EL
IM
IN
BETA RELEASE
43
TIO
N.
BU
OT
RI
Ready Return
Ground
Interrupt 9
Burst Ready
Burst Last
Identification 0
Identification 1
Ground
Local Clock
+5 VDC
Local Bus Size 16
ST
RDYRTN#
GND
IRQ9
BRDY#
BLAST#
ID0
ID1
GND
LCLK
VCC
LBS16#
DI
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
RE
Address 15
+5 VDC
Address 13
Address 11
Address 9
Address 7
Address 5
Ground
Address 3
Address 2
Not connected
Reset
Data/Command
Memory/IO
Write/Read
A15
VCC
A13
A11
A9
A7
A5
GND
A3
A2
n/c
RESET#
DC#
M/IO#
W/R#
FO
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
AR
YB
ET
A
.N
Source: comp.sys.ibm.pc.hardware.* FAQ Part 4

<ralf@alum.wpi.edu>
PR
EL
IM
IN
BETA RELEASE
44
VESA LocalBus (VLB) (Technical)
This file is intended to provide a basic functional overview of the Vesa Local Bus, so that
hobbyists and amateurs can design their own VLB compatible cards.
BU
It is not intended to provide complete coverage of the VLB standard.
VLB Connectors are usually inline with ISA connectors, so that adapter cards may use both.
However, the VLB is separate, and does not need to connect to the ISA portion of the bus.
ST
RI
The 64 bit expansion of the bus (optional) does not add additional pins or connectors.
Instead, it multiplexes the existing pins. The 32 bit VLB bus does not use the 64 bit signals
shown in the above pinouts.
DI
Signal Descriptions
RE
A2-A31
Address Bus
ADS
FO
Address Strobe
BE0-BE3
OT
Byte Enable. Indicates that the 8 data lines corresponding to each signal will deliver valid
data.
BLAST
.N
Burst Last. Indicates a VLB Burst Cycle, which will complete with *BRDY. The VLB Burst
cycle consists of an address phase followed by four data phases.
ET
A
BRDY
Burst Ready. Indicates the end of the current burst transfer.
YB
D0-D31
Data Bus. Valid bytes are indicated by *BE(x) signals.
D/C
M/IO
0
0
0
0
1
1
1
1
D/C
0
0
1
1
0
0
1
1
W/R
0
1
0
1
0
1
0
1
AR
Data/Command. Used with M/IO and W/R to indicate the type of cycle.
INTA sequence
Halt/Special (486)
I/O Read
I/O Write
Instruction Fetch
Halt/Shutdown (386)
Memory Read
Memory Write
PR
EL
IM
IN
TIO
N.
VESA LocalBus (VLB) (Tech) Connector
ID0-ID4
Identification Signals.
ID0 ID1 ID4 CPU Bus WidthBurst
0 0 0 (res)
BETA RELEASE
45
1
0
1
0
1
0
1
(res)
486
486
386
386
(res)
486
16/32
16/32
16/32
16/32
Burst Possible
Read Burst
None
None
16/32/64
Read/Write Burst
TIO
N.
0
1
1
0
0
1
1
BU
0
0
0
1
1
1
1
0 = 1 wait cycle (min)

1 = no wait
ID3 Indicates bus speed: 0 = greater than 33.3 MHz
1 = less than 33.3 MHz
ST
RI
ID2 Indicates wait:
IRQ9
DI
Interrupt Request. Connected to IRQ9 on ISA bus. This allows standalone VLB adapters
(not connected to ISA portion of the bus) to have one IRQ.
RE
LEADS
Local Enable Address Strobe. Set low by VLB master (not CPU). Also used for cache
invalidation signal.
FO
LBS16
Local Bus Size 16. Used by slave device to indicate that it has a transfer width of only 16
bits.
OT
LCLK
.N
Local Clock. Runs at the same frequency as the cpu, up to 50 MHz. 66 MHz is allowed for
on-board devices.
LDEV
ET
A
Local Device: When appropriate address and M/IO signals are present on the bus, the VLB
device must pull this line low to indicate that it is a VLB device. The VLB controller will then
use the VLB bus for the transfer.
YB
LRDY
LGNT
AR
Local Ready. Indicates that the VLB device has completed the cycle. This signal is only used
for single cycle transfers. *BRDY is used for burst transfers.
Local Grant. Indicates that an *LREQ signal has been granted, and control is being
transferred to the new VLB master.
PR
EL
IM
IN
LREQ
Local Request. Used by VLB Master to gain control of the bus.
M/IO
Memory/IO. See D/C for signal description.
RDYRTN
Ready Return. Indicates VLB cycle has been completed. May precede LRDY by one cycle.
RESET
BETA RELEASE
46
Reset. Resets all VLB devices.
TIO
N.
WBACK
64-bit Expansion Signals
BU
ACK64
RI
Acknowledge 64 bit transfer. Indicates that the device can perform the requested 64 bit
transfer cycle.
ST
BE4-BE7
Byte Enable. Indicates which bytes are valid (similar to BE0-BE3).
DI
D32-D63
RE
Upper 32 bits of data bus. Multiplexed with address bus.
LBS64
Local Bus Size 64 bits. Used by VLB Master to indicate that it desires a 64 bit transfer.
FO
W/R
Write/Read. See D/C for signal description.
Address
Phase
_______
___|
Data
Phase
_______
|_______|
____
A2-A31
D34-D63
_______
|_______|
|_______
______________________________________
|_______|
ET
A
*ADS
.N
LCLK
OT
64 Bit Data Transfer Timing Diagram:
_______________ _______________
----<_______________><_______________>------------Address
Data D34-D63
YB
_______________ _______________
D/C
----<_______________><_______________>------------M/IO, W/R
M/IO, W/R
Data D32-33
_____
_____________________________
|_______________|
AR
*LDEV
_____
*LBS64
_____________________________
|_______________|
PR
EL
IM
IN
Write Back.
______
*ACK64
D0-D31
_____________________________
|______________|
_______________
--------------------<_______________>-------------
_____________________
_____________
LRDY
|______________|
Sources: Mark Sokos VLB page <http://www.gl.umbc.edu/~msokos1/vlb.txt>
BETA RELEASE
47
CompactPCI Connector
TIO
N.
CompactPCI
BU
RI
(At the backplane)
ST
(At the device (card))
RE
R
FO
OT
ET
A
.N
Description
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
YB
Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AR
Pin
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Z9
Z10
Z11
Z12
Z13
Z14
Z15
Z16
Z17
Z18
Z19
Z20
Z21
Z22
Z23
Z24
Z25
Z26
Z27
Z28
Z29
Z30
Z31
Z32
Z33
Z34
Z35
Z36
Z37
Z38
Z39
Z40
Z41
DI
7x47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the backplane.

7x47 PIN (IEC917 and IEC1076-4-101) CONNECTOR at the device (card).
PR
EL
IM
IN
PCI=Peripheral Component Interconnect.

CompactPCI is a version of PCI adapted for industrial and/or embedded applications.
BETA RELEASE
48
-12V
5V
INTB#
GND
BRSV
-12 VDC
+5 VDC
Interrupt B
Ground
Bused Reserved (don't use)
TIO
N.
B1
B2
B3
B4
B5
BU
+5 VDC
Test Clock
Interrupt A
Request PCI transfer
Address/Data 30
Address/Data 26
Command: Byte Enable
Address/Data 21
Address/Data 18
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
+3.3 VDC
Device Select
+3.3 VDC
System Error
+3.3 VDC
Address/Data 12
+3.3 VDC
Address/Data 7)
+3.3 VDC
Address/Data 1)
+5 VDC
Clock ?? MHz
Clock ?? MHz
Clock ?? MHz
+3.3 VDC or +5 VDC
Address/Data 63
Address/Data 59
Address/Data 56
Address/Data 52
Address/Data 49
Address/Data 45
Address/Data 42
Address/Data 38
Address/Data 35
User Defined
User Defined
User Defined
User Defined
User Defined
RI
5V
TCK
INTA#
BRSV
BRSV
REQ#
AD(30)
AD(26)
C/BE(3)#
AD(21)
AD(18)
KEY
KEY
KEY
3.3V
DEVSEL#
3.3V
SERR#
3.3V
AD(12)
3.3V
AD(7)
3.3V
AD(1)
5V
CLK1
CLK2
CLK4
V(I/O)
C/BE(5)#
AD(63)
AD(59)
AD(56)
AD(52)
AD(49)
AD(45)
AD(42)
AD(38)
AD(35)
BRSV
BRSV
BRSV
USR
USR
USR
USR
USR
ST
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
DI
Ground
Ground
Ground
Ground
Ground
Ground
RE
GND
GND
GND
GND
GND
GND
AR
YB
ET
A
.N
OT
FO
Z42
Z43
Z44
Z45
Z46
Z47
PR
EL
IM
IN
BETA RELEASE
49
TIO
N.
Test Logic Reset

Test Mode Select
Interrupt C
+3.3 VDC or +5 VDC
Reset
+3.3 VDC
Address/Data 28
+3.3 VDC or +5 VDC
Address/Data 23
+3.3 VDC
Address/Data 16
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Initiator Ready
+3.3 VDC or +5 VDC
Snoop Backoff
BU
TRST#
TMS
INTC#
V(I/O)
RST
3.3V
AD(28)
V(I/O)
AD(23)
3.3V
AD(16)
KEY
KEY
KEY
IRDY#
V(I/O)
SBO#
RI
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
AR
YB
ET
A
.N
OT
FO
Ground
Clock ?? MHz
Ground
Ground
Address/Data 62
Ground
Address/Data 55
Ground
Address/Data 48
Ground
Address/Data 41
Ground
Address/Data 34
Ground
Ground
User Defined
User Defined
User Defined
User Defined
User Defined
ST
Ground
Address/Data 29
Ground
Ground
Address/Data 17
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Snoop Done
Ground
Address/Data 15
Ground
Address/Data 9)
Ground
Address/Data 4)
+5 VDC
DI
GND
AD(29)
GND
IDSEL
GND
AD(17)
KEY
KEY
KEY
FRAME#
GND
SDONE
GND
AD(15)
GND
AD(9)
GND
AD(4)
5V
REQ64#
GND
CLK3
GND
BRSV
GND
AD(62)
GND
AD(55)
GND
AD(48)
GND
AD(41)
GND
AD(34)
GND
BRSV
GND
USR
USR
USR
USR
USR
RE
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
PR
EL
IM
IN
BETA RELEASE
50
+3.3 VDC
Address/Data 14
+3.3 VDC or +5 VDC
Address/Data 8)
+3.3 VDC
Address/Data 3)
+3.3 VDC or +5 VDC
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
+12V
TDO
5V
INTP
GND
CLK
GND
AD(25)
GND
AD(20)
GND
KEY
KEY
KEY
GND
STOP#
GND
PAR
GND
AD(11)
M66EN
AD(6)
5V
AD(0)
3.3V
GNT1#
GNT2#
REQ4#
GND
+12 VDC
Test Data Output
+5 VDC
TIO
N.
3.3V
AD(14)
V(I/O)
AD(8)
3.3V
AD(3)
V(I/O)
BRSV
REQ1#
SYSEN#
GNT3#
C/BE(7)
V(I/O)
AD(61)
V(I/O)
AD(54)
V(I/O)
AD(47)
V(I/O)
AD(40)
V(I/O)
AD(33)
FAL#
DEG#
PRST#
USR
USR
USR
USR
USR
BU
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
ET
A
.N
OT
FO
RE
DI
ST
RI
Grant
+3.3 VDC or +5 VDC
Address/Data 61
+3.3 VDC or +5 VDC
Address/Data 54
+3.3 VDC or +5 VDC
Address/Data 47
+3.3 VDC or +5 VDC
Address/Data 40
+3.3 VDC or +5 VDC
Address/Data 33
Power Supply Status FAL (CompactPCI specific)
Power Supply Status DEG (CompactPCI specific)
Push Button Reset (CompactPCI specific)
User Defined
User Defined
User Defined
User Defined
User Defined
Ground
AR
YB
Ground
Address/Data 25
Ground
Address/Data 20
Ground
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Stop transfer cycle
Ground
Parity for AD0-31 & C/BE0-3
Ground
Address/Data 11
PR
EL
IM
IN
Address/Data 6)
+5 VDC
Address/Data 0)
+3.3 VDC
Grant
Grant
Ground
BETA RELEASE
51
TIO
N.
+5 VDC
Test Data Input
Interrupt D
BU
5V
TDI
INTD#
INTS
GNT#
AD(31)
AD(27)
AD(24)
AD(22)
AD(19)
C/BE(2)#
KEY
KEY
KEY
TRDY#
LOCK#
PERR#
C/BE(1)#
AD(13)
AD(10)
C/BE(0)#
AD(5)
AD(2)
ACK64#
5V
REQ2#
REQ3#
GNT4#
C/BE(6)#
PAR64
AD(60)
AD(57)
AD(53)
AD(50)
AD(46)
AD(43)
AD(39)
AD(36)
AD(32)
GNT5#
BRSV
RI
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
E30
E31
E32
E33
E34
E35
E36
E37
E38
E39
E40
E41
ST

Ground
Address/Data 58
Ground
Address/Data 51
Ground
Address/Data 44
Ground
Address/Data 37
Ground
Ground
User Defined
User Defined
User Defined
User Defined
User Defined
DI
C/BE(4)#
GND
AD(58)
GND
AD(51)
GND
AD(44)
GND
AD(37)
GND
REQ5#
GND
REQ6#
USR
USR
USR
USR
USR
YB
ET
A
.N
OT
FO
Grant
Address/Data 31
Address/Data 27
Address/Data 24
Address/Data 22
Address/Data 19
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Target Ready
Lock resource
Parity Error
Address/Data 13
Address/Data 10
Address/Data 5)
Address/Data 2)
RE
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
AR
+5 VDC
Grant
PR
EL
IM
IN
Address/Data 60
Address/Data 57
Address/Data 53
Address/Data 50
Address/Data 46
Address/Data 43
Address/Data 39
Address/Data 36
Address/Data 32
Grant
BETA RELEASE
52
TIO
N.
BU
RI
ST
DI
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Keyed (no pin)
Keyed (no pin)
Keyed (no pin)
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
RE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
F32
F33
F34
F35
F36
F37
F38
F39
F40
F41
F42
F43
F44
F45
F46
F47
FO
Grant
User Defined
User Defined
User Defined
User Defined
User Defined
OT
GNT6#
USR
USR
USR
USR
USR
AR
YB
ET
A
.N
E42
E43
E44
E45
E46
E47
PR
EL
IM
IN

Sources: CompactPCI specifications v1.0 <http://www.compactpci.com/cspec.htm> at CompactPCI's
homepage <http://www.compactpci.com/>
BETA RELEASE
53
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

BETA RELEASE
54
CompactPCI (Tech) Connector
TIO
N.
CompactPCI (Technical)
Since CompactPCI is based on PCI you should first refer to the PCI standard. This only
explains the extensions CompactPCI specifies.
RI
DI
ST
PCI Industrial Computer Manufacturers Group (PICMG)

c/o Roger Communications
301 Edgewater place
Suite 220
Wakewater
MA01880
Phone: 1-617-224-1100
Fax: 1-617-224-1239
BU
For a copy of the full CompactPCI standard, contact:
RE
Overview:
A CompactPCI system is composed of up to eight CompactPCI card locations:

- One System Slot
- Up to seven Peripheral Slots
OT
FO
The connector has 7 columns with 47 rows. They are divided into groups:
- Row 1-25: 32-bit PCI
- Row 26-47: Additional pins for 64-bit PCI (System Slot boards must use it).
- Row 26-28 and 40-42: Primarily implemented on System Slot boards.
AR
YB
ET
A
.N
The following signals must be terminated:

- AD0-31
- C/BE0#-C/BE3#
- PAR
- FRAME#
- IRDY#
- TRDY#
- STOP#
- LOCK#
- IDSEL
- DEVSEL#
- PERR#
- SERR#
- RST#
PR
EL
IM
IN
This section does not currently contain so much in depth information as I would like.
The following signals must be terminated if used:

- INTA#
- INTB#
- INTC#
- INTD#
- SB0#
- SDOBE
- AD32-AD63
- C/BE4#-C/BE7#
- REQ64#
- ACK64#
BETA RELEASE
55
RI
BU
TIO
N.
The following signals do no require a stub termination:

- CLK
- REQ#
- GNT#
- TDI#
- TDO
- TCK
- TMS
- TRST#
DI
ST
The System Slot board must pullup the following signals (even if not used):
- REQ64#
- ACK64#
FO
12V
DO
5V
INTP
GND
CLK
GND
AD(25)
GND
AD(20)
GND
KEY
KEY
KEY
GND
STOP#
GND
PAR
GND
AD(11)
M66EN
AD(6)
5V
AD(0)
3.3V
GNT1#
GNT2#
REQ4#
GND
C/BE(4)#
GND
AD(58)
GND
AD(51)
GND
AD(44)
GND
AD(37)
GND
REQ5#
OT
TRST#
TMS
INTC#
V(I/O)
RST
3.3V
AD(28)
V(I/O)
AD(23)
3.3V
AD(16)
KEY
KEY
KEY
IRDY#
V(I/O)
SBO#
3.3V
AD(14)
V(I/O)
AD(8)
3.3V
AD(3)
V(I/O)
BRSV
REQ1#
SYSEN#
GNT3#
C/BE(7 )
V(I/O)
AD(61)
V(I/O)
AD(54)
V(I/O)
AD(47)
V(I/O)
AD(40)
V(I/O)
AD(33)
FAL#
.N
-12V
5V
INTB#
GND
BRSV
GND
AD(29)
GND
IDSEL
GND
AS(17)
KEY
KEY
KEY
FRAME#
GND
SDONE
GND
AD(15)
GND
AD(9)
GND
AD(4)
5V
REQ64#
GND
CLK3
GND
BRSV
GND
AD(62)
GND
AD(55)
GND
AD(48)
GND
AD(41)
GND
AD(34)
GND
ET
A
5V
TCK
INTA#
BRSV
BRSV
REQ#
AD(30)
AD(26)
C/BE(3)#
AD(21)
AD(18)
KEY
KEY
KEY
3.3V
DEVSEL#
3.3V
SERR#
3.3V
AD(12)
3.3V
AD(7)
3.3V
AD(1)
5V
CLK1
CLK2
CLK4
V(I/O)
C/BE(5)#
AD(63)
AD(59)
AD(56)
AD(52)
AD(49)
AD(45)
AD(42)
AD(38)
AD(35)
BRSV
YB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RE
Connector:
PR
EL
IM
IN
- PAR64#
5V
TDI
INTD#
INTS
GNT#
AD(31)
AD(27)
AD(24)
AD(22)
AD(19)
C/BE(2)#
KEY
KEY
KEY
TRDY#
LOCK#
PERR#
C/BE(1)#
AD(13)
AD(10)
C/BE(0)#
AD(5)
AD(2)
ACK64#
5V
REQ2#
REQ3#
GNT4#
C/BE(6)#
PAR64
AD(60)
AD(57)
AD(53)
AD(50)
AD(46)
AD(43)
AD(39)
AD(36)
AD(32)
GNT5#
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
KEY
KEY
KEY
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
BETA RELEASE
56
BRSV
BRSV
USR
USR
USR
USR
USR
A
BRSV
GND
USR
USR
USR
USR
USR
B
DEG#
PRST#
USR
USR
USR
USR
USR
C
GND
REQ6#
USR
USR
USR
USR
USR
D
BRSV
GNT6#
USR
USR
USR
USR
USR
E
GND
GND
GND
GND
GND
GND
GND
F
TIO
N.
GND
GND
GND
GND
GND
GND
GND
Z
BU
41
42
43
44
45
46
47
RI
PRST
ST
Push Button Reset.
DEG
DI
Power Supply Status DEG
RE
FAL
Power Supply Status FAL
SYSEN
FO
System Slot Identification
OT
Sources: CompactPCI specifications v1.0 <http://www.compactpci.com/cspec.htm> at CompactPCI's

homepage <http://www.compactpci.com/>
AR
YB
ET
A
.N
Info: CompactPCI - An Open Industrial Computer Standard <http://www.eetoolbox.com/vtc/pavj1/pavjp.htm>

article by Joseph S. Pavlat <jpavlat@prolog.com>
PR
EL
IM
IN
BETA RELEASE
57
IndustrialPCI Connector
TIO
N.
IndustrialPCI (IPCI)
ST
RI
BU
The IPCI connector has three parts:

- Optional 60 pin PCI 64 bit extension (Top)
- Mandatory 120 pin PCI 32 bit (Middle)
- Optional 60 pin Custom I/O (Bottom)
DI
(At the backplane)
RE
UNKNOWN CONNECTOR at the backplane.

UNKNOWN CONNECTOR at the device (card).
Note
ET
A
.N
OT
Description
+3.3 VDC
Address 2
Address 6
Ground
Address 10
Address 13
Ground
Snoop Done
Ground
Indicate Address or Data phase
Address 18
Ground
+5 VDC
Address 24
Address 27
Ground
Request 2
Ground
33 or 66 MHz Clock
YB
Name
+3,3V
AD2
AD6
GND
AD10
AD13
GND
SDONE
GND
FRAME#
AD18
GND
+5V
AD24
AD27
GND
REQ2
GND
CLK1
CLK2
GND
CLK3
CLK4
+3,3V
REQ64#
AD3
+5V
AD8
+3,3V
AD14
PAR
+3,3V
STOP#
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B1
B2
B3
B4
B5
B6
B7
B8
B9
FO
System Slot (Middle)
PR
EL
IM
IN

IndustrialPCI is a version of PCI adapted for industrial and/or embedded applications.
1
1
Ground
+3.3 VDC
Request 64 ???
Address 3
+5 VDC
Address 8
+3.3 VDC
Address 14
Parity
+3.3 VDC
Stop
BETA RELEASE
58
DI
1
1
1
ET
A
.N
OT
FO
RE
Universal Serial Bus (USB)(+)

Acknowledge 64 ???
Ground
Address 7
Address 9
Address 11
Ground
System Error
Parity Error
Device Select
Ground
Address 19
Address 22
Ground
Address 25
Ground
Reserved (1)
Grant 2
Request 4
Sleep/Serial Data (I2C)
Reserved (4)
Interrupt D
Interrupt B
+5 VDC
Universal Serial Bus (USB)(-)
Address 0
Address 4
+3.3 VDC
Address 12
Address 15
+3.3 or +5 VDC
Resource Lock
Test Logic Ready
Address 16
Address 20
+5 VDC
+5 VDC
Address 26
Address 29
Request 1
Request 3
+3.3 or +5 VDC
Reserved (2)
Reserved (5)
+3.3 VDC
ST
:
2
RI
BU
TIO
N.

+3.3 or +5 VDC
Address 21
+3.3 VDC
+3.3 or +5 VDC
Address 28
Address 31
+3.3 VDC
Grant 3
Reset
Non Maskable Interrupt
Reserved (6)
+5 VDC
1
3
1
1
YB
C/BE2#
V(I/O)
AD21
+3,3V
V(I/O)
AD28
AD31
+3,3V
GNT3
RST#
NMI#
X6
+5V
RSTIN#
USB+
ACK64#
GND
AD7
AD9
AD11
GND
SERR#
PERR#
DEVSEL#
GND
AD19
AD22
GND
AD25
GND
X1
GNT2
REQ4
SLEEP#/SDAT
X4
INTD#
INTB#
+5V
USBAD0
AD4
C/BE0#
+3,3V
AD12
AD15
V(I/O)
LOCK#
TRDY#
AD16
AD20
+5V
+5V
AD26
AD29
REQ1
REQ3
V(I/O)
X2
X5
+3,3V
AR
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
PR
EL
IM
IN
1
1
1
1
BETA RELEASE
59
BU
DI
ST
RI
RE
Address 1
Address 5
Ground
Enable 66Mhz PCI-bus
Ground
Snoop Backoff
+5 VDC
Initiator Ready
Address 17
Ground
Address 23
Ground
Address 30
Grant 1
+5 VDC
Grant 4
Reserved (3)
Ground
Interrupt C
-12 VDC
+12 VDC
1
3
TIO
N.
Interrupt A
ICPEN/Serial Clock (I2C)
INTA#
ICPEN#/SCLK
OSC (PWDN)
AD1
AD5
GND
M66EN
GND
C/BE1#
SBO#
+5V
IRDY#
AD17
GND
AD23
C/BE3#
GND
AD30
GNT1
+5V
GNT4
X3
GND
INTC#
-12V
+12V
VBATT
FO
D22
D23
D24
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
OT
1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).

2 = Pullup resistor of 330 ohm on the System Slot (CPU).
3 = Pullup resistor of 4,7 KB ohm, if not supported by the System Slot (CPU).
ET
A
Description
+3.3 VDC
Address 2
Address 6
Ground
Address 10
Address 13
Ground
Snoop Done
Ground
Address 18
Ground
+5 VDC
Address 24
Address 27
Ground
Request 2
YB
Name
+3,3V
AD2
AD6
GND
AD10
AD13
GND
SDONE
GND
FRAME#
AD18
GND
+5V
AD24
AD27
GND
REQ2
CLKM
CLK1
CLK2
GND
CLK3
CLK4
+3,3V
REQ64#
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
B1
.N
Module Bus Slot (Middle)
PR
EL
IM
IN
Note
1
1
33 or 66 MHz Clock
Ground
+3.3 VDC
Request 64 ???
BETA RELEASE
60
TIO
N.
DI
ST
RI
BU
RE
Address 3
+5 VDC
Address 8
+3.3 VDC
Address 14
Parity
+3.3 VDC
Stop
+3.3 or +5 VDC
Address 21
+3.3 VDC
+3.3 or +5 VDC
Address 28
Address 31
+3.3 VDC
Grant 3
Reset
Reserved (6)
+5 VDC
1
1
1
ET
A
.N
OT
FO

Acknowledge 64 ???
Ground
Address 7
Address 9
Address 11
Ground
System Error
Parity Error
Device Select
Ground
Address 19
Address 22
Ground
Address 25
Ground
Reserved (1)
Grant 2
Request 4
Reserved (4)
Interrupt D
Interrupt B
+5 VDC
Address 0
Address 4
+3.3 VDC
Address 12
Address 15
+3.3 or +5 VDC
Resource Lock
Test Logic Ready
Address 16
Address 20
+5 VDC
+5 VDC
YB
AD3
+5V
AD8
+3,3V
AD14
PAR
+3,3V
STOP#
C/BE2#
V(I/O)
AD21
+3,3V
V(I/O)
AD28
AD31
+3,3V
GNT3
RST#
NMI#
X6
+5V
RSTIN#
USB+
ACK64#
GND
AD7
AD9
AD11
GND
SERR#
PERR#
DEVSEL#
GND
AD19
AD22
GND
AD25
GND
X1
GNT2
REQ4
SLEEP#/SDAT
X4
INTD#
INTB#
+5V
USBAD0
AD4
C/BE0#
+3,3V
AD12
AD15
V(I/O)
LOCK#
TRDY#
AD16
AD20
+5V
+5V
AR
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
PR
EL
IM
IN
1
1
1
1
1
BETA RELEASE
61
1
1
DI
ST
RI
BU
1
3
RE
OT
FO
Address 1
Address 5
Ground
Ground
Snoop Backoff
+5 VDC
Initiator Ready
Address 17
Ground
Address 23
Ground
Address 30
Grant 1
+5 VDC
Grant 4
Reserved (3)
Ground
Interrupt C
-12 VDC
+12 VDC
TIO
N.
Address 26
Address 29
Request 1
Request 3
+3.3 or +5 VDC
Reserved (2)
Reserved (5)
+3.3 VDC
Interrupt A
.N
AD26
AD29
REQ1
REQ3
V(I/O)
X2
X5
+3,3V
INTA#
ICPEN#/SCLK
OSC (PWDN)
AD1
AD5
GND
M66EN
GND
C/BE1#
SBO#
+5V
IRDY#
AD17
GND
AD23
C/BE3#
GND
AD30
GNT1
+5V
GNT4
X3
GND
INTC#
-12V
+12V
VBATT
ET
A
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
Name
+3,3V
AD2
AD6
GND
AD10
AD13
GND
SDONE
GND
FRAME#
AD18
GND
+5V
AD24
AD27
GND
IDSEL0
GND
CLK1
Description
+3.3 VDC
Address 2
Address 6
Ground
Address 10
Address 13
Ground
Snoop Done
Ground
Address 18
Ground
+5 VDC
Address 24
Address 27
Ground
IDSEL0
Ground
33 or 66 MHz Clock
Note
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
YB
Card Slot (Middle)
PR
EL
IM
IN
1
1
BETA RELEASE
62
TIO
N.
RE
DI
ST
RI
BU
FO
Ground
Ground
Ground
Ground
+3.3 VDC
Request 64 ???
Address 3
+5 VDC
Address 8
+3.3 VDC
Address 14
Parity
+3.3 VDC
Stop
+3.3 or +5 VDC
Address 21
+3.3 VDC
+3.3 or +5 VDC
Address 28
Address 31
+3.3 VDC
Ground
Reset
Reserved (6)
+5 VDC
ET
A
.N
OT

Acknowledge 64 ???
Ground
Address 7
Address 9
Address 11
Ground
System Error
Parity Error
Device Select
Ground
Address 19
Address 22
Ground
Address 25
Ground
Reserved (1)
Initialization Device Select 1
Ground
Reserved (4)
Interrupt D
Interrupt B
+5 VDC
Address 0
Address 4
+3.3 VDC
Address 12
Address 15
+3.3 or +5 VDC
1
1
1
YB
GND
GND
GND
GND
+3,3V
REQ64#
AD3
+5V
AD8
+3,3V
AD14
PAR
+3,3V
STOP#
C/BE2#
V(I/O)
AD21
+3,3V
V(I/O)
AD28
AD31
+3,3V
GND
RST#
NMI#
X6
+5V
RSTIN#
USB+
ACK64#
GND
AD7
AD9
AD11
GND
SERR#
PERR#
DEVSEL#
GND
AD19
AD22
GND
AD25
GND
X1
IDSEL1
GND
SLEEP#/SDAT
X4
INTD#
INTB#
+5V
USBAD0
AD4
C/BE0#
+3,3V
AD12
AD15
V(I/O)
AR
A20
A21
A22
A23
A24
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
D1
D2
D3
D4
D5
D6
D7
PR
EL
IM
IN
1
1
BETA RELEASE
63
TIO
N.
ST
RI
BU
1
3
RE
1
1
.N
OT
FO
Address 1
Address 5
Ground
Ground
Snoop Backoff
+5 VDC
Initiator Ready
Address 17
Ground
Address 23
Ground
Address 30
Grant 1
+5 VDC
Grant 4
Reserved (3)
Ground
Interrupt C
-12 VDC
+12 VDC
1
1
DI
Resource Lock
Test Logic Ready
Address 16
Address 20
+5 VDC
+5 VDC
Address 26
Address 29
Request 1
Initialization Device Select 2
+3.3 or +5 VDC
Reserved (2)
Reserved (5)
+3.3 VDC
Interrupt A
ET
A
LOCK#
TRDY#
AD16
AD20
+5V
+5V
AD26
AD29
REQ1
IDSEL2
V(I/O)
X2
X5
+3,3V
INTA#
ICPEN#/SCLK
OSC (PWDN)
AD1
AD5
GND
M66EN
GND
C/BE1#
SBO#
+5V
IRDY#
AD17
GND
AD23
C/BE3#
GND
AD30
GNT1
+5V
GNT4
X3
GND
INTC#
-12V
+12V
VBATT
YB
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
AR
64-bit PCI (Top)

Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
Name
GND
X10
AD35
AD38
AD42
V(I/O)
V(I/O)
AD52
AD56
AD60
AD63
GND
X7
Description
Ground
Reserved (10)
Address 35
Address 38
Address 42
+3.3 or +5 VDC
+3.3 or +5 VDC
Address 52
Address 56
Address 60
Address 63
Ground
Reserved (7)
PR
EL
IM
IN
Note
2
2
2
2
2
2
2
BETA RELEASE
64
BU
TIO
N.
2
2
2
2
2
2
2
2
RI
ST
DI
2
2
FO
2
2
2
2
RE
2
2
2
2
2
2
ET
A
.N
OT
Ground
Address 36
Address 39
Address 43
Address 46
Address 49
Address 53
Address 57
Address 61
Ground
Reserved (8)
Address 32
Ground
Address 40
Address 44
Ground
Ground
Address 54
Address 58
Ground
Parity 64 ???
Reserved (9)
Address 33
Address 37
Ground
Address 45
Address 47
Address 50
Address 55
Ground
Address 62
Reserved (11)
Ground
Address 34
+3.3 or +5 VDC
Address 41
Ground
Address 48
Address 51
Ground
Address 59
+3.3 or +5 VDC
Reserved (12)
YB
GND
AD36
AD39
AD43
AD46
AD49
AD53
AD57
AD61
GND
C/BE6#
X8
AD32
GND
AD40
AD44
GND
GND
AD54
AD58
GND
PAR64
C/BE7#
X9
AD33
AD37
GND
AD45
AD47
AD50
AD55
GND
AD62
C/BE4#
X11
GND
AD34
V(I/O)
AD41
GND
AD48
AD51
GND
AD59
V(I/O)
C/BE5#
X12
AR
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
PR
EL
IM
IN
2
2
2
2
2
2
2
2
2 = Pullup resistor of 2,7 kOhm (5V bus system) or 8,2 kOhm (3,3V bus system) on the
backplane.
ISA96/AT96 (Bottom)
Pin
A1
A2
A3
A4
A5
A6
Name
RSTDRV
IRQ9
SD11
SD9
IOCHRDY
IOW#
Description
Note
Interrupt 9
Data 11
Data 9
1
I/O Write
BETA RELEASE
65
ET
A
BU
RI
ST
DI
RE
R
.N
OT
FO
Address 2
Data 15
Data 13
Data 3
Data 1
System Memory Write
Address 18
Address 14
DMA Acknowledge 6
Address 9
Interrupt 3
I/O 16-bit chip select 1
Address 1
Data 7
Data 5
Data 10
Data 8
Address Enable
I/O Read
Address 13
Address 11
Interrupt 5
Address 6
Address 4
Interrupt 11
Data 14
Data 12
Data 2
Data 0
System Memory Read
Address 17
TIO
N.
Address 15
Clock
Address 10
Address 7
Interrupt 7
Address 8
YB
SA15
CLK
SA10
SA7
T/C
SA2
SD15
SD13
SD3
SD1
SMEMW#
SA18
SA14
DACK6#
SA9
IRQ3
IOCS16#
SA1
SD7
SD5
SD10
SD8
AEN
IOR#
SA13
SA11
IRQ5
SA6
SA4
IRQ11
SD14
SD12
SD2
SD0
SMEMR#
SA17
REF#
IRQ7
SA8
MCS16#
BALE
SA0
SD6
SD4
0WS
SBHE#
SA19
SA16
SA12
DRQ6
IRQ4
SA5
SA3
IRQ10
Address 0
Data 6
Data 4
AR
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
Address 19
Address 16
Address 12
DMA Request 6
Interrupt 4
Address 5
Address 3
Interrupt 10
PR
EL
IM
IN
1 = Pullup resistor must be integrated into the System Slot (CPU).
VMEbus (Bottom)
Pin Name
Description
BETA RELEASE
66
BU
TIO
N.
Data 0
Data 2
Data 12
Data 7
RI
Address 14
Address 12
Address 10
DI
ST
Data 10
Data 5
Data 15
ET
A
Address 13
Address 11
Address 9
Data 1
Data 11
Data 6
.N
OT
FO
RE
Address 23
Address 21
Address 19
Address 16
Address 6
Address 4
Address 2
Data 8
Data 3
Data 13
YB
D0
D2
D12
D7
DS1#
BR3#
AM1
AM3
IACKOUT#
A14
A12
A10
BBSY#
D10
D5
D15
SYSRES#
A23
A21
A19
A16
A6
A4
A2
D8
D3
D13
SYSCLK
DS0#
DTACK#
AS#
IACK#
AM4
A13
A11
A9
D1
D11
D6
BG3OUT#
WR#
AM0
AM2
A18
A15
A5
A3
A1
D9
D4
D14
BERR#
AM5
A22
A20
A17
A7
IRQ5#
IRQ3#
A8
Write
Address 18
Address 15
Address 5
Address 3
Address 1
Data 9
Data 4
Data 14
Bus Error
AR
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
PR
EL
IM
IN
Address 22
Address 20
Address 17
Address 7
Interrupt 5
Interrupt 3
Address 8
BETA RELEASE
67
TIO
N.
BU
Description
Data 5
Data 2
Data 4
Address 7
RI
Address 10
RE
DI
ST
Address 13
Reset
Data 0
Data 4
Address 1
Address 17
Not connected
OT
ET
A
.N
Not connected
Data 6
Address 0
Address 5
Address 16
Address 18
FO
Read
Address 12
Address 9
Not connected
Data 7
Address 2
Address 8
YB
Name
D5
D2
A4
A7
BAI
2F
A10
INT#
VCMOS
PWRCLR#
A13
RESET#
D0
D4
A1
WAIT#
A17
IEO
n/c
DMARDY
RD#
IORQ#
?
n/c
D6
A0
A5
A16
A18
BAO
M1#
WR#
n
A12
A9
n/c
D7
A2
A8
BUSRQ#
A19
A11
NMI#
PF
HALT#
RFSH#
MRQ#
n/c
D3
A3
A6
IEI
D1
A14
n/c
n/c
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
Address 19
Address 11
PR
EL
IM
IN
ECB (Bottom)
Not connected
Data 3
Address 3
Address 6
Data 1
Address 14
Not connected
Not connected
BETA RELEASE
68
TIO
N.
DESLCT#
A15
Address 15
BUSAK#
n/c
Not connected
SMP16 (Bottom)
ST
RI
BU
Description
Interrupt 0
Data 11
Data 9
Address 15
RE
DI
Address 10
Address 7
FO
Address 2
Data 15
Data 13
Data 3
Data 1
Address 18
Address 14
.N
ET
A
Address 1
Data 7
Data 5
Data 10
Data 8
OT
Address 9
Interrupt 3
Address 13
Address 11
Interrupt 1
Address 6
Address 4
Interrupt 4
Data 14
Data 12
Data 2
Data 0
YB
Name
NMI#
IRQ0#
D11
D9
RDYIN
IOW#
A15
CLK
A10
A7
TC/EOP#
A2
D15
D13
D3
D1
MEMW#
A18
A14
DACKx#
A9
IRQ3#
IOCS16#
A1
D7
D5
D10
D8
BUSEN
IOR#
A13
A11
IRQ1#
A6
A4
IRQ4#
D14
D12
D2
D0
MEMR#
A17
INTA#
INT#
A8
MECS16#
ALE
A0
D6
D4
MMIO#
BHEN
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
E2
E3
E4
PR
EL
IM
IN
E9
E10
E11
E12
Address 17
Address 8
Address 0
Data 6
Data 4
BETA RELEASE
69
Address 19
Address 16
Address 12
TIO
N.
A19
A16
A12
DRQx#
IRQ2#
A5
A3
IRQ5#
Interrupt 2
Address 5
Address 3
Interrupt 5
BU
E5
E6
E7
E8
E9
E10
E11
E12
ST
DI
RE
R
FO
ET
A
.N
OT
Description
Floppy Select 1
Floppy Select 0
Floppy ?
Floppy Direction
Floppy Step
Floppy Write Data
Floppy Write?
Floppy Track 0
Floppy Write?
Floppy ?
Floppy HD Select
Floppy DiskChange
?
?
IDE ?
IDE ?
IDE ?
IDE ?
IDE ?
IDE Data 14
IDE Data 8
IDE Data 6
IDE Data 11
IDE Data 3
Floppy Me?
Floppy Index
IDE ?
IDE ?
IDE ?
IDE ?
IDE ?
IDE Data 1
IDE ?
IDE Data 10
IDE Data 4
IDE Data 2
IDE LED ?
IDE LED ?
IDE ?
IDE ?
IDE Pull Up ?
IDE ?
IDE Data 15
IDE Data 13
IDE Data 7
Ground
Ground
Ground
YB
Name
FDSEL1
FDSEL0
FDME1
DIR
STEP
WRDATA
WE
TRK0
WP
RDDATA
HDSEL
DSKCHG
DRVDEN1
DRVDEN0
IDECS3P#
IDEA2
IDEIRQS
IDEPUS
IDEDRQP
IDED14
IDED8
IDED6
IDED11
IDED3
FDME0
INDX
IDECS3S#
IDEA0
IDEDAKS#
IDEIOR#
IDEDRQS
IDED1
#IDERST
IDED10
IDED4
IDED2
IDELEDS#
IDELEDP#
IDECS1S#
IDEIRQP
IDEPUP
IDEIOW#
IDED15
IDED13
IDED7
GND
GND
GND
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
RI
Floppy/EIDE (Bottom)
PR
EL
IM
IN
BETA RELEASE
70
TIO
N.
Ground
Ground
IDE ?
IDE ?
IDE ?
IDE ?
IDE Data 0
IDE Data 12
IDE Data 9
IDE Data 5
Ground
Ground
BU
GND
GND
IDECS1P#
IDEA1
IDEDAKP#
IDEIORDY
IDED0
IDED12
IDED9
IDED5
GND
GND
RI
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
DI
Description
RE
Ground
FO
Data 8
Data 9
Data 10
Data 2
Data 4
Ground
.N
ET
A
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
OT
Ground
YB
Name
TERM
GND
I/O#
REQ#
ATN#
D8
D9
D10
D2
D4
DP0
GND
TERM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TERM
GND
C/D#
MSG#
ACK#
D12
DP1
D13
D1
D5
D7
GND
TERM
GND
GND
GND
GND
GND
GND
GND
AR
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
D8
ST
SCSI (Bottom)
Data 12
Data P1
Data 13
Data 1
Data 5
Data 7
Ground
PR
EL
IM
IN
Ground
Ground
Ground
Ground
Ground
Ground
Ground
BETA RELEASE
71
TIO
N.
Ground
Ground
Ground
Ground
BU
Ground
RI
Data 14
Data 15
Data 11
Data 0
Data 3
Data 6
Ground
ST
GND
GND
GND
GND
TERM
GND
SEL#
RST#
BSY#
D14
D15
D11
D0
D3
D6
GND
DI
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
RE
Sources: IndustrialPCI page <http://www.sips.com/ipci.htm> at Standard Industrial PC Systems's (SIPS)

homepage <http://www.sips.com>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
72
SmallPCI Connector
TIO
N.
SmallPCI (SPCI)
BU
UNKNOWN CONNECTOR at the motherboard.

UNKNOWN CONNECTOR at the device.
DI
(At the device)
ST
RI
(At the motherboard)
The specifications can be obtained from:
FO
PCI Special Interest Group

2575 NE Kathryn St. #17
Hillsboro, OR 97124
Phone: 1-800-433-5177
Fax: 1-503-693-8344
RE
I don't have any technical information about SmallPCI at the moment. If you have any
information of value please send it to me.
OT

Source: ?
AR
YB
ET
A
.N
Info: SmallPCI overview <http://www.pcisig.com/current/smallpci.html> at PCI Special Interest Group's

homepage <http://www.pcisig.com>
PR
EL
IM
IN

SmallPCI is a version of PCI adapted for small computers and PDAs.
BETA RELEASE
73
Miniature Card Connector
TIO
N.
Miniature Card
BU
RI
(At the device)
ST
(At the card)
FO
RE
Dir
YB
ET
A
.N
OT
Description
Address Bus
Address Bus
Address Bus
Voltage Refresh
Card Enable High Byte
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Row Address Strobe
Address Bus
Address Bus
Address Bus
Output Enable
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Reserved for future use
Data Bus
Serial Data and Address
Serial Clock
Address Bus
Address Bus
Address Bus
Address Bus
Address Bus
Reset
Address Bus
Voltage Sense 1
Address Bus
Bus Size 8
Address Bus
AR
Pin Name
1 A18
2 A16
3 A14
4 Vccr
5 CEH#
6 A11
7 A9
8 A8
9 A6
10 A5
11 A3
12 A2
13 A0
14 RAS#
15 A24
16 A23
17 A22
18 OE#
19 D15
20 D13
21 D12
22 D10
23 D9
24 D0
25 D2
26 D4
27 RFU
28 D7
29 SDA
30 SCL
31 A19
32 A17
33 A15
34 A13
35 A12
36 RESET#
37 A10
38 VS1#
39 A7
40 BS8#
41 A4
DI

UNKNOWN CONNECTOR at the card.
PR
EL
IM
IN
Developed by Intel.
Miniature Card is a memory-only expansion card.
BETA RELEASE
74
The following three is separate:
TIO
N.
BU
RI
Description Dir
Ground
Power
Card Insertion
Note: Direction is card relative device.
OT
FO
Name
GND
VCC
CINS#
ST
Card Enable Low Byte

Address Bus
Column Address Strobe Low Byte
Column Address Strobe High Byte
Card Detect
Address Bus
Ready/Busy
Write Enable
Data Bus
Data Bus
Voltage Sense 2
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Address Bus
DI
CEL#
A1
CASL#
CASH#
CD#
A21
BUSY#
WE#
D14
RFU
D11
VS2#
D8
D1
D3
D5
D6
RFU
A20
RE
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AR
YB
ET
A
.N
Source: Minicature Card v1.1 spec <http://www.mcif.org/spec.html> at Miniature Card Implementers Forum's
homepage <http://www.mcif.org/spec.html>
PR
EL
IM
IN
BETA RELEASE
75
Miniature Card (Tech) Connector
TIO
N.
Miniature Card (Technical)

BU
A0-A24
ST
RI
Address A0 to A24 are the address bus lines that can address up to 32 Mwords (64 MBytes).
The Miniature Card specification does not require the Miniature Card to decode the upper
address lines. A 2 Mbyte Miniature Card that does not decode the upper address lines would
repeat its address space every 2 Mbytes. Address 0h would access the same physical
location as 200000h, 400000h, 600000h, etc.
D0-D15
DI
Data lines D0 through D15 constitute the data bus. The data bus is composed of two bytes,
the low byte D[7:0] and the high byte D[15:8].
RE
OE#
OE# indicates that the current bus cycle is a read cycle.
WE#
FO
WE# indicates that the current bus cycle is a write cycle.
VS1#
OT
Voltage Sense 1 signal. The card grounds this signal to indicate it can operate at 3.3 Volts.
This signal must either be connected to card GND or left open.
.N
VS2#
ET
A
Voltage Sense 2 signal. The card grounds this signal to indicate it can operate at x.x Volts
(the value to be determined at a later date). This signal must either be connected to card
GND or left open.
CEL#
YB
CEL# enables the low byte of the data bus (D[7:0]) on the card. This signal is not used in
DRAM cards.
CEH#
RAS#
AR
CEH# enables the high byte of the data bus (D[15:8]) on the card. This signal is not used in
DRAM cards.
PR
EL
IM
IN
This section is currently based solely on the Miniature Card specification v1.1.
RAS# strobes in the row address for DRAM cards.
CASL#
CASL# strobes in the low byte column address for DRAM cards.
CASH#
CASH# strobes in the high byte column address for DRAM cards.
RESET#
RESET# controls card initialization. When RESET# transitions from a low state to a high
state, the Miniature Card must reset to a predetermined state.
BETA RELEASE
76
TIO
N.
BU
BUSY# is a signal generated by the card to indicate the status of operations within the
Miniature Card. When BUSY# is high, the Miniature Card is ready to accept the next
command from the host. When BUSY# is low, the Miniature Card is busy and unable to
accept some data operations from the host. For example, in Flash Miniature Cards the
BUSY# signal is tied to the components RY/BY# signal. However, ROM Miniature Cards
would always drive BUSY# high since the host will always be able to read from a ROM
Miniature Card.
RI
Vccr
ST
Vccr provides a low current (refresh) voltage supply. Vccr is a feature used by DRAM
Miniature Cards to "self-refresh" during "sleep" mode.
SDA
DI
I2C: Serial Data/Address.
RE
SCL
I2C: Serial Clock are used to read the attribute information structure (AIS) from the serial
EEPROM in a DRAM card.
CD#
OT
FO
CD# is a grounded interface signal. After a Miniature Card has been inserted, CD# will be
forced low. The card detect signal is located in the center of the second row of interface
signals, and should be one of the last interface signals to connect to the host. Do not
confuse CD# with CINS#. CINS# is an early card detect that is one of the first signals to
connect to the host.
.N
BS8#
ET
A
BS8# is a signal driven by the host to indicate if the data bus is x8 or x16. An 8-bit host must
drive BS8# low and tie the high byte data bus D[15:8] to the low byte data bus D[7:0]. A
16-bit host must drive this signal high.
GND
YB
Ground
Vcc
CINS#
AR
Vcc is used to supply power to the card.
CINS# is a grounded signal on the front of the Miniature Card that can be used for early
detection of a card insertion. CINS# makes contact on the host when the front of the card is
inserted into the socket, before the interface signals connect.
PR
EL
IM
IN
BUSY#

Source: Minicature Card v1.1 spec <http://www.mcif.org/spec.html> at Miniature Card Implementers Forum's
homepage <http://www.mcif.org/spec.html>
BETA RELEASE
77
NuBus Connector
TIO
N.
NuBus
BU
ST
RI
(At the card)
(At the computer)
FO
OT
.N
ET
A
Address/Data 1
Address/Data 3
Address/Data 5
Address/Data 7
Address/Data 9
Address/Data 11
Address/Data 13
Address/Data 15
Address/Data 17
Address/Data 19
Address/Data 21
Address/Data 23
Address/Data 25
Address/Data 27
Address/Data 29
Address/Data 31
Ground
Ground
Description
-12 VDC
YB
Name
-12 V
/SPV
/SP
/TM1
/AD1
/AD3
/AD5
/AD7
/AD9
/AD11
/AD13
/AD15
/AD17
/AD19
/AD21
/AD23
/AD25
/AD27
/AD29
/AD31
GND
GND
/ARB1
/ARB3
/ID1
/ID3
/ACK
+5 V
/RQST
/NMRQ
+12 V
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RE
Row A
DI

UNKNOWN CONNECTOR at the computer.
PR
EL
IM
IN
Available on old Apple Macintosh computers and on NeXT computers.

Standard: IEEE 1196, "Nubus-A simple 32-bit backplane bus".
Texas Instruments owns the standard today.
+5 VDC
+12 VDC
Row B
Pin Name Description

1 -12 V -12 VDC
BETA RELEASE
78
FO
RE
DI
ST
RI
BU
TIO
N.
Ground
Ground
+5 VDC
+5 VDC
+5 VDC
+5 VDC
Reserved ?
Reserved ?
Reserved ?
Reserved ?
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Reserved ?
Reserved ?
Reserved ?
Reserved ?
+5 VDC
+5 VDC
Ground
Ground
OT
GND
GND
+5 V
+5 V
+5 V
+5 V
*
*
*
*
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
**
**
**
**
+5 V
+5 V
GND
GND
+12 V
Row C
+5 VDC
+5 VDC
ET
A
Description
Reset
YB
Name
/RESET
+5 V
+5 V
/TM0
/AD0
/AD2
/AD4
/AD6
/AD8
/AD10
/AD12
/AD14
/AD16
/AD18
/AD20
/AD22
/AD24
/AD26
/AD28
/AD30
GND
/PFW
/ARB0
/ARB2
Address/Data 0
Address/Data 2
Address/Data 4
Address/Data 6
Address/Data 8
Address/Data 10
Address/Data 12
Address/Data 14
Address/Data 16
Address/Data 18
Address/Data 20
Address/Data 22
Address/Data 24
Address/Data 26
Address/Data 28
Address/Data 30
Ground
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
.N
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NuBus Connector
PR
EL
IM
IN
BETA RELEASE
79
/ID0
/ID2
/START
+5 V
+5 V
GND
/CLK
TIO
N.
26
27
28
29
30
31
32
NuBus Connector
+5 VDC
+5 VDC
Ground
Clock
BU
Contributor: Joakim gren, Karsten Wenke <Karsten.Wenke@t-online.de>, Michael Van den Acker
<rdsmv@huntsman.cse.rmit.edu.au>, Godel? <godel@CS.McGill.CA>
RI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
PR
EL
IM
IN
BETA RELEASE
80
NuBus 90 Connector
TIO
N.
NuBus 90
RI
BU
(At the card)
ST
(At the computer)
DI

OT
.N
ET
A
Address/Data 1
Address/Data 3
Address/Data 5
Address/Data 7
Address/Data 9
Address/Data 11
Address/Data 13
Address/Data 15
Address/Data 17
Address/Data 19
Address/Data 21
Address/Data 23
Address/Data 25
Address/Data 27
Address/Data 29
Address/Data 31
Ground
Ground
FO
Description
-12 VDC
YB
Name
-12 V
SB0
/SPV
/SP
/TM1
/AD1
/AD3
/AD5
/AD7
/AD9
/AD11
/AD13
/AD15
/AD17
/AD19
/AD21
/AD23
/AD25
/AD27
/AD29
/AD31
GND
GND
/ARB1
/ARB3
/ID1
/ID3
/ACK
+5 V
/RQST
/NMRQ
+12 V
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RE
Row A
PR
EL
IM
IN
Available on old Apple Macintosh computers.
+5 VDC
+12 VDC
Row B
Pin
1
2
3
Name
-12 V
GND
GND
Description
-12 VDC
Ground
Ground
BETA RELEASE
81
TIO
N.
+5 VDC
+5 VDC
+5 VDC
+5 VDC
RE
DI
ST
RI
BU
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
+5 VDC
+5 VDC
Ground
Ground
+12 VDC
FO
+5 V
+5 V
+5 V
+5 V
/TM2
/CM0
/CM1
/CM2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
/CLK2X
STDBYPWR
/CLK2XEN
/CBUSY
+5 V
+5 V
GND
GND
+12 V
OT
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
+5 VDC
+5 VDC
ET
A
Description
Reset
YB
Address/Data 0
Address/Data 2
Address/Data 4
Address/Data 6
Address/Data 8
Address/Data 10
Address/Data 12
Address/Data 14
Address/Data 16
Address/Data 18
Address/Data 20
Address/Data 22
Address/Data 24
Address/Data 26
Address/Data 28
Address/Data 30
Ground
AR
Name
/RESET
SB1
+5 V
+5 V
/TM0
/AD0
/AD2
/AD4
/AD6
/AD8
/AD10
/AD12
/AD14
/AD16
/AD18
/AD20
/AD22
/AD24
/AD26
/AD28
/AD30
GND
/PFW
/ARB0
/ARB2
/ID0
/ID2
.N
Row C
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NuBus 90 Connector
PR
EL
IM
IN
BETA RELEASE
82

+5 VDC
+5 VDC
Ground
Clock
Contributor: Joakim gren, Karsten Wenke <Karsten.Wenke@t-online.de>
BU
Source: ?
TIO
N.
/START
+5 V
+5 V
GND
/CLK
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
PR
EL
IM
IN
28
29
30
31
32
NuBus 90 Connector
BETA RELEASE
83
Zorro II Connector
TIO
N.
(At the A2000)
BU
86 PIN EDGE CONNECTOR at the A2000.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
YB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AR
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ST
X
X
X
X
X
X
X
X
X
X
X
DI
12
13
14
15
16
17
18
19
20
X
X
RE
X
X
Name
GND
GND
GND
GND
+5V
+5V
n/c
-5V
n/c
28CLOCK
+12V
n/c
/COPCFG
CONFIG IN, Grounded
GND
/C3
CDAC
/C1
/OVR
RDY
/INT2
/PALOPE
n/c
/BOSS
A5
/INT6
A6
A4
GND
A3
A2
A7
A1
A8
FC0
A9
FC1
A10
FC2
A11
GND
A12
A13
/IPL0
A14
/IPL1
X
X
A2000B
X
X
X
X
X
X
X
X
FO
10
11
A2000
X
X
X
X
X
X
X
X
OT
A1000
X
X
X
X
X
X
X
X
X
.N
A500
X
X
X
X
X
X
X
X
X
ET
A
Pin
1
2
3
4
5
6
7
8
9
RI
None: All of my X's suddenly disappeared. I have now put them back again. I hope the table
is correct. Please contact me if not. I don't remember where I found this information.
PR
EL
IM
IN
Zorro II
Description
Ground
Ground
Ground
Ground
+5 Volts DC
+5 Volts DC
-5 Volts DC
28MHz Clock
+12 Volts DC
Configuration Out
Ground
C3 Clock
Clock
C1 Clock
Ready
Interrupt 2
Address 5
Interrupt 6
Address 6
Address 4
Ground
Address 3
Address 2
Address 7
Address 1
Address 8
Processor status 0
Address 9
Processor status 1
Address 10
Processor status 2
Address 11
Ground
Address 12
Address 13
Address 14
BETA RELEASE
84
TIO
N.
BU
Address 18
Reset
Address 19
Halt
Address 20
Address 22
Address 21
Address 23
RI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ground
E Clock
ST
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Address 16
Bus Error
Address
DI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Address 15
RE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
X
X
X
X
FO
X
X
X
X
A15
/IPL2
A16
/BEER
A17
/VPA
GND
ECLK
/VMA
A18
RST
A19
/HLT
A20
A22
A21
A23
/BR
/CBR
GND
/BGACK
D15
/BG
/CBG
D14
/DTACK
D13
R/W
D12
/LDS
D11
/UDS
GND
/AS
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
GND
D5
OT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
.N
61
62
63
64
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ET
A
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
YB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AR
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Zorro II Connector
Ground
Data 15
Data 14
Data 13
Read/Write
Data 12
Data 11
Ground
Data 0
Data 10
Data 1
Data 9
Data 2
Data 8
Data 3
Data 7
Data 4
Data 6
Ground
Data 5
PR
EL
IM
IN

Source: ?
BETA RELEASE
85
Zorro II/III Connector
TIO
N.
(At the computer)
Zorro II
Name
RI
Pin Physical
Name
BU
100 PIN EDGE CONNECTOR at the computer.
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
Zorro III
Address Phase Zorro III
Data Phase
1
Ground
Ground
Ground
Ground
2
Ground
Ground
Ground
Ground
3
Ground
Ground
Ground
Ground
4
Ground
Ground
Ground
Ground
5
+5VDC
+5VDC
+5VDC
+5VDC
6
+5VDC
+5VDC
+5VDC
+5VDC
7
/OWN
/OWN
/OWN
/OWN
8
-5VDC
-5VDC
-5VDC
-5VDC
9
/SLAVEn /SLAVEn
/SLAVEn
/SLAVEn
10 +12VDC
+12VDC
+12VDC
+12VDC
11 /CFGOUTn /CFGOUTn /CFGOUTn
/CFGOUTn
12 /CFGINn
/CFGINn
/CFGINn
/CFGINn
13 Ground
Ground
Ground
Ground
14 /C3
/C3 Clock
/C3 Clock
/C3 Clock
15 CDAC
CDAC Clock CDAC Clock
CDAC Clock
16 /C1
/C1 Clock
/C1 Clock
/C1 Clock
17 /CINH
/OVR
/CINH
/CINH
18 /MTCR
XRDY
/MTCR
/MTCR
19 /INT2
/INT2
/INT2
/INT2
20 -12VDC
-12VDC
-12VDC
-12VDC
21 A5
A5
A5
A5
22 /INT6
/INT6
/INT6
/INT6
23 A6
A6
A6
A6
24 A4
A4
A4
A4
25 Ground
Ground
Ground
Ground
26 A3
A3
A3
A3
27 A2
A2
A2
A2
28 A7
A7
A7
A7
29 /LOCK
A1
/LOCK
/LOCK
30 AD8
A8
A8
D0
31 FC0
FC0
FC0
FC0
32 AD9
A9
A9
D1
33 FC1
FC1
FC1
FC1
34 AD10
A10
A10
D2
35 FC2
FC2
FC2
FC2
36 AD11
A11
A11
D3
37 Ground
Ground
Ground
Ground
38 AD12
A12
A12
D4
39 AD13
A13
A13
D5
40 Reserved (/EINT7)
Reserved
Reserved
41 AD14
A14
A14
D6
Reserved
Reserved
43 AD15
A15
A15
D7
Reserved
Reserved
45 AD16
A16
A16
D8
PR
EL
IM
IN
Zorro II/III
BETA RELEASE
86
OT
.N
BU
RI
RE
DI
ST
/BERR
D9
/MTACK
Ground
E Clock
/DS0
D10
/RESET
D11
/HLT
D12
D14
D13
D15
/BRn
Ground
/BGACK
D31
/BGn
D30
/DTACK
D29
READ
D28
/DS2
D27
/DS3
Ground
/CCS
D16
D26
D17
D25
D18
D24
D19
D23
D20
D22
Ground
D21
Ground
Ground
Ground
Ground
SenseZ3
7M
DOE
/IORST
/BCLR
Reserved
/FCS
/DS1
Ground
Ground
TIO
N.
FO
/BERR
A17
/MTACK
Ground
E Clock
/DS0
A18
/RESET
A19
/HLT
A20
A22
A21
A23
/BRn
Ground
/BGACK
A31
/BGn
A30
/DTACK
A29
READ
A28
/DS2
A27
/DS3
Ground
/CCS
Reserved
A26
Reserved
A25
Reserved
A24
Reserved
Reserved
Reserved
Reserved
Ground
Reserved
Ground
Ground
Ground
Ground
SenseZ3
7M
DOE
/IORST
/BCLR
Reserved
/FCS
/DS1
Ground
Ground
ET
A
/BERR
A17
(/VPA)
Ground
E Clock
(/VMA)
A18
/RST
A19
/HLT
A20
A22
A21
A23
/BRn
Ground
/BGACK
D15
/BGn
D14
/DTACK
D13
READ
D12
/LDS
D11
/UDS
Ground
/AS
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
Ground
D5
Ground
Ground
Ground
Ground
Ground
E7M
DOE
/BUSRST
/GBG
(/EINT1)
No Connect
No Connect
Ground
Ground
YB
/BERR
AD17
/MTACK
Ground
E Clock
/DS0
AD18
/RESET
AD19
/HLT
AD20
AD22
AD21
AD23
/BRn
Ground
/BGACK
AD31
/BGn
AD30
/DTACK
AD29
READ
AD28
/DS2
AD27
/DS3
Ground
/CCS
SD0
AD26
SD1
AD25
SD2
AD24
SD3
SD7
SD4
SD6
Ground
SD5
Ground
Ground
Ground
Ground
SenseZ3
7M
DOE
/IORST
/BCLR
Reserved
/FCS
/DS1
Ground
Ground
AR
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PR
EL
IM
IN

BETA RELEASE
87
Amiga 1200 CPU-port Connector
TIO
N.
(At the computer)
RI
ST
DI
RE
R
FO
OT
ET
A
.N
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Ground
+5 Volts DC
Address 23
Address 22
Address 21
Address 20
Address 19
Address 18
Address 17
Address 16
Ground
+5 Volts DC
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Ground
+5 Volts DC
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Ground
+5 Volts DC
Data 31
Data 30
Data 29
Data 28
Data 27
Data 26
Data 25
Data 24
Ground
YB
Name
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
GND
+5V
A23
A22
A21
A20
A19
A18
A17
A16
GND
+5V
A15
A14
A13
A12
A11
A10
A9
A8
GND
+5V
A7
A6
A5
A4
A3
A2
A1
A0
GND
+5V
D31
D30
D29
D28
D27
D26
D25
D24
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
BU
PR
EL
IM
IN
Amiga 1200 CPU-port
BETA RELEASE
88
TIO
N.
BU
RI
ST
DI
RE
R
FO
OT
ET
A
Reserved
Reset
Halt
Reserved
Reserved
.N
+5 Volts DC
Data 23
Data 22
Data 21
Data 20
Data 19
Data 18
Data 17
Data 16
Ground
+5 Volts DC
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
Ground
+5 Volts DC
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Ground
+5 Volts DC
YB
+5V
D23
D22
D21
D20
D19
D18
D17
D16
GND
+5V
D15
D14
D13
D12
D11
D10
D9
D8
GND
+5V
D7
D6
D5
D4
D3
D2
D1
D0
GND
+5V
/IPL2
/IPL1
/IPL0
n/c
/RST
/HLT
n/c
n/c
SIZE1
SIZE0
/AS
/DS
R/W
/BERR
n/c
/AVEC
/DSACK1
/DSACK2
CPUCKLA
ECLOCK
GND
+5V
FC2
FC1
FC0
/RMC
n/c
n/c
n/c
Address Strobe
Data Strobe
Read/Write
Bus Error
Reserved
AR
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
PR
EL
IM
IN
EClock pulse
Ground
+5 Volts DC
Processor Status 2
Processor Status 1
Processor Status 0
Reserved
Reserved
Reserved
BETA RELEASE
89
TIO
N.
Reserved
Slot specific Bus Arbitration
Slot specific Bus Arbitration
Reserved
FPU Chip select
FPU Sense
R
FO
.N
OT
Interrupt level 2
Interrupt level 6
Ground
+5 Volts DC
System1 Ground
System0 Ground
RE
Keyboard reset
IO Read
IO Write
Output enable
/DTACK Override
External Ready
ST
DI
Realtime Clock Chip select
RI
BU
Reset
Ground
+5 Volts DC
ET
A
n/c
/BR
/BG
n/c
/BOSS
/FPUCS
/FPUSENSE
CCKA
/RESET
GND
+5V
/NETCS
/SPARECS
/RTCCS
/FLASH
/REG
/CCENA
/WAIT
/KBRESET
/IORD
/IOWR
/OE
/WE
/OVR
XRDY
/ZORRO
/WIDE
/INT2
/INT6
GND
+5V
SYSTEM1
SYSTEM0
/xRxD
/xTxD
/CONFIG OUT
AGND
ALEFT
ARIGHT
+12V
-12V
Audio Ground
Audio Left
Audio Right
+12 Volts DC
-12 Volts DC
YB
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Source: ?
AR
PR
EL
IM
IN
BETA RELEASE
90
Amiga 1000 Ramex Connector
TIO
N.
(At the computer)
RI
ST
Ground
Data 14
+5 Volts DC
Data 13
Ground
Data 10
+5 Volts DC
Data 9
Ground
Data 6
+5 Volts DC
Data 5
Ground
Data 2
+5 Volts DC
Data 1
Ground
DI
GND
D14
+5V
D13
GND
D10
+5V
D9
GND
D6
+5V
D5
GND
D2
+5V
D1
GND
DRA3
RE
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
Description
Ground
Data 15
+5 Volts DC
Data 12
Ground
Data 11
+5 Volts DC
Data 8
Ground
Data 7
+5 Volts DC
Data 4
Ground
Data 3
+5 Volts DC
Data 0
Ground
FO
Name
GND
D15
+5V
D12
GND
D11
+5V
D8
GND
D7
+5V
D4
GND
D3
+5V
D0
GND
DRA4
DRA5
DRA6
DRA7
GND
/RAS
GND
GND
/CASU0
GND
/CASL0
+5V
+5V
.N
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BU
60 PIN EDGE CONNECTOR (.156") at the computer.
Ground
Ground
Ground
ET
A
Ground
AR
YB
+5 Volts DC
+5 Volts DC
PR
EL
IM
IN
Amiga 1000 Ramex
BETA RELEASE
91
TIO
N.
Ground
Ground
Ground
Ground
BU
DRA2
DRA1
DRA0
GND
/RRW
GND
GND
/CASU1
GND
/CASL1
+5V
+5V
+5 Volts DC
+5 Volts DC
RI
W
X
Y
Z
AA
BB
CC
DD
EE
FF
HH
JJ
ST

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
DI
PR
EL
IM
IN
BETA RELEASE
92
Amiga Video Expansion Connector
TIO
N.
(At the computer)
RI
ST
DI
RE
FO
OT
.N
GND
RGB20
RGB21
RGB22
GND
RGB12
RGB13
RGB14
GND
RGB5
RGB6
GND
Description
Red Bit 0
Red Bit 1
Audio Line Out Left
Audio Line Out Right
Pixel-Synchronous Clock
+5 Volts DC (1 A)
Analog Red
+5 Volts DC (1 A)
Digital Ground
+12 Volts DC (40 mA)
Analog Green
Digital Ground
Digital Ground
Composite Sync
Analog Blue
Genlock Clock Enable
Digital Ground
Burst Gate
3.55/3.58 MHz Clock
Digital Ground
Digital Ground
Horizontal Sync (47 Ohm)
Blue Bit 4
Digital Ground
Blue Bit 7
Vertical Sync (47 Ohm)
Green Bit 7
Video Blank
Red 7
Genlock Overlay (47 Ohm)
-5 Volts DC
Digital Ground
Genlock Clock
C1 Clock
+5 Volts DC (1 A)
Printer Port Handshake
ET
A
1
2
3
4
5
6
7
8
9
10
11
12
Dir
YB
Name
RGB16
RGB17
LINELF
LINERT
C28D
+5V
ARED
+5V
GND
+12V
AGREEN
GND
GND
/CSYNC
ABLUE
/XCLKEN
GND
BURST
/C4
GND
GND
/HSYNC
RGB4
GND
RGB7
/VSYNC
RGB15
BLANK
RGB23
/PIXELSW
-5V
GND
/XCLK
/C1
+5V
PSTROBE
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BU
PR
EL
IM
IN
Video Expansion (Amiga)
Digital Ground
Red Bit 4
Red Bit 5
Red Bit 6
Digital Ground
Green Bit 4
Green Bit 5
Green Bit 6
Digital Ground
Blue Bit 5
Blue Bit 6
Ground
BETA RELEASE
93
TIO
N.
BU
Sync-On-Green Indicator
50/60 Hz Software Clock Timebase
7.09/7.16 MHz Clock
Printer Port Paper Out
3.55/3.58 MHz Clock
Printer Port Busy
Light Pen Input
Printer Port Acknowledge Handshake
Printer Port Select
Digital Ground
Printer Port Data Bit 0
LED (Audio filter bypass) Setting
Digital Ground
Raw (Unfiltered) Audio Left
Audio Ground
Raw (Unfiltered) Audio Right
Audio Ground
Reserved for future expansion
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Red Bit 2
Red Bit 3
Green Bit 0
Green Bit 1
Green Bit 2
Green Bit 3
Blue Bit 0
Blue Bit 1
Blue Bit 2
Blue Bit 3
DI
ST
RI
RE
.N
OT
FO
ET
A
SOG
TBASE
CDAC
PPOUT
/C3
PBUSY
/LPEN
/PACK
PSEL
GND
PPD0
PPD1
PPD2
PPD3
PPD4
PPD5
PPD6
PPD7
/LED
GND
RAWLF
AGND
RAWRT
AGND
n/c
n/c
GND
GND
n/c
n/c
GND
GND
RGB18
RGB19
RGB8
RGB9
RGB10
RGB11
RGB0
RGB1
RGB2
RGB3
YB
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
AR
Note: Direction is Motherboard relative Card.

Note: Do not mix analog & digital grounds.
PR
EL
IM
IN

BETA RELEASE
94
CD32 Expansion-port Connector
TIO
N.
(At the computer)
OT
FO
RE
DI
ST
RI
Comment
Probably not connected since 68EC020
ET
A
.N
Description
Address 31
Address 30
Address 29
Address 28
Address 27
Address 26
Address 25
Address 24
Data Ground
+5 VDC
Address 23
Address 22
Address 21
Address 20
Address 19
Address 18
Address 17
Address 16
Data Ground
+5 VDC
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Data Ground
+5 VDC
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data Ground
+5 VDC
Data 31
Data 30
Data 29
Data 28
Data 27
Data 26
Data 25
Data 24
Data Ground
YB
Name
A31
A30
A29
A28
A27
A26
A25
A24
DGND
VCC
A23
A22
A21
A20
A19
A18
A17
A16
DGND
VCC
A15
A14
A13
A12
A11
A10
A9
A8
DGND
VCC
A7
A6
A5
A4
A3
A2
A1
A0
DGND
VCC
D31
D30
D29
D28
D27
D26
D25
D24
DGND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
BU
UNKNOWN 182 PIN CONNECTOR (SAME AS MCA) at the computer.
PR
EL
IM
IN
CD32 Expansion-port
BETA RELEASE
95
TIO
N.
BU
RI
ST
Reset
Halt
ECS??
OCS??
Size 1
DI
/RST
/HALT
/ECS
/OCS
SIZE1
RE
+5 VDC
Data 23
Data 22
Data 21
Data 20
Data 19
Data 18
Data 17
Data 16
Data Ground
+5 VDC
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
Data Ground
+5 VDC
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Data Ground
+5 VDC
Interrupt Priority Level 2
ET
A
.N
OT
FO
VCC
D23
D22
D21
D20
D19
D18
D17
D16
DGND
VCC
D15
D14
D13
D12
D11
D10
D9
D8
DGND
VCC
D7
D6
D5
D4
D3
D2
D1
D0
DGND
VCC
/IPL2
/IPL1
/IPL0
YB
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90 SIZE0
Size 0
/AS
/DS
/R/W
/BERR
/AVEC
Autovector Req
97
98
99
100
101
102
103
104
105
106
/DSACK1
/DSACK0
CPUCLK_A
Data Ack 1
Data Ack 0
DGND
VCC
FC2
FC1
FC0
Data Ground
+5 VDC
Function Codes 2
Function Codes 1
Function Codes 0
Indicates number of bytes remaining to

transfer
Indicates number of bytes remaining to
transfer
Address Strobe
Data Strobe
Read/Write
Bus Error
AR
91
92
93
94
95
96
PR
EL
IM
IN
Autovector request during interrupt

acknowledge
Data trasnfer and size acknowledge
Data transfer and size acknowledge
BETA RELEASE
96
TIO
N.
CPU bus request??

Expansion bus granted??
CPU bus granted??
Expansion bus request??
/PUNT
/RESET
/INT2
/INT6
/KB_CLOCK
/KB_DATA
/FIRE0
/FIRE1
/LED
/ACTIVE
/RXD
/TXD
/DKRD
/DKWD
SYSTEM
/DKWE
CONFIG_OUT
BU
/CPU_BR
/EXP_BG
/CPU_BG
/EXP_BR
RI
68020 RESET
Interrupt 2
Interrupt 2
Keyboard clock
Keyboard data
Fire Button 0??
Fire Button 1??
Power On LED ??
Disk active LED
Serial Receive
Serial Transmit
ET
A
.N
Data Ground
+12V DC
Data Ground
+12V DC
Floppy interface (Paula?)
For FMV interface ??

Data Ground
+5 VDC
Digital Red
Digital Green
Digital Blue
Digital Intensity
YB
DGND
+12V
DGND
+12V
17MHZ
EXT_AUDIO
DA_DATA
/MUTE
DA_LRCLK
DA_BCLK
DGND
VCC
DR
DG
DB
DI
/PIXELSW_EXT
/PIXELSW
/BLANK
PIXELCLK
DGND
VCC
/CSYNC
CCK_B
/HSYNC
/VSYNC
VGND
VGND
AR_EXT
AR
AG_EXT
AG
Serial data in
Serial data out
OT
FO
RE
DI
ST
Generate a level 2 interrupt

Generate a level 6 interrupt
AR
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
PR
EL
IM
IN
Pixelclock
Data Ground
+5 VDC
Composite sync
Color clock ??
Horizontal sync
Vertical sync
Video ground
Video ground
Analog Red External
Analog Red
Analog Green External
Analog Green
For manipulating RBG data

Not buffered.
BETA RELEASE
97
TIO
N.
Analog Blue External

Analog Blue
Video ground
Video ground
BU
Enable External video clock (Genlock)

External video clock
(Genlock)
External Video
Disable internal video interfaces
Data Ground
+5 VDC
Audio Ground
+12V DC
Left sound External
Left sound
Right sound External
Right sound
RI
AB_EXT
AB
VGND
VGND
/NTSC
/XCLKEN
XCLK
/EXT_VIDEO
DGND
VCC
AGND
+12V
LEFT_EXT
LEFT
RIGHT_EXT
RIGHT
ST
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
DI
RE
Source: CD32 expansion port info <ftp://ftp.demon.co.uk/pub/amiga/docs/cd32-pinouts.txt>, usenet posting by

Anders Stenkvist <ask_me@elixir.e.kth.se>..
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
98
CardBus Connector
TIO
N.
CardBus
RI
BU
(At the controller)
ST
(At the peripherals)
RE
R
ET
A
.N
OT
FO
Description
Ground
Address/Data 0
Address/Data 1
Address/Data 3
Address/Data 5
Address/Data 7
Command/Byte Enable 0
Address/Data 9
Address/Data 11
Address/Data 12
Address/Data 14
Parity
Parity error
Grant
Interrupt
Vcc
Vpp1
CCLK
Initiator Ready
Address/Data 18
Address/Data 20
Address/Data 21
Address/Data 22
Address/Data 23
Address/Data 24
Address/Data 25
Address/Data 26
Address/Data 27
Address/Data 29
Reserved
CCLKRUN#
Ground
Ground
Card Detect 1
Address/Data 2
Address/Data 4
Address/Data 6
Reserved
Address/Data 8
Address/Data 10
YB
Name
GND
CAD0
CAD1
CAD3
CAD5
CAD7
CCBE0#
CAD9
CAD11
CAD12
CAD14
CCBE1#
CPAR
CPERR#
CGNT#
CINT#
Vcc
Vpp1
CCLK
CIRDY#
CCBE2#
CAD18
CAD20
CAD21
CAD22
CAD23
CAD24
CAD25
CAD26
CAD27
CAD29
RSRVD
CCLKRUN#
GND
GND
CCD1#
CAD2
CAD4
CAD6
RSRVD
CAD8
CAD10
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DI
68 PIN ??? MALE at the controller.

68 PIN ??? FEMALE at the peripherals.
PR
EL
IM
IN
32-bit bus defined by PCMCIA.
BETA RELEASE
99
Address/Data 28
Address/Data 30
Address/Data 31
Card Detect 2
Ground
BU
RI
ST
DI
RE
Reset
System Error
Request ???
Audio ???
TIO
N.
Address/Data 13
Address/Data 15
Address/Data 16
Reserved
Block ???
Stop transfer cycle
Device Select
Vcc
Vpp2
Target Ready
Address/Data 17
CAD19
CVS1
CAD13
CAD15
CAD16
RSRVD
CBLOCK#
CSTOP#
CDEVSEL#
Vcc
Vpp2
CTRDY#
CFRAME#
CAD17
CAD19
CVS2
CRST#
CSERR#
CREQ#
CCBE3#
CAUDIO
CSTSCHG
CAD28
CAD30
CAD31
CCD2#
GND
FO
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
CardBus Connector
Contributor: Joakim gren, Marek Hostasa <maro@adcomsys.net>
OT
Source: PC Card Standard <http://www.pc-card.com/stand_overview.html> at PC Card's homepage

<http://www.pc-card.com>
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
100
PC Card Connector
TIO
N.
PC Card
RI
BU
(At the controller)
ST
FO
RE
Description
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
.N
OT
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Write Enable ???
ET
A
Vcc
Vpp1
Address 16
Address 15
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
YB
Memory I/O+Mem
GND
GND
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
CE1#
CE1#
A10
A10
OE#
OE#
A11
A11
A9
A9
A8
A8
A13
A13
A14
A14
WE#
WE#
READY IREQ#
Vcc
Vcc
Vpp1
Vpp1
A16
A16
A15
A15
A12
A12
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
D0
D0
D1
D1
D2
D2
WP
IOIS16#
GND
GND
GND
GND
CD1# CD1#
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
CE2#
CE2#
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DI

PR
EL
IM
IN
16-bit bus defined by PCMCIA.
Ground
Ground
Card Detect 1
Data 11
Data 12
Data 13
Data 14
Data 15
BETA RELEASE
101
ST
RI
BU
TIO
N.
Reserved / IORD#
Reserved / IOWR#
Address 17
Address 18
Address 19
Address 20
Address 21
Vcc
Vpp2
Address 22
Address 23
Address 24
Address 25
DI
Reset
Reserved / ???
Battery Voltage 2 / Speaker ???

Battery Voltage 1 / ???
Data 8
Data 9
Data 10
RE
VS1#
IORD#
IOWR#
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
VS1#
RSRVD
RSRVD
A17
A18
A19
A20
A21
Vcc
Vpp2
A22
A23
A24
A25
VS2#
RESET
WAIT#
RSRVD
REG#
BVD2
BVD1
D8
D9
D10
CD2#
GND
FO
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PC Card Connector
Ground
OT
Source: PC Card Standard <http://www.pc-card.com/stand_overview.html> at PC Card's homepage

<http://www.pc-card.com>
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
102
PC Card ATA Connector
TIO
N.
PC Card ATA
RI
BU
(At the controller)
ST
INTRQ
VCC
x
x
DA2
DA1
DA0
DD0
DD1
DD2
/IOCS16
Ground
Ground
/CD1
DD11
DD12
DD13
DD14
DD15
/CS1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A9
A8
RE
x 1)
i
i
x
x
/WE
/READY:IREQ
VCC
i
i
i
i
i
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x 1)
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
/WP:IOIS16
Ground
Ground
/CD1
D11
D12
D13
D14
D15
/CE2
ET
A
YB
/CS1
PC-Card equiv
Ground
D3
D4
D5
D6
D7
/CE1
A10
/OE
.N
/SELATA x
Dev
x
x
x
x
x
x
x
i
x
Dir
FO
Host
x
x
x
x
x
x
x
OT
Namel
Ground
DD3
DD4
DD5
DD6
DD7
/CS0
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DI

PR
EL
IM
IN
This specification makes it possible to share ATA & PC Card with the same connectors.
BETA RELEASE
103
x
x
i
x
x
/VS1
/IORD
/IOWR
VCC
VCC
M/SCSEL
x
x
/RESET
IORDY
DMARQ
/DMACK
/DASP
/PDIAG
DD8
DD9
DD10
/CD2
Ground
x
o
o
o
x
x
x
x
x
x
x
x 2)
x 2)
i
x
x 3)
x 3)
o
x
x
x
x
x
x
x
/VS2
RESET
/WAIT
/INPACK
/REG
/BVD2:SPKR
/BVD1:STSCHG
D8
D9
D10
/CD2
Ground
RE
DI
ST
RI
BU
TIO
N.
/DIOR
/DIOW
FO
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Source: ATA-2 specifications
ET
A
.N
OT
x = Required.
i = Ignored by host in ATA mode.
o = Optional.
nothing = Not connected.
1) Device shall support only one /CS1 signal pin.
2) Device shall support either /M/S or CSEL but not both.
3) Device shall hold this signal negated if it does not support this function.
AR
YB
PR
EL
IM
IN
BETA RELEASE
104
PCMCIA Connector
TIO
N.
PCMCIA
RI
BU
(At the controller)
ST
Description
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Card Enable 1
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Write Enable : Program
Ready : Busy (IREQ)
+5V
Programming Voltage (EPROM)
Address 16
Address 15
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Write Protect : IOIS16
Ground
Ground
Card Detect 1
Data 11
Data 12
Data 13
Data 14
Data 15
Card Enable 2
ET
A
.N
OT
FO
RE
Dir
YB
Name
GND
D3
D4
D5
D6
D7
/CE1
A10
/OE
A11
A9
A8
A13
A14
/WE:/P
/READY:/IREQ
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
/WP:/IOIS16
GND
GND
/CD1
D11
D12
D13
D14
D15
/CE2
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DI

PR
EL
IM
IN
PCMCIA=Personal Computer Memory Card International Association.
BETA RELEASE
105
ST
RI
BU
TIO
N.
Refresh
I/O Read
I/O Write
Address 17
Address 18
Address 19
Address 20
Address 21
+5V
Programmeing Voltage 2 (EPROM)
Address 22
Address 23
Address 24
Address 25
RFU
RESET
WAIT
?
?
DI
?
?
?
?
RE
Register Select
Battery Voltage Detect 2 : SPKR
Battery Voltage Detect 1 : STSCHG
Data 8
Data 9
Data 10
Card Detect 2
Ground
/VS1
/IORD
/IOWR
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
/VS2
RESET
/WAIT
/INPACK
/REG
/BVD2:SPKR
/BVD1:STSCHG
D8
D9
D10
/CD2
GND
FO
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PCMCIA Connector
Note: Direction is Controller (computer) relative PCMCIA-card.
OT
AR
YB
ET
A
.N
Source: ?
PR
EL
IM
IN
BETA RELEASE
106
CompactFlash
BU
See PC-Card ATA for more information.
ST
RI
(At the controller)
RE
.N
OT
FO
Description
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Card Enable 1
Address 10
Output Enable
Address 9
Address 8
Address 7
+5V
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Write Protect : IOIS16
Card Detect 2
Card Detect 1
Data 0
Data 0
Data 0
Data 0
Data 0
Card Enable 2
Refresh
I/O Read
I/O Write
Write Enable
Ready : Busy : IREQ
+5V
YB
ET
A
Name
GND
D3
D4
D5
D6
D7
/CE1
A10
/OE
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
/WP:/IOIS16
/CD2
/CD1
D0
D0
D0
D0
D0
/CE2
/VS1
/IORD
/IOWR
/WE
/READY:/RDY:/IREQ
VCC
CSEL
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
DI

PR
EL
IM
IN
Developed by SanDisk.
Is compatible with PC-Card ATA with a simple passive adapter.
TIO
N.
CompactFlash Connector
BETA RELEASE
107
Register Select
Battery Voltage Detect 2 : SPKR
Battery Voltage Detect 1 : STSCHG
Data 8
Data 9
Data 10
Ground
TIO
N.
RFU
Reset
Wait
BU
/VS2
RESET
/WAIT
/INPACK
/REG
/BVD2:SPKR
/BVD1:STSCHG
D8
D9
D10
GND
RI
40
41
42
43
44
45
46
47
48
49
50
ST
Source: SanDisk's CompactFlash ABC <http://www.sandisk.com/sd/support/teched/cfpc_5.htm> at SanDisk's

homepage <http://www.sandisk.com>
AR
YB
ET
A
.N
OT
FO
RE
DI
PR
EL
IM
IN
BETA RELEASE
108
C-bus II Connector
TIO
N.
C-bus II
BU

R
FO
OT
.N
ET
A
YB
Name
GND
AUX18
AUX16
GND
AUX14
AUX12
GND
AUX10
AUX8
GND
AUX6
AUX4
GND
AUX2
AUX0
GND
RESERVED8
RESERVED6
RESERVED4
RESERVED2
RESERVED0
GND
GND
AGND
CID1
CBCLK
GND
CRST#
LED#
GND
CARB2
CARB0
GND
TM2#
TM0#
GND
STRT#
CD31
AR
Pin
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PA32
PA33
PA34
PA35
PA36
PA37
PA38
RE
PA=Component side
PB=Solder side
DI
ST
RI
(At the backplane)
PR
EL
IM
IN
Developed by Corolla
C-bus II is the successor to C-bus & Extended C-bus.
BETA RELEASE
109
TIO
N.
BU
RI
ST
DI
RE
R
FO
OT
.N
+5V
AUX19
AUX17
+5V
AUX15
AUX13
ET
A
PB1
PB2
PB3
PB4
PB5
PB6
YB
GND
CD30
CD29
GND
CD28
CD27
GND
CD26
CD25
GND
CD24
CD23
GND
CD22
CD21
GND
CD20
CD19
GND
CD18
CD17
GND
CD16
E3
GND
E2
CD15
GND
CD14
CD13
GND
CD12
CD11
GND
CD10
CD9
GND
CD8
CD7
GND
CD6
CD5
GND
CD4
CD3
GND
CD2
CD1
GND
CD0
E1
GND
E0
AR
PA39
PA40
PA41
PA42
PA43
PA44
PA45
PA46
PA47
PA48
PA49
PA50
PA51
PA52
PA53
PA54
PA55
PA56
PA57
PA58
PA59
PA60
PA61
PA62
PA63
PA64
PA65
PA66
PA67
PA68
PA69
PA70
PA71
PA72
PA73
PA74
PA75
PA76
PA77
PA78
PA79
PA80
PA81
PA82
PA83
PA84
PA85
PA86
PA87
PA88
PA89
PA90
PA91
C-bus II Connector
PR
EL
IM
IN
BETA RELEASE
110
TIO
N.
BU
RI
ST
DI
RE
R
FO
OT
.N
ET
A
YB
+5V
AUX11
AUX9
+5V
AUX7
AUX5
+5V
AUX3
AUX1
+5V
RESERVED9
RESERVED7
RESERVED5
RESERVED3
RESERVED1
VTERM
+5V
CID3
CID2
CID0
+5V
FAULT#
LOCKCB#
+5V
CARB3
CARB1
+5V
TM3#
TM1#
+5V
ACK#
CD63
+5V
CD62
CD61
+5V
CD60
CD59
+5V
CD58
CD57
+5V
CD56
CD55
+3.3V
CD54
CD53
+3.3V
CD52
CD51
+3.3V
CD50
CD49
+3.3V
CD48
E7
+3.3V
E6
CD47
+3.3V
AR
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PB32
PB33
PB34
PB35
PB36
PB37
PB38
PB39
PB40
PB41
PB42
PB43
PB44
PB45
PB46
PB47
PB48
PB49
PB50
PB51
PB52
PB53
PB54
PB55
PB56
PB57
PB58
PB59
PB60
PB61
PB62
PB63
PB64
PB65
PB66
C-bus II Connector
PR
EL
IM
IN
BETA RELEASE
111
RE
DI
ST
RI
BU
TIO
N.
CD46
CD45
+3.3V
CD44
CD43
+3.3V
CD42
CD41
+3.3V
CD40
CD39
+3.3V
CD38
CD37
+3.3V
CD36
CD35
+3.3V
CD34
CD33
+3.3V
CD32
E5
+3.3V
E4
FO
PB67
PB68
PB69
PB70
PB71
PB72
PB73
PB74
PB75
PB76
PB77
PB78
PB79
PB80
PB81
PB82
PB83
PB84
PB85
PB86
PB87
PB88
PB89
PB90
PB91
C-bus II Connector
OT
Sources: C-bus II Technology architecture <http://www.corollary.com/cbusii.html> at Collary's homepage

<http://www.collary.com>
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
112
SSFDC Connector
TIO
N.
SSFDC
RI
BU
(At the motherboard)
UNKNOWN CONNECTOR at the motherboard.

ST
(At the device)
RE
DI
I don't have any technical information about SSFDC at the moment. If you have any
information of value please send it to me.
Source: ?
Info: Solid State Floppy Disk Card Forum <http://www.ssfdc.com>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
SSFDC=Solid State Floppy Disk Card.
BETA RELEASE
113
PC/104 Connector
TIO
N.
BU
(At the backplane)
OT
ET
A
AR
RE
DI
J2/P2
Row D1
0V
MEMCS16*
IOCS16*
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0*
DRQ0
DACK5*
DRQ5
DACK6*
DRQ6
DACK7*
DRQ7
+5V
MASTER*
0V
(KEY)2 0V
--------------
FO
J2/P2
Row C1
0V
SBHE*
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR*
MEMW*
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
.N
J1/P1
Row B
-0V
RESETDRV
+5V
IRQ9
-5V
DRQ2
-12V
ENDXFR*
+12V
(KEY)2
SMEMW*
SMEMR*
IOW*
IOR*
DACK3*
DRQ3
DACK1*
DRQ1
REFRESH*
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2*
TC
BALE
+5V
OSC
0V
0V
YB
Pin
J1/P1
Number Row A
0
-1
IOCHCHK*
2
SD7
3
SD6
4
SD5
5
SD4
6
SD3
7
SD2
8
SD1
9
SD0
10
IOCHRDY
11
AEN
12
SA19
13
SA18
14
SA17
15
SA16
16
SA15
17
SA14
18
SA13
19
SA12
20
SA11
21
SA10
22
SA9
23
SA8
24
SA7
25
SA6
26
SA5
27
SA4
28
SA3
29
SA2
30
SA1
31
SA0
32
0V
ST

RI
PR
EL
IM
IN
PC/104
--------------

Sources:
<http://www.pc104.org/pc104/consp5.html>
PC/104 v2.3 spec
Sources: PC/104 pinout
<http://www.pc104.org/pc104/pinouts.html>
Info: PC/104 Consortium <http://www.pc104.org/pc104/consp1.html>
BETA RELEASE
114
Unibus Connector
TIO
N.
Unibus
+------------//--------+
|BA1 BB1 BC1 // BU1 BV1|
|BA2 BB2 BC2 // BU2 BV2|
+------------//--------+
RI
BU
+------------//--------+
|AA1 AB1 AC1 // AU1 AV1|
|AA2 AB2 AC2 // AU2 AV2|
+------------//--------+
(At the computer)
DI
RE
R
FO
OT
BG6
POWER(+5v)
BG5
GROUND
/BR5
GROUND
.N
BA1
BA2
BB1
BB2
BC1
BC2
ET
A
SIGNAL
/INIT
POWER(+5v)
/INTR
GROUND
/D00
GROUND
/D02
/D01
/D04
/D03
/D06
/D05
/D08
/D07
/D10
/D09
/D12
/D11
/D14
/D13
/PA
/D15
GROUND
/PB
GROUND
/BBSY
GROUND
/SACK
GROUND
/NPR
GROUND
/BR7
NPG
/BR6
BG7
GROUND
AR
YB
PIN
AA1
AA2
AB1
AB2
AC1
AC2
AD1
AD2
AE1
AE2
AF1
AF2
AH1
AH2
AJ1
AJ2
AK1
AK2
AL1
AL2
AM1
AM2
AN1
AN2
AP1
AP2
AR1
AR2
AS1
AS2
AT1
AT2
AU1
AU2
AV1
AV2
ST
2 x 36 EDGE FEMALE at the backplane.

2 x 36 EDGE MALE at the cards/modules.
PR
EL
IM
IN
Available on the old Digital PDP-11.
BETA RELEASE
115
FO
RE
DI
ST
RI
BU
TIO
N.
GROUND
/BR4
GROUND
BG4
/ACLO
/DCLO
/A01
/A00
/A03
/A02
/A05
/A04
/A07
/A06
/A09
/A08
/A11
/A10
/A13
/A12
/A15
/A14
/A17
/A16
GROUND
/C1
/SSYN
/CO
/MSYN
GROUND
OT
BD1
BD2
BE1
BE2
BF1
BF2
BH1
BH2
BJ1
BJ2
BK1
BK2
BL1
BL2
BM1
BM2
BN1
BN2
BP1
BP2
BR1
BR2
BS1
BS2
BT1
BT2
BU1
BU2
BV1
BV2
Unibus Connector
.N
Contributor: Rob Gill <gillr@mailcity.com>
Source: Digital PDP-11 peripherals handbook
AR
YB
ET
A
PR
EL
IM
IN
BETA RELEASE
116
RS232 Connector
TIO
N.
BU
(At the DTE)
RI
(At the DCE)
OT
FO
RE
DI
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
RESERVED
RESERVED
Select Transmit Channel
Secondary Carrier Detect
Secondary Clear to Send
Secondary Transmit Data
Transmission Signal Element Timing
Secondary Receive Data
Receiver Signal Element Timing
Local Loop Control
Secondary Request to Send
Data Terminal Ready
Remote Loop Control
Ring Indicator
Data Signal Rate Selector
Transmit Signal Element Timing
Test Indicator
.N
ITU-T Dir
101
103
104
105
106
107
102
109
126
?
?
?
114
?
115
141
?
108
140
125
111
113
142
ET
A
Name
GND
TXD
RXD
RTS
CTS
DSR
GND
CD
STF
S.CD
S.CTS
S.TXD
TCK
S.RXD
RCK
LL
S.RTS
DTR
RL
RI
DSR
XCK
TI
YB
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ST
25 PIN D-SUB MALE at the DTE (Computer).

25 PIN D-SUB FEMALE at the DCE (Modem).
AR
Note: Direction is DTE (Computer) relative DCE (Modem).

Note: Do not connect SHIELD(1) to GND(7).
Contributor: Joakim gren, Petr Krc <magneton@mail.firstnet.cz>
Source: ?
PR
EL
IM
IN
RS232
BETA RELEASE
117
Serial (PC 9) Connector
TIO
N.
(At the Computer)
ST
RI
Description
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
System Ground
Data Set Ready
Request to Send
Clear to Send
Ring Indicator
DI
Name Dir
CD
RXD
TXD
DTR
GND
DSR
RTS
CTS
RI
RE
Pin
1
2
3
4
5
6
7
8
9
BU
9 PIN D-SUB MALE at the Computer.
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Serial (PC 9)
BETA RELEASE
118
TIO
N.
(At the computer)
ST
OT
FO
RE
RI
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
DI
Dir
-
Data Terminal Ready

-
.N
Name
SHIELD
TXD
RXD
RTS
CTS
DSR
GND
CD
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
DTR
n/c
RI
n/c
n/c
n/c
Ring Indicator
-
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB MALE at the computer.

YB
AR
PR
EL
IM
IN
Serial (PC 25)
BETA RELEASE
119
Serial (Amiga 1000) Connector
TIO
N.
(At the Amiga 1000)
ST
RI
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
DI
Dir
FO
-5 Volts DC (50mA max)

Amiga Audio Out (Left)
Amiga Audio In (Right)
EB=Buffered Port Clock 716 kHz
Interrupt 2
OT
?
-
RE
Data Terminal Ready

+5 Volts DC
.N
Name
SHIELD
TXD
RXD
RTS
CTS
DSR
GND
CD
n/c
n/c
n/c
n/c
n/c
-5V
AUDO
AUDI
EB
/INT2
n/c
DTR
+5V
n/c
+12V
/C2
/RESET
+12 Volts DC (20 mA max)

C2=Clock 3.58MHz
Reset
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB MALE at the Amiga 1000.

YB
AR
PR
EL
IM
IN
Serial (Amiga 1000)
BETA RELEASE
120
Serial (Amiga) Connector
TIO
N.
BU
(At the computer)
RI
(At the cable)
DI
RE
Description
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
-12 Volts DC (20 mA max)
Amiga Audio Out (Left)
Speed Indicate
OT
.N
FO
Dir
Amiga Audio In (Right)

-
ET
A
Name
SHIELD
TXD
RXD
RTS
CTS
DSR
GND
CD
+12V
-12V
AUDO
n/c
n/c
n/c
n/c
n/c
n/c
AUDI
n/c
DTR
n/c
RI
n/c
n/c
n/c
Data Terminal Ready

-
Ring Indicator
-
YB
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ST

25 PIN D-SUB FEMALE at the cable.
AR

PR
EL
IM
IN
Serial (Amiga)
BETA RELEASE
121
Serial (MSX) Connector
TIO
N.
(At the Computer)
ST
RI
Description
Protective Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
Signal Ground
Carrier Detect
Data Terminal Ready
DI
Name Dir
PG
TXD
RXD
RTS
CTS
DSR
GND DCD
DTR
RE
Pin
1
2
3
4
5
6
7
8
9
BU
9 PIN D-SUB FEMALE at the Computer.
FO
Source: Mayer's SV738 X'press I/O map <http://www.freeflight.com/fms/MSX/Portar.txt>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Serial (MSX)
BETA RELEASE
122
Serial (Printer) Connector
TIO
N.
(At the printer)
RI
RE
ST
Description
Shield Ground
Transmit Data
Receive Data
Not connected
Not connected
Data Set Ready
System Ground
Data Carrier Detect
Not connected
Not connected
Reverse Channel
Not connected
Not connected
Not connected
Not connected
Not connected
TTY Receive Data
Not connected
Not connected
Data Terminal Ready
Not connected
Not connected
TTY Receive Data Return
TTY Transmit Data Return
TTY Receive Data
DI
Dir
FO
OT
.N
Name
SHIELD
TXD
RXD
n/c
n/c
DSR
GND
DCD
n/c
n/c
?
n/c
n/c
n/c
n/c
n/c
TTY-TXD
n/c
n/c
DTR
n/c
n/c
?
?
TTY-RXD
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB MALE at the printer.
YB
Source: ?
AR
PR
EL
IM
IN
Serial (Printer)
BETA RELEASE
123
Mouse (PS/2) Connector
TIO
N.
(At the computer)
RI
Description
Key Data
Not connected
Gnd
Power , +5 VDC
Clock
Not connected
ST
Name Dir
DATA
n/c
GND
VCC
CLK
n/c
-
DI
Pin
1
2
3
4
5
6
BU
6 PIN MINI-DIN FEMALE (PS/2 STYLE) at the computer.
Contributor: Joakim gren, Gilles Ries <gries@glo.be>

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
Note: Direction is Computer relative Mouse.
PR
EL
IM
IN
Mouse (PS/2)
BETA RELEASE
124
Serial (15)
BU
2
4
6
10 12 14
- [][][][][][][][][][][][][][][] 1
3
5
7 8 9 11 13 15
RI
(At the modem)
DTR
CD
TXD
RXD
RE
Data Set Ready

Request to Send
Clear to Send
Ring Indicator
DI
Description
Ground
Ground
+5V DC In
Data Terminal Ready
Carrier Detect
Transmit Data
Receive Data
RS232 Dir
GND
?
DSR
RTS
CTS
RI
?
GND
FO
Name
GROUND
SUSP#
COMBDSR#
COMBRTS#
COMBCTS#
COMBRI#
n/c
GROUND
+5VIN
COMBDTR#
COMBDCD#
COMBTXD
COMBRXD
SPKDATA
GROUND
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ST
15 PIN FEMALE ??? at the modem.
Ground
GND
Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Joerg Brinkel <jb@itm.rwth-aachen.de>
PR
EL
IM
IN
Seems to be available at a 14.4kbps modem called Speedster.
TIO
N.
Serial (15) Connector
BETA RELEASE
125
DEC Dual RS-232 Connector
TIO
N.
DEC Dual RS-232
BU
RI
(At the computer)
2
1
1
2
DI
RE
FO
OT
2
2
2
2
Description
Not connected
Transmit Data
Receive Data
Ready To Send
Clear To Send
Data Set Ready
Ground
Data Carrier Detect
Not connected
Not connected
Data Terminal Ready
Data Carrier Detect
Clear To Send
Transmit Data
Not connected
Receive Data
Not connected
Not connected
Ready To Send
Data Terminal Ready
Not connected
Ring Indicator
Data Set Ready
Not connected
Ring Indicator
.N
1
1
1
1
1
1+2
1
Name Dir
n/c
TXD
RXD
RTS
CTS
DSR
GND DCD
n/c
n/c
DTR
DCD
CTS
TXD
n/c
RXD
n/c
n/c
RTS
DTR
n/c
RI
DSR
n/c
RI
ET
A
Port
YB
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ST
AR
Contributor: Joakim gren, Greg A. Woods <woods@weird.com>

Sources: Tommy's pinout Collection <http://csgrad.cs.vt.edu/~tjohnson/pinouts> by Tommy Johnson
<tjohnson@csgrad.cs.vt.edu>
Sources: Digital UDB Information <http://www.brouhaha.com/~eric/computers/udb.html> by Eric Smith
<eric@brouhaha.com>
PR
EL
IM
IN
Found on the DEC Multia and DEC UDB (Universal Desktop Box). It contains two Serial
ports on one connector. The 1st Port is located on the normal pins, and the 2nd port is
located on some "spare" pins.
BETA RELEASE
126
Macintosh RS-422 Connector
TIO
N.
Macintosh RS-422
BU
8 PIN MINI-DIN FEMALE at the computer.
ST
Description
Output Handshake
Input Handshake or External Clock
Transmit Data (-)
Ground
Receive Data (-)
Transmit Data (+)
General Purpose Input
Receive Data (+)
DI
Name
Dir
HSKo
HSKi/CLK
TXDGND
RXDTXD+
GPi
RXD+
RE
Pin
1
2
3
4
5
6
7
8
RI
(At the computer)
FO
Note: GPi is connected to SCC Data Carrier Detect (or to Receive/Transmit Clock if the VIA1
SYNC signal is high). Not connected on the Macintosh Plus, Classic, Classic II, LC, LC II or
IIsi.
OT
Contributor: Joakim gren, Pierre Olivier <olipie@aei.ca>, Ben Harris <bjh@mail.dotcom.fr>, Nathan Schmidt
<nathans@stanford.edu>
AR
YB
ET
A
.N
Sources: comp.sys.mac.comm FAQ Part 1

<http://www.cis.ohio-state.edu/hypertext/faq/usenet/macintosh/comm-faq/part1/faq.html>
Sources: Apple Tech Info Library, Article ID: TECHINFO-0001699
PR
EL
IM
IN
It's possible to connect RS-232 peripheral to the RS-422 port available on Macintosh
computers. Use RXD- as RXD, TXD- as TXD, Ground RXD+, Leave TXD+ unconnected,
GPi as CD.
BETA RELEASE
127
RS422 Connector
TIO
N.
BU
(At the DTE)
ST
ET
A
.N
OT
FO
RE
Description
Shield Ground
Signal Rate Indicator
Spare
Send Data
Send Timing
Receive Data
Request To Send
Receiver Ready
Clear To Send
Local Loopback
Data Modem
Terminal Ready
Receiver Ready
Remote Loopback
Incoming Call
Select Frequency/Select Rate
Terminal Timing
Test Mode
Ground
Receive Twister-Pair Common
Spare Twister-Pair Return
Send Data TPR
Send Timing TPR
Receive Timing TPR
Request To Send TPR
Receive Timing TPR
Clear To Send TPR
Terminal In Service
Data Mode TPR
Terminal Ready TPR
Receiver TPR
Select Standby
Signal Quality
New Signal
Terminal Timing TPR
Standby Indicator
Send Twister Pair Common
YB
Name Dir
GND
SRI
n/c
SD
ST
RD
RTS
RR
CTS
LL
DM
TR
RR
RL
IC
SF/SR
TT
TM
GND
RC
GND
/SD
GND
GND
/RS
/RT
/CS
IS
/DM
/TR
/RR
SS
SQ
NS
/TT
SB
SC
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
DI
37 PIN D-SUB MALE at the DTE (Computer).

37 PIN D-SUB FEMALE at the DCE (Modem).
RI
(At the DCE)
PR
EL
IM
IN
RS422

Source: ?
BETA RELEASE
128
Macintosh Serial Connector
TIO
N.
Macintosh Serial
RI
BU
(At the Computer)
ST
(At the Equipment)
8
9
Rx+
Rx-
GND
Tx+
Tx+12V
DSR/HSK
OT
3
4
5
6
7
Description
Ground
+5 VDC. Don't use this one, it may be converted into output handshake
in later equipment.
Ground
Transmit Data, positive going component
Transmit Data, negative going component
+12 VDC
Handshake input. Signal name depends on mode: Used for Flow
Control or Clock In.
Receive Data, positive going component
Receive Data, negative going component
RE
Dir
FO
Pin Name
1 GND
2 +5V
DI
9 PIN D-SUB FEMALE at the computer.

9 PIN D-SUB MALE at the mouse cable.
Note: Direction is Computer relative Equipment.
.N
Contributor: Ben Harris <bjh@mail.dotcom.fr>
Source: Apple Tech Info Library, Article ID: TECHINFO-0001424
AR
YB
ET
A
PR
EL
IM
IN
Available on Macintosh Mac 512KE and earlier.
BETA RELEASE
129
C64 RS232 User Port Connector
TIO
N.
C64 RS232 User Port
BU
RI
(At the computer)

DI
ST
Description
Protective Ground
Receive Data (Must be applied to both pins!)
Ready To Send
Data Terminal Ready
Ring Indicator
Data Carrier Detect
Clear To Send
Data Set Ready
Transmit Data
Signal Ground
RE
RS232
GND
RxD
RTS
DTR
RI
DCD
CTS
DSR
TxD
GND
Name
GND
FLAG2+PB0
PB1
PB2
PB3
PB4
PB6
PB7
PA2
GND
FO
Pin
A
B+C
D
E
F
H
K
L
M
N
Contributor: Joakim gren, Arwin Vosselman <0vosselman01@flnet.nl>, Mark Sokos

<msokos1@gl.umbc.edu>
OT
Source: Usenet posting in comp.sys.cbm, Help on modem -> c64

<http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt> by Lasher Glenn <gl8574@lima.albany.edu>
Sources: Commodore 64 Programmer's Reference Guide
AR
YB
ET
A
.N
PR
EL
IM
IN
Available on the Commodore C64/C128. Software emulated. The signals does not have true
RS232 levels. It's TTL level, and RXD/TXD is inverted. It's just the normal User Port, used
as a RS232 port.
BETA RELEASE
130
DEC DLV11-J Serial Connector
TIO
N.
DEC DLV11-J Serial
BU
(at the serial card)
DI
ST
Description
Clock
Ground
Transmit data +
Transmit data - (0V for RS-232, Reader enable for 20mA)
Ground
Not connected (no pin)
Receive data Receive data +
Ground
+12 VDC
RE
Name Dir
CLK ?
GND
TXD+
TXDGND
n/c
RXDRXD+
GND
+12V
Pin
1
2
3
4
5
6
7
8
9
10
RI
10 PIN IDC MALE at the Serial card.
FO
Note: Direction is Serial card relative other Devices.

Source: DEC DLV11-J Printset, M8043-0-1, sheet 7
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Available on the DEC DLV11-J Serial card
BETA RELEASE
131
Cisco Console Port Connector
TIO
N.
Cisco Console Port
BU
(At the cables)
Description
Dir
Request To Send
Data Terminal Ready
Tranceive Data
Not connected
Not connected
Receive Data
Data Set Ready
Clear To Send
FO
Name
RTS
DTR
TXD
n/c
n/c
RXD
DSR
CTS
OT
Pin
1
2
3
4
5
6
7
8
RE
RJ45 FEMALE CONNECTOR at the Cisco routers.

RJ45 MALE CONNECTOR at the cables.
DI
ST
RI
(At the Cisco hub)
Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Damien Miller <dmiller@vitnet.com.sg>
PR
EL
IM
IN
Used to configure a Cisco router.
BETA RELEASE
132
RocketPort Serialport Connector
TIO
N.
RocketPort Serialport
BU
DI
ST
RI
(At the RocketPort card)
(At the cables)
Description
Dir
Request To Send
Data Terminal Ready
Ground
Tranceive Data
Receive Data
Data Carrier Detect
Data Set Ready
Clear To Send
FO
Name
RTS
DTR
GND
TXD
RXD
DCD
DSR
CTS
OT
Pin
1
2
3
3
6
6
7
8
RE
RJ45 FEMALE CONNECTOR at the RocketPort card.

Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Karl Asha <karl@blackdown.com>
PR
EL
IM
IN
Available at RocketPort serialport expansion cards.
BETA RELEASE
133
CoCo Serial Printer
BU
(At the computer)

4 PIN DIN 270 FEMALE at the computer.
ST
RI
Name Description
NC
/BUSY Enabled when the printer is busy
GND
DATA RS-232 level data
DI
Pin
1
2
3
4
RE
Source: Tandy TRP 100 printer manual
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Available on the Tandy Color Computer, also known as CoCo.
TIO
N.
CoCo Serial Printer Connector
BETA RELEASE
134
Conrad Electronics MM3610D Connector
TIO
N.
Conrad Electronics MM3610D
BU
(At the multimeter).
DI
ST
Description
Dir
Request To Send
Receive Data
Transmit Data
Data Terminal Ready
Ground
RE
Conrad Name
1
RTS
2
RXD
3
TXD
4
DTR
5
GND
RI
5 PIN UNKNOWN CONNECTOR at the multimeter
Note: Since the multimeter is a DCE the pin naming can seem strange.
Contributors: Joakim gren, Anselm Belz <a.belz@samson.mbis.de>
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
This connector is available on the Conrad Electronics Multimeter 3610D and is used to
connect it to a computer.
BETA RELEASE
135
Parallel (PC) Connector
TIO
N.
(At the PC)
RI
ST
DI
RE
R
FO
OT
Description
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper End
Select
Autofeed
Error
Initialize
Select In
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
.N
Name
Dir
/STROBE
D0
D1
D2
D3
D4
D5
D6
D7
/ACK
BUSY
PE
SEL
/AUTOFD
/ERROR
/INIT
/SELIN
GND
GND
GND
GND
GND
GND
GND
GND
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB FEMALE at the PC.
Note: Direction is Computer relative Device.
YB

Source: ?
AR
PR
EL
IM
IN
Parallel (PC)
BETA RELEASE
136
Parallel (Amiga) Connector
TIO
N.
(At the Amiga)
OT
FO
RE
DI
ST
RI
Description
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper Out
Select (Shared with RS232 RING-indicator)
Not connected.
Reset
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
.N
Name
Dir
/STROBE
D0
D1
D2
D3
D4
D5
D6
D7
/ACK
BUSY
POUT
SEL
+5V PULLUP
n/c
/RESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB FEMALE at the Amiga.
Note: Direction is Computer relative Peripheral.
YB
AR
PR
EL
IM
IN
Parallel (Amiga)
BETA RELEASE
137
Parallel (Amiga 1000) Connector
TIO
N.
(At the Amiga 1000)
OT
FO
RE
DI
ST
RI
Description
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper Out
Select (Shared with RS232 RING-indicator)
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Not connected.
Reset
.N
Name
Dir
/STROBE
D0
D1
D2
D3
D4
D5
D6
D7
/ACK
BUSY
POUT
SEL
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
n/c
/RESET
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB MALE at the Amiga 1000.
YB
AR
PR
EL
IM
IN
Parallel (Amiga 1000)
BETA RELEASE
138
ECP Parallel Connector
TIO
N.
ECP Parallel
BU
(At the PC)
ST
OT
FO
RE
DI
Description
Strobe
Address, Data or RLE Data Bit 0
Acknowledge
Busy
Paper End
Select
Autofeed
Error
Initialize
Select In
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
.N
Name
Dir
nStrobe
data0
data1
data2
data3
data4
data5
data6
data7
/nAck
Busy
PError
Select
/nAutoFd
/nFault
/nInit
/nSelectIn
GND
GND
GND
GND
GND
GND
GND
GND
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RI
25 PIN D-SUB FEMALE at the PC.
YB

Contributor: Joakim gren, Marco Furter <maf@pop.agri.ch>
Source: Microsoft MSDN Library: Extended Capabilities Port Specs
AR
Info: Microsoft MSDN Library <http://www.microsoft.com/msdn>

PR
EL
IM
IN
ECP = Extended Capabilities Port
BETA RELEASE
139
ECP Parallel (Tech) Connector
TIO
N.
ECP Parallel (Technical)
BU
This file is not intended to be a thorough coverage of the standard. It is for informational
purposes only, and is intended to give designers and hobbyists sufficient information to
design their own ECP compatible devices.
RI
nStrobe
ST
This signal is registers data or address into the slave on the assering edge during .
DI
data 0-7
Contains address, data or RLE data. Can be used in both directions.
RE
nAck
Valid data driven by the peripheral when asserted. This signal handshakes with nAutoFd in
reverse.
FO
Busy
OT
This signal deasserts to indicate that the peripheral can accept data. In forward direction this
handshakes with nStrobe. In the reverse direction this signal indicates that the data is RLE
compressed by being low.
PError
.N
Used to acknowledge a change in the direction of transfer. High=Forward.
Select
ET
A
Printer is online.
nAutoFd
YB
Requests a byte of data from the peripheral when asserted, handshaking with nAck in the
reverse direction. In the forward direction this signal indicates whether the data lines contain
ECP address or data.
AR
nFault
Generates an error interrupt when asserted.
nInit
PR
EL
IM
IN
This file is designed to give a basic overview of the port found in most newer PC computers
called ECP Parallel port.
Sets the transfer direction. High=Reverse, Low=Forward.
nSelectIn
Low in ECP mode.

Source: Microsoft MSDN Library: Extended Capabilities Port Specs
Info: Microsoft MSDN Library <http://www.microsoft.com/msdn>
BETA RELEASE
140
Centronics Connector
TIO
N.
BU
(At the Printer)

36 PIN CENTRONICS FEMALE at the Printer.
ET
A
.N
OT
FO
RE
DI
ST
RI
Description
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper Out
Select
Autofeed
Not used
Logic Ground
Shield Ground
+5 V DC (50 mA max)
Signal Ground (Strobe Ground)
Signal Ground (Data 0 Ground)
Signal Ground (Acknowledge Ground)
Signal Ground (Busy Ground)
Reset Ground
Reset
Fault (Low when offline)
Signal Ground
Not used
+5 V DC
Select In (Taking low or high sets printer on line or off line
respectively)
YB
Name
Dir
/STROBE
D0
D1
D2
D3
D4
D5
D6
D7
/ACK
BUSY
POUT
SEL
/AUTOFEED
n/c
0V
CHASSIS GND
+5 V PULLUP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
/GNDRESET
/RESET
/FAULT
0V
n/c
+5 V
/SLCT IN
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PR
EL
IM
IN
Centronics
Note: Direction is Printer relative Computer.

Contributor: Joakim gren, Peter Korsgaard <jacmet@post5.tele.dk>, Petr Krc <magneton@mail.firstnet.cz>
Source: ?
BETA RELEASE
141
MSX Parallel Connector
TIO
N.
(At the Computer)
DI
ST
RI
Description
Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
RE
Dir
Printer is busy
-
Name
/STB
PDB0
PDB1
PDB2
PDB3
PDB4
PDB5
PDB6
PDB7
n/c
BUSY
n/c
n/c
GND
Signal Ground
FO
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BU
14 PIN CENTRONICS FEMALE at the Computer.
Note: Direction is Computer relative Printer.
OT
AR
YB
ET
A
.N
PR
EL
IM
IN
MSX Parallel
BETA RELEASE
142
Parallel (Olivetti M10) Connector
TIO
N.
Parallel (Olivetti M10)
BU
(At the Computer)
ST
DI
RE
R
FO
OT
Description
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper End
Select In
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Reset Ground
Reset
.N
Name
Dir
/STROBE
D0
D1
D2
D3
D4
D5
D6
D7
/ACK
BUSY
PE
SELIN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RESETGND
/RESET
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
RI
26 PIN IDC MALE at the Computer.
YB

Contributor: Joakim gren, Filippo Fiani <nathannever@rocketmail.com>
AR
Source: ?
PR
EL
IM
IN
Available on an old portable computer called Olivetti M10.
BETA RELEASE
143
Amstrad CPC6128 Printer Port Connector
TIO
N.
(At the computer)
RI
ST
DI
RE
R
FO
OT
.N
ET
A
Description
Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Ground
Not connected
Busy
Not connected
Not connected
Ground
Not connected
Not connected
Not connected
Ground
Not connected
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not connected
Ground
Not connected
Not connected
Not connected
Not connected
Ground
Not connected
Not connected
YB
Name
/STROBE
D0
D1
D2
D3
D4
D5
D6
GND
n/c
BUSY
n/c
n/c
GND
n/c
n/c
n/c
GND
n/c
GND
GND
GND
GND
GND
GND
GND
GND
n/c
GND
n/c
n/c
n/c
n/c
GND
n/c
n/c
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
16
17
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
BU
34 PIN FEMALE EDGE at the computer.
Note: Pin 18 does not exist
PR
EL
IM
IN
Amstrad CPC6128 Printer Port
Contributor: Joakim gren, Agnello Guarracino <aggy@ooh.diron.co.uk>

Source: Amstrad CPC6128 User Instructions Manual
BETA RELEASE
144
Universal Serial Bus (USB) Connector
TIO
N.
Universal Serial Bus (USB)
BU
RI
(At the controller)
ST
Description
+5 VDC
Data Data +
Ground
RE
Name
VCC
DD+
GND
Pin
1
2
3
4
DI

FO
Sources: USB FAQ <http://www.teleport.com/~usb/usbfaq.htm> at USB Implementers Forum

<http://www.usb.org>
Sources: USB Specification v1.0 at USB Implementers Forum <http://www.usb.org>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Developed by Compaq, Digital Equipment Corp, IBM PC Co., Intel, Microsoft, NEC and
Northern Telecom.
BETA RELEASE
145
Universal Serial Bus (USB) (Tech) Connector
TIO
N.
Universal Serial Bus (USB) (Technical)

Features:
ST
RI
BU
- True Plug'n'Play.
- Hot plug and unplug
- Low cost
- Easy of use
- 127 physical devices
- Low cost cables and connectors
DI
Bandwidth:
RE
- Full speed: 12 Mbps speed (requires shielded cable)

- Low speed: 1.5 Mbps speed (non-shielded cable)
Definitions:
FO
USB Host = The computer, only one host per USB system.
USB Device = A hub or a Function.
Power usage:
ET
A
.N
OT
Bus-powered hubs: Draw Max 100 mA at power up and 500 mA normally.

Self-powered hubs: Draw Max 100 mA, must supply 500 mA to each port.
Low power, bus-powered functions: Draw Max 100 mA.
High power, bus-powered functions: Self-powered hubs: Draw Max 100 mA, must supply
500 mA to each port.
Self-powered functions: Draw Max 100 mA.
Suspended device: Max 0.5 mA
Voltage:
Shielding:
AR
YB
- Supplied voltage by a host or a powered hub ports is between 4.75 V and 5.25 V.
- Maximum voltage drop for bus-powered hubs is 0.35 V from it's host or hub to the hubs
output port.
- All hubs and functions must be able to send configuration data at 4.4 V, but only low-power
functions need to be working at this voltage.
- Normal operational voltage for functions is minimum 4.75 V.
PR
EL
IM
IN
USB was developed by Compaq, Digital Equipment Corp, IBM PC Co., Intel, Microsoft, NEC
and Northern Telecom.
Shield should only be connected to Ground at the host. No device should connect Shield to
Ground.
Cable:
Shielded:
Data: 28 AWG twisted
Power: 28 AWG - 20 AWG non-twisted
Non-shielded:
Data: 28 AWG non-twisted
Power: 28 AWG - 20 AWG non-twisted
Power Gauge Max length
BETA RELEASE
146
TIO
N.
0.81 m
1.31 m
2.08 m
3.33 m
5.00 m
Cable colors:
Cable colorDescription
Red
+5 VDC
White
Data Green
Data +
Black
Ground
BU
Name
VCC
DD+
GND
RI
Pin
1
2
3
4
ST
DI
Sources: USB FAQ <http://www.teleport.com/~usb/usbfaq.htm> at USB Implementers Forum

<http://www.usb.org>
Sources: USB Specification v1.0 at USB Implementers Forum <http://www.usb.org>
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
28
26
24
22
20
BETA RELEASE
147
GeekPort Connector
TIO
N.
GeekPort
BU
(At the computer)
ST
RI
(At the device)
RE
R
FO
ET
A
.N
OT
Description
Dir
Ground
Digital A 1
Digital A 3
Digital A 5
Digital A 7
Ground
+5 VDC
Ground
+12 VDC
Ground
-12 VDC
Ground
+5 VDC
Ground
Digital B 0
Digital B 2
Digital B 4
Digital B 6
Ground
Digital A 0
Digital A 2
Digital A 4
Digital A 6
Analog In Reference
Analog In 1
Analog In 2
Analog In 3
Analog In 4
Analog Out 1
Analog Out 2
Analog Out 3
Analog Out 4
Analog Out Reference
Digital B 1
Digital B 3
Digital B 5
Digital B 7
YB
Name
GND
A1
A3
A5
A7
GND
+5V
GND
+12V
GND
-12V
GND
+5V
GND
B0
B2
B4
B6
GND
A0
A2
A4
A6
AIref
A2D1
A2D2
A2D3
A2D4
D2A1
D2A2
D2A3
D2A4
AOref
B1
B3
B5
B7
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
DI
37 PIN D-SUB MALE CONNECTOR at the device.

37 PIN D-SUB FEMALE CONNECTOR at the computer.
PR
EL
IM
IN
The GeekPort is a connector available at Be's BeBox computers.

This is a dream for all hobby engineers who like to connect the computer to the coffee
machine.

BETA RELEASE
148
GeekPort Connector
TIO
N.
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
BU
PR
EL
IM
IN
Sources: BeBox GeekPort DeviceKit <http://www.be.com/documentation/be_book/DeviceKit/geek.html> at Be's

homepage <http://www.be.com>
Sources: BeBox GeekPort DeviceKit: Analog port
<http://www.be.com/documentation/be_book/DeviceKit/A2D2A.html>
Sources: BeBox GeekPort DeviceKit: Digital port
<http://www.be.com/documentation/be_book/DeviceKit/DPort.html>
BETA RELEASE
149
C64/C16/C116/+4 Serial I/O
RI
BU
(At the computer)
6 PIN DIN (DIN45322) FEMALE at the Computer.

6 PIN DIN (DIN45322) MALE at the Cable.
DI
Description
Serial SRQIN
Ground
Serial ATN In/Out
Serial CLK In/Out
Serial DATA In/Out
Reset
RE
Name
/SRQIN
GND
ATN
CLK
DATA
/RESET
Pin
1
2
3
4
5
6
ST
(At the cable)
FO
Contributor: Joakim gren, Arwin Vosselman <0vosselman01@flnet.nl>

Source: SAMS Computerfacts CC8 Commodore 16.
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Available on the Commodore C64, C16, C116 and +4 computers.
TIO
N.
C64 Serial I/O Connector
BETA RELEASE
150
Atari ACSI DMA Connector
TIO
N.
Atari ACSI DMA
RI
BU
(At the Computer)
ST
(At the Devices)
RE
R
FO
OT
Description
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Chip Select
Interrupt Request
Ground
Reset
Ground
Acknowledge
Ground
?
Ground
Read/Write
Data Request
.N
Name
D0
D1
D2
D3
D4
D5
D6
D7
/CS
IRQ
GND
/RST
GND
ACK
GND
A1
GND
R/W
REQ
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DI
19 PIN D-SUB ?? at the Computer.

19 PIN D-SUB ?? at the Devices.
YB
Contributor: Joakim gren, Lawrence Wright <lwright@silk.net>, Steve & Sally Blair
<blair@mailbox.uq.edu.au>
Source: ?
AR
PR
EL
IM
IN
Used to connect Laser printers or Harddrives.
BETA RELEASE
151
VGA (VESA DDC) Connector
TIO
N.
VGA (VESA DDC)
RI
BU
Videotype: Analogue.
ST
(At the videocard)
DI
OT
FO
Description
Red Video (75 ohm, 0.7 V p-p)
Green Video (75 ohm, 0.7 V p-p)
Blue Video (75 ohm, 0.7 V p-p)
Reserved
Ground
Red Ground
Green Ground
Blue Ground
+5 VDC
Sync Ground
Monitor ID Bit 0 (optional)
DDC Serial Data Line
Horizontal Sync (or Composite Sync)
Vertical Sync
DDC Data Clock Line
.N
Name
Dir
RED
GREEN
BLUE
RES
GND
RGND
GGND
BGND
+5V
SGND
ID0
SDA
HSYNC or CSYNC
VSYNC
SCL
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RE
15 PIN HIGHDENSITY D-SUB FEMALE at the videocard.

15 PIN HIGHDENSITY D-SUB MALE at the monitor cable.
Note: Direction is Computer relative Monitor.
YB

Source: ?
AR
PR
EL
IM
IN
VGA=Video Graphics Adapter or Video Graphics Array.

VESA=Video Electronics Standards Association.
DDC=Display Data Channel.
BETA RELEASE
152
VGA (15) Connector
TIO
N.
VGA (15)
BU
RI
(At the videocard)
ST
FO
RE
Description
Red Video (75 ohm, 0.7 V p-p)
Green Video (75 ohm, 0.7 V p-p)
Blue Video (75 ohm, 0.7 V p-p)
Monitor ID Bit 2
Ground
Red Ground
Green Ground
Blue Ground
Key (No pin)
Sync Ground
Monitor ID Bit 0
Monitor ID Bit 1
Horizontal Sync (or Composite Sync)
Vertical Sync
Monitor ID Bit 3
OT
Name
Dir
RED
GREEN
BLUE
ID2
GND
RGND
GGND
BGND
KEY
SGND
ID0
ID1 or SDA
HSYNC or CSYNC
VSYNC
ID3 or SCL
.N
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DI
15 PIN HIGHDENSITY D-SUB FEMALE at the videocard.

15 PIN HIGHDENSITY D-SUB MALE at the monitor cable.

Source: ?
ET
A
AR
YB
PR
EL
IM
IN

BETA RELEASE
153
VGA (9) Connector
TIO
N.
VGA (9)
BU
RI
(At the videocard)
ST
RE
Description
Red Video
Green Video
Blue Video
Horizontal Sync
Vertical Sync
Red Ground
Green Ground
Blue Ground
Sync Ground
FO
Name Dir
RED
GREEN
BLUE
HSYNC
VSYNC
RGND
GGND
BGND
SGND
OT
Pin
1
2
3
4
5
6
7
8
9
DI
9 PIN D-SUB FEMALE at the videocard.

9 PIN D-SUB MALE at the monitor cable.

Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN

BETA RELEASE
154
CGA Connector
TIO
N.
CGA
BU
ST
RI
(At the videocard)
RE
Description
Ground
Ground
Red
Green
Blue
Intensity
Reserved
Horizontal Sync
Vertical Sync
FO
Name
GND
GND
R
G
B
I
RES
HSYNC
VSYNC
OT
Pin
1
2
3
4
5
6
7
8
9
AR
YB
ET
A
.N

Source: ?
DI

PR
EL
IM
IN
CGA=Color Graphics Adapter.

Videotype: TTL, 16 colors.
Also known as IBM RGBI.
BETA RELEASE
155
EGA Connector
TIO
N.
EGA
BU
RI
(At the videocard)
ST
RE
AR
YB
ET
A
.N
Source: ?
Description
Ground
Secondary Red
Primary Red
Primary Green
Primary Blue
Secondary Green / Intensity
Secondary Blue
Horizontal Sync
Vertical Sync
FO
Name
GND
SR
PR
PG
PB
SG/I
SB
H
V
OT
Pin
1
2
3
4
5
6
7
8
9
DI

PR
EL
IM
IN
EGA=Enhanced Graphics Adapter.

Videotype: TTL, 16/64 colors.
BETA RELEASE
156
PGA Connector
TIO
N.
PGA
RI
BU
(At the videocard)
ST
RE
Description
Red
Green
Blue
Composite Sync
Mode Control
Red Ground
Green Ground
Blue Ground
Ground
Name
R
G
B
CSYNC
MODE
RGND
GGND
BGND
GND
FO
Pin
1
2
3
4
5
6
7
8
9
DI

OT

Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
157
MDA (Hercules) Connector
TIO
N.
BU
(At the videocard)
RI
RE
DI
Description
Ground
Ground
Intensity
Mono Video
Horizontal Sync
Vertical Sync
Name
GND
GND
n/c
n/c
n/c
I
M
H
V
FO
Pin
1
2
3
4
5
6
7
8
9
ST

OT
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
MDA (Hercules)
BETA RELEASE
158
VESA Feature Connector
TIO
N.
(At the videocard)
RI
ST
DI
RE
R
FO
.N
n/c
GND
GND
GND
GND
n/c
n/c
Description
DAC Pixel Data Bit 0 (PB)
DAC Pixel Data Bit 1 (PG)
DAC Pixel Data Bit 2 (PR)
DAC Pixel Data Bit 3 (PI)
DAC Pixel Data Bit 4 (SB)
DAC Pixel Data Bit 5 (SG)
DAC Pixel Data Bit 6 (SR)
DAC Pixel Data Bit 7 (SI)
DAC Clock
DAC Blanking
Horizontal Sync
Vertical Sync
Ground
Ground
Ground
Ground
Select Internal Video
Select Internal Sync
Select Internal Dot Clock
Not used
Ground
Ground
Ground
Ground
Not used
Not used
OT
Name
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
CLK
BLK
HSYNC
VSYNC
GND
GND
GND
GND
YB
Source: ?
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
BU
26 PIN IDC at the Video card.
AR
PR
EL
IM
IN
VESA Feature
BETA RELEASE
159
Macintosh Video Connector
TIO
N.
(At the Computer)
RI
ST
DI
RE
Description
Red Ground
Red
Composite sync
Monitor Sense 0
Green
Green Ground
Monitor Sense 1
No connection
Blue
Monitor sense 2
Sync Ground
Vertical Sync
Blue Ground
Horizontal Sync Ground
Horizontal Sync
Name
Dir
RGND
R
CSYNC
SENSE0
G
GGND
SENSE1
n/c
B
SENSE2
SGND
VSYNC
BGND
HSYNCGND
HSYNC
FO
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BU
OT
AR
YB
ET
A
.N
Source: Tommy's pinout Collection <http://csgrad.cs.vt.edu/~tjohnson/pinouts> by Tommy Johnson

PR
EL
IM
IN
Macintosh Video
BETA RELEASE
160
Amiga Video Connector
TIO
N.
(At the Amiga)
OT
FO
RE
DI
ST
RI
Description
Extern Clock
Extern Clock Enable (47 Ohm)
Analog Red (75 Ohm)
Analog Green (75 Ohm)
Analog Blue (75 Ohm)
Digital Intensity (47 Ohm)
Digital Red (47 Ohm)
Digital Green (47 Ohm)
Digital Blue (47 Ohm)
Composite Sync (47 Ohm)
Horizontal Sync (47 Ohm)
Vertical Sync (47 Ohm)
Digital Ground (for /XCLKEN) Don't connect with pin 16-20.
Genlock overlay (47 Ohm)
Clock out (47 Ohm)
Video Ground
Video Ground
Video Ground
Video Ground
Video Ground
-12 Volts DC (10 mA max) (A500/A600/A1200)
-5 Volts DC (10 mA max) (A1000/A2000/A3000/A4000)
.N
22
23
Name
Dir
/XCLK
/XCLKEN
RED
GREEN
BLUE
DI
DR
DG
DB
/CSYNC
/HSYNC
/VSYNC
GNDRTN
/PIXELSW
/C1
GND
GND
GND
GND
GND
-12V
-5V
+12V
+5V
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
BU
23 PIN D-SUB MALE at the Amiga.

YB
AR
PR
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IM
IN
Amiga Video
BETA RELEASE
161
Amiga 1000 RF Monitor Connector
TIO
N.
(At the computer)
ST
RI
Description
Not connected
Ground
Audio Left
Composite Video
Ground
Not connected
+12 VDC
Audio Right
DI
Name
Dir
n/c
GND
AUDL
CVIDEO
GND
n/c
+12V
AUDR

Source: ?
RE
Pin
1
2
3
4
5
6
7
8
BU
8 PIN DIN "C" FEMALE at the computer.
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Amiga 1000 RF Monitor
BETA RELEASE
162
CDTV Video Slot Connector
16
--15
18
--17
20
--19
22
--21
24
--24
26
--25
28
--27
TIO
N.
14
--13
30
--29
BU
2 4 6 8 10 12
-- -- -- -- -- --- -- -- -- -- -1 3 5 7 9 11
RI
(At the computer)

30 PIN ??? CONNECTOR at the computer.
ET
A
.N
OT
FO
RE
DI
ST
Description
Video Ground
Video Ground
External Genlock Clock (in)
Red (in to video card)
Enables External Clock on XCLK.
Buffered Red (out from video card)
Video Ground
Green (in to video card)
Genlock mode 0 (from computer, genlock button)
Buffered Green (out from video card)
Genlock mode 1 (from computer, genlock button)
Blue (in to video card)
Genlock signal
Buffered Blue (out from video card)
Vertical Sync (in to video card)
Horizontal Sync (in to video card)
Composite Sync (in to video card)
Buffered Composite Sync (out from video card)
Video Ground
Audio Right Output (from computer to RF modulator)
Digital Ground
Audio Left Output (from computer to RF modulator)
-12 VDC (can be -5 VDC instead)
Digital Ground
+12 VDC
CD/TV button. (Low=CDTV video on RF, High=Antenna)
+5 VDC
3.58 MHz color clock (C1 clock)
Video Ground
+5 VDC
YB
Name
GND
GND
XCLK
R
/XCLKEN
BR
GND
G
GMS0
BG
GMS1
B
/PIXELSW
BB
VSYNC
CSYNC
HSYNC
BCSYNC
GND
AUDR
DGND
AUDL
-12V
DGND
+12V
/CD/TV
VCC
/CCK
GND
VCC
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Note: Used for RF-modulator usually.
PR
EL
IM
IN
CDTV Video Slot

Source: Darren Ewaniuk's CDTV Technical Information
<http://nyquist.ee.ualberta.ca/~ewaniu/cdtv/cdtv-technical.html>
BETA RELEASE
163
PlayStation A/V Connector
TIO
N.
PlayStation A/V
RI
BU
+--------------+
| oooooooooooo |
+--------------+
1
12
(At the PlayStation)
RE
DI
Description
Ground
Right Audio
Ground
Left Audio
S-Video Y
Composite Sync
S-Video C
Video Ground
Blue
+5 VDC
Red
Green
FO
Name
GND
RT
GND
LT
Y
SYNC
C
VGND
B
+5V
R
G
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
ST
12 PIN ?? at the PlayStation.
Contributor: Lawrence Wright <lwright@silk.net>
AR
YB
ET
A
.N
Source: Sony PlayStation A/V Pinout <http://www.gamesx.com/psxav.htm>
PR
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Availble on the Sony PlayStation Videogame.
BETA RELEASE
164
(At the Monitor)
RI
Description
Green
Horizontal Sync
Ground
Red
Blue
Vertical Sync
ST
Name
G
HSYNC
GND
R
B
VSYNC
DI
Pin
1
2
3
4
5
6
BU
6 PIN DIN FEMALE at the Monitor.
RE
Source: National Amiga's C1084 page <http://www.interlog.com/~gscott/t-1084.html>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Commodore 1084 & 1084S (Analog)
TIO
N.
Commodore 1084 & 1084S (Analog) Connect
BETA RELEASE
165
Commodore 1084 & 1084S (Digital) Connect
TIO
N.
(At the Monitor)
ST
RI
Description
Not connected
Red
Green
Blue
Intensity
Ground
Horizontal Sync
Vertical Sync
DI
Name
n/c
R
G
B
I
GND
HSYNC
VSYNC
RE
Pin
1
2
3
4
5
6
7
8
BU
8 PIN DIN 'C' FEMALE at the Monitor.
Source: National Amiga's C1084 page <http://www.interlog.com/~gscott/t-1084.html>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Commodore 1084 & 1084S (Digital)
BETA RELEASE
166
Commodore 1084d & 1084dS Connector
TIO
N.
(At the Monitor)
RI
Digital Mode
Ground
Ground
Red
Green
Blue
Intensity
n/c
Horizontal Sync
Vertical Sync
ST
Analog Mode
Ground
Ground
Red
Green
Blue
n/c
Composite Sync
n/c
n/c
DI
Name
GND
GND
R
G
B
I
CSYNS
HSYNC
VSYNC
RE
Pin
1
2
3
4
5
6
7
8
9
BU
9 PIN D-SUB FEMALE at the Monitor.
Source: National Amiga's C1084d page <http://www.interlog.com/~gscott/t-1084d.html>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Commodore 1084d & 1084dS
BETA RELEASE
167
Atari Jaguar A/V Connector
TIO
N.
Atari Jaguar A/V

2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
BU
1A
RI
(At the Atari)
ST
12 PIN ?? at the Atari.

Name
AL
AGND
GND
GND (chroma)
B
HSYNC
G
CHROMA
GND ???
+5V ???
+5V ???
?
Description
Audio Left
Audio Ground
Ground
Ground (Chroma)
RGB Blue
Horizontal sync
RGB Green
Chroma
Ground ???
+5 VDC ???
+5 VDC ???
?
1B
2B
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
AR
AGND
GND
R
CSYNC
?
LGND
LUM
GND
CVBSGND
CVBS
?
Right audio
Audio GND
Ground
RGB Red
Composite (Vertical) Sync
?
Luminance Ground
Luminance
Ground
Composite Video Ground
Composite Video
?
YB
ET
A
.N
OT
FO
RE
DI
Pin
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
AR
Source: Scooping out Jaguar RGB by Duncan Brown <BROWN_DU@Eisner.DECUS.Org> in Atari Explorer
Online Vol.3 Issue 6 <http://www.redsun.net/jaguar/aeo/aeo_0306.txt>
PR
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TOP (duh)
BETA RELEASE
168
SNES Video Connector
TIO
N.
SNES Video
RI
BU
+-------------------+
| 11 9 7 5 3 1 |
| 12 10 8 6 4 2 |
+-------------------+
(At the SNES)
RE
DI
Description
Red (Requires 200 uF in series)
Green (Requires 200 uF in series)
Composite Sync
Blue (Requires 200 uF in series)
Ground
Ground
S-Video Y
S-Video C
Composite Video (NTSC)
+5 VDC
Left+Right Audio (Mono)
Left-Right Audio (Used to calculate Stereo)
FO
Name
R
G
CSYNC
B
GND
GND
Y
C
CVBS
+5V
L+R
L-R
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
ST
UNKNOWN CONNECTOR at the SNES.
AR
YB
ET
A
.N
Source: Video Games FAQ (Part 3)

<http://www.lib.ox.ac.uk/internet/news/faq/archive/games.video-games.faq.part3.html>, Pinout from Radio
Electronics April 1992
PR
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Available on the Nintendo SNES.
BETA RELEASE
169
NeoGeo Audio/Video Connector
TIO
N.
NeoGeo Audio/Video
BU
(At the Computer)

ST
RI
Description
Audio out
Ground
Composite Video Out
+5 VDC
Green Video
Red Video
Negative Sync
Blue Video
DI
Name Dir
AOUT
GND
VIDEO
+5V
GREEN
RED
NSYNC
BLUE
RE
Pin
1
2
3
4
5
6
7
8
Contributor: Joakim gren, Enzo <enzo@gaianet.net>, Steffen Kupfer <Steffen_Kupfer@compuserve.com>
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Available on the NeoGeo videogame.
BETA RELEASE
170
Amstrad CPC6128 Monitor Connector
TIO
N.
(At the computer)
ST
RI
Name
RED
GREEN
BLUE
SYNC
GND
LUM
DI
Pin
1
2
3
4
5
6
BU
6 PIN DIN (DIN45322) FEMALE at the computer.
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
Amstrad CPC6128 Monitor
BETA RELEASE
171
Amstrad CPC6128 Plus Monitor Connector
TIO
N.
(At the computer)
ST
RI
Description
Sync?
Green
Lumninace
Red
Blue
Audio Output Left
Audio Output Right
Ground
DI
Name Dir
NSYNC
GREEN
LUM
RED
BLUE
AOL
AOR
GND
RE
Pin
1
2
3
4
5
6
7
8
BU
Source: Amstrad 6128 Plus Home Computer Manual
AR
YB
ET
A
.N
OT
FO
Contributor: Joakim gren, Colin Gaunt <c.gaunt@c-gaunt.prestel.co.uk>
PR
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IN
Amstrad CPC6128 Plus Monitor
BETA RELEASE
172
Atari ST Monitor Connector
TIO
N.
BU
(At the Computer)
RI
(At the Devices)
DI
RE
Description
Audio Out
Composite Video
Clock Select
Monochrome Detect / Clock In
Audio In
Green
Red
+12 VDC (520ST has GND)
Horizontal Sync
Blue
Monochrome Video
Vertical Sync
Ground
FO
Name
AO
CVIDEO
CS
MD
AI
G
R
+12V
HSYNC
B
MVIDEO
VSYNC
GND
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
ST
13 PIN DIN FEMALE at the Computer.

13 PIN DIN MALE at the Devices.
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
Atari ST Monitor
BETA RELEASE
173
Sun Video Connector
TIO
N.
(At the Computer)
DI
ST
RI
Description
Ground*
Vertical Sync*
Sense #2
Sense Ground
Composite Sync
Horizontal Sync*
Ground*
Sense #1
Sense #0
Composite Ground
Red
Green/Gray
Blue
RE
Name
GND
VSYNC
SENSE2
SENSEGND
CSYNC
HSYNC
GND
SENSE1
SENSE0
CGND
RED
GREEN/GRAY
BLUE
Pin
1
2
3
4
5
6
7
8
9
10
R
G
B
BU
13 PIN 13W3 FEMALE at the Computer.
FO
*) Considered obsolete, may not be connected.

Monitor-sense bits defined as:
.N
OT
Bit 2 Bit 1 Bit 0 Resolution

0
0
0
?
0
0
1
Reserved
0
1
0
1280 x 1024 76Hz
0
1
1
1152 x 900 66Hz
1
0
0
1152 x 900 76Hz 19"
1
0
1
Reserved
1
1
0
1152 x 900 76Hz 16-17"
1
1
1
No monitor connected
ET
A
Value
0
1
2
3
4
5
6
7
AR
YB
See http://cvs.anu.edu.au:80/monitorconversion/
<http://cvs.anu.edu.au:80/monitorconversion/> and
http://rugmd0.chem.rug.nl/~everdij/hitachi.html
<http://rugmd0.chem.rug.nl/~everdij/hitachi.html> for info on attaching old workstation
monitors to VGA boards.

PR
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IM
IN
Sun Video
BETA RELEASE
174
ZX Spectrum 128 RGB Connector
TIO
N.
ZX Spectrun 128 RGB
RI
BU
(At the computer)

8 PIN DIN (DIN45326) MALE at the monitor cable.
RE
DI
Description
Composite Video (PAL, 75 ohms, 1.2V p-p)
Ground
Bright Output
Composite Sync
Vertical Sync
Green
Red
Blue
Name Dir
CVBS
GND
BOUT
CSYNC
VSYNC
G
R
B
FO
Pin
1
2
3
4
5
6
7
8
ST
OT
AR
YB
ET
A
.N
Source: Online ZX Spectrum 128 Manual Page 3

<http://users.ox.ac.uk/~uzdm0006/Damien/speccy/128manua/sp128p03.html>
PR
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IN
Can be found at the Sinclair ZX Spectrum 128.
BETA RELEASE
175
3b1/7300 Video Connector
TIO
N.
(At the computer)
DI
ST
RI
Description
Vertical Sync
Ground
Horizontal Sync
Ground
Video
Ground
+12 VDC
Ground
+12 VDC
Speaker
Speaker
?
RE
Name
VSYNC
GND
HSYNC
GND
VIDEO
GND
+12V
GND
+12V
SPK
SPK
?
Pin
1
2
3
4
5
6
7
8
9
10
11
12
BU
12 PIN IDC MALE at the computer.
FO

AR
YB
ET
A
.N
OT
PR
EL
IM
IN
3b1/7300 Video
BETA RELEASE
176
CM-8/CoCo RGB
RI
BU
+-----------+
| 1 3 5 7 9 |
| 2 4
8 10|
+-----------+
(At the CoCo)
RE
DI
Description
Ground
Ground
Red
Green
Blue
No Pin
Audio
Horizontal Sync
Vertical Sync
No Connection
Name
GND
GND
R
G
B
KEY
AUDIO
HSYNC
VSYNC
n/c
FO
Pin
1
2
3
4
5
6
7
8
9
10
ST
UNKNOWN CONNECTOR at the CoCo.
OT
Source: Tandy Color Computer FAQ <http://www.io.com/~vga2000/faqs/coco.faq> at Video Game Advantage's

homepage <http://www.io.com/~vga2000/>
AR
YB
ET
A
.N
PR
EL
IM
IN
Available on the Tandy/Radio Shack Color Computer (CoCo).
TIO
N.
CM-8/CoCo RGB Connector
BETA RELEASE
177
AT&T 53D410 Connector
TIO
N.
(At the computer)
RI
ST
DI
RE
R
FO
OT
Description
?
Vertical Sync
Horizontal Sync
?
Video
?
?
?
?
?
?
?
Ground
Ground
Ground
?
?
?
?
?
?
?
?
?
?
.N
Name
?
VSYNC
HSYNC
?
VIDEO
?
?
?
?
?
?
?
GND
GND
GND
?
?
?
?
?
?
?
?
?
?
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB ??? at the computer.
YB

AR
PR
EL
IM
IN
AT&T 53D410
BETA RELEASE
178
AT&T 6300 Taxan Monitor Connector
TIO
N.
(At the Monitor)
RI
ST
Description
Special TEXT signal (??)
Red
Green
Blue
Intensity
Signal Ground
Horizontal or Composite Sync
Vertical Sync
DI
Name
TEXT
R
G
B
I
GND
HSYNC/CSYNC
VSYNC
RE
Pin
1
2
3
4
5
6
7
8
BU
8 PIN DIN (DIN45326) FEMALE at the Monitor.

AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
AT&T 6300 Taxan Monitor
BETA RELEASE
179
AT&T PC6300 Connector
TIO
N.
(At the computer)
RI
ST
DI
RE
R
FO
OT
Description
Horizontal Sync
Monitor ID 0
Vertical Sync
Red
Green
Blue
Not connected
Not connected
Monitor ID 1
Mode 0
Not connected
Degauss
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Not connected
Not connected
+15 VDC
+15 VDC
.N
Name
HSYNC
ID0
VSYNC
R
G
B
n/c
n/c
ID1
MODE0
n/c
/DEGAUSS
GND
GND
GND
GND
GND
GND
GND
GND
n/c
n/c
+15V
+15V
ET
A
Pin
1
2
3
4
5
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
25 PIN D-SUB ??? at the computer.
Monochrome monitor: ID0 and ID1 are open

Color monitor: ID0 is 0, and ID1 is 1, probably 5V, not 15V
YB

AR
PR
EL
IM
IN
AT&T PC6300
BETA RELEASE
180
Vic 20 Video Connector
TIO
N.
BU
(At the computer)
Description
+6 VDC (10 mA max)
Ground
Audio
Video Low (Unconnected ?)
Video High
DI
Name Dir
+6V
GND
AUDIO
VLOW
VHIGH
RE
Pin
1
2
3
4
5
ST
5 PIN DIN 180 (DIN41524) FEMALE at the Computer.

5 PIN DIN 180 (DIN41524) MALE at the Cable.
RI
(At the cable)
FO
Source: CBM Memorial Page Pinouts <http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Vic 20 Video
BETA RELEASE
181
C64 Audio/Video Connector
TIO
N.
BU
(At the computer)
Description
Luminance
Ground
Audio Out
Video Out
Audio In
DI
Name Dir
LUM
GND
AOUT
VOUT
AIN
RE
Pin
1
2
3
4
5
ST
5 PIN DIN 180 (DIN41524) FEMALE at the Computer.

5 PIN DIN 180 (DIN41524) MALE at the Cable.
RI
(At the cable)
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
C64 Audio/Video
BETA RELEASE
182
C65 Video Connector
TIO
N.
C65 Video
BU
(At the Computer)
ST
Description
Ground
?
Red
Green
Blue
?
Composite Sync
Horizontal Sync
Vertical Sync
DI
Name Dir
GND
?
R
G
B
?
CSYNC
HSYNC
VSYNC
RE
Pin
1
2
3
4
5
6
7
8
9
RI
FO
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Available on the Commodore C65 computer.
BETA RELEASE
183
C128 RGBI Connector
TIO
N.
(At the Computer)
ST
RI
Description
Ground
Ground
Red
Green
Blue
Intensity
Composite Video
Horizontal Sync
Vertical Sync
DI
Name Dir
GND
GND
R
G
B
I
VIDEO
HSYNC
VSYNC
RE
Pin
1
2
3
4
5
6
7
8
9
BU
FO
Source: Usenet posting in comp.sys.cbm, C128 screen cables

<http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt> by Marko Makela <msmakela@cc.helsinki.fi>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
C128 RGBI
BETA RELEASE
184
C128/C64C Video Connector
TIO
N.
C128/C64C Video
BU
(At the Computer)
ST
Description
Luminance (monochrome video)
Ground
Audio out
Composite Video out
Audio in (into the SID chip)
Not connected
Not connected
Chroma
DI
Name Dir
LUM
GND
AOUT
VOUT
AIN
n/c
n/c
C
RE
Pin
1
2
3
4
5
6
7
8
RI
FO
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Seems to be available on the C128 and the C64C (white colour). Compatible with cables for
the 5 pin D-SUB on C64's.
BETA RELEASE
185
C16/C116/+4 Audio/Video Connector
TIO
N.
C16/C116/+4 Audio/Video
BU
(At the Computer)
ST
Description
Luminance (monochrome video)
Ground
Audio out
Composite Video out
Audio in (into the SID chip)
Color ?
Not connected
+5 VDC
DI
Name Dir
LUM
GND
AOUT
VOUT
AIN
COLOR n/c
+5VDC
RE
Pin
1
2
3
4
5
6
7
8
RI
FO
Sources: CBM Memorial Page Pinouts <http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt>

Sources: SAMS Computerfacts CC8 Commodore 16.
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Available on Commodore C16/C116/+4 computers.
BETA RELEASE
186
CBM 1902A Connector
TIO
N.
CBM 1902A
BU
(At the Monitor)

6 PIN DIN FEMALE at the Monitor.
ST
RI
Description
Not connected
Audio
Ground
Chroma
Not connected
Luminance
Note: Direction is Monitor relative Computer.

DI
Name Dir
n/c
AUDIO
GND
C
n/c
L
RE
Pin
1
2
3
4
5
6
Source: comp.sys.cbm General FAQ v3.1 Part 7

<http://www.lib.ox.ac.uk/internet/news/faq/archive/cbm-main-faq.3.1.p7.html>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Available on the Commodore CBM 1902A monitor.
BETA RELEASE
187
(At the computer)
Description
Power
System ground
Audio out
Composite Video out
RF Video out
RI
Name
+5v
GND
AUDIO
VIDEO
RF VID
ST
Pin
1
2
3
4
5
BU
5 PIN DIN 180 (DIN41524) FEMALE at the computer.
DI
RE
Source: Spectravideo SVI 328 mk II User Manual
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Spectravideo SVI318/328 Audio/Video
TIO
N.
Spectravideo SVI318/328 Audio/Video Conne
BETA RELEASE
188
PC Gameport Connector
TIO
N.
BU
(At the computer)
RI
(At the joystick cable)
FO
RE
DI
Description
+5 VDC
Button 1
Joystick 1 - X
Ground
Ground
Joystick 1 - Y
Button 2
+5 VDC
+5 VDC
Button 4
Joystick 2 - X
Ground
Joystick 2 - Y
Button 3
+5 VDC
OT
Name Dir
+5V
/B1
X1
GND
GND
Y1
/B2
+5V
+5V
/B4
X2
GND
Y2
/B3
+5V
.N
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ST

15 PIN D-SUB MALE at the joystick cable.

Source: ?
ET
A
Note: Direction is Computer relative Joystick.

Note: Use 100kohm resistor.
AR
YB
PR
EL
IM
IN
PC Gameport
BETA RELEASE
189
PC Gameport+MIDI Connector
TIO
N.
PC Gameport+MIDI
BU
RI
(At the computer)
ST
RE
R
FO
Description
+5 VDC
Button 1
Joystick 1 - X
Ground
Ground
Joystick 1 - Y
Button 2
+5 VDC
+5 VDC
Button 4
Joystick 2 - X
MIDI Transmit
Joystick 2 - Y
Button 3
MIDI Receive
OT
Name
Dir
+5V
/B1
X1
GND
GND
Y1
/B2
+5V
+5V
/B4
X2
MIDITXD
Y2
/B3
MIDIRXD
.N
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DI

15 PIN D-SUB MALE at the joystick cable.
YB
Source: ?
ET
A

Note: Use 100 kohm resistor.
AR
PR
EL
IM
IN
Some soundcards have some MIDI signals included in their Gameport. Ground and VCC
has been used for this.
BETA RELEASE
190
Amiga Mouse/Joy Connector
TIO
N.
BU
(At the computer)
RI
(At the mouse/joy cable)
Comment
RE
DI
Digital JoystickPaddle
Dir
/FORWARD
BUTTON 3
/BACK
n/c
/LEFT
BUTTON 1
/RIGHT
BUTTON 2
n/c
PotX
/BUTTON 1
n/c
+5V
+5V
GND
GND
BUTTON 2
PotY
Mouse/TrackballLightpen
V-pulse
n/c
H-pulse
n/c
VQ-pulse
n/c
HQ-pulse
n/c
BUTTON 3(M) Penpress
BUTTON 1(L)
/Beamtrigger
+5V
+5V
GND
GND
BUTTON 2(R) BUTTON 2
50 mA max
FO
Pin
1
2
3
4
5
6
7
8
9
ST

9 PIN D-SUB FEMALE at the mouse/joy cable.
OT

Note: Pot is a linear 470 kOhm (10 %)
AR
YB
ET
A
.N
PR
EL
IM
IN
Amiga Mouse/Joy
BETA RELEASE
191
C64 Control Port Connector
TIO
N.
BU
(At the computer)
RI
ST

9 PIN D-SUB FEMALE at the joystick cable.
50 mA max
Control Port 2
.N
Comment
ET
A
Name
Dir
JOYB0
JOYB1
JOYB2
JOYB4
POT BY
BUTTON B
+5V
GND
POT BX
50 mA max
YB
Pin
1
2
3
4
5
6
7
8
9
RE
Comment
FO
Name
Dir
JOYA0
JOYA1
JOYA2
JOYA4
POT AY
BUTTON A/LP
+5V
GND
POT AX
OT
Pin
1
2
3
4
5
6
7
8
9
DI
Control Port 1
AR

Note: Pot is a linear 470 kOhm (10 %)
Sources: Amiga 4000 User's Guide from Commodore
Sources: Commodore 64 Programmer's Reference Guide
PR
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IM
IN
C64 Control Port
BETA RELEASE
192
C16/C116/+4 Joystick Connector
TIO
N.
C16/C116/+4 Joystick
BU
(At the computer)

DI
RE
Is connected to DATA2 thru a buffer.
Joystick 2
OT
Comment
.N
Name
Dir
JOYB0
JOYB1
JOYB2
JOYB3
+5VDC
BUTTON B
?
GND
COMMON B ? ?
Is connected to DATA1 thru a buffer.
ET
A
Pin
1
2
3
4
5
6
7
8
ST
Comment
Name
Dir
JOYA0
JOYA1
JOYA2
JOYA3
+5VDC
BUTTON A
?
GND
COMMON A ? ?
FO
Pin
1
2
3
4
5
6
7
8
RI
Joystick 1

YB
AR
PR
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IM
IN
Available on the Commodore C16, C116 and +4 computers.
BETA RELEASE
193
MSX Joystick Connector
TIO
N.
BU
(At the computer)
RI
DI
RE
Description
Forward
Backward
Left
Right
+5 VDC (50mA max)
Trigger A / Output 1
Trigger A / Output 1
Output 3
Signal Ground
Name
Dir
/FORWARD
/BACK
/LEFT
/RIGHT
+5V
/TRG1
/TRG2
OUTPUT
GND
FO
Pin
1
2
3
4
5
6
7
8
9
ST

.N
OT
Warning: Pin 5 is +5V on MSX and Mouse Button 2 on Amiga. Since Amiga mousebutton is
active low, connecting an Amiga mouse to a MSX and pressing mousebutton 2 will shortcut
the supply voltage.
AR
YB
ET
A
PR
EL
IM
IN
MSX Joystick
BETA RELEASE
194
SGI Mouse (Model 021-0004-002) Connector
TIO
N.
(At the Computer)
RI
Description
+5 VDC
-5 VDC
Not connected
Not connected
Data
Not connected
Not connected
Not connected
Ground
ST
Dir
DI
Name
+5V
-5V
n/c
n/c
MTXD
n/c
n/c
n/c
GND
RE
Pin
1
2
3
4
5
6
7
8
9
BU
9 PIN D-SUB ??? at the Computer.
FO

AR
YB
ET
A
.N
OT
PR
EL
IM
IN
SGI Mouse (Model 021-0004-002)
BETA RELEASE
195
Macintosh Mouse Connector
TIO
N.
Macintosh Mouse
RI
BU
(At the computer)
ST
(At the mouse cable)
RE
Description
Chassis ground
+5 VDC
Chassis ground
Horizontal movement line (connected to VIA PB4 line)
Horizontal movement line (connected to SCC DCDA-line)
Not connected
Mouse button line (connected to VIA PB3)
Vertical movement line (connected to VIA PB5 line)
Vertical movement line (connected to SCC DCDB-line)
Name Dir
CGND
+5V
CGND
X2
X1
n/c
SWY2
Y1
FO
Pin
1
2
3
4
5
6
7
8
9
DI

9 PIN D-SUB MALE at the mouse cable.
OT

AR
YB
ET
A
.N
PR
EL
IM
IN
Available on Macintosh Mac Plus and earlier.
BETA RELEASE
196
Atari Mouse/Joy Connector
TIO
N.
BU
(At the computer)
RI
(At the mouse/joy cable)
DI
Comment
RE
JoystickDir
UP
DOWN
LEFT
RIGHT
n/c
FIRE
+5V
GND
res
Mouse
XB
XA
YA
YB
n/c
LEFTBUTTON
+5V
GND
RIGHTBUTTON
FO
Pin
1
2
3
4
5
6
7
8
9
ST

9 PIN D-SUB FEMALE at the mouse/joy cable.
OT
Contributor: Joakim gren, Steve & Sally Blair <blair@mailbox.uq.edu.au>

Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
Atari Mouse/Joy
BETA RELEASE
197
Atari Enhanced Joystick Connector
TIO
N.
Atari Enhanced Joystick
BU
(At the computer)
ST
DI
OT
RE
Description
Up 0
Down 0
Left 0
Right 0
Paddle 0 Y
Fire 0/Lightgun
+5 VDC
Not connected
Ground
Fire 2
Up 2
Down 2
Left 2
Right 2
Paddle 0 X
Name
UP0
DOWN0
LEFT0
RIGHT0
PAD0Y
FIRE0/LIGHT GUN
VCC
n/c
GND
FIRE2
UP2
DOWN2
LEFT2
RIGHT2
PAD0X
FO
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RI
AR
YB
ET
A
.N
Source: Do-It-Yourself Atari Jaguar Controller <http://dcpu1.cs.york.ac.uk:6666/~andrew/atari/DIYjoypad.txt>

by Andrew Hague <andrew@minster.york.ac.uk>
PR
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IM
IN
Can be found at Atari Falcon, Jaguar & STe.
BETA RELEASE
198
Atari 2600 Joystick Connector
TIO
N.
BU
(At the Atari)
RI
RE
DI
Description
Up
Down
Left
Right
Not connected
Button
Not connected
Ground(-)
Not connected
Color Dir
WHT
BLU
GRN
BRN
n/c ORG
n/c BLK
n/c -
FO
Pin
1
2
3
4
5
6
7
8
9
ST
9 PIN D-SUB MALE at the Atari.

OT

Note: Connect Direction/Button to Ground for action.
AR
YB
ET
A
.N
Source: Classic Atari 2600/5200/7800 Game Systems FAQ

<http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>, Pinout by Greg Alt <galt@cs.utah.edu>
PR
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Atari 2600 Joystick
BETA RELEASE
199
TIO
N.
(At the Atari)
RI
ST
DI
RE
R
Description
Keypad -- right column
Keypad -- middle column
Keypad -- left column
Start, Pause, and Reset common
Keypad -- third row and Reset
Keypad -- second row and Pause
Keypad -- top row and Start
Keypad -- bottom row
Pot common
Horizontal pot (POT0, 2, 4, 6)
Vertical pot (POT1, 3, 5, 7)
5 volts DC
Bottom side buttons (TRIG0, 1, 2, 3)
Top side buttons
0 volts -- ground
FO
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BU
UNKNOWN CONNECTOR at the Atari.
Contributor: Joakim gren, Eric Parent <eparent@equinox.shaysnet.com>
OT

<http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>
AR
YB
ET
A
.N
PR
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IM
IN
Atari 5200 Joystick
BETA RELEASE
200
TIO
N.
BU
(At the Atari)
RI
RE
DI
Description
Up
Down
Left
Right
Button (R)ight (-)
Both buttons (+)
Not connected
Ground(-)
Button (L)eft (-)
Color Dir
WHT
BLU
GRN
BRN
RED
ORG ?
n/c BLK
YLW
FO
Pin
1
2
3
4
5
6
7
8
9
ST
9 PIN D-SUB MALE at the Atari.

OT

Note: Connect Direction and Button(L/R) to Ground for action. And Both Button to Button L
and Button R for action.
AR
YB
ET
A
.N

PR
EL
IM
IN
Atari 7800 Joystick
BETA RELEASE
201
Amstrad Digital Joystick Connector
TIO
N.
Amstrad Digital Joystick
RI
BU
(At the Computer)
ST
(At the Joystick cable)
DI

9 PIN D-SUB FEMALE at the Joystick cable.
Description
Up
Down
Left
Right
Not connected
Fire button 2
Fire button 1
Ground
Not connected
ET
A
Name Dir
UP
DOWN
LEFT
RIGHT
n/c
FIRE2
FIRE1
GND
n/c
-
YB
Pin
1
2
3
4
5
6
7
8
9
.N
Digital Joystick 2
Description
Up
Down
Left
Right
Not connected
Fire button 2
Fire button 1
Ground
Ground
FO
Name Dir
UP
DOWN
LEFT
RIGHT
n/c
FIRE2
FIRE1
GND
GND
OT
Pin
1
2
3
4
5
6
7
8
9
RE
Digital Joystick 1
AR

Contributor: Joakim gren, Colin Gaunt <c.gaunt@c-gaunt.prestel.co.uk>, Agnello Guarracino
<aggy@ooh.diron.co.uk>
PR
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IM
IN
Available at the Amstrad CPC6128 and CPC6128 Plus.

BETA RELEASE
202
NeoGeo Joystick Connector
TIO
N.
NeoGeo Joystick
BU
(At the Computer)

14 PIN CANNON (2 ROWS) ?? at the Computer.
ST
DI
RE
Description
Ground
Not connected
Select Button
"D" Button
"B" Button
Right
Down
Not connected
"D" Button, again?
Not connected
Start Button
"C" Button
"A" Button
Left
Up
Dir
FO
Name
GND
n/c
SELECT
BUTTOND
BUTTONB
RIGHT
DOWN
n/c
BUTTOND
n/c
START
BUTTONC
BUTTONA
LEFT
UP
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RI
Could anyone please tell me what kind of connector it has.

Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Enzo <enzo@gaianet.net>
PR
EL
IM
IN
Available on the NeoGeo videogame.
BETA RELEASE
203
Keyboard (5 PC) Connector
TIO
N.
(At the computer)
Description
Clock
Data
Not connected
Ground
+5 VDC
Technical
CLK/CTS, Open-collector
RxD/TxD/RTS, Open-collector
Reset on some very old keyboards.
RI
Name
CLOCK
DATA
n/c
GND
VCC
ST
Pin
1
2
3
4
5
BU
DI
RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Keyboard (5 PC)
BETA RELEASE
204
TIO
N.
(At the computer)
RI
Description
Key Data
Not connected
Gnd
Power , +5 VDC
Clock
Not connected
ST
Name Dir
DATA
n/c
GND
VCC
CLK
n/c
-
DI
Pin
1
2
3
4
5
6
BU

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
Note: Direction is Computer relative Keyboard.
PR
EL
IM
IN
Keyboard (6 PC)
BETA RELEASE
205
Keyboard (XT) Connector
TIO
N.
(At the computer)
DescriptionTechnical
Clock
CLK/CTS, Open-collector
Data
RxD, Open-collector
Reset
Ground
+5 VDC
DI
RI
Name
CLK
DATA
/RESET
GND
VCC
ST
Pin
1
2
3
4
5
BU
RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Keyboard (XT)
BETA RELEASE
206
Keyboard (5 Amiga) Connector
TIO
N.
(At the computer)
RI
A2000/A3000
KCLK
KDAT
n/c
GND
+5 Volts
RE
Source: ?
ST
A1000
+5 Volts
CLOCK
DATA
GND
n/c
DI
Pin
1
2
3
4
5
BU
5 PIN DIN 180 (DIN41524) FEMALE (A1000/A2000/A3000) at the computer.
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Keyboard (5 Amiga)
BETA RELEASE
207
TIO
N.
(At the computer)
RI
Description
Data
Not connected
Ground
Clock
Not connected
ST
Name Dir
/DATA
n/c
GND
+5V
CLOCK
n/c
-
DI
Pin
1
2
3
4
5
6
BU
6 PIN MINI-DIN FEMALE (PS/2 STYLE) (A4000/CD32/CDTV) at the computer.

AR
YB
ET
A
.N
OT
FO
RE
Contributor: Joakim gren, Dirk Duesterberg <duesterb@unixserv.rz.fh-hannover.de>
PR
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IM
IN
Keyboard (6 Amiga)
BETA RELEASE
208
Keyboard (Amiga CD32)
BU
(At the computer)
ST
Description
Data
Transmit Data (0-5V and reversed)
Ground
Clock
Receive Data (0-5V and reversed)
DI
Name Dir
/DATA
/TxD
GND
+5V
CLOCK
/RxD
RE
Pin
1
2
3
4
5
6
RI
Contributor: Joakim gren, Dirk Duesterberg <duesterb@unixserv.rz.fh-hannover.de>
Source: CD32 keyboard port info <ftp://ftp.demon.co.uk/pub/amiga/docs/cd32-pinouts.txt>, usenet posting by

Klaus Hegemann <Klaus_Hegemann@punk.fido.de>.
AR
YB
ET
A
.N
OT
FO
PR
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IM
IN
The Amiga CD32 keyboard connector also includes a serialport.
TIO
N.
Keyboard (Amiga CD32) Connector
BETA RELEASE
209
Macintosh Keyboard Connector
TIO
N.
Macintosh Keyboard
RI
BU
(At the Computer)
ST
(At the Keyboard)
Name Dir
CGND
KBD1 ?
KBD2 ?
+5V
Description
Chassis ground
Keyboard clock
Keyboard data
+5 VDC
RE
Pin
1
2
3
4
DI
RJ11 FEMALE CONNECTOR at the Computer.

RJ11 MALE CONNECTOR at the Keyboard.
FO
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Available on Macintosh Mac Plus and earlier.
BETA RELEASE
210
AT&T 6300 Keyboard Connector
TIO
N.
(At the Computer)
ST
RI
Description
Data
Clock
Ground
Ground
+12 VDC
Not connected
Not connected
Not connected
Not connected
DI
Name
DATA
CLOCK
GND
GND
+12V
n/c
n/c
n/c
n/c
RE
Pin
1
2
3
4
5
6
7
8
9
BU
9 PIN D-SUB ??? at the Computer.

AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
AT&T 6300 Keyboard
BETA RELEASE
211
Internal Diskdrive Connector
TIO
N.
(At the computer & diskdrives)
RI
ST
DI
RE
Description
Density Select
Reserved
Reserved
Index
Motor Enable A
Drive Sel B
Drive Sel A
Motor Enable B
Direction
Step
Write Data
Floppy Write Enable
Track 0
Write Protect
Read Data
Head Select
Disk Change
Name
Dir
/REDWC
n/c
n/c
/INDEX
/MOTEA
/DRVSB
/DRVSA
/MOTEB
/DIR
/STEP
/WDATE
/WGATE
/TRK00
/WPT
/RDATA
/SIDE1
/DSKCHG
FO
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
BU
34 PIN IDC MALE at the computer & diskdrives.
OT
Note: Direction is Computer relative Diskdrive.

Note: All odd pins are GND, Ground.
.N
Note: Can be an Edge-connector on old PC's.

ET
A
Source: ?
AR
YB
PR
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IM
IN
Internal Diskdrive
BETA RELEASE
212
8" Floppy Diskdrive Connector
TIO
N.
(At the computer)
RE
DI
ST
Description
Reduced Write Current
Reserved
Reserved
Reserved
Disk is two sided
Disk has been changed/door open
Side select
Door lock
Head load
Index Pulse
Ready
Not connected
Select Drive 1
Select Drive 2
Select Drive 3
Select Drive 4
Direction
Step
Write data
Write gate
Track 00 (Zero)
Write protect
Read data
Not connected
Not connected
RI
Dir
OT
FO
.N
Name
/REDWC
n/c
n/c
n/c
/FD2S
/DCG
/SIDE
/DLOCK
/HLD
/INDEX
/READY
n/c
/SEL1
/SEL2
/SEL3
/SEL4
/DIR
/STEP
/WDAT
/WGAT
/TR00
/WPROT
/RDATA
n/c
n/c
ET
A
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
BU
50 PIN EDGE or IDC at the computer??.

YB
Contributor: Joakim gren, Dennis Painter <dwp@rocketmail.com>

Source: ?
AR
PR
EL
IM
IN
8" Floppy Diskdrive
BETA RELEASE
213
Amiga External Diskdrive Connector
TIO
N.
(At the Amiga)
Description
Disk Ready
Disk Read Data
Ground
Ground
Ground
Ground
Ground
Disk Motor Control
Select Drive 2
Disk Reset
Disk Removed From Drive-Latched Low
Select Disk Side (0=Upper, 1=Lower)
Disk is Write Protected
Drive Head position over Track 0
Disk Write Enable
Disk Write Data
Step the Head-Pulse, First low, then high
Select Head Direction (0=Inner, 1=Outer)
Select Drive 3
Select Drive 1
Disk Index Pulse
+12 Volts DC (160 mA max, 540 mA surge
OC
OC
OC
OC
OC
OC
OC
RE
FO
OC
OC
OC
DI
ST
RI
Dir
OT
Name
/RDY
/DKRD
GND
GND
GND
GND
GND
/MTRXD
/SEL2
/DRES
/CHNG
+5V
/SIDE
/WPRO
/TKO
/DKWE
/DKWD
/STEP
DIR
/SEL3
/SEL1
/INDEX
+12V
.N
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
BU
23 PIN D-SUB FEMALE at the Amiga.
ET
A

AR
YB
PR
EL
IM
IN
Amiga External Diskdrive
BETA RELEASE
214
MSX External Diskdrive Connector
TIO
N.
(At the Computer)
OT
FO
RE
DI
ST
RI
Description
+12 VDC
+5 VDC
+5 VDC
Sector hole passed sensor.
Drive Select 1
Direction (0=In, 1=Dir)
Moves head 1 step in DIR direction.
Write Data
Write Gate
Head is over Track 00 (outermost track)
Write protected disk (0=Write protected)
Data read from diskette.
Side Select (0=Side 1, 1=Side 0)
+12 VDC
+12 VDC
+5 VDC
Select Drive 0
Motor On
Ready
Ground
Ground
Ground
Ground
Ground
Ground
.N
Name
Dir
+12V
+5V
+5V
/INDEX
/DSEL1
DIR
/STEP
WRITEDATA
/WRITEGATE
/TRACK00
/WRITEPROTECT
READDATA
/SIDESELECT
+12V
+12V
+5V
/DSEL1
/MOTOR
READY
GND
GND
GND
GND
GND
GND
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
BU
YB
AR
PR
EL
IM
IN
MSX External Diskdrive
BETA RELEASE
215
Amstrad CPC6128 Diskdrive 2 Connector
TIO
N.
(At the computer)
RI
ST
DI
RE
R
FO
OT
.N
YB
ET
A
Name
READY
GND
SIDE 1 SELECT
GND
READ DATA
GND
WRITE PROTECT
GND
TRACK 0
GND
WRITE GATE
GND
WRITE DATA
GND
STEP
GND
DIRECTION SELECT
GND
MOTOR ON
GND
n/c
GND
DRIVE SELECT 1
GND
n/c
GND
INDEX
GND
n/c
GND
n/c
GND
n/c
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
BU
34 PIN MALE EDGE at the computer.

PR
EL
IM
IN
Amstrad CPC6128 Diskdrive 2
BETA RELEASE
216
Amstrad CPC6128 Plus External Diskdrive C
TIO
N.
(At the Computer)
ST
RI
Description
Not connected
Not connected
Not connected
DI
Not connected
Step head
Write Data
Write Gate
Track 00
Write Protect
Read Data
?
?
RE
Not connected
Dir
?
?
?
?
FO
Name
n/c
n/c
n/c
NINDEX
n/c
NDSEL1
n/c
NMOTOR
NDSEL
NSTEP
NWDATA
NWGATE
NTK00
NWRPT
NRDDTA
NSIDE1
NREADY
n/c
Not connected
OT
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
BU
.N

Note: All even pins are GND, Ground.
Contributor: Joakim gren, Colin Gaunt <c.gaunt@c-gaunt.prestel.co.uk>
ET
A
AR
YB
PR
EL
IM
IN
Amstrad CPC6128 Plus External Diskdrive
BETA RELEASE
217
Macintosh External Drive Connector
TIO
N.
BU
(At the Computer)
RI
(At the Diskdrive)
Description
Chassis ground
Chassis ground
Chassis ground
Chassis ground
-12 VDC
+5 VDC
+12 VDC
+12 VDC
Not connected
Regulates speed of the drive
Control line to send commands to the drive
Turns on the ability to write data to the drive
Enables the Rd line (else Rd is tristated)
Data actually read from the drive
Data actually written to the drive
FO
OT
?
?
?
?
?
?
?
?
RE
DI
Dir
.N
Name
CGND
CGND
CGND
CGND
-12V
+5V
+12V
+12V
n/c
PWM
CA0
CA1
CA2
LSTRB
WrReqHdSel
Enbl2Rd
Wr
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ST

19 PIN D-SUB MALE at the Diskdrive.

YB
AR
PR
EL
IM
IN
Macintosh External Drive
BETA RELEASE
218
Atari Floppy Port Connector
TIO
N.
BU
(At the Computer)
RI
(At the Diskdrive)
RE
DI
Description
Read Data
Side 0 Select
Ground
Index
Drive 0 Select
Drive 1 Select
Ground
Motor On
Direction In
Step
Write Data
Write Gate
Track 00
Write Protect
FO
Name
RD
SIDE0
GND
INDEX
SEL0
SEL1
GND
MOTOR
DIR
STEP
WD
WG
TRK00
WP
OT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ST
14 PIN DIN FEMALE at the Computer.

14 PIN DIN MALE at the Diskdrive.
.N
ET
A
Source: ?
AR
YB
PR
EL
IM
IN
Atari Floppy Port
BETA RELEASE
219
SCSI Internal (Single-ended) Connector
TIO
N.
SCSI Internal (Single-ended)
BU
RI
(At the controller & harddisk)
ST
(At the cable.)
RE
R
ET
A
.N
OT
FO
Description
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Data Parity (odd Parity)
Ground
Ground
Ground
Termination Power
Ground
Ground
Attention
Ground
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
YB
Name Dir
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
PARITY
GND
GND
GND
TMPWR
GND
GND
/ATN
GND
/BSY
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
AR
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
DI
50 PIN IDC MALE at the controller & harddisk.

50 PIN IDC FEMALE at the cable.
Note: Direction is Device relative Bus (other Devices).

All odd-numbered pins, except pin 25, are connected to ground. Pin 25 is left open.
PR
EL
IM
IN
SCSI=Small Computer System Interface.

Based on an original design by Shugart Associates. SCSI was ratified in 1986.

Source: ?
BETA RELEASE
220
SCSI Internal (Differential) Connector
TIO
N.
BU
(at the controller & harddisk.)
RI
(At the cable.)
Description
Ground
Ground
+Data Bus 0
-Data Bus 0
+Data Bus 1
-Data Bus 1
+Data Bus 2
-Data Bus 2
+Data Bus 3
-Data Bus 3
+Data Bus 4
-Data Bus 4
+Data Bus 5
-Data Bus 5
+Data Bus 6
-Data Bus 6
+Data Bus 7
-Data Bus Parity7
+Data Bus Parity (odd Parity)
-Data Bus Parity (odd Parity)
???
Ground
Reserved
Reserved
Termination Power
Termination Power
Reserved
Reserved
+Attention
-Attention
Ground
Ground
+Bus is busy
-Bus is busy
+Acknowledge
-Acknowledge
+Reset
-Reset
+Message
-Message
+Select
-Select
+Control or Data
-Control or Data
ET
A
.N
OT
FO
RE
DI
Dir
YB
Name
GND
GND
+DB0
-DB0
+DB1
-DB1
+DB2
-DB2
+DB3
-DB3
+DB4
-DB4
+DB5
-DB5
+DB6
-DB6
+DB7
-DB7
+DBP
-DBP
DIFFSENS
GND
res
res
TERMPWR
TERMPWR
res
res
+ATN
-ATN
GND
GND
+BSY
-BSY
+ACK
-ACK
+RST
-RST
+MSG
-MSG
+SEL
-SEL
+C/D
-C/D
AR
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ST
50 PIN IDC MALE at the controller & harddisk.

PR
EL
IM
IN
SCSI Internal (Differential)
BETA RELEASE
221
+Request
-Request
+In/Out
-In/Out
Ground
Ground
+REQ
-REQ
+I/O
-I/O
GND
GND
TIO
N.
45
46
47
48
49
50
BU

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
PR
EL
IM
IN
BETA RELEASE
222
SCSI External Centronics 50 (Single-ended) C
TIO
N.
RI
BU
(At the controller & devices)
(At the cable)
DI
RE
ET
A
.N
OT
FO
Description
Ground
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Ground
Ground
Ground
Termination Power
Ground
Ground
Attention
Not connected
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
YB
Name Dir
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
PARITY
GND
GND
GND
TMPWR
GND
GND
/ATN
n/c
/BSY
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
AR
Pin
1-25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ST
50 PIN CENTRONICS FEMALE at the controller & devices.

50 PIN CENTRONICS MALE at the cable.

PR
EL
IM
IN
SCSI External Centronics 50 (Single-ended)
Source: ?
BETA RELEASE
223
SCSI External Centronics 50 (Differential) Co
TIO
N.
RI
BU
(At the controller & devices)
(At the cable)
DI
Description
Ground
+Data Bus 0
+Data Bus 1
+Data Bus 2
+Data Bus 3
+Data Bus 4
+Data Bus 5
+Data Bus 6
+Data Bus 7
???
Reserved
Termination Power
Reserved
+Attention
Ground
+Bus is busy
+Acknowledge
+Reset
+Message
+Select
+Control or Data
+Request
+In/Out
Ground
Ground
-Data Bus 0
-Data Bus 1
-Data Bus 2
-Data Bus 3
-Data Bus 4
-Data Bus 5
-Data Bus 6
-Data Bus Parity7
Ground
Reserved
Termination Power
Reserved
-Attention
Ground
-Bus is busy
ET
A
.N
OT
?
-
FO
RE
Dir
YB
Name
GND
+DB0
+DB1
+DB2
+DB3
+DB4
+DB5
+DB6
+DB7
+DBP
DIFFSENS
res
TERMPWR
res
+ATN
GND
+BSY
+ACK
+RST
+MSG
+SEL
+C/D
+REQ
+I/O
GND
GND
-DB0
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-DBP
GND
res
TERMPWR
res
-ATN
GND
-BSY
AR
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
ST
50 PIN CENTRONICS FEMALE at the controller & devices.

50 PIN CENTRONICS MALE at the cable.
PR
EL
IM
IN
SCSI External Centronics 50 (Differential)
BETA RELEASE
224
TIO
N.
-Acknowledge
-Reset
-Message
-Select
-Control or Data
-Request
-In/Out
Ground
-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
GND
BU
43
44
45
46
47
48
49
50
SCSI External Centronics 50 (Differential) Co
RI

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
PR
EL
IM
IN
BETA RELEASE
225
SCSI-II External Hi D-Sub (Single-ended) Co
TIO
N.
BU
(At the controller & devices).
RI
(To the cable).
DI
RE
.N
OT
FO
Description
Ground
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Ground
Ground
Ground
Termination Power
Ground
Ground
Attention
Not connected
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
ET
A
Name Dir
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
PARITY
GND
GND
GND
TMPWR
GND
GND
/ATN
n/c
/BSY
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
YB
Pin
1-25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ST
50 PIN HI-DENSITY D-SUB FEMALE at the controller & devices.

50 PIN HI-DENSITY D-SUB MALE at the cable.
AR

Source: ?
PR
EL
IM
IN
SCSI-II External Hi D-Sub (Single-ended)
BETA RELEASE
226
SCSI-II External Hi D-Sub (Differential) Con
TIO
N.
BU
(At the controller & devices).
RI
(To the cable).
Description
Ground
+Data Bus 0
+Data Bus 1
+Data Bus 2
+Data Bus 3
+Data Bus 4
+Data Bus 5
+Data Bus 6
+Data Bus 7
???
Reserved
Termination Power
Reserved
+Attention
Ground
+Bus is busy
+Acknowledge
+Reset
+Message
+Select
+Control or Data
+Request
+In/Out
Ground
Ground
-Data Bus 0
-Data Bus 1
-Data Bus 2
-Data Bus 3
-Data Bus 4
-Data Bus 5
-Data Bus 6
-Data Bus Parity7
Ground
Reserved
Termination Power
Reserved
-Attention
Ground
-Bus is busy
-Acknowledge
ET
A
.N
OT
?
-
FO
RE
DI
Dir
YB
Name
GND
+DB0
+DB1
+DB2
+DB3
+DB4
+DB5
+DB6
+DB7
+DBP
DIFFSENS
res
TERMPWR
res
+ATN
GND
+BSY
+ACK
+RST
+MSG
+SEL
+C/D
+REQ
+I/O
GND
GND
-DB0
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-DBP
GND
res
TERMPWR
res
-ATN
GND
-BSY
-ACK
AR
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
ST
50 PIN HI-DENSITY D-SUB FEMALE at the controller & devices.

50 PIN HI-DENSITY D-SUB MALE at the cable.
PR
EL
IM
IN
SCSI-II External Hi D-Sub (Differential)
BETA RELEASE
227
-Reset
-Message
-Select
-Control or Data
-Request
-In/Out
Ground
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
GND
TIO
N.
44
45
46
47
48
49
50
SCSI-II External Hi D-Sub (Differential) Con
BU
RI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
PR
EL
IM
IN
BETA RELEASE
228
SCSI External D-Sub (Future Domain)
TIO
N.
SCSI External D-Sub (Future Domain) Conne
RI
BU
(At the controller)
ST
(At the cable)
RE
R
FO
ET
A
.N
OT
Description
Ground
Data Bus 1
Data Bus 3
Data Bus 5
Data Bus 7
Ground
Select
Ground
Termination Power
Reset
Control/Data
Input/Output
Ground
Data Bus 0
Data Bus 2
Data Bus 4
Data Bus 6
Data Parity
Ground
Attention
Message
Acknowledge
Busy
Request
Ground
YB
Name Dir
GND
DB1
DB3
DB5
DB7
GND
/SEL
GND
TMPWR
/RST
C/D
I/O
GND
DB0
DB2
DB4
DB6
PARITY
GND
/ATN
/MSG
/ACK
BSY
/REQ
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DI
25 PIN D-SUB FEMALE at the controller.

25 PIN D-SUB MALE at the cable.

PR
EL
IM
IN
Seems to be available on some Future Domain SCSI-controllers only.
Source: TheRef
TechTalk <http://theref.c3d.rl.af.mil>
BETA RELEASE
229
BU
(At the controller)
RI
(At the cable)
DI
RE
R
FO
.N
OT
Description
Request
Message
Input/Output
Reset
Acknowledge
Busy
Ground
Data Bus 0
Ground
Data Bus 3
Data Bus 5
Data Bus 6
Data Bus 7
Ground
Control/Data
Ground
Attention
Ground
Select
Data Parity
Data Bus 1
Data Bus 2
Data Bus 4
Ground
Termination Power
ET
A
Name Dir
/REQ
/MSG
I/O
/RST
/ACK
BSY
GND
DB0
GND
DB3
DB5
DB6
DB7
GND
C/D
GND
/ATN
GND
/SEL
PARITY
DB1
DB2
DB4
GND
TMPWR
YB
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ST

25 PIN D-SUB MALE at the cable.
AR

Source: ?
PR
EL
IM
IN
SCSI External D-Sub (PC/Amiga/Mac)
TIO
N.
SCSI External D-Sub (PC/Amiga/Mac) Conne
BETA RELEASE
230
Novell and Procomp External SCSI Connecto
TIO
N.
Novell and Procomp External SCSI
BU
(At the controller)
ST
DI
RE
R
ET
A
.N
OT
FO
Description
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Termination Power
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Data Bus Parity
Attention
Busy
Acknowledge
Reset
Message
Select
Control/Data
Request
Input/Output
YB
Name
Dir
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TERMPWR
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
/DBP
/ATN
/BSY
/ACK
/RST
/MSG
/SEL
/C/D
/REQ
/I/O
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
RI
PR
EL
IM
IN
This interface is nowadays considered obsolete.

Contributor: Joakim gren, Randy Hoffman <runtime@borg.pulsenet.com>
Source: Black Box Corporation, FaxBack document for SCSI
BETA RELEASE
231
IDE Internal Connector
TIO
N.
IDE Internal
BU
ST
RI
(At the controller & peripherals)
R
FO
Description
Reset
Ground
Data 7
Data 8
Data 6
Data 9
Data 5
Data 10
Data 4
Data 11
Data 3
Data 12
Data 2
Data 13
Data 1
Data 14
Data 0
Data 15
Ground
Key
Not connected
Ground
Write Strobe
Ground
Read Strobe
Ground
ET
A
.N
OT
Dir
YB
Name
/RESET
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
KEY
n/c
GND
/IOW
GND
/IOR
GND
IO_CH_RDY
ALE
n/c
GND
IRQR
/IOCS16
DA1
n/c
DA0
DA2
/IDE_CS0
/IDE_CS1
/ACTIVE
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RE
40 PIN IDC MALE at the controller & peripherals.

DI
(At the cable)
PR
EL
IM
IN
IDE=Integrated Drive Electronics.

Developed by Compaq and Western Digital.
Newer version of IDE goes under the name ATA=AT bus Attachment.
Address Latch Enable

Not connected
Ground
Interrupt Request
IO ChipSelect 16
Address 1
Not connected
Address 0
Address 2
(1F0-1F7)
(3F6-3F7)
Led driver
Ground
BETA RELEASE
232
TIO
N.
Note: Direction is Controller relative Devices (Harddisks).

Contributors: Joakim gren, Dan Williams <dan_williams@sunshine.net>
Source: ?
BU
RI
ST
DI
RE
R
FO
OT
.N
ET
A
YB
AR
PR
EL
IM
IN
BETA RELEASE
233
ATA Internal Connector
TIO
N.
ATA Internal
BU
Description
Reset
Ground
Data 7
Data 8
Data 6
Data 9
Data 5
Data 10
Data 4
Data 11
Data 3
Data 12
Data 2
Data 13
Data 1
Data 14
Data 0
Data 15
Ground
Key (Pin missing)
DMA Request
Ground
Write Strobe
Ground
Read Strobe
Ground
I/O Ready
Spindle Sync or Cable Select
DMA Acknowledge
Ground
Interrupt Request
IO ChipSelect 16
Address 1
Passed Diagnostics
Address 0
Address 2
(1F0-1F7)
(3F6-3F7)
Led driver
Ground
ET
A
.N
OT
FO
RE
Dir
YB
Name
/RESET
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
KEY
DMARQ
GND
/DIOW
GND
/DIOR
GND
IORDY
SPSYNC:CSEL
/DMACK
GND
INTRQ
/IOCS16
DA1
PDIAG
DA0
DA2
/IDE_CS0
/IDE_CS1
/ACTIVE
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DI
40 PIN IDC MALE at the controller & peripherals.

ST
(At the cable)
RI
PR
EL
IM
IN
ATA=AT bus Attachment..

Developed by Western Digital, Conner & Seagate ?.
?
?
Note: Direction is Controller relative Devices (Harddisks).
BETA RELEASE
234
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
Source: ?
TIO
N.
BU
RI

BETA RELEASE
235
ATA (44) Internal Connector
TIO
N.
ATA (44) Internal
BU
This connector is mostly used for 2.5" internal harddisks.

See ATA for pin 1-40.
(At the cable)
ST
RI
Description
+5 VDC (Logic)
+5 VDC (Motor)
Ground
Type (0=ATA)
RE
Name Dir
+5VL
+5VM
GND
/TYPE
Pin
41
42
43
44
DI
44 PIN IDC (0.75") MALE at the controller & peripherals.

44 PIN IDC (0.75") FEMALE at the cable.
FO
Note: Direction is Controller relative Devices (harddisks).

Contributor: Joakim gren, Nick Schirmer <nes@oz.net>
OT
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
ATA=AT bus Attachment.
BETA RELEASE
236
ESDI Connector
TIO
N.
ESDI
BU
ST
RI
(At the controller)
DI
(At the controller)
34 PIN IDC MALE at the Controller.

OT
34 PIN IDC FEMALE at the Harddisk.

FO
(At the harddisk)
RE
(At the harddisk)
.N
Control connector
AR
YB
ET
A

2
Head Sel 3
4
Head Sel 2
6
Write Gate
8
Config/Stat Data
10
Transfer Acknowledge
12
Attention
14
Head Sel 0
16
Sect/Add MK Found
18
Head Sel 1
20
Index
22
Ready
24
Transfer Request
26
Drive Sel 1
28
Drive Sel 2
30
Drive Sel 3
32
Read Gate
34
Command Data
PR
EL
IM
IN
ESDI=Enhanced Small Device Interface.

Developed by Maxtor in the early 1980's as an upgrade and improvement to the ST506
design.
Note: All odd are GND, Ground.
Data connector
1
Drive Selected
2
Sect/Add MK Found
3
Seek Complete
4
Address Mark Enable
BETA RELEASE
237
RI
BU
TIO
N.
(reserved, for step mode)

GND Ground
Write Clock+
Write ClockCartridge Changed
Read Ref Clock+
Read Ref ClockGND Ground
NRZ Write Data+
NRZ Write DataGND Ground
GND Ground
NRZ Read Data+
NRZ Read DataGND Ground
GND Ground
ST
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ESDI Connector
DI
RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
238
ST506/412 Connector
TIO
N.
RE
R
(At the controller)
DI
(At the controller)
ST
RI
BU
Developed by Seagate.
Also known as MFM or RLL since these are the encoding methods used to store data.
Seagate originally developed it to support their ST506 (5 MB) and ST412 (10 MB) drives.
The first drives used an encoding method called MFM (Modified Frequency Modulation).
Later a new encoding method was developed, RLL (Run Length Limited). RLL had the
advantage that it was possible to store 50% more with it. But it required better drives. This is
almost never an problem. Often called 2,7 RLL because the recording scheme involves
patterns with no more than 7 successive zeros and no less than two.
FO
(At the harddisk)
OT
(At the harddisk)
.N

Control connector
ET
A

AR
YB

2
Head Sel 8
4
Head Sel 4
6
Write Gate
8
Seek Complete
10
Track 0
12
Write Fault
14
Head Sel 1
16 RES (reserved)
18
Head Sel 2
20
Index
22
Ready
24
Step
26
Drive Sel 1
28
Drive Sel 2
30
Drive Sel 3
32
Drive Sel 4
34
Direction In
PR
EL
IM
IN
ST506/412
Data connector
BETA RELEASE
239
DI
ST
RI
BU
TIO
N.
Name Description
Drive Selected
GND Ground
RES (reserved)
GND Ground
RES (reserved)
GND Ground
RES (reserved)
GND Ground
RES (reserved)
RES (reserved)
GND Ground
GND Ground
Write Data+
Write DataGND Ground
GND Ground
Read Data+
Read DataGND Ground
GND Ground
RE
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ST506/412 Connector

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
240
Paravision SX-1 External IDE Connector
TIO
N.
Paravision SX-1 External IDE
BU
(At the controller)
ST
DI
RE
R
FO
ET
A
.N
OT
Description
Drive Reset
Data bit 0
Data bit 2
Data bit 4
Data bit 6
Ground
Data bit 8
Data bit 10
Data bit 12
Data bit 14
Ground
Ground
Ground
Ground
Ground
Ground
Ground
5V Power
5V Power
Ground
Data bit 1
Data bit 3
Data bit 5
Data bit 7
Ground
Data bit 9
Data bit 11
Data bit 13
Data bit 15
I/O Write
I/O Read
Interrupt Request
Address bit 2
Address bit 1
Address bit 0
Chip Select 1
Chip Select 0
YB
Name
/IDE-RESET
D0
D2
D4
D6
GND
D8
D10
D12
D14
GND
GND
GND
GND
GND
GND
GND
+5V
+5V
GND
D1
D3
D5
D7
GND
D9
D11
D13
D15
/IOW
/IOR
IDE-IRQ
IDE-A2
IDE-A1
IDE-A0
/BICS1
/BICS0
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
RI
PR
EL
IM
IN
Paravision was formerly Microbotics.

Source: SX-1 External IDE connector <ftp://ftp.demon.co.uk/pub/amiga/docs/cd32-pinouts.txt>, usenet posting
by Mike Pinso <microbotics1@bix.com> at Paravision.
BETA RELEASE
241
Mitsumi CD-ROM Connector
TIO
N.
BU
(at the controller & CD-ROM)
RI
(at the cable.)
DI
RE
R
FO
ET
A
.N
OT
Description
Address Bit 0
Ground
Address Bit 1
Ground
Not connected
Ground
Not connected
Ground
Not connected
Ground
Not connected
Ground
Interrupt
Ground
Data request For DMA
Ground
Data Acknowledge For DMA
Ground
Read Enable
Ground
Write Enable
Ground
Bus Enable
Ground
Data Bit 0
Ground
Data Bit 1
Ground
Data Bit 2
Ground
Data Bit 3
Ground
Data Bit 4
Ground
Data Bit 5
Ground
Data Bit 6
Ground
Data Bit 7
Ground
YB
Name
A0
GND
A1
GND
n/c
GND
n/c
GND
n/c
GND
n/c
GND
INT
GND
REQ
GND
ACK
GND
RE
GND
WE
GND
EN
GND
DB0
GND
DB1
GND
DB2
GND
DB3
GND
DB4
GND
DB5
GND
DB6
GND
DB7
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ST
40 PIN IDC MALE at the controller & CD-ROM.

PR
EL
IM
IN
Mitsumi CD-ROM
Contributor: Keith Solomon <zarathos@thorn.bluedream.com>

Source: SoundFX 16-bit Multimedia Kit Hardware Manual from Reveal
BETA RELEASE
242
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

BETA RELEASE
243
Panasonic CD-ROM Connector
TIO
N.
BU
RI
(at the cable.)
DI
RE
R
FO
ET
A
.N
OT
Description
Ground
CD-Reset
Ground
Ground
Ground
Operation Mode Bit 0
Ground
Operation Mode Bit 1
Ground
CD-Write
Ground
CD-Read
Ground
CD-Status Bit 0
Ground
No Connection
Ground
No Connection
Ground
CD-Status Bit 1
Ground
CD-Data Enable
Ground
CD-Status Bit 2
Ground
CD-Status/Data Enable
Ground
CD-Status Bit 3
ground
ground
CD-Data 7
CD-Data 6
ground
CD-Data 5
CD-Data 4
CD-Data 3
ground
CD-Data 2
CD-Data 1
CD-Data 0
YB
Name
GND
RESET
GND
GND
GND
MODE0
GND
MODE1
GND
WRITE
GND
READ
GND
ST0
GND
n/c
GND
n/c
GND
ST1
GND
EN
GND
ST2
GND
S/DE
GND
ST3
GND
GND
D7
D6
GND
D5
D4
D3
GND
D2
D1
D0
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ST

PR
EL
IM
IN
Panasonic CD-ROM

BETA RELEASE
244
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

BETA RELEASE
245
BU
RI
(at the cable.)
DI
RE
R
ET
A
.N
OT
FO
Description
Reset
Ground
Data Bit 7
Ground
Data Bit 6
Ground
Data Bit 5
Ground
Data Bit 4
Ground
Data Bit 3
Ground
Data Bit 2
Ground
Data Bit 1
Ground
Data Bit 0
Ground
Write Enable
Ground
Read Enable
Ground
Data Acknowledge For DMA
Ground
Data Request For DMA
Ground
Interrupt
Ground
Address Bit 1
Ground
Address Bit 0
Ground
Bus Enable
Ground
YB
Name
RESET
GND
DB7
GND
DB6
GND
DB5
GND
DB4
GND
DB3
GND
DB2
GND
DB1
GND
DB0
GND
WE
GND
RE
GND
ACK
GND
REQ
GND
INT
GND
A1
GND
A0
GND
EN
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
ST

PR
EL
IM
IN
Sony CD-ROM
TIO
N.
Sony CD-ROM Connector

BETA RELEASE
246
C64 Cassette Connector
TIO
N.
(At the computer)
RI
Description
Ground
+5 Volts DC
Cassette Motor
Cassette Read
Cassette Write
Cassette Sense
ST
Name Dir
GND
+5V
MOTOR
READ
WRITE
SENSE
DI
Pin
A-1
B-2
C-3
D-4
E-5
F-6
BU
6 PIN MALE EDGE at the computer.
Note: Direction is Computer relative Cassette.

Source: Commodore 64 Programmer's Reference Guide
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
C64 Cassette
BETA RELEASE
247
C16/C116/+4 Cassette Connector
TIO
N.
C16/C116/+4 Cassette
BU
(At the computer)

ST
RI
Description
Ground
+5 Volts DC
Cassette Motor
Cassette Read
Cassette Write
Cassette Sense
Ground
DI
Name Dir
GND
+5V
MOTOR
READ
WRITE
SENSE
GND
RE
Pin
1
2
3
4
5
6
7
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Available on the Commodore C16, C116 and +4 computers.
BETA RELEASE
248
CoCo Cassette
BU
(At the CoCo)
ST
Description
Motor Relay
Ground
Motor Relay
Signal Input
Signal Output
DI
Pin
1
2
3
4
5
RI
UNKNOWN CONNECTOR at the CoCo.
RE
Source: Tandy Color Computer FAQ <http://www.io.com/~vga2000/faqs/coco.faq> at Video Game Advantage's

homepage <http://www.io.com/~vga2000/>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Available on the Tandy/Radio Shack Color Computer (CoCo).
TIO
N.
CoCo Cassette Connector
BETA RELEASE
249
MSX Cassette Connector
TIO
N.
BU
(At the computer)
RI
(At the cassette cable)
DI
Description
Ground
Ground
Ground
Sound Output
Sound Input
Remote control (from relay)
Remote control (from relay)
Ground
RE
Name
Dir
GND
GND
GND
CMTOUT
CMTIN
REM+
REMGND
Pin
1
2
3
4
5
6
7
8
ST

8 PIN DIN (DIN45326) MALE at the cassette cable.
FO

OT
AR
YB
ET
A
.N
PR
EL
IM
IN
MSX Cassette
BETA RELEASE
250
Spectravideo SVI318/328 Cassette Connector
TIO
N.
Spectravideo SVI318/328 Cassette
BU
7 PIN FEMALE EDGE CONNECTOR at the computer.
ST
Description
Power 100mA
Cassette data read
Cassette data write
Cassette audio
System ground
DI
Name
12v
CASR
CASW
AUDIO
GND
ME
READY
RE
Pin
1
2
3
4
5
6
7
RI
(At the computer)
System Ready
Source: SVI mk II user manual
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
+-------------+
|1 2 3 4 5 6 7|
+-------------+
BETA RELEASE
251
Amstrad CPC6128 Tape Connector
TIO
N.
(At the computer)
RI
Name
REMOTE SWITCH
GND
REMOTE SWITCH
DATA IN
DATA OUT
ST
Pin
1
2
3
4
5
BU
DI
RE
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Amstrad CPC6128 Tape
BETA RELEASE
252
30 pin SIMM Connector
TIO
N.
30 pin SIMM
BU
RI
(At the computer)
DI
RE
R
FO
ET
A
.N
OT
Description
+5 VDC
Column Address Strobe
Data 0
Address 0
Address 1
Data 1
Address 2
Address 3
Ground
Data 2
Address 4
Address 5
Data 3
Address 6
Address 7
Data 4
Address 8
Address 9
Address 10
Data 5
Write Enable
Ground
Data 6
Address 11
Data 7
Data Parity Out
Row Address Strobe
Something Parity ????
Data Parity In
+5 VDC
YB
Name
VCC
/CAS
DQ0
A0
A1
DQ1
A2
A3
GND
DQ2
A4
A5
DQ3
A6
A7
DQ4
A8
A9
A10
DQ5
/WE
GND
DQ6
A11
DQ7
QP
/RAS
/CASP
DP
VCC
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ST
30 PIN SIMM at the computer.
Note: SIMM above is a 4MBx9.

QP & DP is N/C on SIMMs without parity.
A9 is N/C on 256kB.
A10 is N/C on 256kB & 1MB. A11 is N/C on 256kB, 1MB & 4MB.
PR
EL
IM
IN
SIMM=Single Inline Memory Module.
Contributor: Joakim gren, Helfried Behrendt <helfried.behrendt@ffm-r1.ffm1.siemens.net>

Source: comp.sys.ibm.pc.hardware.* FAQ Part 4
<ralf@alum.wpi.edu>
BETA RELEASE
253
TIO
N.
72 pin SIMM
BU
RI
(At the computer)
ET
A
.N
OT
FO
RE
DI
Description
Ground
Data 0
Data 16
Data 1
Data 17
Data 2
Data 18
Data 3
Data 19
+5 VDC
Not connected
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 10
Data 4
Data 20
Data 5
Data 21
Data 6
Data 22
Data 7
Data 23
Address 7
Address 11
+5 VDC
Address 8
Address 9
Row Address Strobe 3
Parity bit 3 (for the 3rd byte, bits 16-23)
Parity bit 1 (for the 1st byte, bits 0-7)
Parity bit 2 (for the 2nd byte, bits 8-15)
Parity bit 4 (for the 4th byte, bits 24-31)
Ground
Column Address Strobe 0
YB
Non-ParityParity
VSS
VSS
DQ0
DQ0
DQ16
DQ16
DQ1
DQ1
DQ17
DQ17
DQ2
DQ2
DQ18
DQ18
DQ3
DQ3
DQ19
DQ19
VCC
VCC
n/c
n/c
A0
A0
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A10
A10
DQ4
DQ4
DQ20
DQ20
DQ5
DQ5
DQ21
DQ21
DQ6
DQ6
DQ22
DQ22
DQ7
DQ7
DQ23
DQ23
A7
A7
A11
A11
VCC
VCC
A8
A8
A9
A9
/RAS3
/RAS3
/RAS2
/RAS2
n/c
PQ3
n/c
PQ1
n/c
PQ2
n/c
PQ4
VSS
VSS
/CAS0
/CAS0
/CAS2
/CAS2
/CAS3
/CAS3
/CAS1
/CAS1
/RAS0
/RAS0
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ST
PR
EL
IM
IN
SIMM=Single Inline Memory Module
BETA RELEASE
254
Size
4 or 64 MB
2 or 32 MB
1 or 16 MB
8 MB
PD3
GND
NC
GND
NC
TIO
N.
BU
RI
ST
DI
Accesstime
50, 100 ns
80 ns
70 ns
60 ns
AR
PD4
GND
GND
NC
NC
YB
Accesstime:
ET
A
PD1
GND
NC
GND
NC
.N
Size:
PD2
GND
GND
NC
NC
RE

Not connected
Read/Write
Not connected
Data 8
Data 24
Data 9
Data 25
Data 10
Data 26
Data 11
Data 27
Data 12
Data 28
+5 VDC
Data 29
Data 13
Data 30
Data 14
Data 31
Data 16
Not connected
Presence Detect 1
Presence Detect 2
Presence Detect 3
Presence Detect 4
Not connected
Ground
/RAS1
n/c
/WE
n/c
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
VCC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ16
n/c
PD1
PD2
PD3
PD4
n/c
VSS
FO
/RAS1
n/c
/WE
n/c
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
VCC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ16
n/c
PD1
PD2
PD3
PD4
n/c
VSS
OT
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Notes: A9 is a N/C on 256k and 512k modules.

A10 is a N/C on 256k, 512k, 1M and 4M modules.
RAS1/RAS3 are N/C on 256k, 1M and 4M modules.
PR
EL
IM
IN
Contributors: Joakim gren, Mark Brown <bugman@total.net>, Karsten Wenke <Karsten.Wenke@t-online.de>,

SOYO Computer Inc <http://www.soyo.com.tw>
Source: Various productsheets at IBM Memory Products <http://www.chips.ibm.com/products/memory/>
BETA RELEASE
255
72 pin ECC SIMM Connector
TIO
N.
72 pin ECC SIMM
BU
RI
ET
A
.N
OT
FO
RE
OptimizedDescription
VSS
Ground
DQ0
Data 0
DQ1
Data 1
DQ2
Data 2
DQ3
Data 3
DQ4
Data 4
DQ5
Data 5
DQ6
Data 6
DQ7
Data 7
VCC
+5 VDC
PD5
Presence Detect 5
A0
Address 0
A1
Address 1
A2
Address 2
A3
Address 3
A4
Address 4
A5
Address 5
A6
Address 6
n/c
Not connected
DQ8
Data 8
DQ9
Data 9
DQ10
Data 10
DQ11
Data 11
DQ12
Data 12
DQ13
Data 13
DQ14
Data 14
DQ15
Data 15
A7
Address 7
DQ16
Data 16
VCC
+5 VDC
A8
Address 8
A9
Address 9
n/c
Not connected
/RAS1
DQ17
Data 17
DQ18
Data 18
DQ19
Data 19
DQ20
Data 20
VSS
Ground
/CAS0
A10
Address 10
A11
Address 11
/CAS1
YB
ECC
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
PD5
A0
A1
A2
A3
A4
A5
A6
n/c
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A7
DQ16
VCC
A8
A9
n/c
/RAS1
DQ17
DQ18
DQ19
DQ20
VSS
/CAS0
A10
A11
/CAS1
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DI
ST
(At the computer)
PR
EL
IM
IN
SIMM=Single Inline Memory Module

ECC=Error Correcting Code.
BETA RELEASE
256
BU
RI
ST
DI
RE
Data 22
Data 23
Data 24
Data 25
Data 26
Data 27
Data 28
Data 29
Data 30
Data 31
+5 VDC
Data 32
Data 33
Data 34
Data 35
Data 36
Data 37
Data 38
Presence Detect 1
Presence Detect 2
Presence Detect 3
Presence Detect 4
Data 39
Ground
TIO
N.

Data 21
Read/Write
/RAS0
/RAS1
DQ21
/WE
/ECC
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
PD1
PD2
PD3
PD4
DQ39
VSS
FO
/RAS0
/RAS1
DQ21
/WE
/ECC
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VCC
DQ32
DQ33
DQ34
DQ35
n/c
n/c
n/c
PD1
PD2
PD3
PD4
n/c
VSS
OT
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
257
72 pin SO DIMM Connector
TIO
N.
72 pin SO DIMM
BU
(At the computer)
ST
DI
YB
ET
A
.N
OT
FO
RE
Non-ParityParity Description
VSS
VSS Ground
DQ0
DQ0 Data 0
DQ1
DQ1 Data 1
DQ2
DQ2 Data 2
DQ3
DQ3 Data 3
DQ4
DQ4 Data 4
DQ5
DQ5 Data 5
DQ6
DQ6 Data 6
DQ7
DQ7 Data 7
VCC
VCC +5 VDC
PD1
PD1 Presence Detect 1
A0
A0
Address 0
A1
A1
Address 1
A2
A2
Address 2
A3
A3
Address 3
A4
A4
Address 4
A5
A5
Address 5
A6
A6
Address 6
A10
A10 Address 10
n/c
PQ8 Data 8 (Parity 1)
DQ9
DQ9 Data 9
DQ10
DQ10 Data 10
DQ11
DQ11 Data 11
DQ12
DQ12 Data 12
DQ13
DQ13 Data 13
DQ14
DQ14 Data 14
DQ15
DQ15 Data 15
A7
A7
Address 7
A11
A11 Address 11
VCC
VCC +5 VDC
A8
A8
Address 8
A9
A9
Address 9
/RAS3
RAS3 Row Address Strobe 3
/RAS2
DQ16
DQ16 Data 16
n/c
PQ17 Data 17 (Parity 2)
DQ18
DQ18 Data 18
DQ19
DQ19 Data 19
VSS
VSS Ground
/CAS0
CAS0 Column Address Strobe 0
/CAS2
/CAS3
/CAS1
/RAS0
/RAS1
A12
A12 Address 12
/WE
WE Read/Write
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
RI
72 PIN SO DIMM at the computer.
PR
EL
IM
IN
SO DIMM=Small Outline Dual Inline Memory Module
BETA RELEASE
258
TIO
N.
BU
RI
ST
DI
Address 13
Data 20
Data 21
Data 22
Data 23
Data 24
Data 25
Data 26 (Parity 3)
Data 27
Data 28
Data 29
Data 31
Data 30
+5 VDC
Data 32
Data 33
Data 34
Data 35 (Parity 4)
Presence Detect 2
Presence Detect 3
Presence Detect 4
Presence Detect 1
Presence Detect 6
Presence Detect 7
Ground
RE
A13
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
PQ26
DQ27
DQ28
DQ29
DQ31
DQ30
VCC
DQ32
DQ33
DQ34
PQ35
PD2
PD3
PD4
PD5
PD6
PD7
VSS
A13
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
n/c
DQ27
DQ28
DQ29
DQ31
DQ30
VCC
DQ32
DQ33
DQ34
n/c
PD2
PD3
PD4
PD5
PD6
PD7
VSS
FO
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Contributor: Joakim gren, Mark Brown <bugman@total.net>, Jim Burd <JimBurd@aol.com>
OT
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
259
TIO
N.
144 pin SO DIMM
BU
(At the computer)
ST
DI
RE
ET
A
.N
OT
FO
Description
Ground
Ground
Data 0
Data 32
Data 1
Data 33
Data 2
Data 34
Data 3
Data 35
+5 VDC
+5 VDC
Data 4
Data 36
Data 5
Data 37
Data 6
Data 38
Data 7
Data 39
Ground
Ground
+5 VDC
+5 VDC
Address 0
Address 3
Address 1
Address 4
Address 2
Address 5
Ground
Ground
Data 8
Data 40
Data 9
Data 41
Data 10
Data 42
Data 11
Data 43
+5 VDC
+5 VDC
Data 12
YB
Normal ECC
VSS
VSS
VSS
VSS
DQ0
DQ0
DQ32 DQ32
DQ1
DQ1
DQ33 DQ33
DQ2
DQ2
DQ34 DQ34
DQ3
DQ3
DQ35 DQ35
VCC
VCC
VCC
VCC
DQ4
DQ4
DQ36 DQ36
DQ5
DQ5
DQ37 DQ37
DQ6
DQ6
DQ38 DQ38
DQ7
DQ7
DQ39 DQ39
VSS
VSS
VSS
VSS
/CAS0 /CAS0
/CAS4 /CAS4
/CAS1 /CAS1
/CAS5 /CAS5
VCC
VCC
VCC
VCC
A0
A0
A3
A3
A1
A1
A4
A4
A2
A2
A5
A5
VSS
VSS
VSS
VSS
DQ8
DQ8
DQ40 DQ40
DQ9
DQ9
DQ41 DQ41
DQ10 DQ10
DQ42 DQ42
DQ11 DQ11
DQ43 DQ43
VCC
VCC
VCC
VCC
DQ12 DQ12
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
RI
144 PIN SO SIMM at the computer.
PR
EL
IM
IN
SO SIMM=Small Outline Single Inline Memory Module
BETA RELEASE
260
ST
DI
RE
R
.N
OT
Not connected
Ground
Ground
FO
Don't use
Don't use
+5 VDC
+5 VDC
Don't use
Don't use
Read/Write
Not connected
Not connected
Not connected
RI
BU
TIO
N.
Data 44
Data 13
Data 45
Data 14
Data 46
Data 15
Data 47
Ground
Ground
+5 VDC
+5 VDC
Data 16
Data 48
Data 17
Data 49
Data 18
Data 50
Data 19
Data 51
Ground
Ground
Data 20
Data 52
Data 21
Data 53
Data 22
Data 54
Data 23
Data 55
+5 VDC
+5 VDC
Address 6
Address 7
Address 8
Address 11
Ground
ET
A
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
CB0
CB4
CB1
CB5
DU
DU
VCC
VCC
DU
DU
/WE
n/c
/RAS0
n/c
/RAS1
n/c
/OE
n/c
VSS
VSS
CB2
CB6
CB3
CB7
VCC
VCC
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
VCC
VCC
A6
A7
A8
A11
VSS
YB
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
VSS
VSS
n/c
n/c
n/c
n/c
DU
DU
VCC
VCC
DU
DU
/WE
n/c
/RAS0
n/c
/RAS1
n/c
/OE
n/c
VSS
VSS
n/c
n/c
n/c
n/c
VCC
VCC
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
VSS
VSS
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
VCC
VCC
A6
A7
A8
A11
VSS
AR
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
PR
EL
IM
IN
BETA RELEASE
261
TIO
N.
BU
RI
ST
DI
RE
FO
Ground
Address 9
Address 12
Address 10
Address 13
+5 VDC
+5 VDC
Ground
Ground
Data 24
Data 56
Data 25
Data 57
Data 26
Data 58
Data 27
Data 59
+5 VDC
+5 VDC
Data 28
Data 60
Data 29
Data 61
Data 30
Data 62
Data 31
Data 63
Ground
Ground
OT
VSS
A9
A12
A10
A13
VCC
VCC
/CAS2
/CAS6
/CAS3
/CAS7
VSS
/VSS
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VCC
VCC
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VCC
VCC
.N
VSS
A9
A12
A10
A13
VCC
VCC
/CAS2
/CAS6
/CAS3
/CAS7
VSS
/VSS
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
VCC
VCC
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
VSS
VSS
SDA
SCL
VCC
VCC
ET
A
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
+5 VDC
+5 VDC
Contributor: Joakim gren, Mark Brown <bugman@total.net>
YB
AR
PR
EL
IM
IN
BETA RELEASE
262
168 pin DRAM DIMM (Unbuffered)
BU
(At the computer)

168 PIN DIMM at the computer.
ET
A
YB
RE
DI
Description
Ground
Data 0
Data 1
Data 2
Data 3
+5 VDC or +3.3 VDC
Data 4
Data 5
Data 6
Data 7
Data 8
Ground
Data 9
Data 10
Data 11
Data 12
Data 13
+5 VDC or +3.3 VDC
Data 14
Data 15
Parity/Check Bit Input/Output 0
Ground
+5 VDC or +3.3 VDC
Read/Write Input
Output Enable
Ground
Address 0
Address 2
Address 4
Address 6
Address 8
Address 10
Address 12
+5 VDC or +3.3 VDC
+5 VDC or +3.3 VDC
Don't Use
OT
FO
80 ECC?
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VCC
/WE0
/CAS0
/CAS1
/RAS0
/OE0
VSS
A0
A2
A4
A6
A8
A10
A12
VCC
VCC
DU
.N
Non-Parity?Parity? 72 ECC?
VSS
VSS
VSS
DQ0
DQ0 DQ0
DQ1
DQ1 DQ1
DQ2
DQ2 DQ2
DQ3
DQ3 DQ3
VCC
VCC VCC
DQ4
DQ4 DQ4
DQ5
DQ5 DQ5
DQ6
DQ6 DQ6
DQ7
DQ7 DQ7
DQ8
DQ8 DQ8
VSS
VSS
VSS
DQ9
DQ9 DQ9
DQ10
DQ10 DQ10
DQ11
DQ11 DQ11
DQ12
DQ12 DQ12
DQ13
DQ13 DQ13
VCC
VCC VCC
DQ14
DQ14 DQ14
DQ15
DQ15 DQ15
n/c
CB0
CB0
n/c
CB1
CB1
VSS
VSS
VSS
n/c
n/c
n/c
n/c
n/c
n/c
VCC
VCC VCC
/WE0
/WE0 /WE0
/CAS0
/CAS0 /CAS0
/CAS1
/CAS1 /CAS1
/RAS0
/RAS0 /RAS0
/OE0
/OE0 /OE0
VSS
VSS
VSS
A0
A0
A0
A2
A2
A2
A4
A4
A4
A6
A6
A6
A8
A8
A8
A10
A10
A10
A12
A12
A12
VCC
VCC VCC
VCC
VCC VCC
DU
DU
DU
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
ST
Front, Left
RI
Front Side (left side 1-42, right side 43-84)

Back Side (left side 85-126, right side 127-168)
PR
EL
IM
IN
DIMM=Dual Inline Memory Module
TIO
N.
168 pin DRAM DIMM (Unbuffered) Connecto
BETA RELEASE
263
ET
A
YB
Back, Left
Pin
85
86
87
88
89
90
91
92
93
94
VSS
VSS
VSS
DQ32
DQ32 DQ32
DQ33
DQ33 DQ33
DQ34
DQ34 DQ34
DQ35
DQ35 DQ35
VCC
VCC VCC
DQ36
DQ36 DQ36
DQ37
DQ37 DQ37
DQ38
DQ38 DQ38
DQ39
DQ39 DQ39
TIO
N.
80 ECC?
VSS
/OE2
/RAS2
/CAS2
/CAS3
/WE2
VCC
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
n/c
DU
n/c
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
n/c
n/c
n/c
SDA
SCL
VCC
Description
Ground
80 ECC?
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
Description
Ground
Data 32
Data 33
Data 34
Data 35
+5 VDC or +3.3 VDC
Data 36
Data 37
Data 38
Data 39
RE
DI
ST
RI
BU

Read/Write Input
+5 VDC or +3.3 VDC
Ground
Data 16
Data 17
Data 18
Data 19
+5 VDC or +3.3 VDC
Data 20
Not connected
Don't Use
Not connected
Ground
Data 21
Data 22
Data 23
Ground
Data 24
Data 25
Data 26
Data 27
+5 VDC or +3.3 VDC
Data 28
Data 29
Data 30
Data 31
Ground
Not connected
Not connected
Not connected
Serial Data
Serial Clock
+5 VDC or +3.3 VDC
FO
OT
.N
VSS
VSS
VSS
/OE2
/OE2 /OE2
/RAS2
/RAS2 /RAS2
/CAS2
/CAS2 /CAS2
/CAS3
/CAS3 /CAS3
/WE2
/WE2 /WE2
VCC
VCC VCC
n/c
n/c
n/c
n/c
n/c
n/c
n/c
CB2
CB2
n/c
CB3
CB3
VSS
VSS
VSS
DQ16
DQ16 DQ16
DQ17
DQ17 DQ17
DQ18
DQ18 DQ18
DQ19
DQ19 DQ19
VCC
VCC VCC
DQ20
DQ20 DQ20
n/c
n/c
n/c
DU
DU
DU
n/c
n/c
n/c
VSS
VSS
VSS
DQ21
DQ21 DQ21
DQ22
DQ22 DQ22
DQ23
DQ23 DQ23
VSS
VSS
VSS
DQ24
DQ24 DQ24
DQ25
DQ25 DQ25
DQ26
DQ26 DQ26
DQ27
DQ27 DQ27
VCC
VCC VCC
DQ28
DQ28 DQ28
DQ29
DQ29 DQ29
DQ30
DQ30 DQ30
DQ31
DQ31 DQ31
VSS
VSS
VSS
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
n/c
SDA
SDA SDA
SCL
SCL
SCL
VCC
VCC VCC
AR
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PR
EL
IM
IN
Front, Right
BETA RELEASE
264
ET
A
Back, Right
YB
VSS
VSS
VSS
DU
DU
DU
/RAS3
/RAS3 /RAS3
/CAS6
/CAS6 /CAS6
/CAS7
/CAS7 /CAS7
DU
DU
DU
VCC
VCC VCC
n/c
n/c
n/c
n/c
n/c
n/c
n/c
CB6
CB6
n/c
CB7
CB7
VSS
VSS
VSS
DQ48
DQ48 DQ48
DQ49
DQ49 DQ49
DQ50
DQ50 DQ50
DQ51
DQ51 DQ51
VCC
VCC VCC
DQ52
DQ52 DQ52
n/c
n/c
n/c
DU
DU
DU
n/c
n/c
n/c
VSS
VSS
VSS
DQ53
DQ53 DQ53
DQ54
DQ54 DQ54
AR
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
DI
ST
RI
BU
TIO
N.
Data 40
Ground
Data 41
Data 42
Data 43
Data 44
Data 45
+5 VDC or +3.3 VDC
Data 46
Data 47
Ground
+5 VDC or +3.3 VDC
Don't Use
Don't Use
Ground
Address 1
Address 3
Address 5
Address 7
Address 9
Address 11
Address 13
+5 VDC or +3.3 VDC
Don't Use
Don't Use
RE
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
n/c
n/c
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
FO
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
n/c
n/c
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
OT
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
n/c
n/c
VSS
n/c
n/c
VCC
DU
/CAS4
/CAS5
/RAS1
DU
VSS
A1
A3
A5
A7
A9
A11
A13
VCC
DU
DU
.N
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PR
EL
IM
IN
80 ECC?
VSS
DU
/RAS3
/CAS6
/CAS7
DU
VCC
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
n/c
DU
n/c
VSS
DQ53
DQ54
Description
Ground
Don't Use
Don't Use
+5 VDC or +3.3 VDC
Ground
Data 48
Data 49
Data 50
Data 51
+5 VDC or +3.3 VDC
Data 52
Not connected
Don't Use
Not connected
Ground
Data 53
Data 54
BETA RELEASE
265
Data 55
Ground
Data 56
Data 57
Data 58
Data 59
+5 VDC or +3.3 VDC
Data 60
Data 61
Data 62
Data 63
Ground
TIO
N.
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VCC
BU
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VCC
RI
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VCC
Not connected
Serial Address 0
Serial Address 1
Serial Address 2
+5 VDC or +3.3 VDC
ST
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VCC
RE
Contributor: Joakim gren, Mark Brown <bugman@total.net>
DI
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
266
168 pin SDRAM DIMM (Unbuffered)
BU
(At the computer)

168 PIN DIMM at the computer.
YB
FO
RE
DI
Description
Ground
Data 0
Data 1
Data 2
Data 3
+5 VDC or +3.3 VDC
Data 4
Data 5
Data 6
Data 7
Data 8
Ground
Data 9
Data 10
Data 11
Data 12
Data 13
+5 VDC or +3.3 VDC
Data 14
Data 15
Ground
+5 VDC or +3.3 VDC
Read/Write
Byte Mask signal 0
Byte Mask signal 1
Chip Select 0
Don't Use
Ground
Address 0
Address 2
Address 4
Address 6
Address 8
Address 10
Bank Address 1
+5 VDC or +3.3 VDC
+5 VDC or +3.3 VDC
Clock signal 0
.N
OT
80 ECC?
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
CB1
VSS
CB8
CB9
VDD
/WE
DQMB0
DQMB1
/S0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
CK0
ET
A
Non-Parity72 ECC?
VSS
VSS
DQ0
DQ0
DQ1
DQ1
DQ2
DQ2
DQ3
DQ3
VDD
VDD
DQ4
DQ4
DQ5
DQ5
DQ6
DQ6
DQ7
DQ7
DQ8
DQ8
VSS
VSS
DQ9
DQ9
DQ10
DQ10
DQ11
DQ11
DQ12
DQ12
DQ13
DQ13
VDD
VDD
DQ14
DQ14
DQ15
DQ15
n/c
CB0
n/c
CB1
VSS
VSS
n/c
n/c
n/c
n/c
VDD
VDD
/WE
/WE
DQMB0
DQMB0
DQMB1
DQMB1
/S0
/S0
DU
DU
VSS
VSS
A0
A0
A2
A2
A4
A4
A6
A6
A8
A8
A10/AP
A10/AP
BA1
BA1
VDD
VDD
VDD
VDD
CK0
CK0
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
ST
Front, Left
RI
Front Side (left side 1-42, right side 43-84)

Back Side (left side 85-126, right side 127-168)
PR
EL
IM
IN
DIMM=Dual Inline Memory Module
TIO
N.
168 pin SDRAM DIMM (Unbuffered) Connec
BETA RELEASE
267
Non-Parity72 ECC?
VSS
VSS
DQ32
DQ32
DQ33
DQ33
DQ34
DQ34
DQ35
DQ35
VDD
VDD
DQ36
DQ36
DQ37
DQ37
DQ38
DQ38
DQ39
DQ39
TIO
N.
80 ECC?
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
Description
Ground
Data 32
Data 33
Data 34
Data 35
+5 VDC or +3.3 VDC
Data 36
Data 37
Data 38
Data 39
RE
DI
ST
RI
BU
Description
Ground
Don't Use
Chip Select 2
Byte Mask signal 2
Byte Mask signal 3
Don't Use
+5 VDC or +3.3 VDC
Ground
Data 16
Data 17
Data 18
Data 19
+5 VDC or +3.3 VDC
Data 20
Not connected
OT
FO
Clock Enable Signal 1

Ground
Data 21
Data 22
Data 23
Ground
Data 24
Data 25
Data 26
Data 27
+5 VDC or +3.3 VDC
Data 28
Data 29
Data 30
Data 31
Ground
Clock signal 2
Not connected
Not connected
Serial Data
Serial Clock
+5 VDC or +3.3 VDC
.N
YB
Back, Left
Pin
85
86
87
88
89
90
91
92
93
94
80 ECC?
VSS
DU
/S2
DQMB2
DQMB3
DU
VDD
CB10
CB11
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
n/c
Vref,NC
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
CK2
n/c
n/c
SDA
SCL
VDD
ET
A
Non-Parity72 ECC?
VSS
VSS
DU
DU
/S2
/S2
DQMB2
DQMB2
DQMB3
DQMB3
DU
DU
VDD
VDD
n/c
n/c
n/c
n/c
n/c
CB2
n/c
CB3
VSS
VSS
DQ16
DQ16
DQ17
DQ17
DQ18
DQ18
DQ19
DQ19
VDD
VDD
DQ20
DQ20
n/c
n/c
Vref,NC
Vref,NC
CKE1
CKE1
VSS
VSS
DQ21
DQ21
DQ22
DQ22
DQ23
DQ23
VSS
VSS
DQ24
DQ24
DQ25
DQ25
DQ26
DQ26
DQ27
DQ27
VDD
VDD
DQ28
DQ28
DQ29
DQ29
DQ30
DQ30
DQ31
DQ31
VSS
VSS
CK2
CK2
n/c
n/c
n/c
n/c
SDA
SDA
SCL
SCL
VDD
VDD
AR
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
PR
EL
IM
IN
Front, Right
BETA RELEASE
268
ET
A
Back, Right
TIO
N.
BU
RI
ST
DI
RE
80 ECC?
VSS
CKE0
/S3
DQMB6
DQMB7
A13
VDD
CB14
CB15
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
n/c
Vref,NC
n/c
VSS
DQ53
DQ54
YB
Non-Parity72 ECC?
VSS
VSS
CKE0
CKE0
/S3
/S3
DQMB6
DQMB6
DQMB7
DQMB7
A13
A13
VDD
VDD
n/c
n/c
n/c
n/c
n/c
CB6
n/c
CB7
VSS
VSS
DQ48
DQ48
DQ49
DQ49
DQ50
DQ50
DQ51
DQ51
VDD
VDD
DQ52
DQ52
n/c
n/c
Vref,NC
Vref,NC
n/c
n/c
VSS
VSS
DQ53
DQ53
DQ54
DQ54
AR
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Data 40
Ground
Data 41
Data 42
Data 43
Data 44
Data 45
+5 VDC or +3.3 VDC
Data 46
Data 47
Ground
+5 VDC or +3.3 VDC
Byte Mask signal 4
Byte Mask signal 5
Chip Select 1
Row Address Strobe
Ground
Address 1
Address 3
Address 5
Address 7
Address 9
Bank Address 0
Address 11
+5 VDC or +3.3 VDC
Clock signal 1
Address 12
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
CB12
CB13
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
A12
FO
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
CB5
VSS
n/c
n/c
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
A12
OT
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
n/c
n/c
VSS
n/c
n/c
VDD
/CAS
DQMB4
DQMB5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VDD
CK1
A12
.N
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
PR
EL
IM
IN
Description
Ground
Clock Enable Signal 0
Chip Select 3
Byte Mask signal 6
Byte Mask signal 7
Address 13
+5 VDC or +3.3 VDC
Ground
Data 48
Data 49
Data 50
Data 51
+5 VDC or +3.3 VDC
Data 52
Not connected
Not connected
Ground
Data 53
Data 54
BETA RELEASE
269
TIO
N.
Data 55
Ground
Data 56
Data 57
Data 58
Data 59
+5 VDC or +3.3 VDC
Data 60
Data 61
Data 62
Data 63
Ground
Clock signal 3
Not connected
Serial address 0
Serial address 1
Serial address 2
+5 VDC or +3.3 VDC
BU
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VDD
RI
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VDD
ST
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
CK3
n/c
SA0
SA1
SA2
VDD
DI
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
RE
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
270
CDTV Memory Card Connector
TIO
N.
BU
1111111111222222222233333333334
1234567890123456789012345678901234567890
+----------------------------------------+
|OOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO|
+----------------------------------------+
RI
(At the computer)
ET
A
.N
OT
FO
RE
DI
Description
Data Bus 0
Data Bus 1
Data Bus 2
Data Bus 3
Data Bus 4
Data Bus 5
Data Bus 6
Data Bus 7
Data Bus 8
Data Bus 9
Data Bus 10
Data Bus 11
Data Bus 12
Data Bus 13
Data Bus 14
Data Bus 15
Address Bus 1
Address Bus 2
Address Bus 3
Address Bus 4
Address Bus 5
Address Bus 6
Address Bus 7
Address Bus 8
Address Bus 9
Address Bus 10
Address Bus 11
Address Bus 12
Address Bus 13
Address Bus 14
Address Bus 15
Address Bus 16
Address Bus 17
Read/Write (High=Read)
Chip Select Odd Bytes
Chip Select Even Bytes
+5 Volts DC
Ground
Address Bus 18 (Short J16 to connect A18 to processor bus)
Address Bus 19 (Short J17 to connect A19 to processor bus)
YB
Name
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
R/W
/CSMCOD
/CSMCEN
VCC
GND
A18
A19
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ST
PR
EL
IM
IN
CDTV Memory Card Port
Note: Address space=$E00000-$E7FFFF

BETA RELEASE
271
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

BETA RELEASE
272
SmartCard AFNOR Connector
TIO
N.
DI
ST
RI
BU
-------------+------------|
8
|
4
|
|
|
|
+-------\
|
/-------+
|
7
+----+----+
3
|
|
|
|
|
+--------|
|--------+
|
6
|
|
2
|
|
+
+----+
|
+-------/
|
\-------+
|
5
|
1
|
|
|
|
-------------+-------------
RE
(At the card)

Description
+5 VDC
Read/Write
Clock
Reset
Ground
+21 VDC
In/Out
Fuse
FO
Name
VCC
R/W
CLOCK
RESET
GND
VPP
I/O
FUSE
OT
Pin
1
2
3
4
5
6
7
8
.N
Source: Telecard/Smartcard Technical Spec & Info <http://www.physic.ut.ee/~kalev/smartcar.txt> by Stephane

Bausson <sbausson@ensem.u-nancy.fr>
AR
YB
ET
A
PR
EL
IM
IN
SmartCard AFNOR
BETA RELEASE
273
SmartCard ISO 7816-2 Connector
TIO
N.
DI
ST
RI
BU
-------------+------------|
1
|
5
|
|
|
|
+-------\
|
/-------+
|
2
+----+
+
6
|
|
|
|
|
+--------|
|--------+
|
3
|
|
7
|
|
+----+----+
|
+-------/
|
\-------+
|
4
|
8
|
|
|
|
-------------+-------------
RE
(At the card)

Description
+5 VDC
Reset
Clock
Not connected
Ground
Not connected
In/Out
Not connected
FO
Name
VCC
RESET
CLOCK
n/c
GND
n/c
I/O
n/c
OT
Pin
1
2
3
4
5
6
7
8
.N

AR
YB
ET
A
PR
EL
IM
IN
SmartCard ISO 7816-2
BETA RELEASE
274
SmartCard ISO Connector
TIO
N.
DI
ST
RI
BU
-------------+------------|
1
|
5
|
|
|
|
+-------\
|
/-------+
|
2
+----+
+
6
|
|
|
|
|
+--------|
|--------+
|
3
|
|
7
|
|
+----+----+
|
+-------/
|
\-------+
|
4
|
8
|
|
|
|
-------------+-------------
RE
(At the card)

Description
+5 VDC
Read/Write
Clock
Reset
Ground
+21 VDC
In/Out
Fuse
FO
Name
VCC
R/W
CLOCK
RESET
GND
VPP
I/O
FUSE
OT
Pin
1
2
3
4
5
6
7
8
.N
SmartCard ISO 7816-2
Pin
1
2
3
4
5
6
7
8
Name
VCC
RESET
CLOCK
n/c
GND
n/c
I/O
n/c
AR
YB
ET
A
-------------+------------|
1
|
5
|
|
|
|
+-------\
|
/-------+
|
2
+----+
+
6
|
|
|
|
|
+--------|
|--------+
|
3
|
|
7
|
|
+----+----+
|
+-------/
|
\-------+
|
4
|
8
|
|
|
|
-------------+-------------
Description
+5 VDC
Reset
Clock
Not connected
Ground
Not connected
In/Out
Not connected
PR
EL
IM
IN
SmartCard ISO

BETA RELEASE
275
SCART Connector
TIO
N.
BU
(At the video/TV)
RI
(At the cable)
Audio Out Right
AOR
8
9
10
11
12
13
14
15
RGB Blue In
SWTCH
G GND
CLKOUT
G
DATA
R GND
DATAGND
R
16 BLNK
OT
Audio Ground
RGB Blue Ground
Audio In Left + Mono
.N
AGND
B GND
AIL
Data 1: Data Out (Unavailable ??)

RGB Red Ground
Data Ground
RGB Red In / Chrominance
17 VGND
Composite Video Ground
18 BLNKGND Blanking Signal Ground
19 VOUT
Composite Video Out
Composite Video In / Luminance
21 SHIELD
0.5 V rms
<1k
ohm
0.5 V rms
>10k
ohm
0.7 V
75
ohm
Audio/RGB switch / 16:9

RGB Green Ground
Data 2: Clockpulse Out (Unavailable ??)
RGB Green In
0.7 V
Blanking Signal
20 VIN
>10k
ohm
ET
A
4
5
6
Audio Out Left + Mono
0.5 V rms
FO
AOL
<1k
ohm
75
ohm
YB
Audio In Right
AIR
Imped
0.5 V rms
AR
Signal Level
DI
Description
RE
Pin Name
ST
21 PIN SCART FEMALE at the Video/TV.

21 PIN SCART MALE at the Cable.
PR
EL
IM
IN
SCART
0.7 V (Chrom.: 0.3 V burst)

75
ohm
1-3 V=RGB, 0-0.4 V=Composite
75
ohm
1V
75
ohm
1V
75
ohm
Ground/Shield (Chassis)
BETA RELEASE
276
SCART Connector
TIO
N.
Source: Various sources, Video Demystified at Keith Jack's pages

<http://www.mindspring.com/~kjack1/scart.html>
BU
RI
ST
DI
RE
R
FO
OT
.N
ET
A
YB
AR
PR
EL
IM
IN
BETA RELEASE
277
S-Video Connector
TIO
N.
(At the peripheral)
Description
Ground (Y)
Ground (C)
Intensity (Luminance)
Color (Chrominance)
RI
Name
GND
GND
Y
C
ST
Pin
1
2
3
4
BU
4 PIN MINI-DIN FEMALE at the peripheral.
DI
Source: Video Demystified at Keith Jack's pages <http://www.mindspring.com/~kjack1/svideo.html>
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
S-Video
BETA RELEASE
278
DIN Audio Connector
TIO
N.
BU
(At the peripheral)
In R
5
5
1
1
1
4
4
4
FO
Out L Out R Ground

2
1
4
2
3
5
2
1
4
2
3
5
2
3
5
2
3
5
2
2
DI
In L
3
3
RE
Connected
Pickup, tuner
Taperecorder
Amplifier
Taperecorder
Amplifier
Amplifier
Receiver
Microphone
Peripheral
Amplifier
Amplifier
Tuner
Tuner
Recordplayer
Taperecorder
Taperecorder
Taperecorder
ST
5 PIN DIN 180 (DIN41524) FEMALE at the peripheral.

5 PIN DIN 180 (DIN41524) MALE at the cable.
RI
(At the cable)
Source: ELFA <http://www.elfa.se>'s catalog Nr 44
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
DIN Audio
BETA RELEASE
279
3.5 mm Mono Telephone plug
TIO
N.
(At the cable)
BU
3.5 mm MONO TELEPHONE MALE at the cable.
RI
Name
Description
SIGNAL Signal
GROUND Ground
ST

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
DI
PR
EL
IM
IN
BETA RELEASE
280
3.5 mm Stereo Telephone plug
TIO
N.
(At the cable)
RI
Description
Left Signal
Right Signal
Ground
ST
Name
L
R
GROUND
BU
3.5 mm STEREO TELEPHONE MALE at the cable.
Contributor: Joakim gren, Uwe Hartmann <uhartmann@i-stud.htw-zittau.de>
DI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
BETA RELEASE
281
TIO
N.
BU
(At the cable)

6.25 mm MONO TELEPHONE MALE at the cable.
ST
RI
Name
Description
SIGNAL Signal
GROUND Ground
DI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
BETA RELEASE
282
TIO
N.
BU
(At the cable)

RI
Description
Left Signal
Right Signal
Ground
ST
Name
L
R
GROUND
DI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
BETA RELEASE
283
5.25" Power Connector
TIO
N.
5.25" Power
RI
BU
(At the powersupply cable)
Name
+12V
GND
GND
+5V
Color
Yellow
Black
Black
Red
Description
+12 VDC
+12 V Ground (Same as +5 V Ground)
+5 V Ground
+5 VDC
RE
Pin
1
2
3
4
DI
UNKNOWN CONNECTOR at the powersupply cable.

UNKNOWN CONNECTOR at the peripheral.
ST
(At the peripheral)
FO
Contributors: Joakim gren, Eric Sprigg <Eric_Sprigg@compuserve.com>, Sven Gunnar Bilen

<sbilen@umich.edu>, Scott Lindenthaler <scott@teraflop.com>
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Used for harddisks & 5.25" peripherals.
BETA RELEASE
284
TIO
N.
3.5" Power
RI
BU
(At the powersupply cable)
Name
+5V
GND
GND
+12V
Color
Red
Black
Black
Yellow
Description
+5 VDC
+5 V Ground
+12 V Ground (Same as +5 V Ground)
+12 VDC
RE
Pin
1
2
3
4
DI
UNKNOWN CONNECTOR at the powersupply cable.

UNKNOWN CONNECTOR at the peripheral.
ST
(At the peripheral)
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Used for floppies.
BETA RELEASE
285
Motherboard Power Connector
TIO
N.
BU
(At the Computer)
RI
(At the Powersupply cables)
ST
2x MOLEX 15-48-0106 CONNECTOR at the Computer.

2x MOLEX 90331-0001 CONNECTOR at the Powersupply cables.
Color
Orange
Red
Yellow
Blue
Black
Black
Description
Power Good, +5 VDC when all voltages has stabilized.
+5 VDC (or n/c)
+12 VDC
-12 VDC
Ground
Ground
Name
GND
GND
-5V
+5V
+5V
+5V
Color
Black
Black
White or Yellow
Red
Red
Red
RE
Name
PG
+5V
+12V
-12V
GND
GND
FO
Pin
1
2
3
4
5
6
DI
P8
P9
.N
OT
Description
Ground
Ground
-5 VDC
+5 VDC
+5 VDC
+5 VDC
ET
A
Pin
1
2
3
4
5
6
Note: Pins part number is 08-50-0276, Product specification is PS-90331.

Contributor: Joakim gren, Bill Shepherd <contrav@usaor.net>
YB
Source: ?
AR
PR
EL
IM
IN
Motherboard Power
BETA RELEASE
286
Turbo LED Connector
TIO
N.
(At the computer)
Description
+5 VDC
HighSpeed
+5 VDC
RI
Name
+5V
/HS
+5V
ST
Pin
1
2
3
BU
DI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
Turbo LED
BETA RELEASE
287
AT Backup Battery Connector
TIO
N.
(At the computer)
Description
Battery+
Key
Ground
Ground
RI
Name
BATT+
key
GND
GND
ST
Pin
1
2
3
4
BU
DI

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
AT Backup Battery
BETA RELEASE
288
AT LED/Keylock Connector
TIO
N.
(At the computer)
Description
LED Power
Ground
Ground
Key Switch
Ground
RI
Name
LED
GND
GND
KS
GND
ST
Pin
1
2
3
4
5
BU
DI
RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
AT LED/Keylock
BETA RELEASE
289
PC Speaker Connector
TIO
N.
(At the computer)
Description
-Speaker
Key
Ground
+Speaker +5 VDC
RI
Name
-SP
key
GND
+SP5V
ST
Pin
1
2
3
4
BU
DI

Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
PC Speaker
BETA RELEASE
290
Motherboard IrDA Connector
TIO
N.
Motherboard IrDA
1 2 3 4 5
. . . . .
Description
Power
Not connected
IR Module data received
System GND
IR Module data transmit
RI
Name
+5v
n/c
IRRX
GND
IRTX
ST
Pin
1
2
3
4
5
BU
5 PIN IDC MALE at the motherboard.
DI
Source: ASUS motherboard manual
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
For motherboards with a IrDA compliant Infrared Module connector.
BETA RELEASE
291
Motherboard CPU Cooling fan Connector
TIO
N.
Motherboard CPU Cooling fan

1 2 3
. . .
Name
GND
+12V
GND
BU
Pin
1
2
3
RI
ST
Source: ASUS Motherboard Manual
AR
YB
ET
A
.N
OT
FO
RE
DI
PR
EL
IM
IN
3 PIN IDC MALE at the motherboard
BETA RELEASE
292
Ethernet 10/100Base-T
BU
DI
ST
RI
(At the network interface cards/hubs)
(At the cables)
Description
Tranceive Data+
Tranceive DataReceive Data+
Not connected
Not connected
Receive DataNot connected
Not connected
FO
Name
TX+
TXRX+
n/c
n/c
RXn/c
n/c
OT
Pin
1
2
3
4
5
6
7
8
RE
RJ45 FEMALE CONNECTOR at the network interface cards/hubs.

.N
Note: TX & RX are swapped on Hub's.
Contributor: Joakim gren, Jeffrey R. Broido <broidoj@gti.net>
ET
A
Source: ?
AR
YB
PR
EL
IM
IN
Same connector and pinout for both 10Base-T and 100Base-TX.
TIO
N.
Ethernet 10/100Base-T Connector
BETA RELEASE
293
Ethernet 100Base-T4
BU
DI
ST
RI
(At the network interface cards/hubs)
(At the cables)
Description
Tranceive Data+
Tranceive DataReceive Data+
Bi-directional Data+
Bi-directional DataReceive DataBi-directional Data+
Bi-directional Data-
FO
Name
TX_D1+
TX_D1RX_D2+
BI_D3+
BI_D3RX_D2BI_D4+
BI_D4-
OT
Pin
1
2
3
4
5
6
7
8
RE
RJ45 FEMALE CONNECTOR at the network interface cards/hubs.

.N
Note: TX & RX are swapped on Hub's. Don't know about Bi-directional data.
Contributor: Joakim gren, Kim Scholte <KScholte@BigFoot.Com>
ET
A
Source: ?
AR
YB
PR
EL
IM
IN
100Base-T4 uses all four pairs. 100Base-TX only uses two pairs.
TIO
N.
Ethernet 100Base-T4 Connector
BETA RELEASE
294
AUI Connector
TIO
N.
AUI
BU
(At the Ethernet card)
RE
DI
ST
Description
control in circuit shield
control in circuit A
data out circuit A
data in circuit shield
data in circuit A
voltage common
?
control out circuit shield
control in circuit B
data out circuit B
data out circuit shield
data in circuit B
voltage plus
voltage shield
?
FO
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RI
15 PIN D-SUB FEMALE at the Ethernet card.
OT
AR
YB
ET
A
.N

PR
EL
IM
IN
Is the directions right???
BETA RELEASE
295
Atari 2600 Cartridge Connector
TIO
N.
BU
Top
D3
D4
D5
D6
D7
A12 A10 A11 A9
A8 +5V
SGND
--1- --2- --3- --4- --5- --6- --7- --8- --9- -10- -11- -12GND D2
D1
D0
A0
A1
A2
A3
A4
A5
A6
A7
Bottom
RI
(At the Atari)
ST

Connect a 2716 or 2732/2532 EPROM.
RE
R
Description
Data 3
Data 4
Data 5
Data 6
Data 7
Address 12
Address 10
Address 11
Address 9
Address 8
+5 VDC
Shield Ground
FO
CPU Name
D3
D4
D5
D6
D7
A12
A10
A11
A9
A8
+5V
SGND
OT
2716 Pin
13
14
15
16
17
*
19
n/c
22
23
24
12
.N
Pin
1
2
3
4
5
6
7
8
9
10
11
12
DI
Top Row
* to inverter and back to 18 for chip select
CPU Name
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
Description
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Ground
YB
2716 Pin
1
2
3
4
5
6
7
8
9
10
11
n/c
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
ET
A
Bottom Row
PR
EL
IM
IN
Atari 2600 Cartridge

BETA RELEASE
296
TIO
N.
(At the Atari)
RI
ST
DI
RE
R
YB
ET
A
.N
OT
FO
Name
D0
D1
D2
D3
D4
D5
D6
D7
Enable 80-8F
Enable 40-7F
Not Connected
Ground
Ground
Ground (System Clock 02 on 2 port)
A6
A5
A2
Interlock
A0
A1
A3
A4
Ground
Ground (Video In on 2 port)
Ground
+5 VDC
A7
Not Connected
A8
Audio In (2 port)
A9
A13
A10
A12
A11
Interlock
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BU
PR
EL
IM
IN

BETA RELEASE
297
Atari 5200 Expansion Connector
TIO
N.
(At the Atari)
RI
ST
DI
RE
R
FO
OT
.N
ET
A
YB
Name
+5 VDC
Audio Out (2 port)
Ground
R/W Early
Enable E0-EF
D6
D4
D2
D0
IRQ
Ground
Serial Data In
Serial In Clock
Serial Out Clock
Serial Data Out
Audio In
A14
System Clock 01
A11
A7
A6
A5
A4
A3
A2
A1
A0
Ground
D1
D3
D5
D7
Not connected
Ground
Not connected
+5 VDC
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
BU
PR
EL
IM
IN
Atari 5200 Expansion

BETA RELEASE
298
TIO
N.
(At the Atari)
RI
ST
DI
RE
R
FO
OT
.N
ET
A
Description
Read/Write
Halt
Data 3
Data 4
Data 5
Data 6
Data 7
Address 12
Address 10
Address 11
Address 9
Address 8
+5 VDC
Ground
Address 13
Address 14
Address 15
EAudio ???
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Gnd
Interrupt
Clock 2 ???
YB
Name
R/W
HALT
D3
D4
D5
D6
D7
A12
A10
A11
A9
A8
+5V
GND
A13
A14
A15
EAUDIO
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
Gnd
IRQ
CLK2
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
BU

PR
EL
IM
IN
BETA RELEASE
299
Atari 7800 Expansion

-16-- -15-- -14-- -13-- -12-- --11-- -10-Rdy
MCol MLum2 MLum1 Msync Clk2 ExtOsc
BU
-18-- -17-Gnd Audio
RI
(At the Atari)
OT
FO
RE
DI
Description
Ground
+5 VDC
Input to RF modulator (Video+Audio)
Maria Luminance Bit 0
Blanking output
Disable 14.31818 MHz Master Clock
External Maria Enable Input
Ground
External clock to replace Master Clock
Phase 2 Clock from the 6502
Maria Composite Sync
Maria Color Phase Angle
Input to the 6502
Audio
Ground
.N
Name
GND
+5V
CVIDEO
MLUM0
MLUM3
BLANK
OSCDIS
EXTMEN
GND
EXTOSC
CLK2
MSYNC
MLUM1
MLUM2
MCOL
RDY
AUDIO
GND
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
ST

<http://www.dhp.com/~sloppy/files/classic/atari/atari.faq>, Pinout by Harry Dodgson
AR
YB
PR
EL
IM
IN
Gnd
+5v CVideo MLum0 Mlum3 Blank OscDis ExtMen Gnd
--1-- --2-- --3-- --4-- --5-- --6-- --7-- ---8-- --9--
TIO
N.
BETA RELEASE
300
Atari Cartridge Port Connector
TIO
N.
BU
(At the Computer)
RI
(At the Devices)
DI
RE
R
FO
OT
.N
ET
A
Description
+5 VDC
+5 VDC
Data 14
Data 15
Data 12
Data 13
Data 10
Data 11
Data 8
Data 9
Data 6
Data 7
Data 4
Data 5
Data 2
Data 3
Data 0
Data 1
Address 13
Address 15
Address 8
Address 14
Address 7
Address 9
Address 6
Address 10
Address 5
Address 12
Address 11
Address 4
ROM Select 3
Address 3
ROM Select 4
Address 2
Upper Data Strobe
Address 1
Lower Data Strobe
Ground
Ground
Ground
YB
Name
+5V
+5V
D14
D15
D12
D13
D10
D11
D8
D9
D6
D7
D4
D5
D2
D3
D0
D1
A13
A15
A8
A14
A7
A9
A6
A10
A5
A12
A11
A4
RS3
A3
RS4
A2
UDS
A1
LDS
GND
GND
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ST
40 PIN EDGE ?? at the Computer.

40 PIN EDGE ?? at the Devices.
PR
EL
IM
IN
Atari Cartridge Port
BETA RELEASE
301
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

Source: ?
BETA RELEASE
302
GameBoy Cartridge Connector
TIO
N.
GameBoy Cartridge
BU
(At the GameBoy)
ET
A
.N
OT
FO
RE
DI
ST
Description
+5 VDC
? Connected on Gameboy, but not used on GamePaks.
Reset
Write
? Used by paging PAL on high capacity GamePaks.
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Address 14
Chip Select
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Read
? Connected on Gameboy, but not used on Game-Paks.
Ground
YB
Name
VCC
?
/RESET
/WR
?
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
/CS
D0
D1
D2
D3
D4
D5
D6
D7
/RD
?
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RI
UNKNOWN CONNECTOR at the GameBoy.
PR
EL
IM
IN
Available on the Nintendo GameBoy.
Source: Nintendo GameBoy FAQ <http://www.freeflight.com/fms/stuff/gameboy.faq>, Pinout by Peter Knight &

Josef Mollers
BETA RELEASE
303
MSX Expansion Connector
TIO
N.
RI
BU
49 47 45
5 3 1
+---------//-----+
| H H H //H H H |
| ======//====== |
| H H H// H H H |
+-----//---------+
50 48 46 6 4 2
ST
(At the Computer)

50 PIN ?? at the Computer.
ET
A
.N
OT
FO
RE
DI
Description
Memory Read in addresses 4000-7FFF
Memory Read in addresses 8000-BFFF
Memory Read in addresses 4000-BFFF
Low when Slot 2 (cartridge slot) is selected
Not connected.
Refresh signal from CPU
OC, Tells CPU to wait. Refresh signal is not maintained
OC, Requests a interrupt to CPU (call to addr 38h)
CPU fetches first part of instruction from memory.
NC, was used to control the data direction.
I/O request signal. (Address=Port)
Memory request signal. (Address=Address)
Write signal (strobe)
Read signal (strobe)
Reset
Not connected.
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Address 14
Address 15
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Ground
CPU clock, 3.579 MHz
Ground
YB
Name
Dir
/CS1
/CS2
/CS12
/SLTSL
n/c
/RFSH
/WAIT
/INT
/M1
/BUSDIR
/IORQ
/MREQ
/WR
/RD
/RESET
n/c
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
GND
CLOCK
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PR
EL
IM
IN
MSX Expansion
BETA RELEASE
304
SW1
+5V
SW2
+5V
+12V
SOUNDIN
-12V
NC, Insert/remove detection for protection

+5 VDC (300mA max /slot)
NC, Insert/remove detection for protection
Sound input (-5dBm)
-12 VDC (50mA max /slot)
BU
TIO
N.
44
45
46
47
48
49
50
RI
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
PR
EL
IM
IN
BETA RELEASE
305
Vic 20 Memory Expansion Connector
TIO
N.
Vic 20 Memory Expansion
RI
BU
1
TOP
22
+-------------------//----------------+
| =================//================ |
+-----------------//------------------+
A
BOTTOM
Z
UNKNOWN CONNECTOR at the Computer.
ET
A
.N
OT
FO
RE
DI
Description
Ground
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Decoded I/O block 2, starting at $9130
Decoded I/O block 3, starting at $9140
Phase 2 System Clock
Non maskable Interrupt
6502 Reset
Not connected
Ground
Ground
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
BLK 1 (Memory location $2000 - $3fff)
BLK 5 (Memory location $a000 - $bfff)
RAM 1 (Memory location $0400 - $07ff)
RAM 2 (Memory location $0800 - $0bff)
RAM 3 (Memory location $0c00 - $0fff)
Read/Write from Vic chip (1=R, 0=W)
Read/Write from CPU (1=R, 0=W)
6502 Interrupt Request
Not connected
+5 VDC
YB
Name
GND
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CA10
CA11
CA12
CA13
I/O 2
I/O 3
S02
/NMI
/RESET
n/c
GND
GND
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
/BLK 1
/BLK 2
/BLK 3
/BLK 5
RAM 1
RAM 2
RAM 3
V R/W
C R/W
/IRQ
n/c
+5V
AR
Pin
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
ST
(At the Computer)
PR
EL
IM
IN
Available on Commodore Vic 20 computers. On the left side.
BETA RELEASE
306

22 GND
Ground
TIO
N.
Sources: Inside your Vic 20 <http://ccnga.uwaterloo.ca/pub/cbm/vic-20/cartgrab.txt> by Ward Shrake

<wardshrake@aol.com>
Sources: "The Vic Revealed" by Nick Hampshire, 1982, Hayden Book Co, Inc.
Sources: "Vic20 Programmer's Reference Guide", 1992, Commodore Business, Machines, Inc. and Howard W.
Sams & Company, Inc.
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
BU
PR
EL
IM
IN
BETA RELEASE
307
C64 Cartridge Expansion Connector
TIO
N.
(At the computer)
Name
GND
+5V
+5V
/IRQ
/CR/W
DOTCLK
I/O 1
/GAME
/EXROM
I/O 2
/ROML
BA
/DMA
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
GND
Description
Ground
+5 Volts DC
+5 Volts DC
Interrupt Request
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
GND
/ROMH
/RESET
/NMI
S02
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
GND
Ground
ROM High
Reset
ST
RI
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BU
DI
Dot Clock
RE
Game
FO
OT
ET
A
.N
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Cartridge Data 7
Ground
ROM Low
AR
YB
Cartridge Address 15
Cartridge Address 9
Cartridge Address 8
Cartridge Address 7
Cartridge Address 6
Cartridge Address 5
Cartridge Address 4
Cartridge Address 3
Cartridge Address 2
Cartridge Address 1
Cartridge Address 0
Ground
PR
EL
IM
IN
C64 Cartridge Expansion

BETA RELEASE
308
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

BETA RELEASE
309
C64 User Port Connector
TIO
N.
(At the computer)
BU
24 PIN MALE EDGE (DZM 12 DREH) at the computer.

Name
GND
+5V
/RESET
CNT1
SP1
CNT2
SP2
/PC2
ATN
+9V AC
+9V AC
GND
Description
Ground
+5 VDC (100 mA max)
Reset, will force a Cold Start. Also a reset output for devices.
Counter 1, from CIA #1
Serial Port 1, from CIA #1
Counter 2, from CIA #2
Serial Port 2, from CIA #2
Handshaking line, from CIA #2
Serial Attention In
+9 VAC (+ phase) (100 mA max)
+9 VAC (- phase) (100 mA max)
Ground
A
B
C
D
E
F
H
J
K
L
M
N
GND
/FLAG2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA2
GND
Ground
Flag 2
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
PA2
Ground
ET
A
.N
OT
FO
RE
DI
ST
RI
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Contributor: Joakim gren, Nikolas Engstrm <nikolas.engstrom@pop.landskrona.se>, Arwin Vosselman

<0vosselman01@flnet.nl>, Jestin Nesselroad
YB
AR
PR
EL
IM
IN
C64 User Port
BETA RELEASE
310
C128 Expansion Bus Connector
TIO
N.
C128 Expansion Bus
BU
(At the computer)
Name
GND
+5V
+5V
/IRQ
R/W
DClock
I/O1
/GAME
/EXROM
I/O2
/ROML
BA
/DMA
D7
D6
D5
D4
D3
D2
D1
D0
GND
Description
System Ground
System Vcc
System Vcc
Interrupt request
System Read/Write Signal
8.18MHz Video Dot Clock
I/O Chip select $de00-deff
Sensed for memory map configuration
Sensed for memory map configuration
I/O Chip select $df00-dfff
External ROM select $8000-Bfff
Bus available output
Direct memory access input
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
System Ground
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
GND
/ROMH
/RESET
/NMI
1MHz
TA15
TA14
TA13
TA12
TA11
TA10
TA9
TA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND
System Ground
External ROM Select $c000-ffff
System Reset Signal
Non-Maskable Interrupt
System 1MHz clock
Translated address bit 15
Shared address bit 7
System Ground
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RI
PR
EL
IM
IN
Available at the Commodore 128.
BETA RELEASE
311
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
TIO
N.
BU
RI

Source: Commodore 128 Programmers reference guide.
BETA RELEASE
312
C16/+4 Expansion Bus Connector
TIO
N.
C16/C116/+4 Expansion Bus
BU
(At the Computer)
ET
A
.N
OT
FO
RE
DI
ST
Description
Ground
+5 VDC
+5 VDC
Interrupt
Read/Write (1=Read, 0=Write)
External Cartridge Chip Selects C1 High
External Cartridge Chip Selects C2 Low (reserved)
External Cartridge Chip Selects C2 High (reserved)
Chip Select Line 1
Chip Select Line 0
DRAM address multiplex control signal
Bus Available (Low=DMA)
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
Address Enable Code
External Audio In
Artificial Phi 2 signal
Ground
Ground
External Cartridge Chip Selects C1 Low
Reset
Row Address Strobe
Artificial Phi 0 Signal
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Not connected
YB
Name
GND
+5V
+5V
/IRQ
R/W
C1HIGH
C2LOW
C2HIGH
/CS1
/CS0
/CAS
MUX
BA
D7
D6
D5
D4
D3
D2
D1
D0
AEC
EAI
PHI 2
GND
GND
C1LOW
/RESET
/RAS
PHI 0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
n/c
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A
B
C
D
E
F
H
J
K
L
M
N
P
R
S
T
U
V
W
X
Y
Z
RI
50 PIN FEMALE EDGE (2 mm pitch) at the Computer.
PR
EL
IM
IN
Available on Commodore C16, C116 and +4 computers.
BETA RELEASE
313

Not connected
Not connected
Ground
TIO
N.
AA n/c
BB n/c
CC GND
BU
Sources: Usenet posting in comp.sys.cbm, Pinout specs for cbm machines needed
<http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt> by Lonnie McClure <lmcclure@delphi.com>
Sources: Article in C'T September 1986.
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
PR
EL
IM
IN
PHI 2: Address valid on the rising edge, data valid on the falling edge
BETA RELEASE
314
+4 User Port Connector
TIO
N.
+4 User Port
BU
(At the Computer)
ST
DI
RE
R
FO
OT
Description
Ground
+5 VDC
?
Data 2/Cassette Sense
Data 3
Data 4
Data 5
Receive Clock
Attention?
+9 VAC
+9 VAC
Ground
Ground
Data 0
Receive Data
Request to Send
Data Terminal Ready
Data 7
Data Carrier Detect
Data 6
Clear to Send
Data Set Ready
Transmit Data
Ground
.N
Name
GND
+5V
/BRESET
P2/CSE
P3
P4
P5
RxC
ATN
+9V
+9V
GND
GND
P0
RxD
RTS
DTR
P7
DCD
P6
CTS
DSR
TxD
GND
ET
A
Pin
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
G
H
I
J
K
L
RI
UNKNOWN CONNECTOR at the Computer.
YB
Sources: Usenet posting in comp.sys.cbm, Pinout specs for cbm machines needed
<http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt> by Lonnie McClure <lmcclure@delphi.com>
AR
PR
EL
IM
IN
Available on Commodore +4 computer.
BETA RELEASE
315
CDTV Diagnostic Slot Connector
TIO
N.
(At the computer)
ET
A
.N
OT
FO
RE
DI
ST
RI
Description
Ground
Ground
+5 VDC
+5 VDC
Configout AutoConfig signal (not connected)
Configin AutoConfig signal (grounded)
Ground
3.58 MHz CCKQ clock (C3)
7.16 MHz CDAC clock (90 before system clock)
3.58 MHz CCK clock (C1)
Override (Disables /DTACK generation of Gary)
External Ready (Generates wait states while low).
Level 2 Interrupt
not connected
Address Bus 5
Level 6 Interrupt
Address Bus 6
Address Bus 4
Ground
Address Bus 3
Address Bus 2
Address Bus 7
Address Bus 1
Address Bus 8
Processor Function Code Status (bit 0)
Address Bus 9
Address Bus 10
Address Bus 11
Ground
Address Bus 12
Address Bus 13
Interrupt Priority Level (bit 0)
Address Bus 14
Address Bus 15
Address Bus 16
Bus Error
Address Bus 17
Valid Peripheral Address (asserted by Gary)
Ground
E Clock
Valid Memory Address (asserted by Gary)
Address Bus 18
Reset
Address Bus 19
Halt
YB
Name
GND
GND
VCC
VCC
/CFGOUT
/CFGIN
GND
CCKQ
CDAC
CCK
/OVR
XRDY
/INT2
n/c
A5
/INT6
A6
A4
GND
A3
A2
A7
A1
A8
/FC0
A9
/FC1
A10
/FC2
A11
GND
A12
A13
/IPL0
A14
/IPL1
A15
/IPL2
A16
/BERR
A17
/VPA
GND
E
/VMA
A18
/RST
A19
/HLT
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
BU
PR
EL
IM
IN
CDTV Diagnostic Slot
BETA RELEASE
316
RE
DI
ST
RI
BU
TIO
N.
Address Bus 20
Address Bus 22
Address Bus 21
Address Bus 23
Bus Request
Ground
Bus Grant Acknowledge
Data Bus 15
Bus Grant
Data Bus 14
Data Transfer Acknowledge (normally asserted by Gary)
Data Bus 13
Read/Write (high=read, low=write)
Data Bus 12
Lower Data Strobe
Data Bus 11
Upper Data Strobe
Ground
Address Strobe
Data Bus 0
Data Bus 10
Data Bus 1
Data Bus 9
Data Bus 2
Data Bus 8
Data Bus 3
Data Bus 7
Data Bus 4
Data Bus 6
Ground
Data Bus 5
FO
A20
A22
A21
A23
/BR
GND
/BGACK
D15
/BG
D14
/DTACK
D13
R/W
D12
/LDS
D11
/UDS
GND
/AS
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
GND
D5
OT
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
ET
A
.N
Note: Pin 7-80 is equivalent with the Amiga 500's pin 13-86 at the 86 pin Amiga 500
connector.
AR
YB
PR
EL
IM
IN
BETA RELEASE
317
CDTV Expansion Slot Connector
16
--15
18
--17
20
--19
22
--21
24
--24
26
--25
28
--27
TIO
N.
14
--13
30
--29
BU
2 4 6 8 10 12
-- -- -- -- -- --- -- -- -- -- -1 3 5 7 9 11
RI
(At the computer)
DI
RE
R
FO
ET
A
.N
OT
Description
Ground
Ground
+5 VDC
+5 VDC
Data Bus 1
Data Bus 0
Data Bus 3
Data Bus 2
Data Bus 5
Data Bus 4
Data Bus 7
Data Bus 6
DMA Request
Interrupt Request
Chip Select
DMA Acknowledge
I/O Read
I/O Write
Address Bus 8
7.16 MHz System Clock
Address Bus 6
Address Bus 7
Address Bus 4
Address Bus 5
Address Bus 2
Address Bus 3
+5 VDC
Address Bus 1
Ground
Ground
YB
Name
GND
GND
VCC
VCC
SD1
SD0
SD3
SD2
SD5
SD4
SD7
SD6
/SDREQ
/INTX
/CSS
/SDACK
/IOR
/IOW
A8
7M
A6
A7
A4
A5
A2
A3
/IFRST
A1
GND
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ST
PR
EL
IM
IN
CDTV Expansion Slot

BETA RELEASE
318
PC-Engine Cartridge Connector
TIO
N.
PC-Engine Cartridge
BU
(At the PC Engine)
DI
RE
R
FO
OT
.N
ET
A
Address 18
Address 16
Address 15
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 0
Data 1
Data 2
Ground
Data 3
Data 4
Data 5
Data 6
Data 7
Chip Select
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Address 17
Address 19
Read/Write
ST
Description
YB
Name
?
?
A18?
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
D3
D4
D5
D6
D7
/CE
A10
/OE
A11
A9
A8
A13
A14
A17
A19?
R/W
?
?
?
+5V
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
RI
UNKNOWN CONNECTOR at the PC Engine.
PR
EL
IM
IN
Available on the PC Engine.
+5 VDC
Pin 1 is the short pin on the left (if the card is to inserted forwards)
Pin 38 is the long pin on the right.
<http://www.lib.ox.ac.uk/internet/news/faq/archive/games.video-games.faq.part3.html>, Pinout by David Shadoff
<daves@interlog.com>
BETA RELEASE
319
SNES Cartridge Connector
TIO
N.
SNES Cartridge
RI
BU
+-------------------------------//----------------------------+
| 32 33 34 35 | 36 37 38 39 40 //53 55 56 57 58 | 59 60 61 62 |
| 01 02 03 04 | 05 06 07 08 09// 22 24 25 26 27 | 28 29 30 31 |
+----------------------------//-------------------------------+
(At the SNES)
Description
GND
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/IRQ
D0
D1
D2
D3
/READ
CIC
CIC
/RAM ENABLE
VCC
Ground
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Interrupt
Data 0
Data 1
Data 2
Data 3
Read
?
?
RAM Enable
+5 VDC
YB
ET
A
.N
OT
FO
RE
DI
Name
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ST
UNKNOWN CONNECTOR at the SNES.
PR
EL
IM
IN
Available on the Nintendo SNES.
GND
A12
A13
A14
A15
A16
A17
A18
A19
Ground
Address 12
Address 13
Address 14
Address 15
Address 16
Address 17
Address 18
Address 19
BETA RELEASE
320
RI
BU
TIO
N.
Address 20
Address 21
Address 22
Address 23
ROM Enable
Data 4
Data 5
Data 6
Data 7
Write
?
?
Not connected
+5 VDC
ST
A20
A21
A22
A23
/ROM ENABLE
D4
D5
D6
D7
/WRITE
CIC
CIC
n/c
VCC
DI
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
RE

<http://www.lib.ox.ac.uk/internet/news/faq/archive/games.video-games.faq.part3.html>, Pinout by Thomas
Rolfes <rolfes@uni-muenster.de>
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
321
TG-16 Cartridge Connector
TIO
N.
TG-16 Cartridge
BU
(At the TG-16)
DI
RE
R
FO
OT
.N
ET
A
Address 18
Address 16
Address 15
Address 12
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
Address 0
Data 7
Data 6
Data 5
Ground
Data 4
Data 3
Data 2
Data 1
Data 0
Chip Select
Address 10
Output Enable
Address 11
Address 9
Address 8
Address 13
Address 14
Address 17
Address 19
Read/Write
ST
Description
YB
Name
?
?
A18?
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
GND
D4
D3
D2
D1
D0
/CE
A10
/OE
A11
A9
A8
A13
A14
A17
A19?
R/W
?
?
?
+5V
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
RI
UNKNOWN CONNECTOR at the TG-16.
PR
EL
IM
IN
Available on the TG-16.
+5 VDC
Pin 1 is the short pin on the left (if the card is to inserted forwards)
Pin 38 is the long pin on the right.
<http://www.lib.ox.ac.uk/internet/news/faq/archive/games.video-games.faq.part3.html>, Pinout by David Shadoff
<daves@interlog.com>
BETA RELEASE
322
ZX Spectrum AY-3-8912 Connector
TIO
N.
ZX Spectrum AY-3-8912
BU
(At the computer)
.N
OT
FO
RE
DI
ST
Description
Sound C (Can be tied together with A & B)
?
+5 VDC
Sound B (Can be tied together with A & C)
Sound A (Can be tied together with B & C)
Ground
?
?
?
?
?
?
?
?
?
Reset
Address 8?
?
?
?
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
ET
A
Name
SOUND C
PORT
VCC
SOUND B
SOUND A
GND
PORT
PORT
PORT
PORT
PORT
PORT
PORT
CLOCK
CLOCK
RESET
A8
BDIR
BC2
BC1
D7
D6
D5
D4
D3
D2
D1
D0
YB
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RI
AR
Source: ZX Spectrum FAQ <http://users.ox.ac.uk/~uzdm0006/Damien/speccy/pinouts.html>

PR
EL
IM
IN
Can be found at Sinclair ZX Spectrum's, I think
BETA RELEASE
323
ZX Spectrum ULA Connector
TIO
N.
ZX Spectrum ULA
BU
(At the computer)
Description
/WR
/RD
/WE
A0
A1
A2
A3
A4
A5
A6
/INT
+5V
+5V
U
V
/Y
D0
T0
T1
D1
D2
T2
T3
D3
T4
D4
SOUND
D5
D6
D7
CLOCK
/IO-ULA
/ROM CS
/RAS
A14
A15
/MREQ
Q
Write
Read
Write Enable
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Interrupt
+5 VDC (One of the +5V is decoupled through a RC-low-pass.)
+5 VDC (One of the +5V is decoupled through a RC-low-pass.)
Color-difference signals.
Color-difference signals.
Inverted Video+Sync.
Data 0
Keyboard Data 0
Keyboard Data 1
Data 1
Data 2
Keyboard Data 2
Keyboard Data 3
Data 3
Keyboard Data 4
Data 4
Analog-I/O-line for beep, save and load.
Data 5
Data 6
Data 7
The clock-source to the CPU including the inhibited T-states.
(A0(CPU) OR /IORQ) for the I/O-port FEh
ROM ChipSelect
Row Address Strobe
Address 14
Address 15
???
The 14 MHz crystal. Other side grounded through capacitor.
YB
ET
A
.N
OT
FO
RE
DI
ST
Name
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RI
PR
EL
IM
IN
Can be found at Sinclair ZX Spectrum's, I think

Source: ZX Spectrum FAQ <http://users.ox.ac.uk/~uzdm0006/Damien/speccy/pinouts.html>
BETA RELEASE
324
Spectravideo SVI318/328 Expansion Bus Con
TIO
N.
50 PIN MALE EDGE the computer.

Description
Power, 300mA
Game adapter control signal
Power, 100mA
Power, 50mA
Game adapter control signal
Z80 WAIT
Z80 RST
Buffered 3.58MHz system clock
Buffered Address bus
"
"
"
"
"
"
"
"
"
"
"
"
"
"
"
RAM expansion refresh
Video-CPU write select
Z80 M1
CPU-Video write select
Z80 WR
Z80 MREQ
Z80 IORQ
Z80 RD
Buffered Data Bus
"
"
"
"
"
"
"
Audio input signal
Z80 INT
Disable user RAM
Disable basic ROM
Enable bank 32 Memory (8000-ffff)
Enable bank 31 Memory (0000-7FFF)
Enable bank 22 Memory (8000-FFFF)
Enable bank 21 Memory (0000-7FFF)
System Ground
ET
A
.N
OT
FO
RE
DI
ST
RI
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
YB
Name
+5v
/CNTRL2
+12v
-12v
/CNTRL1
/WAIT
/RST
CPU CLK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
/RFSH
/EXCSR
/M1
/EXCSW
/WR
/MREQ
/IORQ
/RD
D0
D1
D2
D3
D4
D5
D6
D7
CSOUND
/INT
/RAMDIS
/ROMDIS
/BK32
/BK31
/BK22
/BK21
GND
AR
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
BU
(At the computer)
PR
EL
IM
IN
Spectravideo SVI318/328 Expansion Bus
BETA RELEASE
325

50 GND
Spectravideo SVI318/328 Expansion Bus Con
System Ground
TIO
N.

Source: SVI 328 Mk II User Manual
BU
RI
ST
DI
RE
R
FO
OT
.N
ET
A
YB
AR
PR
EL
IM
IN
BETA RELEASE
326
Spectravideo SVI318/328 Game Cartridge Co
TIO
N.
(At the computer)
ET
A
.N
OT
FO
RE
DI
ST
RI
Name
+5v
+5v
A7
A12
A6
A13
A5
A8
A4
A9
A3
A11
A10
A2
A0
A1
D0
D7
D1
D6
D2
D5
D3
D4
CCS3
CCS4
CCS1
CCS2
GND
GND
YB
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BU
AR
Source: SVI 328 mk II user manual

PR
EL
IM
IN
Spectravideo SVI318/328 Game Cartridge
BETA RELEASE
327
MIDI Out Connector
TIO
N.
MIDI Out
(At the cable)
DI
Description
Not connected
Ground
Not connected
Current Sink
Current Source
RE
Name
n/c
GND
n/c
CSINK
CSRC
Pin
1
2
3
4
5
ST

RI
BU
(At the peripheral)
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
MIDI=Musical Instrument Digital Interface.
BETA RELEASE
328
MIDI In Connector
TIO
N.
MIDI In
(At the cable)
DI
Description
Not connected
Not connected
Not connected
Current Source
Current Sink
RE
Name
n/c
n/c
n/c
CSRC
CSINK
Pin
1
2
3
4
5
ST

RI
BU
(At the peripheral)
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
MIDI=Musical Instrument Digital Interface.
BETA RELEASE
329
Minuteman UPS Connector
TIO
N.
Minuteman UPS
BU
(At the UPS)
DI
ST
Description
Unused
Battery power
Unused
Common (same as 7)
Low battery
RS-232 level shutdown
Common (same as 4)
Ground level shutdown (A500 and above, reserved on <A500)
Reserved
RE
Pin
1
2
3
4
5
6
7
8
9
RI
9 PIN D-SUB ??? at the UPS.
FO
Pins 2 and 5 are connected to Common when they are true.

On pin 6, an rs-232 high level (>9V) will shutdown, when running off the battery.
On pin 8, shorting to ground will shutdown.
OT

AR
YB
ET
A
.N
PR
EL
IM
IN
Is the directions right???
BETA RELEASE
330
C64 Power Supply Connector
TIO
N.
C64 Power Supply
BU
(At the computer)

7 PIN DIN 'O' FEMALE at the computer.
DI
ST
RI
Name
Shield Ground
Shield Ground
Shield Ground
nc
+5v In
9Vac in
9Vac in

Source: Commodore 64 Programmers Reference Guide
AR
YB
ET
A
.N
OT
FO
RE
Pin
1
2
3
4
5
6
7
PR
EL
IM
IN
Available at the Commodore 64.
BETA RELEASE
331
Amstrad CPC6128 Stereo Connector
TIO
N.
BU
(At the computer)
RI
(At the cable)
DI
Description
Left Channel
Right Channel
Ground
RE
Pin
L
R
GND
ST
3.5 mm STEREO TELEPHONE FEMALE at the computer.

AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Amstrad CPC6128 Stereo
BETA RELEASE
332
TIO
N.
BU
DI
ST
RI
Connector Top 10 Menu
RE
This is not exactly 10 entries, but the most common connectors. If you don't find what you
are searching for here, look at the full list.
In/Out:
Video:
AR
YB
- VGA (15)
- VGA (9)
- Amiga Video
FO
ET
A
.N
- Serial (PC 9)
- Serial (PC 25)
- Parallel (PC)
- Centronics Printer
OT
- ISA - (Technical)
- EISA - (Technical)
- PCI - (Technical)
- VESA LocalBus (VLB) - (Technical)
Buses:
Joystick/Mouse:
- Gameport (PC)
- Mouse/Joy (Amiga)
PR
EL
IM
IN
Chapter 2
Diskdrive:
- Internal Diskdrive
Keyboard:
- Keyboard (5 PC)
- Keyboard (6 PC)
Data storage interfaces:

- SCSI Internal
BETA RELEASE
333
Chapter 2: Connector Top 10 Menu
TIO
N.
Memories:
BU
- SIMM 30-pin
- SIMM 72-pin
RI
Home audio/video:
ST
- SCART
Networking:
DI
- Ethernet 10Base-T
RE
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
- SCSI External Centronics 50

- SCSI External (Amiga/Mac)
- IDE Internal
- ATA Internal
BETA RELEASE
334
TIO
N.
BU
DI
ST
RI
Cable Menu
RE
Nullmodem:
FO
- Nullmodem (9p to 9p)

- Mac to C64 Nullmodem
ET
A
.N
- Modem (9p to 25p)

- Modem (25p to 25p)
- Two-Wire Modem (9p to 25p)
- Two-Wire Modem (25p to 25p)
- Macintosh Modem (With DTR)
- Macintosh Modem (Without DTR)
- RocketPort Serial (25) Cable
- Modem (9p to 15p)
OT
Modem:
YB
Printer:
Parallel:
AR
- Centronics Printercable
- Serial Printer (9p to 25p)
- Serial Printer (25p to 25p)
- C64 Centronics Printer
PR
EL
IM
IN
Chapter 3
- LapLink/InterLink Parallel
- ParNet Parallel
- 64NET
- GEOCable
Misc Serial:
- Cisco Console (9p)

- Cisco Console (25p)
- Conrad Electronics MM3610D (9p)
- Conrad Electronics MM3610D (25p)
BETA RELEASE
335
Chapter 3: Cable Menu
TIO
N.
- Mac to HP48
RI
BU
- Parallel Port Loopback (Norton)

- Parallel Port Loopback (CheckIt)
- Serial Port Loopback (9p Norton)
- Serial Port Loopback (25p Norton)
- Serial Port Loopback (9p CheckIt)
- Serial Port Loopback (25p CheckIt)
Data storage:
TV/Video/Monitor:
.N
OT
FO
- Video to TV SCART cable

- Amiga to SCART cable
- 9 to 15 pin VGA cable
- Amiga to C1084 Monitor cable
- C128/C64C to CBM 1902A Monitor cable
- C128/C64C to SCART (S-Video) cable
- NeoGeo to SCART cable
RE
DI
ST
- Floppy cable
- IDE cable
- SCSI cable (Amiga/Mac)
- SCSI Cable (D-Sub to Hi D-Sub)
- ST506/412 cable
- ESDI cable
- Paravision SX1 to IDE
ET
A
Networking:
YB
- Ethernet 10/100Base-T Crossover cable

- Ethernet 10/100Base-T Straight Thru cable
- Ethernet 100Base-T4 Crossover cable
Misc:
AR
- ParaLoad cable
- X1541 cable
- MIDI cable
- Misc unsupported cables
PR
EL
IM
IN
Loopback plugs:

BETA RELEASE
336
Short tutorial
First at each page there a short heading describing the cable.
BU
ST
RI
or how it looks.
DI
(To the computer)
RE
picture:
FO
(To the computer)
.N
OT
a female connector and the send a male. The texts insde parentheses will tell you at which
kind of the device it will look like that.
YB
ET
A
(To the Computer)
(To the Printer)
AR
physical connector.
25 PIN D-SUB MALE to the Computer
36 PIN CENTRONICS MALE to the Printer.
PR
EL
IM
IN
Heading
TIO
N.
Cable Tutorial
Pin table
Contains mostly the following three columns; Name, Pin 1, Pin 2. Sometimes when not the
same pin is connected to each side there is another column describing the name at
connector 2.
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
25-DSub
1
2
3
4
36-Cen
1
2
3
4
BETA RELEASE
337
5
6
7
8
9
...
5
6
7
8
9
...
TIO
N.
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
...
Cable Tutorial
BU
RI
ST
AR
YB
ET
A
.N
OT
FO
RE
DI
PR
EL
IM
IN
BETA RELEASE
338
Nullmodem (9-9) Cable
TIO
N.
RI
BU
(To Computer 1).
9 PIN D-SUB FEMALE to Computer 1.

Transmit Data
Receive Data
Data Set Ready + Carrier Detect
System Ground
Data Terminal Ready
Clear to Send
Request to Send
RE
D-Sub 2
3
2
6+1
5
4
8
7
D-Sub 1
2
3
4
5
6+1
7
8
FO
Receive Data
Transmit Data
Data Terminal Ready
System Ground
Request to Send
Clear to Send
DI
ST
(To Computer 2).
OT
Note: DSR & CD are jumpered to fool the programs to think that they are online.
Source: ?
AR
YB
ET
A
.N

, Drew Sullivan <drew@ss.org>, Niklas Edmundsson
<nikke@ing.umu.se>, Don Rifkin <Don.Rifkin@mci.com>
PR
EL
IM
IN
Use this cable between two DTE devices (for instance two computers).
BETA RELEASE
339
TIO
N.
RI
BU
(To Computer 1).
ST
(To Computer 2).
Transmit Data
Receive Data
System Ground
Data Terminal Ready
Clear to Send
Request to Send
RE
D-Sub 25
2
3
6+8
7
20
5
4
D-Sub 9
2
3
4
5
6+1
7
8
FO
Receive Data
Transmit Data
Data Terminal Ready
System Ground
Request to Send
Clear to Send
DI

OT
Contributor: Joakim gren, Drew Sullivan <drew@ss.org>, Niklas Edmundsson <nikke@ing.umu.se>, Don
Rifkin <Don.Rifkin@mci.com>
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
BETA RELEASE
340
TIO
N.
RI
BU
(To Computer 1).

Transmit Data
Receive Data
System Ground
Data Terminal Ready
Clear to Send
Request to Send
RE
D-Sub 2
2
3
6+8
7
20
5
4
D-Sub 1
3
2
20
7
6+8
4
5
FO
Receive Data
Transmit Data
Data Terminal Ready
System Ground
Request to Send
Clear to Send
DI
ST
(To Computer 2).
OT
Contributor: Joakim gren, Drew Sullivan <drew@ss.org>, Niklas Edmundsson

<nikke@ing.umu.se>, Don Rifkin <Don.Rifkin@mci.com>, Richard Marker
<richmarker@aol.com>
AR
YB
ET
A
.N
Source: ?
PR
EL
IM
IN
BETA RELEASE
341
Mac to C64 Nullmodem Cable
TIO
N.
BU
ST
RI
(At the Computer)
(To the C64).
RE
C64
1+12+A+N
M
B+C
D+E
GND
TXD (PA2)
RXD (FLAG2+PB0)
RTS+DTR (PB1+PB2)
Mac
GND+RXD- 4+5
RXD+
8
TXD+
6
DI
8 PIN MINI-DIN MALE to the Macintosh.

DZM 12 DREH to the C64 UserPort.
FO
Contributor: Joakim gren, Pierre Olivier <olipie@aei.ca>
Source: Usenet posting in comp.sys.cbm, A very simple C64 to Macintosh serial cable
<http://stekt.oulu.fi/~jopi/electronics/cbm/C64_to_mac> by Chris Baird <c8923075@cs.newcastle.edu.au>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
The RS-232 standard on the C64 is a little bit strange. It uses inverted TTL level for the
signals. The RS-422 ports on the Macintosh has both an inverted and non-inverted input. By
using the inverted instead of non-inverted the inverted C64 level is back to normal.
BETA RELEASE
342
Modem (9-25) Cable
TIO
N.
Modem (9-25) Cable
BU
RI
(To Computer).
ST
(To Modem).
RE
R
FO
Female Male Dir

1
3
2
2
3
7
4
8
5
6
6
5
7
1
8
4
20
9
22
OT
Shield
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
Data Terminal Ready
Ring Indicator
DI
9 PIN D-SUB FEMALE to the Computer

25 PIN D-SUB MALE to the Modem
Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Sren Graversen <graver@post1.tele.dk>
PR
EL
IM
IN
This cable should be used for DTE to DCE (for instance computer to modem) connections
with hardware handshaking.
BETA RELEASE
343
Modem (25-25) Cable
TIO
N.
Modem (25-25) Cable
BU
RI
(To Computer).
ST
(To Modem).
RE
R
Male Dir
1
2
3
4
5
6
7
8
20
22
FO
Female
1
2
3
4
5
6
7
8
20
22
OT
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
System Ground
Carrier Detect
Data Terminal Ready
Ring Indicator
DI

Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Sren Graversen <graver@post1.tele.dk>
PR
EL
IM
IN
with hardware handshaking.
BETA RELEASE
344
Two-Wire Modem (9-25) Cable
TIO
N.
BU
RI
(To Computer).
ST
(To Modem).
Jumper these:
Request to Send
Clear to Send
7
8
RE
Female Male Dir

1
3
2
2
3
5
7
FO
Shield Ground
Transmit Data
Receive Data
System Ground
DI

.N
OT
Data Set Ready

6
Carrier Detect
1
Data Terminal Ready 4
4
5
Data Set Ready

Carrier Detect
Data Terminal Ready
6
8
20
YB
ET
A
Request to Send
Clear to Send
Source: ?
AR
PR
EL
IM
IN
without hardware handshaking.
BETA RELEASE
345
TIO
N.
BU
RI
(To Computer).
ST
(To Modem).
Jumper these:
Request to Send
Clear to Send
4
5
Male Dir
1
2
3
7
RE
Female
1
2
3
7
FO
Shield Ground
Transmit Data
Receive Data
System Ground
DI

.N
OT
Data Set Ready

6
Carrier Detect
8
Data Terminal Ready 20
4
5
Data Set Ready

Carrier Detect
Data Terminal Ready
6
8
20
YB
ET
A
Request to Send
Clear to Send
Source: ?
AR
PR
EL
IM
IN
without hardware handshaking.
BETA RELEASE
346
Macintosh Modem (With DTR) Cable
TIO
N.
BU
RI
(At the Computer)
ST
(To the Modem).
RE
Modem
4+20 RTS+DTR
5
CTS
2
TxD
3
RxD
7
GND
8
DCD
Mac Dir
1
2
3
5
4+8 5
FO
HSKo
HSKi
TxDRxDGND+RxD+
GPi
DI
8 PIN MINI-DIN MALE to the Computer.

OT
Source: comp.sys.mac.comm FAQ Part 1

AR
YB
ET
A
.N
PR
EL
IM
IN
with DTR.
BETA RELEASE
347
Macintosh Modem (Without DTR) Cable
TIO
N.
BU
RI
(At the Computer)

Modem
4
RTS
5
CTS
2
TxD
3
RxD
7
GND
6+20 DSR+DTR
RE
Dir
Mac
1
2
3
5
4+8
FO
HSKo
HSKi
TxDRxDGND+RxD+
DI
ST
(To the Modem).
OT
Source: comp.sys.mac.comm FAQ Part 1

AR
YB
ET
A
.N
PR
EL
IM
IN
without DTR.
BETA RELEASE
348
RocketPort Serial (25) Cable
TIO
N.
BU
RI
(To the modem).
D-Sub Dir
4
20
7
2
3
8
6
5
FO
RJ45
1
2
3
3
6
6
7
8
OT
Description
Request To Send
Data Terminal Ready
Ground
Tranceive Data
Receive Data
Data Carrier Detect
Data Set Ready
Clear To Send
RE
RJ45 MALE CONNECTOR to the RocketPort card.

25 PIN D-SUB MALE to the modem
DI
ST
(To the RocketPort card)
Source: ?
AR
YB
ET
A
.N
Contributor: Joakim gren, Karl Asha <karl@blackdown.com>
PR
EL
IM
IN
Use this cable to connect a RocketPort serialport card to a modem.
BETA RELEASE
349
Modem (9-15) Cable
TIO
N.
Modem (9-15) Cable
RI
BU
(To Computer).
ST
(At the modem)
RE
R
9 pin 15 pin Dir

1
11
2
13
3
12
4
10
5
1+8+15
6
3
7
4
8
5
9
6
FO
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
System Ground
Data Set Ready
Request to Send
Clear to Send
Ring Indicator
DI

15 PIN FEMALE ??? to the modem.
OT
Contributor: Joakim gren, Joerg Brinkel <jb@itm.rwth-aachen.de>

Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
This cable should be used to connect an internal 14.4kbps Speedster modem to a computer.
BETA RELEASE
350
Printer Cable
TIO
N.
BU
(To the Computer)
DI
RE
R
FO
ET
A
.N
OT
36-Cen
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
36
33
19,20
21,22
23,24
25,26
27
28,29
30,16
Shield+17
YB
25-DSub
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Shield
AR
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper Out
Select
Autofeed
Error
Reset
Select
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Signal Ground
Shield
ST

RI
(To the Printer)

Source: ?
PR
EL
IM
IN
Printer Cable
BETA RELEASE
351
Serial Printer (9-25) Cable
TIO
N.
RI
BU
(To Computer).
ST
(To Printer).
D-Sub 2
3
Transmit Data
2
Receive Data
20
Data Terminal Ready
RE
D-Sub 1
3
2
8+6
1+4
5
Ground
Receive Data
Transmit Data
Clear To Send + Data Set Ready
Carrier Detect + Data Terminal Ready
Ground
DI
9 PIN D-SUB FEMALE to Computer.

25 PIN D-SUB FEMALE to Printer.
FO

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Use this cable between two a computer (DTE) and a printer (DTE) devices.
BETA RELEASE
352
TIO
N.
RI
BU
(To Computer).
ST
(To Printer).
D-Sub 2
3
Transmit Data
2
Receive Data
20
Data Terminal Ready
RE
D-Sub 1
2
3
5+6
8 + 20
7
Ground
Receive Data
Transmit Data
Clear To Send + Data Set Ready
Carrier Detect + Data Terminal Ready
Ground
DI

25 PIN D-SUB FEMALE to Printer.
FO

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Use this cable between two a computer (DTE) and a printer (DTE) devices.
BETA RELEASE
353
C64 Centronics Printer Cable
TIO
N.
RE
.N
Ground
Acknowledge
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Strobe
Initialize Printer
Printer
19-30,33
10
2
3
4
5
6
7
8
9
1
31
FO
C64
Dir
1,12,A,N
B
C
D
E
F
H
J
K
L
M
3
OT
GND
FLAG2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA2
GND
ST

DI
(To the Printer)
RI
BU
(To the C64).
ET
A
Source: CBM Memorial Page Pinouts <http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt>, pinout by

Roy Kannady <kannady@pogo.den.mmc.com>
AR
YB
PR
EL
IM
IN
Requires a cartridge with Centronics support (TFCIII or ActionReplay.)
BETA RELEASE
354
LapLink/InterLink Parallel Cable
TIO
N.
RI
DI
ST
(To Computer 1).
RE
(To Computer 2).
FO
OT
YB
Source: ?
Name
Error
Select
Paper Out
Acknowledge
Busy
Data Bit 3
Data Bit 4
Data Bit 2
Data Bit 1
Data Bit 0
Reset
Select
Signal Ground
.N
Pin
15
13
12
10
11
5
6
4
3
2
16
17
25
ET
A
Pin
2
3
4
5
6
10
11
12
13
15
16
17
25
25 PIN D-SUB MALE to Computer 1.

Name
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Acknowledge
Busy
Paper Out
Select
Error
Reset
Select
Signal Ground
BU
Will work with:

- LapLink from Travelling Software
- MS-DOS v6.0 InterLink from Microsoft
- Windows 95 Direct Cable connection from Microsoft
- Norton Commander v4.0 & v5.0 from Symantec
AR
PR
EL
IM
IN
BETA RELEASE
355
ParNet Parallel Cable
TIO
N.
BU
(To Computer 1).
RI
(To Computer 2).
RE
DI
Name
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge + Select
Busy
Paper Out
Signal Ground
Pin
2
3
4
5
6
7
8
9
10+13
11
12
17-25
FO
Pin
2
3
4
5
6
7
8
9
10+13
11
12
17-25
OT
Name
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge + Select
Busy
Paper Out
Signal Ground
ST

AR
YB
ET
A
.N
Source: ?
PR
EL
IM
IN
BETA RELEASE
356
64NET Cable
TIO
N.
BU
(To C64).
RI
(To PC).
DI
GND
/ACK
BUSY
PE
D3
D4
D5
D6
D7
RE
PC
25
10
11
12
5
6
7
8
9
C64 Dir
A
C
D
E
F
H
J
K
L
FO
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
ST

25 PIN D-SUB MALE to the PC
OT
Source: 64NET v1.82.58 documentation by Paul Gardner-Stephen <gardners@ist.flinders.edu.au>
AR
YB
ET
A
.N
PR
EL
IM
IN
64NET Cable
BETA RELEASE
357
GEOCable Cable
TIO
N.
BU
(To the C64).
RE
DI
Printer
33
Ground
11
Busy
2
Data 1
3
Data 2
4
Data 3
5
Data 4
6
Data 5
7
Data 6
8
Data 7
9
Data 8
1
Strobe
16
Ground
FO
C64
A
B
C
D
E
F
H
J
K
L
M
N
OT
Ground
Flag 2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA2
Ground
ST

36 PIN CENTRONICS MALE at the Printer.
RI
(To the Printer)
AR
YB
ET
A
.N
Source: comp.sys.cbm General FAQ v3.1 Part 7

PR
EL
IM
IN
GEOCable Cable
BETA RELEASE
358
Cisco Console (9) Cable
TIO
N.
ST
RI
BU
(To Computer).
2
8
1
Dir
Male
3
6
7
FO
Female
2
3
4
5
6
7
8
OT
Receive Data
Transmit Data
Data Terminal Ready
Ground (use as shield)
Data Set Ready
Request to Send
Clear to Send
RE

RJ45 MALE CONNECTOR to the Cisco router.
DI
(To the Cisco router)
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
Use this cable to configure a Cisco router thru the Console port at the router.
BETA RELEASE
359
TIO
N.
ST
RI
BU
(To Computer).
6
3
8
1
2
7
Dir
Male
FO
Female
1
2
3
4
5
6
20
OT
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
Data Terminal Ready
RE

RJ45 MALE CONNECTOR to the Cisco router.
DI
(To the Cisco router)
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
Use this cable to configure a Cisco router thru the Console port at the router.
BETA RELEASE
360
Conrad Electronics MM3610D Cable
TIO
N.
Conrad Electronics MM3610D (9) Cable
RI
BU
(To PC).
Conrad Dir
1
2
3
4
5
RE
PC
7
2
3
4
5
Request To Send
Receive Data
Transmit Data
Data Terminal Ready
Ground
DI
9 PIN D-SUB FEMALE to PC.

5 PIN UNKNOWN CONNECTOR to the multimeter
ST
(To multimeter).
FO
Contributor: Joakim gren, Anselm Belz <a.belz@samson.mbis.de>

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Use this cable to connect a Conrad Electronics Multimeter 3610D to a PC:s serialport.
BETA RELEASE
361
Conrad Electronics MM3610D Cable
TIO
N.
RI
BU
(To PC).
Conrad Dir
1
2
3
4
5
RE
PC
4
3
2
20
7
Request To Send
Receive Data
Transmit Data
Data Terminal Ready
Ground
DI
25 PIN D-SUB FEMALE to PC.

5 PIN UNKNOWN CONNECTOR to the multimeter
ST
(To multimeter).
FO
Contributor: Joakim gren, Anselm Belz <a.belz@samson.mbis.de>

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Use this cable to connect a Conrad Electronics Multimeter 3610D to a PC:s serialport.
BETA RELEASE
362
Mac to HP48 Cable
TIO
N.
BU
(At the Computer)
RI
(To the HP48).
RxD
TxD
GND
Shield
DI
Mac
HP48
3
5
4+8
SHIELD SHIELD
RE
TxDRxDGND+RxD+
Shield
ST

4 PIN ??? FEMALE to the HP48
FO
Sources: Usenet posting in comp.sys.cbm, Mac to C64 Interface

<http://stekt.oulu.fi/~jopi/electronics/cbm/C64_to_mac> by Tomas Moberg <fr94tmg@ing.umu.se>
Sources: Usenet posting in comp.sys.cbm, A very simple C64 to Macintosh serial cable
<http://stekt.oulu.fi/~jopi/electronics/cbm/C64_to_mac> by Chris Baird <c8923075@cs.newcastle.edu.au>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Mac to HP48 Cable
BETA RELEASE
363
Parallel Port Loopback (Norton)
TIO
N.
BU
(To Computer).
Pin
15
13
12
10
11
Name
Error
Select
Paper Out
Acknowledge
Busy
ST
Pin
2
3
4
5
6
DI
Name
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
RI
25 PIN D-SUB MALE to Computer.
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Used to verify that a port is working. This one works with Norton Utilities: Norton Diagnostics
from Symantec.
BETA RELEASE
364
Parallel Port Loopback (CheckIt)
BU
(To Computer).
Pin
17
16
14
1
15
Name
Select Input
Initialize
Auto Feed
Strobe
Error
ST
Pin
11
10
12
13
2
DI
Name
Busy
Acknowledge
Paper end
Select
Data Bit 0
RI
25 PIN D-SUB MALE to Computer.
RE
Contributor: Joakim gren, "Coolsys" <coolsys@geocities.com>

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Used to verify that a port is working. This one works with CheckIt.
TIO
N.
BETA RELEASE
365
Serial Port Loopback (9 Norton)
TIO
N.
BU
(To Computer).
Pin Pin
3
8
4 6
Pin
ST
Pin
2
7
1
DI
Name
Jumpering 1
Jumpering 2
Jumpering 3
RI
RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
from Symantec.
BETA RELEASE
366
TIO
N.
BU
(To Computer).
Pin Pin
3
5
8 20
Pin
ST
Pin
2
4
6
22
DI
Name
Jumpering 1
Jumpering 2
Jumpering 3
RI
RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
from Symantec.
BETA RELEASE
367
Serial Port Loopback (9 CheckIt)
BU
(To Computer).
Pin
6
9
3
6
8
Name
DSR
RI
TXD
DSR
CTS
ST
Pin
1
1
2
4
7
DI
Name
CD
CD
RXD
DTR
RTS
RI
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
TIO
N.
BETA RELEASE
368
BU
(To Computer).
Pin
2
4
6
Pin Pin
3
5
8 20
Pin
22
DI
ST
Name
Jumpering 1
Jumpering 2
Jumpering 3
RI
Source: ?
AR
YB
ET
A
.N
OT
FO
RE
PR
EL
IM
IN
TIO
N.
BETA RELEASE
369
Floppy Cable
TIO
N.
RE
DI
ST
RI
Controller
Drive 2
Twist
Drive 1
+--+
+--+
+--+
|::|===================| |============| | <-Pin 1
|::|===================| |=====\/=====| |
|::|===================| |=====/\=====| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
+--+
+--+
+--+
BU
The original floppy cable required that each drive was jumpered to the right ID. But IBM
come up with an idea to avoid jumpering the floppies.
If wire 10-16 are twisted before the last connector the jumpering is avoided. Each drive
should be jumpered to act as Drive 2. If only one drive is used then leave the middle
connector free.
The IDC could also be an edge connector on some old drives.
FO
(To the Controller)
OT
(To the Drive 2)
(To the Drive 1)
YB
ControllerDrive 1 Drive 2
1-9
1-9
1-9
10
16
10
11
15
11
12
14
12
13
13
13
14
12
14
15
11
15
16
10
16
17-34
17-34 17-34
AR
Wire 1-9
Wire 10
Wire 11
Wire 12
Wire 13
Wire 14
Wire 15
Wire 16
Wire 17-34
ET
A
.N
34 PIN IDC FEMALE to the Controller.

34 PIN IDC FEMALE to the Drive 2.
PR
EL
IM
IN
Floppy Cable
Source: TheRef TechTalk <http://theref.c3d.rl.af.mil>

BETA RELEASE
370
IDE Cable
TIO
N.
RE
DI
ST
RI
Controller
Drive 1 or 2
Drive 1 or 2
+--+
+--+
+--+
|::|===================|::|============|::| <-Pin 1
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
|::|===================|::|============|::|
+--+
+--+
+--+
BU
The IDE interface requires only one cable. All pins straight from 1 to 1, 2 to 2 and so on. The
drives can be connected in any order. Only remember that one should be jumpered as
Master and the other as Slave. If only one drive is used, jumper it as Single (if such a mode
exists, or most common Master else).
(To the Controller)
FO
(To the Drive 1)
OT
(To the Drive 2)
.N


Source: ?
ET
A
Wire 1-40 1-40
1-40
1-40
AR
YB
PR
EL
IM
IN
IDE Cable
BETA RELEASE
371
SCSI Cable (Amiga/Mac)
TIO
N.
BU
(To the Amiga/Mac).
RI
(To the peripheral).
DI
RE
R
FO
OT
IDC
48
42
50
40
38
36
2
8
12
14
16
46
32
44
18
4
6
10
26
.N
DSub
1
2
3
4
5
6
8
10
11
12
13
15
17
19
20
21
22
23
25
ET
A
Request
Message
Input/Output
Reset
Acknowledge
Busy
Data Bus 0
Data Bus 3
Data Bus 5
Data Bus 6
Data Bus 7
Control/Data
Attention
Select
Data Parity
Data Bus 1
Data Bus 2
Data Bus 4
Termination Power
ST
25 PIN D-SUB FEMALE to the Amiga/Mac.

50 PIN IDC FEMALE to the peripheral.
Note: All the other pins (7+9+14+16+18+24) at the DSub should be connected to the all odd
pins except 25 at the IDC connector.
YB

Source: ?
AR
PR
EL
IM
IN
BETA RELEASE
372
SCSI Cable (D-Sub to Hi D-Sub)
TIO
N.
BU
(To the Amiga/Mac).
ST
RE
R
FO
OT
Hi DSub
49
46
50
45
44
43
26
29
31
32
33
48
41
47
34
27
28
30
38
.N
DSub
1
2
3
4
5
6
8
10
11
12
13
15
17
19
20
21
22
23
25
ET
A
Request
Message
Input/Output
Reset
Acknowledge
Busy
Data Bus 0
Data Bus 3
Data Bus 5
Data Bus 6
Data Bus 7
Control/Data
Attention
Select
Data Parity
Data Bus 1
Data Bus 2
Data Bus 4
Termination Power
DI
25 PIN D-SUB MALE to the Amiga/Mac.

50 PIN HI-DENSITY D-SUB MALE to the peripheral.
RI
(To the peripheral).
Note: All the other pins (7+9+14+16+18+24) at the DSub should be connected to pins 1-25
at the Hi-density D-Sub connector.
YB

Source: ?
AR
PR
EL
IM
IN
BETA RELEASE
373
ST506/412 Cable
TIO
N.
ST
RI
Controller
Drive 2
Twist
Drive 1
+--+
+--+
+--+
|::|===================| |============| | <-Pin 1
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |=====\/=====| |
|::|===================| |=====/\=====| |
|::|===================| |============| |
+--+
+--+
+--+
BU
The ST506/412 interface requires two cables, one for control and one for data. The control
cable is shared between the two drives. But each drive has each own data cable. By twisting
some wires on the control cable it won't be necessary to set the ID for each drive, since the
twist will do the job. Wires 25 to 29 should be twisted between drive 1 & drive 2.
RE
DI
Control cable
FO
(To the Controller)
OT
(To the Drive 2)
(To the Drive 1)
YB
1-9
1-9
1-9
25
29
25
26
28
26
27
27
27
28
26
28
29
25
29
30-34
30-34 30-34
Data cable
AR
Wire 1-24
Wire 25
Wire 26
Wire 27
Wire 28
Wire 29
Wire 30-34
ET
A
.N

PR
EL
IM
IN
ST506/412 Cable
(To the Controller)
(To the Drive)

20 PIN IDC FEMALE to the Drive.
BETA RELEASE
374

Drive
1-20
TIO
N.
Controller
Wire 1-20 1-20
ST506/412 Cable
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
RI
BU
PR
EL
IM
IN
BETA RELEASE
375
ESDI Cable
TIO
N.
ST
RI
Controller
Drive 2
Twist
Drive 1
+--+
+--+
+--+
|::|===================| |============| | <-Pin 1
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |============| |
|::|===================| |=====\/=====| |
|::|===================| |=====/\=====| |
|::|===================| |============| |
+--+
+--+
+--+
BU
The ESDI interface requires two cables, one for control and one for data. The control cable
is shared between the two drives. But each drive has each own data cable. By twisting some
wires on the control cable it won't be necessary to set the ID for each drive, since the twist
will do the job. Wires 25 to 29 should be twisted between drive 1 & drive 2.
RE
DI
Control cable
FO
(To the Controller)
OT
(To the Drive 2)
(To the Drive 1)
YB
1-9
1-9
1-9
25
29
25
26
28
26
27
27
27
28
26
28
29
25
29
30-34
30-34 30-34
Data cable
AR
Wire 1-24
Wire 25
Wire 26
Wire 27
Wire 28
Wire 29
Wire 30-34
ET
A
.N

PR
EL
IM
IN
ESDI Cable
(To the Controller)
(To the Drive)

20 PIN IDC FEMALE to the Drive.
ControllerDrive
BETA RELEASE
376
YB
AR
PR
EL
IM
IN
OT
.N
ET
A
R
FO
RE
ST
DI
Wire 1-20 1-20

TIO
N.
BU
RI

ESDI Cable
1-20
BETA RELEASE
377
Paravision SX1 to IDE Cable
TIO
N.
BU
RI
(To the controller)
ST
(To the Harddrive)
RE
R
FO
OT
.N
ET
A
IDC
1
17
13
9
5
2
4
8
12
16
19
22
24
26
n/c
n/c
30
21
22
23
24
40
26
27
28
29
23
25
31
36
33
35
38
37
YB
D-Sub
1
2
3
4
5
6
7
8
9
10
11+12
13+14
15+16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
AR
Description
Drive Reset
Data bit 0
Data bit 2
Data bit 4
Data bit 6
Ground
Data bit 8
Data bit 10
Data bit 12
Data bit 14
Ground
Ground
Ground
Ground
5V Power
5V Power
Ground
Data bit 1
Data bit 3
Data bit 5
Data bit 7
Ground
Data bit 9
Data bit 11
Data bit 13
Data bit 15
I/O Write
I/O Read
Interrupt Request
Address bit 2
Address bit 1
Address bit 0
Chip Select 1
Chip Select 0
DI
37 PIN D-SUB FEMALE to the controller.

40 PIN IDC FEMALE to the harddisk.
PR
EL
IM
IN
Can be used to connect a normal IDE harddisk to the Paravision SX1. Paravision was earlier
known as Microbotics.
Note: Pin 18+19 (+5V) can be used to power the harddisk. But most harddisks require both
+5V and +12V.
Source: ?
BETA RELEASE
378
Video to TV SCART Cable
TIO
N.
BU
(To the TV)
RI
(To the Video Recorder)
ST
21 PIN SCART MALE to the TV.

21 PIN SCART MALE to the Video Recorder.
TV
1
2
3
6
4
VCR
2
1
6
3
4
Audio Right In
Audio Right Out
Audio Left In
Audio Left Out
Audio Ground
Red
Red Ground
Green
Green Ground
Blue
Blue Ground
15
13
11
9
7
5
15
13
11
9
7
5
Red
Red Ground
Green
Green Ground
Blue
Blue Ground
Status / 16:9
Reserved
Reserved
Fast Blanking Ground
Fast Blanking
Video Out Ground
Video In Ground
Video Out
Video In Ground
Ground
8
10
12
14
16
17
18
19
20
21
8
10
12
14
16
18
17
20
19
21
Status / 16:9
Reserved
Reserved
Fast Blanking Ground
Fast Blanking
Video In Ground
Video Out Ground
Video In
Video Out
Ground
YB
ET
A
.N
OT
FO
RE
DI
Audio Right Out

Audio Right In
Audio Left Out
Audio Left In
Audio Ground

Source: ?
AR
PR
EL
IM
IN
Video to TV SCART cable
BETA RELEASE
379
Amiga to SCART Cable
TIO
N.
BU
(To the Amiga)
RI
(To the TV)
RGB Red In
RGB Green In
RGB Blue In
Video In
Video GND
Blanking GND
Blanking (Connect via a 150 Ohm resistor)
Audio/RGB switch (Connect via a 1 kOhm resistor)
Phono Right
Phono Right GND
2
4
Audio IN Right
GND
Phono Left
Phono Left GND
6
4
Audio IN Left
GND
OT
FO
RE
DI
TV
15
11
7
20
17
18
16
8
Analog Red
Analog Green
Analog Blue
Composite Sync
Video GND
GND
+12V
+12V
Amiga
3
4
5
10
17
19
22
22
ST
23 PIN D-SUB FEMALE to the Amiga

21 PIN SCART MALE to the TV
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
Amiga to SCART cable
BETA RELEASE
380
9 to 15 pin VGA Cable
TIO
N.
(To the Monitor)
RE
DI
15-Pin
1
2
3
13
14
6
7
8
10 + 11
9-Pin
1
2
3
4
5
6
7
8
9
FO
Red Video
Green Video
Blue Video
Horizontal Sync
Vertical Sync
Red GND
Green GND
Blue GND
Sync GND
ST

15 PIN HIGHDENSITY D-SUB FEMALE to the Monitor
RI
BU
(To the Computer)
OT
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
9 to 15 pin VGA cable
BETA RELEASE
381
Amiga to C1084 Monitor Cable
TIO
N.
BU
(To the Amiga)
RI
(At the Monitor)
R
G
B
HSYNC
GND
DI
Amiga C1084
3
4
4
1
5
5
10
2
16
3
RE
R
G
B
SYNC
GND
ST
23 PIN D-SUB FEMALE to the Amiga.

6 PIN DIN MALE at the Monitor.
FO
Source: Usenet posting in sfnet.harrastus.elektroniikka, Philips 1084 monarin kytkenta

<http://www.vuse.vanderbilt.edu/~thompsbb/cbm_conn.txt> by Kari Hautanen <kari.hautanen@compart.fi>
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
BETA RELEASE
382
C128/C64C to CBM 1902A Monitor Cable
TIO
N.
BU
(At the Computer)
RI
(At the Monitor)
LUM
CHROMA
GND
AUDIO
DI
ComputerC1902A
1
6
8
4
2
3
3
2
RE
LUM
CHROMA
GND
AOUT
ST
8 PIN DIN (DIN45326) MALE at the Computer.

6 PIN DIN MALE at the Monitor.
Source: cbm.comp.sys General FAQ v3.1 Part 7

AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
383
C128/C64C to SCART (S-Video) Cable
TIO
N.
BU
(To the Computer)
RI
(To the TV)
LUM
CHROMA
GND
AUDIO
DI
ComputerTV
1
20
8
15
2
4+17
3
2+6
RE
LUM
CHROMA
GND
AOUT
ST
8 PIN DIN (DIN45326) MALE at the Computer.

Contributor: Joakim gren, Claudio Brazzale <brzcld@dei.unipd.it>
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
BETA RELEASE
384
NeoGeo to SCART Cable
TIO
N.
BU
(To the Computer)
RI
(To the TV)
Audio In Left+Right
Blanking Signal Ground
Composite Video In
Blanking Signal
RGB Green In
RGB Red In
RGB Blue In
DI
TV
6+2
18
20
16
11
15
7
RE
NeoGeo
1
2
3
4
5
6
8
Audio Out
Ground
Composite Video Out
?
Green
Red
Blue
ST
8 PIN DIN (DIN45326) MALE to the Computer.

FO
Contributor: Joakim gren, Enzo <enzo@gaianet.net>, Steffen Kupfer <Steffen_Kupfer@compuserve.com>

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
BETA RELEASE
385
Ethernet 10/100Base-T Crossover Cable
TIO
N.
BU
RI
(To network interface card 2).
RE
DI
ST
NIC2
3
6
1
2
Name
RX+
RXTX+
TX-
OT
NIC1
1
2
3
6
.N
Name
TX+
TXRX+
RX-
FO
RJ45 MALE CONNECTOR to network interface card 1.

Note 1: It's important that each pair is kept as a pair. TX+ & TX- must be in the pair, and
RX+ & RX- must together in another pair. (Just as the table above shows).
ET
A
Note 2: You could also connect 4-4, 5-5, 7-7, 8-8.

Contributors: Joakim gren, Jim C? <jimc@megalink.net>, Jason D. Pero <JDP6640@ritvax.isc.rit.edu> ,
Oscar Fernandez Sierra <oscar@charpy.etsiig.uniovi.es>, Cayce Balara <CayceB@yardboy.com>, Jeffrey R.
Broido <broidoj@gti.net>, Patrick Smart <Patrick@mail.beon.be>
YB
Source: ?
AR
PR
EL
IM
IN
This cable can be used to cascade hubs, or for connecting two Ethernet stations
back-to-back without a hub. It works with both 10Base-T and 100Base-TX.
BETA RELEASE
386
Ethernet 10/100Base-T Straight Thru Cable
TIO
N.
BU
RI
RE
DI
ST
(To network interface card).
(To hub).
Pin
1
2
3
4
5
6
7
8
Name
TX+
TXRX+
OT
Cable Color
White/Orange
Orange
White/Green
Blue
White/Blue
Green
White/Brown
Brown
.N
RX-
Pin
1
2
3
4
5
6
7
8
RX-
ET
A
Name
TX+
TXRX+
FO
RJ45 MALE CONNECTOR to network interface card).

RJ45 MALE CONNECTOR to hub).
Note: It's important that each pair is kept as a pair. TX+ & TX- must be in the pair, and RX+
& RX- must together in another pair. (Just as the table above shows).
Pins
4&5
1&2
3&6
7&8
Common color
Blue
Orange
Green
Brown
AR
Pair
1
2
3
4
YB
Just for your information, this is how the pairs are named:
The + side of each pair is called the "tip" and the - side is called the "ring", a reference to old
telephone connectors.
PR
EL
IM
IN
This cable will work with both 10Base-T and 100Base-TX and is used to connect a network
interface card to a hub or network outlet. These cables are sometimes called "whips".
Contributor: Joakim gren , Oscar Fernandez Sierra <oscar@charpy.etsiig.uniovi.es>, Jeffrey R. Broido

<broidoj@gti.net>
Source: ?
BETA RELEASE
387
Ethernet 100Base-T4 Crossover Cable
TIO
N.
BU
RI
RE
DI
ST
Name
RX_D2+
RX_D2TX_D1+
TX_D1BI_D4+
BI_D4BI_D3+
BI_D3-
OT
Pin
3
6
1
2
7
8
4
5
.N
Pin
1
2
3
6
4
5
7
8
ET
A
Name
TX_D1+
TX_D1RX_D2+
RX_D2BI_D3+
BI_D3BI_D4+
BI_D4-
FO

Note 1: It's important that each pair is kept as a pair. TX+ & TX- must be in the pair, and
RX+ & RX- must together in another pair etc. (Just as the table above shows).
YB
Contributors: Joakim gren, Kim Scholte <KScholte@BigFoot.Com>

Source: ?
AR
PR
EL
IM
IN
This cable can be used to cascade hubs, or for connecting two Ethernet stations
back-to-back without a hub.
BETA RELEASE
388
ParaLoad Cable
TIO
N.
BU
(To C64).
RI
(To Amiga).
RE
DI
Amiga
17-25 Ground
1
Strobe
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
11
Busy
C64
A
B
C
D
E
F
H
J
K
L
M
FO
Ground
FLAG2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA2
ST
DZM 12 DREH at the C64 UserPort.

25 PIN D-SUB MALE at the Amiga
OT

Source: ParaLoad documentation
AR
YB
ET
A
.N
PR
EL
IM
IN
ParaLoad Cable
BETA RELEASE
389
X1541 Cable
TIO
N.
X1541 Cable
BU
RI
(To the PC).
ST
(To the Diskdrive)
Diskdrive
2
GND
3
ATN
4
CLOCK
5
DATA
6
RESET
RE
PC
18-25
1
14
17
16
GND
STROBE
AUTOFEED
SELECTIN
INIT
DI
25 PIN D-SUB MALE to the PC.

6 PIN DIN (DIN45322) MALE to the Cable
FO
Contributor: Joakim gren, Magnus.Eriksson <magnus.eriksson@mbox309.swipnet.se>

Source: X1541 documentation
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Used to transfer data from a Commodore 1541/1581 diskdrive to a PC. The X1541 software
is written by Leopoldo Ghielmetti <GHIELMET@eldi.epfl.ch>.
BETA RELEASE
390
MIDI Cable
TIO
N.
BU
(To the 1st peripheral)
DI
2nd
2
4
5
RE
1st
Shield
2
Current Source 4
Current Sink
5
ST
5 PIN DIN 180 (DIN41524) MALE to the 1st peripheral.

5 PIN DIN 180 (DIN41524) MALE to the 1st peripheral.
RI
(To the 2nd peripheral)
Note: Although that pin 2 only is connected at MIDI Out it's simpler to connect it to both ends.
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
MIDI Cable
BETA RELEASE
391
Misc Unsupported Cables
TIO
N.
Misc unsupported Cables
BU
Amiga to IBM RGBI Cable
ST
RI
(To the Monitor).
(To the Amiga).
RE
Comment
(Via 2 Hex Inverters, i.e 74LS04)

(Power for the IC)
FO
23 Pin
16
16
9
8
9
6
11
12
23
OT
9 Pin
1
2
3
4
5
6
8
9
.N
Ground
Ground
Digital Red
Digital Green
Digital Blue
Digital Intensity
Horizontal Sync
Verical Sync
+5V
DI
9 PIN D-SUB ?? to the Monitor.

23 PIN D-SUB FEMALE to the Amiga.
ET
A
C128 80 columns to 1702 monitor Cable
YB
(To the C128).
AR
(To the C1702).

9 PIN D-SUB MALE to the C128.
PHONO MALE to the Monitor.
PR
EL
IM
IN
These cables may or may not be correctly constructed. Handle with care.
C128 C1702
Ground
1
1
Ground
Monochrome out 7
2
Signal
Source: Gordon <GAJ2@psuvm.psu.edu>
BETA RELEASE
392
TIO
N.
BU
DI
ST
RI
Adapter Menu
RE
What does the information that is listed for each adapter mean? See the tutorial.
Serial:
FO
- Nullmodem adapter
- 9p to 25p Serial adapter
Parallel:
OT
- Centronics to LapLink adapter
Keyboard:
ET
A
.N
- Mini-DIN to DIN Keyboard adapter

- DIN to Mini-DIN Keyboard adapter
- PS/2 Keyboard (Gateway) Y Adapter
- PS/2 Keyboard (IBM Thinkpad) Y Adapter
Mouse:
YB
- PS/2 to Serial Mouse Adapter

- Serial to PS/2 Mouse Adapter
Joysticks:
Video:
AR
- Amiga 4 Joysticks adapter

- PC 2 Joysticks adapter
PR
EL
IM
IN
Chapter 4
- Macintosh Video to VGA Adapter
Misc:
- A1000 to Amiga Parallel adapter

BETA RELEASE
393
Chapter 4: Adapter Menu
Short tutorial
First at each page there a short heading describing the adapter.
BU
ST
RI
After that there is at each page there is one or more pictures of the connectors, usually
there's two connectors. Sometimes there is some question marks only. This means that I
don't know what kind of connector it is or how it looks.
DI
(To the computer)
RE
picture:
FO
(To the computer)
.N
OT
a female connector and the send a male. The texts inside parentheses will tell you at which
ET
A
(To the Computer).
YB
(To the Serialcable).
AR
physical connector.
9 PIN D-SUB FEMALE to the Computer.
25 PIN D-SUB MALE to the Serialcable.
PR
EL
IM
IN
Heading
TIO
N.
Adapter Tutorial
Pin table
The pin table is perhaps the information you are looking for. It should be quite simple to read.
Contains mostly the following three columns; Name, Pin 1, Pin 2. Sometimes when not the
same pin is connected to each side there is another column describing the name at
connector 2.
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
9-Pin
1
2
3
4
25-Pin
8
3
2
20
BETA RELEASE
394

7
6
4
5
22
TIO
N.
5
6
7
8
9
RI
BU
AR
YB
ET
A
.N
OT
FO
RE
DI
ST
PR
EL
IM
IN
System Ground
Data Set Ready
Request to Send
Clear to Send
Ring Indicator
Adapter Tutorial
BETA RELEASE
395
Nullmodem Adapter
TIO
N.
Nullmodem Adapter
RI
BU
(To the Computer).
ST
Shield Ground
Receive Data
Transmit Data
Clear to Send
Request to Send
Data Terminal Ready
Data Set Ready
Ground
OT
Source: ?
RE
Male
1
3
2
5
4
20
6
7
Female
1
2
3
4
5
6
20
7
FO
Shield Ground
Transmit Data
Receive Data
Request to Send
Clear to Send
Data Set Ready
Data Terminal Ready
Ground
DI

AR
YB
ET
A
.N
PR
EL
IM
IN
This adapter will enable you to use a normal serialcable as a nullmodem.
BETA RELEASE
396
9 to 25 Serial Adapter
TIO
N.
BU
RI
(To the Computer).
ST
RE
AR
YB
ET
A
.N
Source: ?
25-Pin
8
3
2
20
7
6
4
5
22
FO
9-Pin
1
2
3
4
5
6
7
8
9
OT
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
System Ground
Data Set Ready
Request to Send
Clear to Send
Ring Indicator
DI

PR
EL
IM
IN
This adapter will enable you to connect a 25 pin serialcable to a 9 pin connector at the
computer.
BETA RELEASE
397
Centronics to LapLink Adapter
TIO
N.
(To the Computer)
BU
RE
Name
Error
Select
Paper Out
Acknowledge
Busy
Data Bit 3
Data Bit 4
Data Bit 2
Data Bit 1
Data Bit 0
Reset
Select
Signal Ground
FO
25-DSub
15
13
12
10
11
5
6
4
3
2
16
17
18-25
OT
36-Cen
2
3
4
5
6
10
11
12
13
32
16
17
19-30+33
.N
Name
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Acknowledge
Busy
Paper Out
Select
Error
Reset
Select
Signal Ground
DI
36 PIN CENTRONICS FEMALE to the Printer cable.

25 PIN D-SUB MALE to the Computer.
ST
RI
(To the Printer cable)
ET
A
Source: ?
AR
YB
PR
EL
IM
IN
This adapter will allow you to use a normal printercable (Centronics) as a LapLink/InterLink
cable.
BETA RELEASE
398
Mini-DIN to DIN Keyboard Adapter
TIO
N.
BU
RI
(To the keyboard)
ST
(To the computer)
RE
Mini-DIN DIN
Shield
Shield
1
2
3
4
4
5
5
1
Shield
Data
Ground
+5 VDC
Clock
DI
6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the keyboard.

5 PIN DIN 180 (DIN41524) MALE to the computer.
FO

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
This adapter will enable you to use a keyboard with a 6 pin Mini-DIN connector to a
computer with a 5 pin DIN connector.
BETA RELEASE
399
DIN to Mini-DIN Keyboard Adapter
TIO
N.
BU
RI
(To the keyboard)
Mini-DIN
Shield
5
1
3
4
RE
DIN
Shield
1
2
4
5
Shield
Clock
Data
Ground
+5 VDC
DI
5 PIN DIN 180 (DIN41524) FEMALE to the keyboard.

6 PIN MINI-DIN MALE (PS/2 STYLE) to the computer.
ST
(To the computer)
FO

Source: ?
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
This adapter will enable you to use a keyboard with a 5 pin DIN connector to a computer
with a 6 pin Mini-DIN connector.
BETA RELEASE
400
PS/2 Keyboard (Gateway) Y Adapter
TIO
N.
BU
RI
(To the Computer)
DI
ST
(To the Keyboard)
(To the Mouse)
RE
6 PIN MINI-DIN MALE (PS/2 STYLE) to the Computer.

6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Keyboard.
6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Mouse.
OT
FO
ComputerKeyboardMouse
1
2
2
2
3
3
3
4
4
4
5
6
6
6
.N

AR
YB
ET
A
PR
EL
IM
IN
This adapter will enable you to use a keyboard and mouse at the same time. For Gateway
computer, may work with other computers (Let me know).
BETA RELEASE
401
PS/2 Keyboard (IBM Thinkpad) Y Adapter
TIO
N.
BU
RI
(To the Computer)
DI
ST
(To the Keyboard)
(To the Mouse)
RE
6 PIN MINI-DIN MALE (PS/2 STYLE) to the Computer.

6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Keyboard.
6 PIN MINI-DIN FEMALE (PS/2 STYLE) to the Mouse.
OT
FO
ComputerKeyboardMouse
1
2
2
1,2
3
3
3
4
4
4
5
6
5
6
6
.N

AR
YB
ET
A
PR
EL
IM
IN
This adapter will enable you to use a keyboard and mouse at the same time. For IBM
Thinkpad computer, may work with other computers (Let me know).
BETA RELEASE
402
PS/2 to Serial Mouse Adapter
TIO
N.
BU
This requires that the mouse handles both protocols. A mouse like this is sometimes
referred to as a combo-mouse.
ST
RI
(To the mouse)
DI
(To the computer)
GND
RxD
TxD
RTS
Mini-DIN D-SUB
3
5
2
2
6
3
4
7
FO
GND
RxD
TxD
+5V
RE
6 PIN MINI-DIN FEMALE to the mouse.

9 PIN D-SUB FEMALE to the computer.
Contributor: Joakim gren, Tomas gren <stric@ts.umu.se>, Thomas Eschenbacher

<Thomas.H.Eschenbacher@stud.uni-erlangen.de>
OT
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
This adapter will enable you to use a mouse with a 6 pin Mini-DIN (PS/2) connector to a
computer with a 9 pin D-SUB (Serial) connector.
BETA RELEASE
403
Serial to PS/2 Mouse Adapter
TIO
N.
RI
BU
This requires that the mouse handles both protocols. A mouse like this is sometimes
referred to as a combo-mouse.
ST
(To the mouse)
DI
(To the computer)
DTR+RTS+RI
CD
TXD+GND
DSR
Mini-DIN D-SUB
4
4+7+9
1
1
3
3+5
5
6
FO
+5V
Data
Gnd
Clock
RE
9 PIN D-SUB MALE to the mouse.

6 PIN MINI-DIN MALE to the computer.
Contributor: Joakim gren, Tomas gren <stric@ts.umu.se>, Thomas Eschenbacher

<Thomas.H.Eschenbacher@stud.uni-erlangen.de>
OT
Source: ?
AR
YB
ET
A
.N
PR
EL
IM
IN
This adapter will enable you to use a mouse with a 9 pin D-SUB (Serial) connector to a
computer with a 6 pin Mini-DIN (PS/2) connector.
BETA RELEASE
404
Amiga 4 Joysticks Adapter
TIO
N.
Amiga 4 Joysticks adapter
BU
ST
RI
(To the 1st Joystick).
RE
OT
.N
Parport Joy 1 Joy 2

2
1
3
2
4
3
5
4
6
1
7
2
8
3
9
4
11
6
13
6
18
8
19
8
ET
A
Up 1
Down 1
Left 1
Right 1
Up 2
Down 2
Left 2
Right 2
Fire 2
Fire 1
Ground 2
Ground 1
FO
9 PIN D-SUB MALE to the 1st Joystick.

9 PIN D-SUB MALE to the 2nd Joystick.
25 PIN D-SUB MALE to the Parallelcable.
(To the Computer).
DI
(To the 2nd Joystick).
YB

Source: Tomi Engdahl's Joystick page <http://www.hut.fi/~then/circuits/joystick.html>
AR
PR
EL
IM
IN
This adapter will make it possible to connect 2 extra joysticks to the Amiga. This requires
that the game is aware of this Multi-Joystick Extender in order to use it. The adapter is
connected to the parallelport of the Amiga.
BETA RELEASE
405
PC 2 Joysticks Adapter
TIO
N.
PC 2 Joysticks adapter
BU
ST
RI
(To the Computer)
(To the 2nd Joystick)
FO
OT
.N
Joy 1 Joy 2
1
2
3
4
4
5
5
6
7
8
9
1
10
2
11
3
12
13
6
14
7
15
8
ET
A
PC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
YB
+5 VDC
Button 1
Joystick 1 - X
Ground
Ground
Joystick 1 - Y
Button 2
+5 VDC
+5 VDC
Button 4
Joystick 2 - X
Ground
Joystick 2 - Y
Button 3
+5 VDC

15 PIN D-SUB FEMALE to the 1st Joystick.
15 PIN D-SUB FEMALE to the 2nd Joystick.
RE
DI
(To the 1st Joystick)
AR
Note: Since pin 12 is often used for MIDI-signals on gameport equipped soundcards it's
better to use the ground from pin 4 & 5, pin 15 is also used for MIDI-signals...
Source: Tomi
Engdahl's Joystick page <http://www.hut.fi/~then/circuits/joystick.html>
PR
EL
IM
IN
This adapter will make it possible to connect 1 extra joystick to the PC. The gameport
contains pins for two joysticks but you will need this adapter to be able to connect two
joysticks to one connector.
BETA RELEASE
406
Macintosh Video to VGA Adapter
TIO
N.
Macintosh to VGA Video
RI
BU
(To the Computer)
ST
(To the Monitor-cable)
RE
R
FO
VGA Dir
6
1
13
4
2
7
11
n/c
3
12
10
14
8
n/c
n/c
OT
Mac
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
.N
Description
Red Ground
Red
Composite sync
Monitor Sense 0
Green
Green Ground
Monitor Sense 1
No connection
Blue
Monitor sense 2
Sync Ground
Vertical Sync
Blue Ground
Horizontal Sync Ground
Horizontal Sync
DI

15 PIN HIGHDENSITY D-SUB FEMALE to the Monitor-cable.
ET
A
Contributor: Joakim gren, Michael Van den Acker <rdsmv@huntsman.cse.rmit.edu.au>

Source: ?
AR
YB
PR
EL
IM
IN
Use this adapter to connect a standard VGA (or higher) monitor to your Apple Macintosh.
BETA RELEASE
407
A1000 to Amiga Parallel Adapter
TIO
N.
25 PIN D-SUB FEMALE to the Amiga 1000.

25 PIN D-SUB FEMALE to the Amiga peripheral.
BU
RE
Amiga
23
24
25
14
15
16
A1000
14
15
16
23
24
25
All other straight over, 1 to 1, 2 to 2...
OT
AR
YB
ET
A
.N
Source: ?
FO
Ground
Ground
Ground
+5V
n/c
Reset
DI
(To the Amiga peripheral).
ST
RI
(To the Amiga 1000).
PR
EL
IM
IN
This adapter will enable you to connect normal Amiga peripherals to an Amiga 1000. The
Amiga 1000 has a male connector at the computer instead of a normal female connector.
And some signals has changed places.
BETA RELEASE
408
TIO
N.
BU
DI
ST
RI
Circuit Menu
RE
Need help with the circuits? See the tutorial.
Basic circuit blocks
FO
OT
YB
ET
A
.N
- Butterworth 1st order Lowpass

- Butterworth 1st order Highpass
- Butterworth 2nd order Lowpass
- Butterworth 2nd order Highpass
- Butterworth 3rd order Lowpass
- Butterworth 3rd order Highpass
- Butterworth 4th order Lowpass
- Butterworth 4th order Highpass
- Bessel 2nd order Lowpass
- Bessel 2nd order Highpass
- Bessel 3rd order Lowpass
- Bessel 3rd order Highpass
- Bessel 4th order Lowpass
- Bessel 4th order Highpass
- Linkwitz 4th order Lowpass
- Linkwitz 4th order Highpass
Active Filters:
AR

PR
EL
IM
IN
Chapter 5
BETA RELEASE
409
Chapter 5: Circuit Menu
Circuit Tutorial
TIO
N.
Short tutorial
First at each page there a short heading describing what the connector is.
BU
ST
RI
or how it looks.
DI
(At the computer)
RE
picture:
FO
(At the computer)
ET
A
(At the videocard)
.N
OT
a female connector and the send a male. The texts insde parentheses will tell you at which
YB
AR
physical connector.
5 PIN DIN 180 (DIN41524) at the computer.
PR
EL
IM
IN
Heading
Pin table
Contains mostly the following three columns; Pin, Name & Description.
Pin
1
2
3
4
5
Name
CLOCK
GND
DATA
VCC
n/c
Description
Key Clock
GND
Key Data
+5 VDC
Not connected
BETA RELEASE
410
Circuit Tutorial
TIO
N.
BU
RI
ST
DI
RE
R
FO
OT
.N
ET
A
YB
AR
PR
EL
IM
IN
BETA RELEASE
411
Active Filter: Butterworth 6dB Lowpass
TIO
N.
BU
RI
ST
R=4.7k-10 kOhm
C=1.000/(2*pi*Fc*R)
DI
Units: R [Ohm], C [F], Fc [Hz]

RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Active Filter: Butterworth

(1st order, 6 dB/octave, Lowpass)
BETA RELEASE
412
Active Filter: Butterworth 6dB Highpass
TIO
N.
BU
RI
ST
C=4.7n-10nF
R=1.000/(2*pi*Fc*C)
DI
Units: R [Ohm], C [F], Fc [Hz]

RE
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

(1st order, 6 dB/octave, Highpass)
BETA RELEASE
413
TIO
N.
BU
RI
ST
R=4.7k-10 kOhm
Ca=1.414/(2*pi*Fc*R)
Cb=0.7071/(2*pi*Fc*R)
DI
Units: R [Ohm], Cx [F], Fc [Hz]
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

(2nd order, 12 dB/octave, Lowpass)
BETA RELEASE
414
TIO
N.
BU
RI
ST
C=4.7n-10nF
Ra=0.7071/(2*pi*Fc*C)
Rb=1.414/(2*pi*Fc*C)
DI
Units: Rx [Ohm], C [F], Fc [Hz]
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
415
TIO
N.
BU
RI
DI
ST
R=4.7k-10 kOhm
Ca=2.000/(2*pi*Fc*R)
Cb=0.500/(2*pi*Fc*R)
Cc=1.000/(2*pi*Fc*R)
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
416
TIO
N.
BU
RI
DI
ST
C=4.7n-10nF
Ra=0.500/(2*pi*Fc*C)
Rb=2.000/(2*pi*Fc*C)
Rc=1.000/(2*pi*Fc*C)
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
417
TIO
N.
BU
RI
RE
DI
ST
R=4.7k-10 kOhm
Ca=1.0824/(2*pi*Fc*R)
Cb=0.9239/(2*pi*Fc*R)
Cc=2.6130/(2*pi*Fc*R)
Cd=0.3827/(2*pi*Fc*R)
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

(4th order, 24 dB/octave, Lowpass)
BETA RELEASE
418
TIO
N.
BU
RI
RE
DI
ST
C=4.7n-10nF
Ra=0.9239/(2*pi*Fc*C)
Rb=1.0824/(2*pi*Fc*C)
Rc=0.3827/(2*pi*Fc*C)
Rd=2.6130/(2*pi*Fc*C)
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

(4th order, 24 dB/octave, Highpass)
BETA RELEASE
419
Active Filter: Bessel 12dB Lowpass
TIO
N.
BU
RI
ST
R=4.7k-10 kOhm
Ca=0.9076/(2*pi*Fc*R)
Cb=0.6809/(2*pi*Fc*R)
DI
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Active Filter: Bessel

(2nd order, 12 dB/octave, Lowpass)
BETA RELEASE
420
Active Filter: Bessel 12dB Highpass
TIO
N.
BU
RI
ST
C=4.7n-10nF
Ra=1.1017/(2*pi*Fc*C)
Rb=1.4688/(2*pi*Fc*C)
DI
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
421
TIO
N.
BU
RI
DI
ST
R=4.7k-10 kOhm
Ca=0.9548/(2*pi*Fc*R)
Cb=0.4998/(2*pi*Fc*R)
Cc=0.7560/(2*pi*Fc*R)
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
422
TIO
N.
BU
RI
DI
ST
C=4.7n-10nF
Ra=1.0474/(2*pi*Fc*C)
Rb=2.0008/(2*pi*Fc*C)
Rc=1.3228/(2*pi*Fc*C)
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
423
TIO
N.
BU
RI
RE
DI
ST
R=4.7k-10 kOhm
Ca=0.7298/(2*pi*Fc*R)
Cb=0.6699/(2*pi*Fc*R)
Cc=1.0046/(2*pi*Fc*R)
Cd=0.3872/(2*pi*Fc*R)
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

BETA RELEASE
424
TIO
N.
BU
RI
RE
DI
ST
C=4.7n-10nF
Ra=1.3701/(2*pi*Fc*C)
Rb=1.4929/(2*pi*Fc*C)
Rc=0.9952/(2*pi*Fc*C)
Rd=2.5830/(2*pi*Fc*C)
Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN

(4th order, 24 dB/octave, Highpass)
BETA RELEASE
425
Active Filter: Linkwitz 24dB Lowpass
TIO
N.
BU
RI
DI
ST
R=4.7k-10 kOhm
Ca=Cc=2*Cb
Cb=Cd=1/(2*sqr(2)*pi*Fc*R)
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Active Filter: Linkwitz

BETA RELEASE
426
Active Filter: Linkwitz 24dB Highpass
TIO
N.
BU
RI
DI
ST
C=4.7n-10nF
Ra=Rc=1/(2*sqr(2)*pi*Fc*C)
Rb=Rd=2Ra
RE

Source: ?
AR
YB
ET
A
.N
OT
FO
PR
EL
IM
IN
Active Filter: Linkwitz

BETA RELEASE
427
YB
AR
PR
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IM
IN
OT
.N
ET
A
DI
Background & Information:
- SCSI Information
RE
Definitions:
- DTE & DCE
FO
ST
Misc Menu
TIO
N.
BU
RI
Chapter 6
BETA RELEASE
428
Chapter 6: Misc Menu
SCSI Information
TIO
N.
SCSI Information
BU
It all started back in 1979 when the diskdrive manufacturer come with the bright idea to
make a new transfer protocol. The protocol was named Shugart Associates Systems
Interface, SASI. This protocol wasn't an ANSI standard, so NCR join Shugart and the ANSI
committee X3T9.2 was formed. The new name for the protocol was, Small Computer
Systems Interface, SCSI.
ST
RI
Common Command Set, CCS, was added in 1985. ANSI finished the SCSI standard in 1986.
SCSI-II devices was released in 1988 and was an official standard in 1994. SCSI-III is
currently not yet official.
Usage
RE
DI
SCSI is used to connect peripherals to an computer. It allows you to connect harddisks, tape
devices, CD-ROMs, CD-R units, DVD, scanners, printers and many other devices. SCSI is
in opposite to IDE/ATA very flexible. Today SCSI is most often used servers and other
computers which require very good performance. IDE/ATA is more popular due to the fact
that IDE/ATA devices tend to be cheaper.
FO
Definitions
SCSI
OT
Short for Small Computer Systems Interface. The original SCSI protocol. ANSI standard
X3.131-1996. Busspeed 5 MHz. Datawidth 8 bits.
SCSI-II
.N
SCSI-II adds support for CD-ROM's, scanners and tapedrives.
ET
A
Fast SCSI-II
Uses the busspeed of 10MHz instead of the original 5MHz.
Wide SCSI-II
YB
Uses 16 bits instead of the original 8 bits.
Ultra SCSI-III
AR
Uses the busspeed of 20MHz.

Contributors: Joakim gren
Source: From the head of Joakim gren

PR
EL
IM
IN
Background
BETA RELEASE
429
Chapter 6: Misc Menu
Defintion: DTE & DCE
TIO
N.
Definition: DTE & DCE

DTE is acronym for Data Terminal Equipment.
BU
Examples of DTE is computers, printers & terminals.
DCE
RI
DCE is acronym for Data Communication Equipment.
ST
Examples of DCE is modems.
Wiring
DI
Wiring a cable for DTE to DCE communication is easy. All wires goes straight from pin x to
pin x.
RE
But wiring a cable for DTE to DTE (nullmodem) or DCE to DCE requires that some wires are
crossed. A signal should be wired from pin x to the opposite signal at the other end. With
opposite signals I mean for example Transmit & Receive.
Contributors: Joakim gren , Richard L. Lane <rlane@eastman.com> , Rob Gill <gillr@mailcity.com>
FO
Source: ?
AR
YB
ET
A
.N
OT
PR
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IN
DTE
BETA RELEASE
430
YB
AR
PR
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IN
OT
.N
ET
A
R
FO
DI
- AWG, American Wire Gauge standard

- SI Prefixes , Is 1 kW equal 1000000mW ?
RE
ST
Table Menu
TIO
N.
BU
RI
Chapter 7
BETA RELEASE
431
Chapter 7: Table Menu
AWG Table
TIO
N.
AWG
22
20
19
18
16
14
13
12
BU
RI
ST
DI
RE
R
FO
OT
32
30
29
27
26
25
24
.N
33
R
I at 3A/mm2
ohm/km mA
13700 3,8
8750
6
6070
9
4460
12
3420
15
2700
19
2190
24
1810
28
1520
33
1300
40
1120
45
970
54
844
60
757
68
676
75
605
85
547
93
351
147
243
212
178
288
137
378
108
477
87,5
588
72,3
715
60,7
850
51,7
1,0 A
44,6
1,16 A
38,9
1,32 A
34,1
1,51 A
30,2
1,70 A
26,9
1,91 A
24,3
2,12 A
21,9
2,36 A
18,1
2,85 A
15,2
3,38 A
13,0
3,97 A
11,2
4,60 A
9,70
5,30 A
8,54
6,0 A
7,57
6,7 A
6,76
7,6 A
6,05
8,5 A
5,47
9,4 A
ET
A
34
Area
mm2
0,0013
0,0020
0,0028
0,0039
0,0050
0,0064
0,0078
0,0095
0,011
0,013
0,015
0,018
0,020
0,023
0,026
0,028
0,031
0,049
0,071
0,096
0,13
0,16
0,20
0,24
0,28
0,33
0,39
0,44
0,50
0,57
0,64
0,71
0,78
0,95
1,1
1,3
1,5
1,8
2,0
2,3
2,6
2,8
3,1
YB
36
35
Diam
mm
0,04
0,05
0,06
0,07
0,08
0,09
0,10
0,11
0,12
0,13
0,14
0,15
0,16
0,17
0,18
0,19
0,20
0,25
0,30
0,35
0,40
0,45
0,50
0,55
0,60
0,65
0,70
0,75
0,80
0,85
0,90
0,95
1,00
1,10
1,20
1,30
1,40
1,50
1,60
1,70
1,80
1,90
2,00
AR
Gauge
AWG
46
44
42
41
40
39
38
37
PR
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IM
IN
AWG=American Wire Gauge standard

Source: ?
BETA RELEASE
432
Chapter 7: Table Menu
SI Prefixes Table
TIO
N.
SI Prefixes
FO
RE
DI
ST
RI
BU
Symbol Prefix Factor

Z
Zetta 1021
E
Exa 1018
P
peta 1015
T
tera 1012
G
giga 109
M
Mega 106
k
kilo 103
h
hecto 102
da
deca 101
d
deci 10-1
c
centi 10-2
m
milli 10-3
micro 10-6
n
nano 10-9
p
pico 10-12
f
femto 10-15
a
atto 10-18
z
zepto 10-21
y
yokto 10-24
Note: In the computer world things are a bit different:
.N
OT
Symbol Prefix Factor Factor

P
peta 250
1125899906842624
T
tera 240
1099511627776
G
giga 230
1073741824
M
Mega 220
1048576
k
kilo 210
1024
ET
A
Contributor: Joakim gren, Haudy Kazemi <hkazemi@geocities.com>, Knut Kristan Weber

<kweber@ix.urz.uni-heidelberg.de>
Source: Farnell Components Catalogue
AR
YB
PR
EL
IM
IN
Example: 1 TW=1000 GW (W=Watt)
BETA RELEASE
433
TIO
N.
BU
DI
ST
RI
Download Menu
RE
The Hardware Book is available in some other formats as well. Since these are converted
from HTML the result may sometimes look a little bit strange. If there is some major visual
errors or if a link does not work, feel free to send an e-mail. These versions is currently to be
considered as beta. And btw, if you like to see HwB in some other format, let me know.
FO
Visit HwB at Internet <http://www.blackdown.org/~hwb/hwb.html> to download these

versions.
AR
YB
ET
A
.N
OT
PR
EL
IM
IN
Chapter 8
BETA RELEASE
434
TIO
N.
BU
DI
ST
RI
HwB-News Menu
FO
RE
If you would like to be informed about what's happening with the Hardware Book, the
HwB-News letter may be something for you. It will contain:
- Updates of The Hardware Book
- News concerning HwB.
- Info about HwB errors/typos.
- Related WWW Links
To subscribe to the HwB-News mailinglist send a mail with the text SUBSCRIBE in the body
to hwb-news-request@www.blackdown.org <hwb-news-request@www.blackdown.org>
OT
To unsubscribe to the HwB-News mailinglist send a mail with the text UNSUBSCRIBE in the
body to hwb-news-request@www.blackdown.org <hwb-news-request@www.blackdown.org>
.N
The mailing list is not a discussion mailinglist. It only contains mail from me, Joakim gren.
AR
YB
ET
A
Note: It's a low traffic mailing list. Unsubscribe whenever you want, every mail contains
unsubscribe instructions.
PR
EL
IM
IN
Chapter 9
BETA RELEASE
435
TIO
N.
BU
DI
ST
RI
Wanted
RE
Please help me make this reference guide larger. I guess there is much more to add. Don't
hesitate to send some strange pinout, circuit or cable.
If you have a strange serial-port on your dish-washer, SEND it to me :-)

If it does not have one you could send me a circuit on how to add a serial-port to it. :-)
I have already heard from two people that has a serial port on their dish-washers :)
AR
YB
ET
A
.N
OT
FO
I am especially searching for the following standards:

- ECB
- EIB
- IEEE1394 Firewire
- SMP16
- SA1000
- JVC bus?
- PC-Engine/TurboGrafix 16 connectors
- Qbus
- STEbus
- SBus
- MULTIBUS
- MULTIBUS II
- MTM-Bus
- GIO
- FutureBus+
- Nec PC-FX connectors
- Kenwood CD-Player RS232-port (For example DP-M7750).
- IBM PS/2 Motherboard Power connector
- Epson Sample E04974 Diskdrive with Signals+Power in the usual 34 pin connector.
- 40 pin diskdrive connector (not IDE..)
- XTA Interface
PR
EL
IM
IN
Chapter 10
Other information of value:

- Filters
If you have any of the above listed please send an e-mail to Joakim gren
.
BETA RELEASE
436
TIO
N.
BU
DI
ST
RI
About Hardware Book
RE
What about this? Your free reference guide to electronics.
The Hardware Book is a compilation of pinouts I've found from different sources. I've tried to
have the same style for all pages. This makes it easier to find information for you. I am not
trying to sell anything.
OT
FO
It has been developed on my sparetime and is made available to you for free. This also
means that I can't guarantee that the presented information is correct. Use it on you own risk.
I can't take the whole credit for HwB. I have since the first release received a great lot of
mails with suggestions, questions and information. With the help of many contributors HwB
has grown. Keep sending me mails...
YB
ET
A
.N
This is me, Joakim gren:
Could it be even better? Perhaps if You help me. Please send any material you have that
might be of interest for this project. Send it to qtech@mailhost.net.
AR
I am looking for a sponsor, if you are interested please let me know and I will tell you
more.
All new information since the last update is marked
information is marked
.
PR
EL
IM
IN
Chapter 11
and updated or changed
I would like to thank the following people:

Niklas Edmundsson for helping me find some of the information in HwB and being a nice
friend..
Karl Asha
for letting me use his web-server to store HwB.
Tomas gren
my brother, for comments and helping me with HwB.
Rob Gill
for sending me many nice pinouts etc.
Petr Krc
for sending me many nice pinouts etc.
Marco Budde
maintainer of the HwB Linux Debian package.
BETA RELEASE
437
YB
AR
PR
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IN
OT
.N
ET
A
R
FO
RE
ST
DI
BU
This is what I feel like doing when nothing works :-)
RI
TIO
N.
Chapter 11: About Hardware Book
BETA RELEASE
438
TIO
N.
BU
DI
ST
RI
Contacting the author HwB
RE
I will not be able to answer any questions at the moment. But please send
me pinouts etc.
OT
FO
I receive many e-mails every day. Please help me categorize the e-mails:
- Pinout, Connector pinouts. <hwb-pinout@usa.net>
- Cable, Cable & adapters descriptions. <hwb-cable@usa.net>
- Circuits, Circuits for the coming Circuit-section. <hwb-circuit@usa.net>
- General, General info for HwB. <hwb@usa.net>
.N
Please don't send questions like "Do you have the pinout to Xyz" or "Can you help me to
repair my Xyz", please redirect these to a UseNet newsgroup instead. Try DejaNews
<http://www.dejanews.com>
AR
YB
ET
A
PR
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IM
IN
Chapter 12
BETA RELEASE
439
.N
ET
A
YB
AR
RE
DI
ST
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BU
TIO
N.
Atari ST Monitor Connector

C-bus II Connector
C128 RGBI Connector
C128/C64C Video Connector
C16/C116/+4 Audio/Video Connector
C16/C116/+4 Cassette Connector
C16/C116/+4 Joystick Connector
C64 Audio/Video Connector
C64 Cassette Connector
C64 Control Port Connector
C64 Power Supply Connector
C64 RS232 User Port Connector
C64 Serial I/O Connector
C64 User Port Connector
C65 Video Connector
CBM 1902A Connector
CDTV Expansion Slot Connector
CDTV Video Slot Connector
CGA Connector
CM-8/CoCo RGB Connector
Cable Menu
Cable Tutorial
CardBus Connector
Centronics Connector
Circuit Menu
Circuit Tutorial
Cisco Console Port Connector
CoCo Cassette Connector
CoCo Serial Printer Connector
Commodore 1084 & 1084S (Analog) Connector
Commodore 1084 & 1084S (Digital) Connector
Commodore 1084d & 1084dS Connector
Connector Menu
Connector Top 10 Menu
Connector Tutorial
Conrad Electronics MM3610D Connector
Contacting the author HwB
DEC DLV11-J Serial Connector
DEC Dual RS-232 Connector
DIN Audio Connector
Defintion: DTE & DCE
Download Menu
ECP Parallel (Tech) Connector
ECP Parallel Connector
EGA Connector
EISA Connector
ESDI Cable
ESDI Connector
Ethernet 10/100Base-T Connector
Ethernet 100Base-T4 Connector
Floppy Cable
GEOCable Cable
GameBoy Cartridge Connector
GeekPort Connector
HwB-News Menu
IDE Cable
ISA Connector
FO
315
260
263
267
280
281
285
253
176
284
282
283
357
256
254
258
213
381
397
408
288
289
178
211
179
180
236
234
295
432
437
421
420
423
422
425
424
415
414
417
416
419
418
413
412
427
426
393
394
162
91
88
405
214
191
161
93
382
380
216
171
217
172
144
332
252
202
296
199
297
298
200
299
300
201
151
301
198
219
168
197
OT
+4 User Port Connector

168 pin DRAM DIMM (Unbuffered) Connector
168 pin SDRAM DIMM (Unbuffered) Connector
3b1/7300 Video Connector
64NET Cable
8" Floppy Diskdrive Connector
9 to 15 pin VGA Cable
AT Backup Battery Connector
AT LED/Keylock Connector
AT&T 53D410 Connector
AT&T 6300 Keyboard Connector
AT&T 6300 Taxan Monitor Connector
AT&T PC6300 Connector
ATA (44) Internal Connector
AUI Connector
AWG Table
About Hardware Book
Active Filter: Linkwitz 24dB Highpass
Active Filter: Linkwitz 24dB Lowpass
Adapter Menu
Adapter Tutorial
Amiga 1000 RF Monitor Connector
Amiga 4 Joysticks Adapter
Amiga External Diskdrive Connector
Amiga Mouse/Joy Connector
Amiga Video Connector
Amiga to SCART Cable
Amstrad CPC6128 Diskdrive 2 Connector
Amstrad CPC6128 Monitor Connector
Amstrad CPC6128 Plus External Diskdrive Connector
Amstrad CPC6128 Plus Monitor Connector
Amstrad CPC6128 Printer Port Connector
Amstrad CPC6128 Stereo Connector
Amstrad CPC6128 Tape Connector
Amstrad Digital Joystick Connector
Atari ACSI DMA Connector
Atari Enhanced Joystick Connector
Atari Floppy Port Connector
Atari Jaguar A/V Connector
Atari Mouse/Joy Connector
PR
EL
IM
IN
Index
BETA RELEASE
173
109
311
184
185
383
384
313
186
248
193
182
308
247
354
192
331
130
150
310
183
187
95
316
318
271
163
155
177
335
337
99
141
398
409
410
360
359
132
249
134
165
166
167
107
55
48
2
333
8
362
361
135
439
131
126
279
400
430
434
140
139
156
29
26
376
237
293
386
387
294
388
370
358
303
148
435
371
232
13
10
440
AR
YB
ET
A
RE
DI
ST
RI
BU
TIO
N.
RS232 Connector
RS422 Connector
RocketPort Serialport Connector
S-Video Connector
SCART Connector
SCSI External Centronics 50 (Differential) Connector
SCSI External Centronics 50 (Single-ended) Connector
SCSI External D-Sub (Future Domain) Connector
SCSI External D-Sub (PC/Amiga/Mac) Connector
SCSI Information
SCSI Internal (Single-ended) Connector
SCSI-II External Hi D-Sub (Differential) Connector
SCSI-II External Hi D-Sub (Single-ended) Connector
SGI Mouse (Model 021-0004-002) Connector
SI Prefixes Table
SNES Video Connector
SSFDC Connector
ST506/412 Cable
ST506/412 Connector
Serial (15) Connector
Serial (Amiga 1000) Connector
Serial (Amiga) Connector
Serial (MSX) Connector
Serial (Printer) Connector
SmallPCI Connector
SmartCard AFNOR Connector
SmartCard ISO 7816-2 Connector
SmartCard ISO Connector
Sony CD-ROM Connector
Spectravideo SVI318/328 Audio/Video Connector
Spectravideo SVI318/328 Cassette Connector
Spectravideo SVI318/328 Expansion Bus Connector
Spectravideo SVI318/328 Game Cartridge Connector
Sun Video Connector
TG-16 Cartridge Connector
Table Menu
The Hardware Book (PDF)
Turbo LED Connector
Unibus Connector
Universal Serial Bus (USB) Connector
VESA Feature Connector
VGA (15) Connector
VGA (9) Connector
VGA (VESA DDC) Connector
Vic 20 Video Connector
Video to TV SCART Cable
Wanted
X1541 Cable
ZX Spectrum 128 RGB Connector
ZX Spectrum AY-3-8912 Connector
ZX Spectrum ULA Connector
Zorro II Connector
FO
58
212
207
204
208
205
209
206
355
158
391
329
328
250
304
215
194
142
342
363
218
210
347
348
196
127
129
160
407
399
76
74
330
428
392
242
344
350
343
292
291
286
124
170
203
385
231
81
78
341
340
339
396
406
103
101
189
190
290
319
114
37
33
105
157
401
402
403
244
356
389
138
137
143
136
365
364
241
378
164
351
OT
.N
Internal Diskdrive Connector
Keyboard (Amiga CD32) Connector
Keyboard (XT) Connector
MDA (Hercules) Connector
MIDI Cable
MIDI In Connector
MIDI Out Connector
MSX Cassette Connector
MSX External Diskdrive Connector
MSX Joystick Connector
MSX Parallel Connector
Mac to HP48 Cable
Macintosh External Drive Connector
Macintosh Keyboard Connector
Macintosh Mouse Connector
Macintosh RS-422 Connector
Macintosh Serial Connector
Macintosh Video Connector
Macintosh Video to VGA Adapter
Minuteman UPS Connector
Misc Menu
Misc Unsupported Cables
Modem (25-25) Cable
Modem (9-15) Cable
Modem (9-25) Cable
Motherboard CPU Cooling fan Connector
Motherboard IrDA Connector
Motherboard Power Connector
Mouse (PS/2) Connector
NeoGeo Audio/Video Connector
NeoGeo Joystick Connector
Novell and Procomp External SCSI Connector
NuBus 90 Connector
NuBus Connector
Nullmodem Adapter
PC 2 Joysticks Adapter
PC Card Connector
PC Gameport Connector
PC Gameport+MIDI Connector
PC Speaker Connector
PC-Engine Cartridge Connector
PC/104 Connector
PCI Connector
PCMCIA Connector
PGA Connector
ParaLoad Cable
Parallel (Amiga 1000) Connector
Parallel (Amiga) Connector
Parallel (Olivetti M10) Connector
Parallel (PC) Connector
Paravision SX-1 External IDE Connector
PlayStation A/V Connector
Printer Cable
PR
EL
IM
IN
Index
BETA RELEASE
117
128
349
133
278
276
372
373
224
223
229
230
429
221
220
227
226
195
433
320
169
113
374
239
125
120
121
122
119
118
123
369
367
368
366
353
352
404
73
273
274
275
246
188
251
325
327
174
322
431
1
287
346
345
115
146
145
159
45
42
153
154
152
306
181
379
436
390
175
323
324
84
86
441

HWBOOK

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HWBOOK

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TIO

Visit Cable City at <http://www.cablecity.com>

Created and maintained by Joakim gren.

Welcome to the Hardware Book. Your electronic reference guide.

Current version 1.3 BETA.

Pinouts for connectors, buses etc.

The Hardware Book

Note: This PDF file may NOT be sold in printed form.

- Universal Serial Bus (USB) - (Technical)

- VGA (VESA DDC)

Chapter 1: Connector Menu

- Amstrad CPC6128 Monitor

Chapter 1: Connector Menu

Chapter 1: Connector Menu

- SCSI Internal (Single-ended)

Misc data storage:

- MSX External Diskdrive

Chapter 1: Connector Menu

- Ethernet 10Base-T & 100Base-T

- Atari 2600 Cartridge

(C) Joakim gren 1996,1997

Chapter 1: Connector Menu

Chapter 1: Connector Menu

Pictures of the connectors

(At the computer)

(At the computer)

(At the videocard)

(At the monitor cable)

Texts describing the connectors

Contributor & Source

Chapter 1: Connector Menu

Source: Amiga 4000 User's Guide from Commodore

Chapter 1: Connector Menu

(At the card)

(At the computer)

62+36 PIN EDGE CONNECTOR MALE at the card.

ISA=Industry Standard Architecture

System bus high enable (data available on SD8-15)

Chapter 1: Connector Menu

Used with DRQ to gain control of system

Note: Direction is Motherboard relative ISA-Cards.

Contributor: Joakim gren , Rob Gill <gillr@mailcity.com>

Sources: IBM PC/AT Technical Reference, pages 1-25 through 1-37

Please send any comments to Joakim gren.

Chapter 1: Connector Menu

Chapter 1: Connector Menu

ISA (Tech) Connector

(At the card)

(At the computer)

ISA (Tech) Connector

(At the card)

(At the computer)

+5, -5, +12, -12

Power supplies. -5 is often not implemented.

Chapter 1: Connector Menu

DMA Acknowledge. The active-low DMA Acknowledge 0 to 3 and 5 to 7 are the

Chapter 1: Connector Menu

ISA (Tech) Connector

Chapter 1: Connector Menu

ISA (Tech) Connector

Chapter 1: Connector Menu

ISA (Tech) Connector

8 Bit Memory or I/O Transfer Timing Diagram (4 wait states

Note: W1 through W4 indicate wait cycles.

_______ _ _______