EXPERIMENT NO.

6
Aim
To implement VHDL code for 4:2 and 8:3 priority encoder.

Tool required

Mentor Graphics
FPGA advantage 8.1ps
Model sim 6.3a

Theory
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the ordinal
number starting from zero of the most significant input bit. They are often used to control
interrupt requests by acting on the highest priority request.
If two or more inputs are given at the same time, the input having the highest priority will take
precedence. An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are
to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output
since it is superseded by higher-priority input.
Priority encoders can be easily connected in arrays to make larger encoders, such as one 16-to-4
encoder made from six 4-to-2 priority encoders - four 4-to-2 encoders having the signal source
connected to their inputs, and the two remaining encoders take the output of the first four as
input.
The priority encoder is an improvement on a simple encoder circuit, in terms of handling all
possible input configurations.

4:2 priority encoder

A 4-bit priority encoder (also sometimes called a priority decoder). This circuit basically
converts the 4-bit input into a binary representation. If the input n is active, all lower inputs
(n-1 .. 0) are ignored:

Truth Table
Input

Output

D3 D2 D1 D0 Q1 Q0 ANY

Logic Equation
A1 = D2 + D3
A0 = D1D2 + D3
ANY = D1 + D2 + D3

8:3 priority encoder

Truth Table
Digital Inputs

Binary Output

D7

D6

D5

D4

D3

D2

D1

D0

Q2

Q1

Q0

Logic Equation
Q2 = D4 + D5 + D6 + D7
Q1 = D5D4D2 + D5D4D3 + D6 + D7
Q0 = D6D4D2D1 + D6D4D3 + D6D5 + D7

VHDL code for 4:2 Priority Encoder

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY PENC4 IS
PORT( D3,D2,D1,D0 : IN STD_LOGIC; A1,A0,ANY:OUT STD_LOGIC);
END ENTITY PENC4;
ARCHITECTURE PENC4_ARCH OF PENC4 IS
BEGIN
PROCESS(D3,D2,D1,D0)
BEGIN
IF(((D3='0' AND D2='0') AND D1='0') AND D0='0') THEN
ANY<='0';
A0<='0';
A1<='0';
ELSIF(((D3='0' AND D2='0') AND D1='0') AND D0='1') THEN
ANY<='1';
A0<='0';
A1<='0';
ELSIF((D3='0' AND D2='0') AND D1='1') THEN
ANY<='1';
A0<='1';
A1<='0';
ELSIF(D3='0' AND D2='1') THEN
ANY<='1';
A0<='0';
A1<='1';
ELSIF(D3='1') THEN
ANY<='1';
A0<='1';
A1<='1';
END IF;
END PROCESS;
END ARCHITECTURE PENC4_ARCH;

Output:

Result window of 4:2 Priority Encoder

VHDL code for 8:3 Priority Encoder

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY PRIORITY IS
port(D7,D6,D5,D4,D3,D2,D1,D0:in std_logic;
A2,A1,A0,ANY:OUT STD_LOGIC);
END ENTITY tristate_buffer;
-ARCHITECTURE buffer_data OF tristate_buffer IS
BEGIN
process(D7,D6,D5,D4,D3,D2,D1,D0)
begin
if(D7='0' AND D6='0' AND D5='0' AND D4='0' AND D3='0' AND D2='0' AND D1='0'
AND D0='0') THEN
A2<='0';
A1<='0';
A0<='0';
ANY<='0';
ELSIF(D7='0' AND D6='0' AND D5='0' AND D4='0' AND D3='0' AND D2='0' AND
D1='0' AND D0='1') THEN
A2<='0';
A1<='0';
A0<='0';
ANY<='1';

ELSIF(D7='0' AND D6='0' AND D5='0' AND D4='0' AND D3='0' AND D2='0' AND
D1='1')THEN
A2<='0';
A1<='0';
A0<='0';
ANY<='1';
ELSIF(D7='0' AND D6='0' AND D5='0' AND D4='0' AND D3='0' AND D2='1') THEN
A2<='0';
A1<='1';
A0<='0';
ANY<='1';
ELSIF(D7='0' AND D6='0' AND D5='0' AND D4='0' AND D3='1') THEN
A2<='0';
A1<='1';
A0<='1';
ANY<='1';
ELSIF(D7='0' AND D6='0' AND D5='0' AND D4='1') THEN
A2<='1';
A1<='0';
A0<='0';
ANY<='1';
ELSIF(D7='0' AND D6='0' AND D5='1') THEN
A2<='1';
A1<='0';
A0<='1';
ANY<='1';
ELSIF(D7='0' AND D6='1') THEN
A2<='1';
A1<='1';
A0<='0';
ANY<='1';
ELSIF(D7<='1') THEN
A2<='1';
A1<='1';
A0<='1';
ANY<='1';
END IF;
END PROCESS;
END ARCHITECTURE buffer_data;

Output:

Result Window of 8:3 Priority Encoder

Result
The VHDL code for 4:2 and 8:3 Priority Encoders were implemented and simulated successfully.