EXPERIMENT NO.

11
Aim
To implement VHDL code for up counter, down counter, up-down counter and BCD counter.

Tool required
Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

Theory

Counter
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal.

Up Counter
An up counter is simply a digital counter which counts up at some predefined increment.

Fig 11.1

Truth Table
TABLE (11.1)

CLOCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Fig (11.2)

Down Counter
A down counter is simply a digital counter which counts down at some predefined decrement.

Fig (11.3)

Truth Table
CLOCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Q3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Q2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Q0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

TABLE (11.2)

Up/down counter
A counter that can change state in either direction, under the control of an up/down selector input, is known as an up/down counter. When the selector is in the up state, the counter increments its value. When the selector is in the down state, the counter decrements the count.
Fig (11.4)

Fig (11.5)

Truth Table
TABLE (11.3)

CLOCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

input(m) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1

Q3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1

Q2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0

Q1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

22 23 24 25 26 27 28 29 30 31 32

1 1 1 1 1 1 1 1 1 1 1

1 1 1 0 0 0 0 0 0 0 0

0 0 0 1 1 1 1 0 0 0 0

1 0 0 1 1 0 0 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0

BCD Counter
BCD stands for Binary Coded Decimal. A BCD counter has four outputs usually labelled A, B, C, D. By convention A is the least significant bit, or LSB. The easiest way to understand what a BCD counter does is to follow the counting sequence in truth table form:

Truth Table
TABLE (11.4)

CLOCK 0 1 2 3 4 5 6 7 8 9 10

D 0 0 0 0 0 0 0 0 1 1 0

C 0 0 0 0 1 1 1 1 0 0 0

B 0 0 1 1 0 0 1 1 0 0 0

A 0 1 0 1 0 1 0 1 0 1 0

Circuit Diagram of 4-bit BCD or (mod 10) counter

Fig (11.6)

Timing Diagram

Fig (11.7)

VHDL code for up counter

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY counter IS port(cr,pr,clk:in std_logic; q:inout std_logic_vector(0 to 3)); END ENTITY counter; ARCHITECTURE counter_up OF counter IS signal temp:std_logic_vector(0 to 3); BEGIN process(cr,pr,clk) begin if(cr='0')then temp<="0000"; elsif(pr='0')then temp<="1111"; elsif(clk='1' and clk 'event)then temp<=temp+'1'; end if; end process; q<=temp; END ARCHITECTURE counter_up;

Output

Result window of up counter

VHDL code for down counter

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY counter IS port(cr,pr,clk:in std_logic; q:inout std_logic_vector(0 to 3)); END ENTITY counter; ARCHITECTURE counter_down OF counter IS signal temp:std_logic_vector(0 to 3); BEGIN

process(cr,pr,clk) begin if(cr='0')then temp<="0000"; elsif(pr='0')then temp<="1111"; elsif(clk='1' and clk 'event)then temp<=temp-'1'; end if; end process; q<=temp; END ARCHITECTURE counter_down;

Output

Result window of down counter

VHDL code for up\ down counter

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY counter IS port(cr,pr,clk,m:in std_logic; q:inout std_logic_vector(0 to 3)); END ENTITY counter; ARCHITECTURE counter_up OF counter IS signal temp:std_logic_vector(0 to 3); BEGIN process(cr,pr,clk) begin if(cr='0')then temp<="0000"; elsif(pr='0')then temp<="1111"; elsif(clk='1' and clk 'event)then if(m='0')then temp<=temp+'1'; elsif(m='1')then temp<=temp-'1'; end if; end if; end process; q<=temp; END ARCHITECTURE counter_up;

Output

Result window of up\ down counter

VHDL code for BCD counter

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_signed.all; ENTITY counter IS port(cr,pr,clk:in std_logic; q:inout std_logic_vector(0 to 3)); END ENTITY counter; ARCHITECTURE counter_up OF counter IS signal temp:std_logic_vector(0 to 3); BEGIN

process(cr,pr,clk) begin if(temp="1010")then temp<="0000"; end if; if(cr='0')then temp<="0000"; elsif(pr='0')then temp<="1111"; elsif(clk='1' and clk 'event)then temp<=temp+'1'; end if; end process; q<=temp; END ARCHITECTURE counter_up;

Output

Result window of down counter

Result - The VHDL code for Up, Down, Up\down and BCD counter were implemented and simulated successfully.