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Design of Counters
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9.0 Introduction
Counter is another class of sequential circuits that tally a series of input pulses
which may be regular or irregular in nature. Counter can be divided into
binary/non-binary and synchronous/asynchronous types.
In the chapter the design of counter using various types of flip-flop are
discussed.
09 Design of Counters
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09 Design of Counters
From the timing diagram, it shows there are propagation delays due to transition
from clock pulse to output of flip-flop 0 Q0, from output of flip-flop 0 Q0 to
output flip-flop 1 Q1, and from output of flip-flop 1 Q1 to output flip-flop 2 Q2.
If the output Q1 is ANDed with output Q 0 , the ideal result i.e. the
assumption of no propagation delay is shown in Fig. 9.5, whereas the result
shown in Fig. 9.6 is different for the case where there is propagation delay.
There are glitches for the non-ideal case.
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09 Design of Counters
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09 Design of Counters
Qt
0
0
1
1
Qt+1
0
1
0
1
S
0
1
0
X
R
X
0
1
0
Qt
0
0
1
1
Qt+1
0
1
0
1
D
0
1
0
1
Qt
0
0
1
1
Qt+1
0
1
0
1
J
0
1
X
X
K
X
X
1
0
Qt
0
0
1
1
Qt+1
0
1
0
1
T
0
1
1
0
09 Design of Counters
Since there are ten states, four JK flip-flops are required. The truth tables of
present and next state for the decade counter are shown in Fig. 9.10. Using the
excitation table of JK flip-flop and the outputs of J and K are filled.
Present State
Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
Q3
0
0
0
0
0
0
0
1
1
0
Next State
Q2 Q1
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
Q0
1
0
1
0
1
0
1
0
1
0
J3 K3
0 X
0 X
0 X
0 X
0 X
0 X
0 X
1 X
X 0
X 1
J2
0
0
0
1
X
X
X
X
0
0
Output
K2 J1
X 0
X 1
X X
X X
0 0
0 1
0 X
1 X
X 0
X 0
K1
X
X
0
1
X
X
0
1
X
X
J0 K0
1 X
X 1
1 X
X 1
1 X
X 1
1 X
X 1
1 X
X 1
Figure 9.10: Truth table and state table of a synchronous decade counter
The Karnaugh maps of the output J0, K0, J1, K1, J2, K2, J3, and K3 are shown in
Fig. 9.11, 9.12, 9.13, and 9.14 respectively. The simplified results are at the
bottom of the Karnaugh maps.
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09 Design of Counters
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09 Design of Counters
Based on the results obtained from the Karnaugh maps, the circuit design of
synchronous decade counter is shown in Fig. 9.15.
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09 Design of Counters
R2
0
0
1
X
0
0
S2
X
X
0
0
1
X
Output
R1 S1
1
0
X 0
X 0
0
1
0 X
0 X
R0 S0
0 X
1 0
0 1
1 0
X 0
0 1
Figure 9.17: Truth table and state table of the modulus-six counter
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09 Design of Counters
The Karnaugh maps of the output R0, S0, R1, S1, R2, and S2 are shown in Fig.
9.19, 9.20, and 9.21 respectively. The simplified results are at the bottom of the
Karnaugh maps.
With the known output logic functions, the logic design of the synchronous
modulus six counter is hown ing Fig. 9.21.
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09 Design of Counters
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09 Design of Counters
Tutorials
9.1.
9.2.
Draw the timing diagrams of the decade counter shown in Fig. 9.14.
9.3.
9.4.
Using the truth table shown in Fig. 9.16, design this counter using T flipflop.
References
1. Thomas L. Floyd, "Digital Fundamentals", Seventh Edition, Prentice-Hall
International, Inc., 2000.
2. Donald D. Givone, "Digital Principles and Designs", McGraw- Hill 2003.
3. Victor P. Nelson, H. Try Nagle, Bill D. Carroll, and J. David Irwin, "Digital
Logic Circuit Analysis & Design", Prentice-Hall Englewood Cliffs.NJ,
1995.
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