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Glitches by Ajay
Glitches by Ajay
Hazards/Glitches
Chapter Overview
Time Response in Combinational Networks
Gate Delays and Timing Waveforms
Hazards/Glitches and How To Avoid Them
Terms:
gate delay -- time for change at input to cause change at output.
rise time -- time for output to transition from low to high voltage
fall time -- time for output to transition from high to low voltage
A' A = 0
3 gate delays
D remains high for
three gate delays after
A changes from low to high
F is not always 0!
+
Resistor
A
Open
Switch
Close Switch
Initially undefined
Open Switch
B
D
1
Static
1-hazard
Static
0 0-hazard
0
1
0
1
Dynamic
1 hazards
0
Kinds of Hazards
A
\C
\A
D
G1
1
0
G2
A
\C
1
G3
\A
D
G1
1
0
1
G3
G2
01
\A
D
1
0
1
G1
G3
G2
A
\C
ABCD = 1101
F
\A
D
0
G1
1
0
1
10
11
10
0
G3
G2
11
F = A' D + A C'
01
ABCD = 1101
ABCD = 1100
A
\C
AB
00
CD
00 0
A
\C
F
\A
D
0
G1
1
1
0
G3
G2
ABCD = 0101 (A is 1)
01
A
01
11
10
1
D
Glitch present!
Add term: (C' + D)
This expression is equivalent
to the hazard-free SoP form of F
11
10
100
A
B
C
D
F
F2
1's hazards in F
corrected in F2
AB
00
CD
00 0
01
A
01
11
10
11
F(A,B,C,D) = m(1,3,5,7,8,9,12,13,14,15)
10
01
\B 1 0
\C
1
G1
01
Slow
G2
G3
1 01
10
A 0
\B
10
G5
G4
10
V ery slow
1 01 0
F