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R09

Code No: C0601, C5503, C7703, C6803, C5703, C7003, C4507, C3803
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
M.Tech I Semester Examinations, October/November-2011
VLSI TECHNOLOGY AND DESIGN
(COMMON TO DIGITAL SYSTEMS & COMPUTER ELECTRONICS, EMBEDDED
SYSTEMS, EMBEDDED SYSTEMS & VLSI DESIGN, VLSI & EMBEDDED SYSTEMS,
VLSI SYSTEM DESIGN, ELECTRONICS & COMMUNICATION ENGINEERING,
SYSTEMS & SIGNAL PROCESSING, DIGITAL ELECTRONICS & COMMUNICATION
SYSTEMS)

Time: 3hours

Max. Marks: 60
Answer any five questions
All questions carry equal marks
---

1.a)
b)

Derive the relevant expressions Ids versus Vds in the Non-Saturated and
Saturated regions.
Explain the pseudo-NMOS logic during the low to high transition.
[12]

D
L

2.a)
b)

Explain about various layout design and tools in VLSI design. With diagrams.
Design the layout for an n-diffusion wire connected to a p-diffusion wire. [12]

3.

Explain about 1 - clocking rules for flip-flops and 2 - clocking disciplines

for latches.
[12]

4.a)
b)

Explain how capacitive coupling lead to crosstalk.

Discuss graph model for path delay through combinational logic in the
combinational network delay.
[12]

5.a)
b)

Explain about off-chip connections related to floor planning in VLSI design.

Explain about the process sequence in the realization of CMOS Inverter. [12]

6.a)

Generate a set of sequential tests for the 01 string recognizer which tests for
all stuck at-0/1 faults, assuming you dont know the machines initial state.
Explain how the simple wiring plans in the data paths.
[12]

b)

R
O

W
U

T
N

7.a)
b)

Explain the structure of a Booth multiplier.

Design of an SRAM core cell and explain it briefly.

[12]

8.
a)
b)

Explain briefly on
Design validation and testing.
Placement and routing in floor planning.

[12]

******

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