entity P10 is

port (key: in std_logic_vector(0 to 9);

p10: out std_logic_vector(0 to 9));
end;
architecture P10 of P10 is
begin
p10(0) <= key(2);
p10(1) <= key(4);
p10(2) <= key(1);
p10(3) <= key(6);
p10(4) <= key(3);
p10(5) <= key(9);
p10(6) <= key(0);
p10(7) <= key(8);
p10(8) <= key(7);
p10(9) <= key(5);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity P8 is
port (input: in std_logic_vector(0 to 9);
permute8 : out std_logic_vector(0 to 7));
end;
architecture P8
begin
permute8(0)
permute8(1)
permute8(2)
permute8(3)
permute8(4)
permute8(5)
permute8(6)
permute8(7)
end;

of P8 is
<=
<=
<=
<=
<=
<=
<=
<=

input(5);
input(2);
input(6);
input(3);
input(7);
input(4);
input(9);
input(8);

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity IP is
port (input: in std_logic_vector(0 to 7);
ip : out std_logic_vector(0 to 7));
end;
architecture
begin
ip(0) <=
ip(1) <=
ip(2) <=
ip(3) <=
ip(4) <=
ip(5) <=
ip(6) <=
ip(7) <=

IP of IP is
input(1);
input(5);
input(2);
input(0);
input(3);
input(7);
input(4);
input(6);

end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity RIP is
port (input: in std_logic_vector(0 to 7);
rip : out std_logic_vector(0 to 7));
end;
architecture RIP of RIP is
begin
rip(0) <= input(3);
rip(1) <= input(0);
rip(2) <= input(2);
rip(3) <= input(4);
rip(4) <= input(6);
rip(5) <= input(1);
rip(6) <= input(7);
rip(7) <= input(5);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FKFSM is
port (clk, rst, en: in std_logic;
en_f: in std_logic;
out_en: out std_logic);
end;
architecture FKFSM of FKFSM is
type STATES is (INIT, SXOR, SFK);
signal state: STATES;
signal enable: std_logic;
begin
process (clk, rst, en)
begin
if (en='1') then
enable <= '1';
end if;
if (rst='0') then
state<=INIT;
enable<='0';
elsif rising_edge(clk) then
if (enable='1') then
case state is
when INIT=>
out_en <= '0';
state <= SFK;
when SFK=>
if(en_f='1') then
state <= SXOR;
end if;
when SXOR=>
out_en <= '1';

--state <= INIT;

end case;
end if;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity Fk is
port (clk, rst, en: in std_logic;
ip: in std_logic_vector(0 to 7);
key : in std_logic_vector(0 to 7);
fked : out std_logic_vector(0 to 7);
outen_fk: out std_logic);
end;
architecture Fk of Fk is
component F is
port (clk, rst, en_f: in std_logic;
input: in std_logic_vector(0 to 3);
key: in std_logic_vector(0 to 7);
fed : out std_logic_vector(0 to 3);
outen_f: out std_logic);
end component;
component reg4
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 3);
outp: out std_logic_vector(0 to 3));
end component;
component XOR41
port(
inp1: in std_logic_vector(0 to 3);
inp2: in std_logic_vector(0 to 3);
outp: out std_logic_vector(0 to 3));
end component;
component FKFSM
port (clk, rst, en: in std_logic;
en_f: in std_logic;
out_en: out std_logic);
end component;
signal p4ed, r_p4ed, xored: std_logic_vector(0 to 3);
signal out_en, outen_f: std_logic;
begin
FF: F port map(clk, rst, en, ip(4 to 7), key, p4ed, outen_f);
R_41: reg4 port map(outen_f ,clk,p4ed,r_p4ed);
S_XOR: XOR41 port map(r_p4ed, ip(0 to 3), xored);
R_42: reg4 port map(out_en,clk,xored,fked(0 to 3));
FKCTRL: FKFSM port map(clk, rst, en, outen_f, out_en);
fked(4 to 7) <= ip(4 to 7);
outen_fk <= out_en;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity SW is
port (input: in std_logic_vector(0 to 7);
switched : out std_logic_vector(0 to 7));
end;
architecture SW
begin
switched(0)
switched(1)
switched(2)
switched(3)
switched(4)
switched(5)
switched(6)
switched(7)
end;

of SW is
<=
<=
<=
<=
<=
<=
<=
<=

input(4);
input(5);
input(6);
input(7);
input(0);
input(1);
input(2);
input(3);

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity S0 is
port(input: in std_logic_vector(0 to 3);
output: out std_logic_vector(0 to 1));
end;
architecture S0 of S0 is
type array_s is array (0 to 3,0 to 3) of std_logic_vector(0 to 1);
signal s_0 : array_s := (("01","00","11","10"),
("11","10","01","00"),
("00","10","01","11"),
("11","01","11","10"));
begin
output <= s_0(conv_integer(input(0) & input(3)),conv_integer(input(1 to 2)))
;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity S1 is
port(input: in std_logic_vector(0 to 3);
output: out std_logic_vector(0 to 1));
end;
architecture S1 of S1 is
type array_s is array (0 to 3,0 to 3) of std_logic_vector(0 to 1);
signal s_1 : array_s := (("00","01","10","11"),
("10","00","01","11"),
("11","00","01","00"),
("10","01","00","11"));
begin
output <= s_1(conv_integer(input(0) & input(3)),conv_integer(input(1 to 2)))
;
end;
library IEEE;
use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;
entity EP is
port(input: in std_logic_vector(0 to 3);
eped: out std_logic_vector(0 to 7));
end;
architecture EP of EP is
begin
eped(0) <= input(3);
eped(1) <= input(0);
eped(2) <= input(1);
eped(3) <= input(2);
eped(4) <= input(1);
eped(5) <= input(2);
eped(6) <= input(3);
eped(7) <= input(0);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity P4 is
port(input: in std_logic_vector(0 to 3);
p4ed: out std_logic_vector(0 to 3));
end;
architecture P4 of P4 is
begin
p4ed(0) <= input(1);
p4ed(1) <= input(3);
p4ed(2) <= input(2);
p4ed(3) <= input(0);
end;
library IEEE;
use IEEE.std_logic_1164.all;
entity reg10 is
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 9);
outp: out std_logic_vector(0 to 9));
end reg10;
architecture rtl of reg10 is
begin
seq: process (en,clk,inp)
begin
if en='1' then
if rising_edge(clk) then
outp<=inp;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;

entity reg8 is
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 7);
outp: out std_logic_vector(0 to 7));
end reg8;
architecture rtl of reg8 is
begin
seq: process (en,clk,inp)
begin
if en='1' then
if rising_edge(clk) then
outp<=inp;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity reg4 is
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 3);
outp: out std_logic_vector(0 to 3));
end reg4;
architecture rtl of reg4 is
begin
seq: process (en,clk,inp)
begin
if en='1' then
if rising_edge(clk) then
outp<=inp;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
entity reg2 is
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 1);
outp: out std_logic_vector(0 to 1));
end reg2;
architecture rtl of reg2 is
begin
seq: process (en,clk,inp)
begin
if en='1' then
if rising_edge(clk) then

outp<=inp;
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FFSM is
port (clk, rst, en_f: in std_logic;
sig_ep, sig_xor, sig_s0s1: out std_logic;
out_en: out std_logic);
end;
architecture FFSM of FFSM is
type STATES is (INIT, SEP, SXOR, SS0S1,SP4);
signal state: STATES;
signal enable: std_logic;
begin
process (clk, rst, en_f)
begin
if(en_f='1') then
enable <= '1';
end if;
if (rst='0') then
state<=INIT;
enable<='0';
elsif rising_edge(clk) then
if(enable='1') then
case state is
when INIT=>
sig_ep <= '0';
sig_xor <= '0';
sig_s0s1 <= '0';
out_en <= '0';
state <= SEP;
when SEP=>
sig_ep <= '1';
state <= SXOR;
when SXOR=>
sig_ep <= '0';
sig_xor <= '1';
state <= SS0S1;
when SS0S1=>
sig_xor <= '0';
sig_s0s1 <= '1';
state <= SP4;
when SP4=>
sig_s0s1 <= '0';
out_en <= '1';
--state <= INIT;
end case;
end if;
end if;
end process;
end;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity F is
port (clk, rst, en_f:in std_logic;
input: in std_logic_vector(0 to 3);
key: in std_logic_vector(0 to 7);
fed : out std_logic_vector(0 to 3);
outen_f: out std_logic);
end;
architecture F of F is
component S0
port(input: in std_logic_vector(0 to 3);
output: out std_logic_vector(0 to 1));
end component;
component S1
port(input: in std_logic_vector(0 to 3);
output: out std_logic_vector(0 to 1));
end component;
component EP
port(input: in std_logic_vector(0 to 3);
eped: out std_logic_vector(0 to 7));
end component;
component P4
port(input: in std_logic_vector(0 to 3);
p4ed: out std_logic_vector(0 to 3));
end component;
component reg2
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 1);
outp: out std_logic_vector(0 to 1));
end component;
component reg4
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 3);
outp: out std_logic_vector(0 to 3));
end component;
component reg8
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 7);
outp: out std_logic_vector(0 to 7));
end component;
component XOR8
port (
inp1: in std_logic_vector(0 to 7);
inp2: in std_logic_vector(0 to 7);
outp: out std_logic_vector(0 to 7));
end component;
component FFSM
port (clk, rst, en_f: in std_logic;
sig_ep, sig_xor, sig_s0s1: out std_logic;
out_en: out std_logic);
end component;
signal eped, r_eped, xored, r_xored: std_logic_vector(0 to 7);
signal p4ed: std_logic_vector(0 to 3);

signal esed0, r_esed0, esed1, r_esed1: std_logic_vector(0 to 1);

signal sig_ep, sig_xor, sig_s0s1, out_en: std_logic;
begin
EX: EP port map(input, eped);
R_81: reg8 port map(sig_ep,clk,eped,r_eped);
S_XOR: XOR8 port map(r_eped, key, xored);
R_82: reg8 port map(sig_xor,clk,xored,r_xored);
S_0: S0 port map(r_xored(0 to 3), esed0);
R_21: reg2 port map(sig_s0s1,clk,esed0, r_esed0);
S_1: S1 port map(r_xored(4 to 7), esed1);
R_22: reg2 port map(sig_s0s1,clk,esed1, r_esed1);
P_4: P4 port map(input(0 to 1)=>r_esed0, input(2 to 3)=>r_esed1, p4ed=>p
4ed);
R_41: reg4 port map(out_en,clk,p4ed,fed);
FCTRL: FFSM port map(clk, rst, en_f, sig_ep, sig_xor, sig_s0s1, out_en);
outen_f <= out_en;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity XOR8 is
port(
inp1: in std_logic_vector(0 to 7);
inp2: in std_logic_vector(0 to 7);
outp: out std_logic_vector(0 to 7));
end;
architecture XOR8 of XOR8 is
begin
outp<=inp1 xor inp2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity XOR41 is
port(
inp1: in std_logic_vector(0 to 3);
inp2: in std_logic_vector(0 to 3);
outp: out std_logic_vector(0 to 3));
end;
architecture XOR41 of XOR41 is
begin
outp<=inp1 xor inp2;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LS1 is
port (input: in std_logic_vector(0 to 9);
ls1 : out std_logic_vector(0 to 9));
end;
architecture LS1 of LS1 is

begin
ls1 <= input(1 to 4)&input(0)&input(6 to 9)&input(5);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity LS2 is
port (input: in std_logic_vector(0 to 9);
ls2 : out std_logic_vector(0 to 9));
end;
architecture LS2 of LS2 is
begin
ls2 <= input(2 to 4)&input(0 to 1)&input(7 to 9)&input(5 to 6);
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity KFSM is
port (clk, rst: in std_logic;
sig_p10, sig_p8, sig_ls1, sig_ls2: out std_logic;
out_en: out std_logic);
end;
architecture KFSM of KFSM is
type STATES is (INIT, SP10, SLS1, SP81, SLS2, SP82);
signal state: STATES;
begin
process (clk, rst)
begin
if (rst='0') then
state<=INIT;
elsif rising_edge(clk) then
case state is
when INIT=>
out_en <= '0';
sig_p10 <= '0';
sig_p8 <= '0';
sig_ls1 <= '0';
sig_ls2 <= '0';
state <= SP10;
when SP10=>
sig_p10 <= '1';
state <= SLS1;
when SLS1=>
sig_p10 <= '0';
sig_ls1 <= '1';
state <= SP81;
when SP81=>
sig_ls1 <= '0';
sig_p8 <= '1';
state <= SLS2;
when SLS2=>
sig_p8 <= '0';

sig_ls2 <= '1';

state <= SP82;
when SP82=>
sig_ls2 <= '0';
out_en <= '1';
--state <= INIT;
end case;
end if;
end process;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity KEYGEN is
port (clk, rst: in std_logic;
key10: in std_logic_vector(0 to 9);
key2_8: out std_logic_vector(0 to 15);
keys_ready: out std_logic);
end;
architecture KEYGEN of KEYGEN is
component reg10
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 9);
outp: out std_logic_vector(0 to 9));
end component;
component reg8
port (
en,clk: in std_logic;
inp: in std_logic_vector(0 to 7);
outp: out std_logic_vector(0 to 7));
end component;
component P10
port (key: in std_logic_vector(0 to 9);
p10: out std_logic_vector(0 to 9));
end component;
component P8
port (input: in std_logic_vector(0 to 9);
permute8 : out std_logic_vector(0 to 7));
end component;
component LS1
port (input: in std_logic_vector(0 to 9);
ls1 : out std_logic_vector(0 to 9));
end component;
component LS2
port (input: in std_logic_vector(0 to 9);
ls2 : out std_logic_vector(0 to 9));
end component;
component KFSM
port (clk, rst: in std_logic;
sig_p10, sig_p8, sig_ls1, sig_ls2: out std_logic;
out_en: out std_logic);
end component;
signal p10ed, r_p10ed, lsed1, r_lsed1, lsed2, r_lsed2: std_logic_vector(0 to 9);
signal p8ed1, p8ed2: std_logic_vector(0 to 7);
signal sig_p10, sig_p8 ,sig_ls1, sig_ls2, out_en: std_logic;
begin

P_10: P10 port map(key10, p10ed);

R_101: reg10 port map(sig_p10,clk,p10ed,r_p10ed);
LS_1: LS1 port map(r_p10ed, lsed1);
R_102: reg10 port map(sig_ls1,clk,lsed1,r_lsed1);
P_81: P8 port map(r_lsed1, p8ed1);
R_81: reg8 port map(sig_p8,clk,p8ed1,key2_8(0 to 7));
LS_2: LS2 port map(r_lsed1, lsed2);
R_103: reg10 port map(sig_ls2,clk,lsed2,r_lsed2);
P_82: P8 port map(r_lsed2,p8ed2);
R_82: reg8 port map(out_en,clk,p8ed2,key2_8(8 to 15));
KEYFSM: KFSM port map(clk, rst, sig_p10, sig_p8, sig_ls1, sig_ls2, out_e
n);
keys_ready<=out_en;
end;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SFSM is
port (clk, rst: in std_logic;
sig_fk1, sig_fk2: in std_logic;
sig_ip, sig_sw: out std_logic;
out_en: out std_logic);
end;
architecture SFSM of SFSM is
type STATES is (INIT, SIP, SFK1, SSW, SFK2, SRIP);
signal state: STATES;
signal enable: std_logic;
begin
process (clk, rst)
begin
if (rst='0') then
state<=INIT;
elsif rising_edge(clk) then
case state is
when INIT=>
sig_ip <= '0';
sig_sw <= '0';
out_en <= '0';
state <= SIP;
when SIP=>
sig_ip <= '1';
state <= SFK1;
when SFK1=>
sig_ip <= '0';
if(sig_fk1='1') then
state <= SSW;
end if;
when SSW=>
sig_sw <= '1';
state <= SFK2;
when SFK2=>
sig_sw <= '0';
if(sig_fk2='1') then
state <= SRIP;
end if;
when SRIP=>

out_en <= '1';

--state <= INIT;
end case;
end if;
end process;
end;
-------------- encrypt -------------library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity sdes is
port(clk, rst: std_logic;
input :in std_logic_vector(0 to 7);
key: in std_logic_vector(0 to 9);
output: out std_logic_vector(0 to 7));
end;
architecture sdes of sdes is
component reg8
port (en,clk: in std_logic;
inp: in std_logic_vector(0 to 7);
outp: out std_logic_vector(0 to 7));
end component;
component IP
port (input: in std_logic_vector(0 to 7);
ip : out std_logic_vector(0 to 7));
end component;
component Fk
port (clk, rst, en: in std_logic;
ip: in std_logic_vector(0 to 7);
key : in std_logic_vector(0 to 7);
fked : out std_logic_vector(0 to 7);
outen_fk: out std_logic);
end component;
component SW
port (input: in std_logic_vector(0 to 7);
switched : out std_logic_vector(0 to 7));
end component;
component RIP
port (input: in std_logic_vector(0 to 7);
rip : out std_logic_vector(0 to 7));
end component;
component KEYGEN
port (clk, rst: in std_logic;
key10: in std_logic_vector(0 to 9);
key2_8: out std_logic_vector(0 to 15);
keys_ready: out std_logic);
end component;
component SFSM
port (clk, rst: in std_logic;
sig_fk1, sig_fk2: in std_logic;
sig_ip, sig_sw: out std_logic;
out_en: out std_logic);
end component;

signal
signal
signal
signal

switch, r_switch, fked1, fked2: std_logic_vector(0 to 7);

r_fked1,r_fked2, riped, iped, r_iped: std_logic_vector(0 to 7);
sig_ip, sig_sw, out_en, en_fk1, en_fk2, keys_ready: std_logic;
keys: std_logic_vector(0 to 15);

begin
KK: KEYGEN port map(clk,rst,key,keys, keys_ready);
IP_0: IP port map(input, iped);
R_81: reg8 port map(sig_ip,clk,iped,r_iped);
FK1: Fk port map(clk, rst, keys_ready, r_iped, keys(0 to 7), fked1, en_f
k1);
R_82: reg8 port map(en_fk1,clk,fked1,r_fked1);
SW_0: SW port map(r_fked1, switch);
R_83: reg8 port map(sig_sw,clk,switch,r_switch);
FK2: Fk port map(clk, rst, sig_sw, r_switch, keys(8 to 15), fked2, en_fk
2);
R_84: reg8 port map(en_fk2,clk,fked2,r_fked2);
RIP_0: RIP port map(r_fked2, riped);
R_85: reg8 port map(out_en,clk,riped,output);
ACTRL: SFSM port map(clk, rst, en_fk1, en_fk2, sig_ip, sig_sw, out_en);