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Ec6601 Vlsi
Ec6601 Vlsi
QUESTION BANK
SUBJECT CODE: EC6601
YEAR/BRANCH: III / ECE
UNIT I
MOS TRANSISTOR PRINCIPLE
Part A
1. What are four generations of Integration Circuits?
2.What are the different layers in MOS transistors?
3.What is Enhancement mode transistor?
4.What is Depletion mode Device?
5.When the channel is said to be pinched off?
6.Give the different types of CMOS process?
7.Draw the schematic diagram of the tristate inverter. (May/June 2009)
8. What is the fundamental goal in Device modeling?
9. Define Short Channel devices?
10.What is pull down and pull up device?
11.Why NMOS technology is preferred more than PMOS technology?
12.What are the different operating regions for an MOS transistor?
13.What are the different MOS layers?
14.What is Stick Diagram?
15.What are the uses of Stick diagram?
16.Give the various color coding used in stick diagram?
17.Define Threshold voltage in CMOS?
18.What is Body effect?(May/June 2009)
19.What is Channel-length modulation?(May/June 2009)
20.Give the basic inverter circuit.
21.Give the CMOS inverter DC transfer characteristics and operating region
22Define Rise time,Fall time,and Delay time.(Nov/Dec 2008)
23.State the differences between CMOS and Bipolar Technology(April/May 2008)
24.Define SSI, MSI, LSI and VLSI. (May/June 2009)
25.Give the exp. for Rise Time & Fall Time in CMOS Inverter Circuit. (April/May
2008)
PART B
1.Draw a NMOS inverter, its stick diagram and MOS layout diagram.(April/May
2008)
19.Explain different types of power dissipation in Cmos circiuts and how it can be
reduced.
20.Interconnect increases circuit delay,discuss.
21.Explain the different realibility problems(hard errors) in detail.
22.With neat diagram of Latch-up effect in p-well structure explain Latch-up
problem and the steps involved to overcome it. (April/May 2008)
23.What are Ratioed circuits explain different types in detail.
24.Explain different Dynamic circuits in detail.
25.Explain the design of latches and flip flops using transmission gate.
26.Write short notes on Time Borrowing. Draw timing diagram and explain.
27.Explain how communication is done between two asynchronous systems.
UNIT III
SEQUENTIAL LOGIC CIRCUITS
Part A
1. What is synchronous sequential logic circuit?
2. What is bistability principle?
3. What is metastable?
4. List the timing parameters of reisters.
5. What is race condition?
6. Define global clock?
7. What is clock skew?
8. What is clock jitter?
9. Define pipelining.
10.What is sense amplifier?
11.Design one transistor D-RAM cell. (May-June 2015)
12.Differentiate latch and flip-flop.
(Nov-Dec 2014)
13.What are synchronizers
(May-June 2014/13)
14.Design a one bit dynamic register using pass transistor. (Nov-Dec 2013)
15.Mention the qualities of an ideal sequencing method. (Nov-Dec 2012)
16.What are the Factors That Cause Timing Failures? (May-June 2012)
17.What are the different memory control circuits?
18.Differentiate between S-RAM and D-RAM.
19.What are the different low power memory circuits?
20.What are the clocking strategies of Sequential circuit design?
PART-B
1. a) Design a D-latch and D flip-flop using Transmission gate
b) Design a one bit dynamic inverting and 2 bit non inverting register using
pass transistor
(May-June 2015/Nov-Dec 2013)
2. What are Klass semi dynamic flip flops? Explain with their logic circuits.
(Nov-Dec 2014)
3. Explain the methodology of sequential circuit design of latches and flip-flops.
(May-June 2014)
4. a) Draw and explain the operation of conventional CMOS, pulsed and
resettable latches
5.
6.
7.
8.
UNIT V
IMPLEMENTATION STRATEGIES
Part A
Differentiate between the standard cell based ASICs and full custom ASIC.
What are macros?
What is Programmable Interconnects?
Compare Antifuse, SRAM, EPROM and EEPROM technologies with respect to
erasing mechanism.
5. What is meant by CBIC?
6. How granularity of logic block influences the performance of an FPGA?
7. What is meant by FPGA?
8. Draw the ACT1 logic module
9. What is the difference between Act2 and Act3 logic modules
10. Define the terms connectivity matrix, and PIPs.
11. Distinguish between Altera 5000 and 7000.
12. Give the XILINX Configurable Logic Block.
13. Differentiate between Altera MAX 9000 and Altera FLEX interconnects
architecture?
14. Compare between Xilinx LCA, Actel Act and Altera MAX architecture?
15. What are the advantages and disadvantages of FPGA compared to ASIC?
16. Define flexible blocks.
17. What is standard cell?
18. Define Manufacturing lead time.
1.
2.
3.
4.
Part B
1. Describe the salient features of Xilinx LCA interconnect architecture.
2. Explain configurable logic block and Programmable routing matrix of Xilinx
XC 4000 FPGA.
3. How sequential circuit is implemented in Altera Flex 8000 FPGA.
4. Explain the configurable logic block of Xilinx XC4000 FPGA.
5. Explain the performance & characteristics for the following design styles.
a) Standard cells.
b) Cell based ASIC.
6. a). What are the various methodologies of FPGA? Explain the same with neat
diagram?
b). Discuss the different types of I/O cells used in programmable ASICs
7. Explain the ASIC design flow with a neat diagram and write the difference
between custom IC and standard IC?
8. Explain in detail about the FPGA building block architectures with neat
diagrams.
9. Explain about ASIC cell libraries in detail.