Sequential vs Combinational Circuits

Memory vs memoryless circuits

Basic Memory Elements

Latch, Flip-flop (Level-sensitive vs Edge-sensitive)

Basic Model of a Synchronous Circuit

Inference of Basic Memory Elements

D latch

Inference of Basic Memory Elements

D flip-flop

Inference of Basic Memory Elements

D flip-flop

Inference of Basic Memory Elements

D flip-flop

Inference of Basic Memory Elements

D flip-flop with Asynchronous Reset

Inference of Basic Memory Elements

Register (8-bit) with Asynchronous Reset

D FF with Sync Enable

Arbitrary Sequence Counter

Binary Counter Free-Running

Binary Counter featured/controlled

Decade (mod-10) Counter

Programmable mod-m Counter

Efficient Programmable mod-m Counter

Gray Code Incrementor

 Direct Implementation

Gray Counter

Linear Feedback Shift Register (LFSR)

 E.g. 4-bit LFSR