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All Devices Discontinued!: GAL 22V10 Device Datasheet
All Devices Discontinued!: GAL 22V10 Device Datasheet
September 2010
GAL22V10D
Product Status
Reference PCN
PCN#09-10
PCN#13-10
PCN#09-10
Discontinued
PCN#13-10
PCN#06-07
PCN#09-10
PCN#13-10
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
GAL22V10D
(Contd)
Product Status
Reference PCN
PCN#13-10
PCN#09-10
Discontinued
PCN#13-10
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
Specifications GAL22V10
ree
Lead-Fage
P a c k ns
Optio le!
b
Availa
GAL22V10
Features
HIGH PERFORMANCE E2CMOS TECHNOLOGY
4 ns Maximum Propagation Delay
Fmax = 250 MHz
3.5 ns Maximum from Clock Input to Data Output
UltraMOS Advanced CMOS Technology
RESET
I/CLK
8
OLMC
I/O/Q
OLMC
I/O/Q
I
10
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
12
PROGRAMMABLE
AND-ARRAY
(132X44)
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
14
16
16
14
12
APPLICATIONS INCLUDE:
DMA Control
State Machine Control
High Speed Graphics Processing
Standard Logic Speed Upgrade
OLMC
10
PRESET
Pin Configuration
I/O/Q
28
I/O/Q
Vcc
I/CLK
NC
PLCC
Description
DIP
26
25
I
I
I/O/Q
GAL22V10
NC
Top View
23
21
11
I/O/Q
I/O/Q
I/O/Q
I/O/Q
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
13
18
12
13
12
GND
I
I
I
I
I
GND
6
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
Vcc
24
GAL
22V10
I/O/Q
Top View
1
Vcc
GAL22V10
I/CLK
I
I
I
24
NC
SOIC
I/O/Q
I/O/Q
19
18
16
NC
14
12
I/CLK
I/O/Q
GND
I/O/Q
Copyright 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
22v10_12
December 2006
Specifications GAL22V10
GAL22V10 Ordering Information
Conventional Packaging
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
2.5
3.5
140
GAL22V10D-4LJ
28-Lead PLCC
140
GAL22V10D-5LJ
28-Lead PLCC
7.5
Ordering #
Package
4. 5
4.5
140
GAL22V10D-7LP
4.5
4.5
140
GAL22V10D-7LJ
28-Lead PLCC
55
GAL22V10D-10QP
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
10
Icc (mA)
15
25
10
15
15
55
GAL22V10D-10QJ
28-Lead PLCC
130
GAL22V10D-10LP
130
GAL22V10D-10LJ
28-Lead PLCC
30
GAL22V10D-10LS1
24-Pin SOIC
55
GAL22V10D-15QP
55
GAL22V10D-15QJ
28-Lead PLCC
90
GAL22V10D-15LP
90
GAL22V10D-15LJ
28-Lead PLCC
90
GAL22V10D-15LS1
24-Pin SOIC
55
GAL22V10D-25QP
55
GAL22V10D-25QJ
28-Lead PLCC
90
GAL22V10D-25LP
90
GAL22V10D-25LJ
28-Lead PLCC
90
GAL22V10D-25LS1
24-Pin SOIC
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
Tsu (ns)
Tco (ns)
Icc (mA)
7.5
4.5
160
GAL22V10D-7LPI
4.5
4.5
160
GAL22V10D-7LJI
28-Lead PLCC
160
GAL22V10D-10LPI
160
GAL22V10D-10LJI
28-Lead PLCC
130
GAL22V10D-15LPI
130
GAL22V10D-15LJI
28-Lead PLCC
130
GAL22V10D-20LPI
130
GAL22V10D-20LJI
28-Lead PLCC
130
GAL22V10D-25LPI
130
GAL22V10D-25LJI
28-Lead PLCC
10
15
20
25
10
14
15
10
15
Ordering #
Package
Specifications GAL22V10
Lead-Free Packaging
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
2.5
3.5
14 0
GAL22V10D-4LJN
140
GAL22V10D-5LJN
7.5
4.5
4. 5
14 0
GAL22V10D-7LPN
4.5
4.5
14 0
GAL22V10D-7LJN
55
GAL22V10D-10QPN
55
GAL22V10D-10QJN
130
GAL22V10D-10LPN
Package
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
10
Ordering #
15
25
10
15
15
130
GAL22V10D-10LJN
55
GAL22V10D-15QPN
55
GAL22V10D-15QJN
90
GAL22V10D-15LPN
90
GAL22V10D-15LJN
55
GAL22V10D-25QPN
55
GAL22V10D-25QJN
90
GAL22V10D-25LPN
90
GAL22V10D-25LJN
10
15
20
25
Tsu (ns)
Tco (ns)
Icc (mA)
Ordering #
Package
4.5
160
GAL22V10D-7LPNI
4.5
4.5
160
GAL22V10D-7LJNI
160
GAL22V10D-10LPNI
160
GAL22V10D-10LJNI
10
14
15
10
15
130
GAL22V10D-15LPNI
130
GAL22V10D-15LJNI
130
GAL22V10D-20LPNI
130
GAL22V10D-20LJNI
130
GAL22V10D-25LPNI
130
GAL22V10D-25LJNI
XXXXXXXX _ XX
X XX X
Grade
Speed (ns)
L = Low Power
Power
Q = Quarter Power
Blank = Commercial
I = Industrial
Specifications GAL22V10
Output Logic Macrocell (OLMC)
The GAL22V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to eight
product terms (pins 14 and 23, DIP pinout), two have ten product
terms (pins 15 and 22), two have twelve product terms (pins 16 and
21), two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
A R
4 TO 1
MUX
CLK
SP
2 TO 1
MUX
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
on (dedicated output), off (dedicated input), or product-term
driven (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMCs D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flops /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
Specifications GAL22V10
Registered Mode
AR
AR
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
CLK
CLK
SP
SP
ACTIVE LOW
ACTIVE HIGH
S0 = 0
S1 = 0
S0 = 1
S1 = 0
Combinatorial Mode
ACTIVE LOW
ACTIVE HIGH
S0 = 0
S1 = 1
S0 = 1
S1 = 1
Specifications GAL22V10
GAL22V10 Logic Diagram / JEDEC Fuse Map
DIP (PLCC) Package Pinouts
1 (2)
0
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
0000
0044
.
.
.
0396
OLMC
S0
5808
S1
5809
0440
.
.
.
.
0880
10
OLMC
22 (26)
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
S0
5810
S1
5811
23 (27)
2 (3)
0924
.
.
.
.
.
1452
12
OLMC
S0
5812
S1
5813
3 (4)
1496
.
.
.
.
.
.
2112
14
OLMC
21 (25)
20 (24)
S0
5814
S1
5815
4 (5)
2156
.
.
.
.
.
.
.
2860
16
OLMC
19 (23)
S0
5816
S1
5817
5 (6)
2904
.
.
.
.
.
.
.
3608
16
OLMC
18 (21)
S0
5818
S1
5819
6 (7)
3652
.
.
.
.
.
.
4268
14
OLMC
17 (20)
S0
5820
S1
5821
7 (9)
4312
.
.
.
.
.
4840
12
OLMC
S0
5822
S1
5823
8 (10)
4884
.
.
.
.
5324
10
OLMC
S0
5824
S1
5825
9 (11)
5368
.
.
.
5720
OLMC
S0
5826
S1
5827
10 (12)
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
5764
11 (13)
5828, 5829 ...
Electronic Signature
L
S
B
16 (19)
15 (18)
14 (17)
13 (16)
Specifications
SpecificationsGAL22V10D
GAL22V10
Absolute Maximum Ratings1
Industrial Devices:
Ambient Temperature (TA) ............................ -40 to 85C
Supply voltage (VCC)
with Respect to Ground ..................... +4.50 to +5.50V
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
DC Electrical Characteristics
SYMBOL
VIL
VIH
IIL1
IIH
VOL
VOH
IOL
IOH
IOS2
MIN.
TYP.3
MAX.
UNITS
Vss 0.5
0.8
2.0
Vcc+1
PARAMETER
CONDITION
100
10
0.4
2.4
16
mA
3.2
mA
30
130
mA
COMMERCIAL
ICC
Operating Power
Supply Current
INDUSTRIAL
ICC
Operating Power
Supply Current
VCC = 5V
L-4/-5/-7
90
140
mA
L-10
90
130
mA
L-15/-25
75
90
mA
Q-10/-15/-25
45
55
mA
L-7/-10
90
160
mA
L-15/-20/-25
75
130
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 C
Specifications
GAL22V10D
Specifications
GAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions
PARAM
TEST
COND.1
tpd
tco
tcf2
tsu
th
COM
COM
COM/IND
-4
-5
-7
DESCRIPTION
UNITS
7.5
ns
3.5
4.5
ns
2.5
ns
2.5
4.5
ns
ns
167
142.8
111
MHz
200
166
133
MHz
250
200
166
MHz
2.5
ns
2.5
ns
7.5
ns
tdis
tar
5.5
7.5
ns
4.5
5.5
ns
tarw
tarr
tspr
4.5
4.5
ns
ns
ns
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
fmax3
twh
twl
ten
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
pF
CI/O
I/O Capacitance
pF
Specifications
SpecificationsGAL22V10D
GAL22V10
AC Switching Characteristics
Over Recommended Operating Conditions
PARAM.
TEST
COND.1
COM / IND
IND
COM / IND
-10
-15
-20
-25
DESCRIPTION
UNITS
10
15
20
25
ns
10
15
ns
2.5
2.5
13
ns
10
12
15
ns
ns
83.3
55.5
41.6
33.3
MHz
110
80
45.4
35.7
MHz
125
83.3
50
38.5
MHz
10
13
ns
10
13
ns
10
15
20
25
ns
15
20
25
ns
13
20
25
25
ns
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
tpd
tco
tcf2
COM / IND
tsu
th
fmax3
twh
twl
ten
tdis
tar
tarw
tarr
15
20
25
ns
10
20
25
ns
tspr
10
14
15
ns
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
pF
CI/O
I/O Capacitance
pF
Specifications GAL22V10
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
tsu
th
t pd
CLK
COMBINATORIAL
OUTPUT
tco
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
REGISTERED
OUTPUT
Combinatorial Output
1/ fmax
(external fdbk)
Registered Output
INPUT or
I/O FEEDBACK
t dis
t en
OUTPUT
CLK
tsu
t cf
REGISTERED
FEEDBACK
tw l
tw h
CLK
1 / fm a x
(w/o fdbk)
Clock Width
INPUT or
I/O FEEDBACK
DRIVING SP
INPUT or
I/O FEEDB ACK
DRIVI NG AR
tsu
t spr
th
tarw
CLK
CLK
tarr
tco
R E G I S T ER E D
OUTPUT
REGISTERED
OUTPUT
tar
Synchronous Preset
Asynchronous Reset
10
Specifications GAL22V10
fmax Descriptions
CL K
LOGIC
ARR AY
CLK
LOGIC
ARRAY
R EG I S T E R
REGISTER
ts u
tc o
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
t cf
t pd
Note: fmax with external feedback is calculated from measured tsu and tco.
CLK
LOGIC
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tcf = 1/fmax - tsu). The value of tcf is
used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
REGISTER
tsu + th
11
Specifications GAL22V10
Switching Test Conditions
Input Pulse Levels
GND to 3.0V
D-4/-5/-7
Fall Times
D-10/-15/-20/-25
1.5V
1.5V
Output Load
Test Condition
A
B
See Figure
CL
50
50pF
50
50pF
50
50pF
50
50pF
50
50pF
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
R1
+1.45V
R2
CL
300
390
50pF
Active High
390
50pF
Active Low
300
390
50pF
Active High
390
5pF
Active Low
300
390
5pF
Test Condition
A
TEST POINT
+5V
R1
TEST POINT
R2
C L*
12
Z0 = 50, CL*
R1
Specifications GAL22V10
Electronic Signature
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
The GAL22V10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
Input Buffers
The JEDEC map for the GAL22V10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However,
the GAL22V10 device can still be programmed with a standard
22V10 JEDEC map (5828 fuses) with any qualified device programmer.
GAL22V10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
Security Cell
The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However,
Lattice Semiconductor recommends that all unused inputs and
tri-stated I/O pins be connected to an adjacent active input, Vcc,
or ground. Doing so will tend to improve noise immunity and
reduce Icc for the device. (See equivalent input and I/O schematics on the following page.)
I n p u t C u r r e n t (u A )
Latch-Up Protection
-20
-40
-60
1.0
2.0
3.0
In p u t V o lt ag e ( V o lt s)
Device Programming
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
13
4.0
5.0
Specifications GAL22V10
Power-Up Reset
Vcc (min.)
Vcc
t su
t wl
CLK
t pr
Internal Register
Reset to Logic "0"
ACTIVE LOW
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
ACTIVE HIGH
OUTPUT REGISTER
Device Pin
Reset to Logic "0"
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
INTERNAL REGISTER
Q - OUTPUT
Circuitry within the GAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
PIN
PIN
Feedback
Vcc
Active Pull-up
Circuit
Active Pull-up
Circuit
Vcc
ESD
Protection
Circuit
Vref
Tri-State
Control
Vcc
PIN
Vcc
Vref
Data
Output
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
14
Specifications GAL22V10
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
0.95
RISE
FALL
1.05
0.95
RISE
FALL
1.05
Normalized Tsu
Normalized Tco
RISE
FALL
1.1
0.95
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Normalized Tpd
1.05
1.1
1.1
0.9
0.9
4.5
4.75
5.25
0.9
4.5
5.5
4.75
5.25
5.5
4.5
1.1
1.2
RISE
FALL
1.1
0.9
-55
25
50
75
100
1.1
0.8
-25
Temperature (deg. C)
25
50
75
125
-55
-25
-0.1
RISE
FALL
-0.2
-0.1
-0.2
RISE
FALL
-0.3
-0.4
10
10
12
12
RISE
FALL
-4
50
100
150
200
250
300
RISE
FALL
-4
0
25
50
75
100
Temperature (deg. C)
-0.3
100
Temperature (deg. C)
125
RISE
FALL
0.9
0.8
-25
5.5
0.9
-55
5.25
1.3
Normalized T
Normalized Tco
RISE
FALL
1.2
1.2
4.75
1.3
Normalized Tpd
50
100
150
200
250
15
300
125
Specifications GAL22V10
GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
Voh vs Ioh
3.95
0.6
3.85
3.75
Vol (V)
Voh (V)
0.4
Voh (V)
0.2
3.65
3.55
3.45
3.35
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
3.25
3.15
0.00
10
15
20
25
30
35
40
10 1 5 2 0 2 5 3 0 3 5 4 0 4 5 50 55 60
0.9
5.25
0.9
0.7
-55
5.5
25
50
88
100
125
20
40
3
2
60
80
100
0.5
1.5
2.5
Vin (V)
3.5
4.5
-3
1.05
-2.5
-2
-1.5
Vik (V)
16
-1
-0.5
15
25
50
Frequency (MHz)
Iik (mA)
1.1
0.95
-25
Temperature (deg. C)
5.00
1.15
1.1
0.8
4.75
4.00
Normalized Icc
Normalized Icc
Normalized Icc
3.00
1.2
1.2
1.1
2.00
Ioh(mA)
1.3
1.2
0.8
4.5
1.00
Ioh(mA)
Iol (mA)
75
1 00
Specifications GAL22V10
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
0.95
RISE
FALL
Normalized Tsu
Normalized Tco
RISE
FALL
1.05
1.05
RISE
FALL
1.1
0.9
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Normalized Tpd
1.1
0.8
0.95
0.9
4.5
4.75
5.25
4.5
5.5
4.75
5.25
4.5
5.5
RISE
FALL
1.2
RISE
FALL
1.1
0.9
0.9
1.1
0.9
25
50
75
100
0.8
-55
125
-25
25
50
75
100
0.8
-55
125
-25
Temperature (deg. C)
Temperature (deg. C)
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.5
-0.6
-0.7
RISE
FALL
-0.8
-0.9
-0.4
-0.5
-0.6
-0.7
RISE
FALL
-0.8
-0.9
-1
-1
-1.1
-1.1
10
10
12
12
RISE
FALL
-4
RISE
FALL
-4
0
50
100
150
200
250
300
50
100
150
200
250
17
25
50
75
100
Temperature (deg. C)
-25
0.8
-55
5.5
1.3
Normalized Tsu
Normalized Tco
1.1
5.25
1.2
RISE
FALL
1.3
1.2
4.75
Normalized Tpd
300
125
Specifications GAL22V10
GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
0.5
Voh vs Ioh
3.8
3.7
0.4
3.6
0.2
Voh (V)
Voh (V)
Vol (V)
3.5
0.3
3.4
3.3
3.2
3.1
1
0.1
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
2.9
10
15
20
25
30
10
15
30
35
1.1
1.2
Normalized Icc
1.3
1.05
0.95
0.9
0.85
5.25
0.9
10
20
30
40
Iik (mA)
5
4
25
100
60
70
80
90
0.5
1.5
2.5
Vin (V)
3.5
4.5
100
-2.5
1.05
-2
-1.5
-1
Vik (V)
18
-0.5
15
25
50
Frequency (MHz)
50
1.1
0.95
5.00
Temperature (deg. C)
10
4.00
1.1
3.00
1.15
0.7
-55
5.5
2.00
1.2
0.8
4.75
1.00
Ioh (mA)
1.15
4.5
2.8
0.00
40
Normalized Icc
Normalized Icc
25
Ioh (mA)
Iol (mA)
20
75
100
Specifications GAL22V10
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.15
0.95
Normalized Tsu
RISE
FALL
1.1
Normalized Tco
RISE
FALL
1.05
1.05
0.95
RISE
FALL
1.1
0.9
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Normalized Tpd
1.1
0.9
4.5
4.75
5.25
0.9
4.5
5.5
4.75
0.8
4.5
5.5
1.1
1
0.9
5.25
5.5
1.45
1.35
RISE
FALL
1.2
Normalized Tsu
Normalized Tco
RISE
FALL
1.3
1.2
4.75
1.1
0.9
RISE
FALL
1.25
1.15
1.05
0.95
0.85
25
50
75
100
125
0.8
-55
Temperature (deg. C)
25
50
75
100
0.75
-55
1 25
-25
Temperature (deg. C)
-25
-0.4
RISE
FALL
-0.8
-1.2
-0.4
RISE
FALL
-0.8
-1.2
10
10
20
20
16
16
RISE
FALL
12
8
4
0
RISE
FALL
12
8
4
0
-4
-4
-8
0
50
100
150
200
250
3 00
50
100
150
200
250
19
25
50
75
Temperature (deg. C)
-25
Normalized Tpd
5.25
1.3
0.8
-55
3 00
100
1 25
Specifications GAL22V10
GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
Voh vs Ioh
4.5
0.6
4.5
4
3.5
Voh (V)
Vol (V)
0.2
Voh (V)
0.4
2.5
2
1.5
3.5
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
0.5
0
10
15
20
25
30
35
40
20
0.9
1.4
1.25
1.3
1.15
1.05
0.95
0.85
5.25
5.5
0.75
-55
25
50
88
100
1 25
10
30
Iik (mA)
20
5
4
3
40
50
60
70
80
0.5
1.5
2.5
Vin (V)
3.5
4.5
90
-2.5
4.00
5.00
1.2
1.1
1
-2
-1.5
-1
Vik (V)
20
-0.5
15
25
50
Frequency (MHz)
3.00
0.9
-25
Temperature (deg. C)
2.00
1.35
Normalized Icc
Normalized Icc
1.1
4.75
1.00
Ioh (mA)
1.2
0.8
4.5
2.5
0.00
60
Ioh (mA)
Iol (mA)
Normalized Icc
40
75
1 00
Specifications GAL22V10
Notes
Revision History
Version
Change Summary
22v10_08
August 2004
22v10_09
July 2006
22v10_10
August 2006
22v10_11
December 2006
22v10_12
A
D LL
IS
C DE
O
N VIC
TI
N ES
U
ED
Date
21