Design and Simulation of a 24.

0 GHz RFIC VCO

with 2.0 GHz Tunning Range
Sahand Noorizadeh
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia 30332–0250
Email: sahand@gatech.edu

Abstract—This paper is the final project report of the RF

Engineering II (ECE 4418) course in Spring 2010 at Georgia
Institute of Technology.

I. I NTRODUCTION
A commonly used topology for voltage controlled oscil-
lators is the LC tank with negative resistance feedback. An
ideal LC tank circuit would oscillate at the resonant frequency
indefinitely without damping but the parasitic resistance of the
components eventually dissipate the power and the oscillation
will not be sustained. The negative resistance feedback is used
to remove the equivalent parallel parasitic resistance of an
LC tank circuit. The idea of the negative resistance is that
by increasing the voltage, the current draw decreases. An
example of such device are tunneling diodes. Their I − V
curve starts behaving similar to a normal diode but within
a certain voltage range the current flow takes a reverse turn
because its resistance increases as the voltage increases. This
behavior can be replicated with a BJT by using the collector
port of the transistor as the negative resistor.
In discrete RF circuits, it is good practice (and sometimes
necessary) to use minimum number of components to reduce
the noise and other unwanted effects; however, in IC de-
sign, there is a unique option of modifying the components
structure to improve performance. For example, depending on
the fabrication technology, the emitter area of transistors can
be changed to achieve a certain gain and noise figure. This
flexibility allows RFIC designers to use topologies usually
avoided by discrete microwave circuit designers.
This paper is the report of the design process and simulation
of a 24.0 GHz VCO with 2 GHz tunning range using ibm7hp
technology.
II. BACKGROUND
For a self-sustaining oscillator at a resonance frequency ω0 ,
the Barkhuasen criteria must hold. This means that the overall
system frequency response H(jω) = +1. In other words,
at the resonance frequency, the gain must be equal 1 and
the phase shift be equal to 0 degree. A more intuitive way
of understanding the LC oscillator with negative resistance
feedback is to note that the LC circuit must be ideal (i.e. no
parasitic resistance) in order for it to sustain the oscillation.
Figure 1 shows this concept. Where the resonance frequency
Fig. 1. Block diagram of an LC tank oscillator with negative resistance
feedback.
is given by Eq. 1
1
fr = √ (1)
2π LC
A. BJT as a Negative Resistor Network
The idea behind the negative resistance is that when the
voltage increases the current flow decreases. The collector port
of a BJT can act as a negative resistor. When the voltage of the
collector increases it increases the emitter voltage which tries
to push the base-emitter junction to the OFF state. This in turn
reduces the base current which decreases the collector voltage
by 1/β. Therefore, any increase in the collector voltage will
reduce the collector current.
B. Phase Noise
In the frequency domain, an ideal oscillator will have a
single spectral line at the desired oscillation frequency. But a
real oscillator has a spectrum similar to a modulated signal
with the oscillation frequency as the carrier. All the unwanted
spectral lines are considered noise. To quantify the phase
noise, a unit bandwidth at an offset ∆ω with respect to
ωc is considered. Then the noise power is measured in this
bandwidth and is divided by the power of the carrier frequency.
The results are presented in ”dB with respect to carrier or dB-
c.
III. D ESIGN A PPROACH
The ibm7hp technology in Cadence design suite was used
for this design project. The LC tank circuit, shown in Figure
4, was designed with two varactors in series with the tuning
voltage node in the middle and two inductors in series.
The physical dimensions of the varactors and inductors were
chosen to have a resonance frequency of 25.0 GHz with
V tune = 1V .
The negative resistance network was chosen to be a cross-
coupled BJT with a current source as the bias circuit. The
collectors of this circuit will be ports of the negative resistance
block. Figure 3 shows this circuit.
input capacitor to the buffer circuit was placed to block the DC
components feeding back to the VCO core circuit in order to
improve the phase. This, however, added additional attenuation
but as it will be discussed in the following sections, the phase
noise was improved by a considerable amount to sacrifice gain.

Fig. 2. Tank circuit.

Fig. 5. Output buffer circuit.

Fig. 3. Negative Resistance circuit.

Fig. 6. The overall VCO circuit.

The overall circuit of the designed VCO is shown in Figure

6 with the VCO core circuit broken into to hierarchical blocks.
Fig. 4. Tank circuit.
IV. R ESULTS
Loading the VCO circuit would cause the Q of the LC
tank to degrade and shift the oscillation frequency. In order to TABLE I
prevent this, a buffer network for each of the output nodes was VCO F REQUENCY OVER THE T UNNING VOLTAGE R ANGE
designed to provide a large input resistance. Figure 5 shows
Vtune Frequency
the buffer circuit topology designed as the load for the VCO 0.6 V 25.0 GHz
core circuit. A BJT current source was also used to provide a 0.5 V 24.67 GHz
stable bias point for the emitter-follower BJT as well a BJT 0.45 V 24.0 GHz
diode to reverse bias its base-collector junction. The 100f F 0.4 V 23.0 GHz
 All the simulations were performed by the Agilent ADS
simulator triggered by the Analog Environment utility of the
Cadence design suite. Figures 7 to 10 show the simulated
results. All the spectrum and phase noise simulations were
performed at the output of the VCO core. The phase noise
simulation was done by the harmonic balance (hb) simulation
of ADS with a single tone at 24.0 GHz.

Fig. 10. Phase noise simulation at 100 M Hz separation from 24.0 GHz.

TABLE II
VCO S IMULATED PARAMETERS R ESULTS AT 24.0 GHz

Phase Noise -112.873 dB-c

VCO core Swing Voltage 55 mVpp
Buffer Output Swing Voltage 28 mVpp
Dissipated Power 61.85 mW

Fig. 7. Transient analysis of the output of the core VCO circuit.

the impedance of the capacitor in series with the base of the
emitter-follower in the buffer circuit. These capacitors were
placed to block the DC feedback to the VCO core circuit
to improve the phase noise. Without these capacitors, the
phase noise was approximately -83 dB-c. The values for these
capacitors were chosen by tweaking its values until a good
phase noise improvement was achieved. Also these values
had to be small enough in order not to affect the oscillation
frequency. The values of the inductors of the tank circuit had
to be tweaked to compensate for this frequency shift. The
improvement in noise phase was preferred in this design. One
way to improve the output swing voltage but not used in this
design is to cascade a common-emitter amplifier.
Fig. 8. Transient analysis of the output of the buffer circuit.
The DC-block capacitor of the buffer voltage also made it
necessary to bias the buffer transistors using a separate bias
network. At first, resistor voltage dividers were tried to bias the
common-collector BJT’s of the buffer circuit but this degraded
the phase noise. As a result, another BJT was used as a diode
to reveres bias the base-collectors of the buffer transistor.

Fig. 9. Spectrum analysis.

V. D ISCUSSION
From the transient analysis of the buffer and the VCO core,
it is shown that about 50% of the voltage from the VCO core
is attenuated by the buffer networks. This large loss is due to