Qualcomm Interview Questions

1. How do you proceed to floorplan?

2. What are the checks you do before floorplan?
3. How do you place macros?
4. What are the guidelines to place macros?
5. Channel length calculation?
6. What are the issues that you faced in floorplan?
7. What are the issues that you faced in placement?
8. How do you resolve congestion and what are the techniques?
9. What is meant by cellpadding?
10. To which cells you add cellpading?
11. Why you add cell padding to complex cells?
12. How do you finalize the placement?
13. Equation dor setuptime and expalin in detail?
14. Equation dor holdtime and expalin in detail?
15. What are early path delay and latepath delay and which is applied to clockpa
th and datapath for setup time and holdtime analysis?
16. What is slew?
17. Will positive skew effect setup or hold?
18. What is your design latency?
19. What is AOCV?
20. Why do you fix hold violation after CTS?
21. What is useful skew?
22. What is the difference betweeen latency and insertion delay?
23. What us the max logic depth in your design?
24. What are the major issues faced in routing stage?