2-bit ripple binary counter using JK

flip flops (asynchronous counters)

1
J

Q0

Q1

K
Q0
CP
Q0
Q0
Q1

g
n

E
O

o
D

c
.
rs

e
e
in

CP

m
o

J
0
0
1
1

Q1

a
a
F

K
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)

3-bit ripple binary counter using JK

flip flops (asynchronous counters)

1
J
CP

Q0

Q0

E
O

Q0

Q1
Q2

a
a
F

o
D

Q2

m
o

c
.
rs

e
e
in

Q1

g
n

CP

Q0

Q1

Q2

Simple Registers

m
o

No external gates.
Example: A 4-bit register. A new 4-bit data is loaded
on every clock cycle.

c
.
rs

A4

g
n

e
e
in

A3

E
O

A2

A1

o
D

I4

I3

I2

I1

a
a
F
CP

4-bit register with parallel load

(Control Signal)
Load

S Q

I1

I2

g
n

E
O

I4

CP
Clear

aa

o
D

m
o

c
.
rs

A2

S Q

A3

e
e
in

I3

A1

S Q

R
S Q
R

A4

Register with Parallel Load Using D Flip

Load
Flops Load A + Load I
1

D Q

m
o

I1

ee

c
.
rs

n
i
g

I2

n
E

O
o

I3

D
a
a

F
I4

CP
Clear

A1

D Q

A2

D Q

A3

D Q

A4

Using Registers to implement Sequential

Circuits
A sequential circuit may consist of a register (memory) and a
combinational circuit.
Next-state value

m
o

Register

c
.
rs

Clock
Pulse

E
O

g
n

Inputs

o
D

e
e
in

Combinational
Circuit

Outputs

The external inputs and present states of the register determine

the next states of the register and the external outputs, through
the combinational circuit.
The combinational circuit may be implemented by any of the
methods covered in MSI components and Programmable
Logic Devices.

a
a
F

Using Registers to implement

Sequential Circuits

Example 1: Design a Sequential Circuit whose state table is given below

A1+ = m(4,6) = A1. x'
A2+ = m(1,2,5,6) = A2.x' + A'2 .x = A2 x
y = m(3,7) = A2.x
Present
State
A1
A2
0
0

Input
x
0

1
1
1

Next
State
A1+ A2+
0
0
0

a
a
F
1

Logic Diagram

g
n

Output
y
0

E
O

o
D

m
o

c
.
rs

e
e
in

State Table

using two flip-flops.

A1 . x
A2 x

A1
A2

Sequential Circuit Implementation

Using Registers to implement Sequential

Circuits

Example 2: Repeat example 1, but use a ROM &Register.

Address
Outputs
1
2 3
1 2 3
A1 A2 x
A1 A 2 y
0
0 0
0 0 0
0
0 1
0 1 0
0
1 0
0 1 0
0
1 1
0 0 1
1
0 0
1 0 0
1
0 1
0 1 0
1
1 0
1 1 0
1
1 1
0 0 1
ROM truth table

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

A1

A2

2
3

8X3
ROM

1
2
3

Sequential circuit using a register and a ROM

Serial IN/Serial Out Shift Registers

m
o

Accepts data serially one bit at a time and also

produces output serially.

c
.
rs

Serial Input
(SI)

Q0

Q1

g
n

e
e
in
D

E
O

o
D

CLK

a
a
F

Shift Register

Q2

Q3 Serial Output
(SO)

Serial In/Serial Out Shift Registers

Application: Serial transfer of data from one register to another.

m
o

SI
Clock

CP

0010

SI

n
i
g

Shift register B

n
E

O
o

D
a
a

Clock

ee

SO

Shift register A
CP

Shift Control

Shift Control

1011

c
.
rs

Wordtime

T1

T2

T3

T4

SO

Serial In/Serial Out Shift Registers

Serial-transfer example.

m
o

Timing Pulse
Initial value
After T1
After T2
After T3

Shift Register A

After T4

c
.
s
Shift Register
B Serial output of B
r
e
e
0 n0 1 0
0
g1i 0 0 1
1

1
1
1
0
1

1
0
1
1
1

1
1
0
1
1

n
E

O
o

D
a
a

0
1
1
1
0

1
0
1

1
1
0

0
1
1

0
0
1

0
0
1

Bidirectional Shift Registers

4-bit bidirectional shift register with parallel load
Parallel outputs

Clear

A4

A3

Q
D

CLK

A2

m
o

c
.
rs

e
e
in

Q
D

A1

Q
D

g
n

S1
S0

Serial
input for
shift-right

o
D

E
O

4x1
MUX
3 2 1 0

a
a
F
I4

4x1
MUX
3 2 1 0

I3

4x1
MUX
3 2 1 0

I2
Parallel inputs

4x1
MUX
3 2 1 0

I1

Serial
input for
shift-left

Bidirectional Shift Registers

4-bit bidirectional shift register with parallel
m
o
load.
c
.
s
r
Mode Control
e
e
n
i
s1
s0
Register Operation
g
n
E
0
0
No change
O
o
0
1D
Shift right
a
a
1 F 0
Shift left
1
1
Parallel load

An Application-Serial Addition
Most operations in digital computers are done in parallel.
Serial operations are slower but require less equipment.
A serial adder is shown below. A A+B.

m
o

c
.
rs

Shift-right
CP
External input

SI

1010

g
n

Shift register A
SI

a
a
F

o
D

E
O
0111

e
e
in

Shift register B

SO

SO

x
y FA
z

S
C

Q D

Clear

Excitation table for a serial adder

Example: Design a serial adder using a sequential logic
procedure
Q(t) Q(t+1) J K
with JK flip-flops.
Next

Present
Inputs

State

Output
S

Flip-flop

State

c
.
rs

ee

inputs

n
i
g

JQ

KQ

X 1

X 0

O
o

n
E
0

aD

a
F

m
o

S=x+y + Q
JQ = xy
KQ = xy =(x+y)

Shift register A

Shift-right
CP
External input

SO=x

Shift register B

c
.
s

r
e

SO=y

e
in

m
o

J Q

g
n

E
O

aa

o
D

Clear

S=x+y + Q
JQ = xy
KQ = xy =(x+y)

Second form of a serial adder

4-bit binary ripple counter

A4

A3

A2

Q(t+1)

Q(t)

c
.
s

Q(t)

A1

r
e

e
in

g
n

E
O

m
o
J

o
D

To next stage

a
a
F
K

Count
pulses
1

Count sequence for a binary ripple counter

Count sequence
A4
A3 A2
A1

Condition for complementing flip-flops

Complement A1

Complement A1

Complement A1

Complement A1

c
.
rs

A1 will go from 1 to 0 and complement A2

e
e
in

A1 will go from 1 to 0 and complement A2

g
n

E
O

A2 will go from 1 to 0 and complement A3

Complement A1

o
D

a
a
F
0

m
o

Complement A1

A1 will go from 1 to 0 and complement A2

Complement A1
Complement A1

A1 will go from 1 to 0 and complement A2;

A2 will go from 1 to 0 and complement A3;

A3 will go from 1 to 0 and complement A4

And so on

State diagram of a decimal BCD counter

m
o

0000

0001

0010

c
.
rs

0011

0100

0110

0101

e
e
in

g
n

E
O

o
D

1001

a
a
F

1000

0111

Logic diagram of a BCD ripple counter

0

Q8

Q4

Q2

Q1

0
Q

r
e

e
in

g
n

E
O

c
.
s

m
o
Q

1
Count
pulses

a
a
F

o
D

J
0
0
1
1

K
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)

Timing diagram for the decimal counter

Count
pulses

m
o

Q1
1

0
e
e

0
n
E

Q2 0

Q3 0

Q4 0

Q5 0

O
o
0
0
D
a

a
F0

c
.
rs

n
i
g

Block diagram of a 3-decade decimal BCD counter

Q8 Q4 Q2 Q1

Q8 Q4 Q2 Q1

m
o

e
e
in

c
.
rs

Q8 Q4 Q2 Q1

g
n

BCD
Counter

o
D

E
O

BCD
Counter

BCD
Counter

102 digit

101 digit

100 digit

0-999

0-99

0-9

a
a
F

Count
pulses

J
0
0
1
1

To
next
stage

K
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)

4-bit synchronous binary counter

m
o

A4

Q/

A3

Q/

a
a
F

o
D

e
e
in

A2

Q/

Q/

g
n

E
O

c
.
rs

A1

CP

Count
enable

T
0
1

Q(t+1)
Q(t)
Q(t)

4-bit up-down binary counter

A4

Q/

A3

A2

Q
T

g
n

m
o

c
.
rs

e
e
in

A1

Q/

T
CP

E
O

To
Next
stage

a
a
F

o
D

UP

Down

Design a BCD counter using T flip-flops

Excitation table for a BCD counter

Count Sequence

Flip-flop inputs

Output Carry

Q8

Q4

Q2

Q1

TQ8

TQ4

TQ2

TQ1

r
e

0
0
0

e
in

g
n

Using K-maps, we get

TQ1 =1
TQ2 = Q/8Q1
TQ4 = Q2Q1
TQ8 = Q8Q1 + Q4Q2Q1
y = Q8Q1

aa

c
.
s
1

E
O

o
D

m
o

Now logic diagram can be drawn for BCD synchronous

counter

Q(t) Q(t+1)

Q8

Q2

Q8

Q4
Q4

Q2

Q1
Q1

c
.
rs

CP

ee

n
i
g

m
o

n
E

O
o

D
a
a

F
y

TQ1 =1
TQ2 = Q/8Q1
TQ4 = Q2Q1
TQ8 = Q8Q1 + Q4Q2Q1
y = Q8Q1

Counters with Parallel Load

4-bit counter with
parallel load.

Count

Clear

CP

Load

Count

Function

Clear to 0

No Change

Load inputs

Next State
(counting)

J
0
0
1
1

K
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)

m
o

c
.
rs

e
e
in

I2

g
n

E
O

o
D

aa

Load
I1

I3

JQ

A1

K
JQ

A2

K
JQ

A3

K
I4

JQ

A4

K
Clear
CP

4-bit binary counter with parallel load

Carry
out

Counters with Parallel Load

Different ways of getting a MOD-6 counter
A4 A3 A2 A1

A4 A3 A2 A1
Count = 1
Clear = 1
CP

Load
I 4 I 3 I2 I1

Clear

Carry-out
Load

a
a
F

I4 I 3 I2 I 1

1 0 1 0

g
n

E
O

o
D

A4 A3 A2 A1

c
.
rs

I 4 I 3 I2 I1

Count = 1
Load = 0
CP

e
e
i(b)nBinary states 0,1,2,3,4,5

Inputs = 0

(a) Binary states 0,1,2,3,4,5

m
o

Count = 1
Clear = 1
CP

A4 A3 A2 A1
Load
I4 I 3 I2 I 1

Count = 1
Clear = 1
CP

0 0 1 1

(c) Binary states 10,11,12,13,14,15 (d) Binary states 3,4,5,6,7,8

Timing Sequences
Start

S Q
CP
Stop

3-bit counter

CP

c
.
rs

Count enable

D
a
a

Start

m
o

e
e
n
(a) Circuit Diagram
i
g
n
E
O
o

CP

Stop

Word-time
control

Word-time = 8 pulses

(b) Generation of a word-time control for serial operations

Shift right

T0

T1

T2

T3

(a) ring-counter (initial value = 1000)

T0 T1 T2 T3

e
e
in

E
O

a
a
F

T2

g
n

2X4
decoder

o
D

Count
enable

c
.
rs

CP
T0

2-bit counter

(b) Counter and Decoder

m
o

T1

T3

(c) Sequence of four timing signals

D Q

A/

D Q

B/

D Q

D Q

C/

E/

m
o

c
.
rs

CP

e
e
in

(a) 4-stage switch tail ring counter

Sequence
number

g
n

Flip-flop outputs
A
B
C
E

And gate required

for outputs

E
O
0

A/ E/

A B/

B C/

C E/

AE

A/ B

B/ C

C/ E

1
2
3
4

o
D

a
a
F
1
1

(b) Count
sequence and
required
decoding