om ERE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VS SYSTEMS, VOL 2, NO. 4 DECEMBER 14 Low-Power Digital Systems Based on Adiabatic-Switching Principles ‘William C, Athas, Lars “I.” Svensson, Member, IEEE, Jeffrey G. Koller, Nestoras Tzartzanis, and Eric Ying-Chin Chou, Student Member, IEEE Alsract— Adiabatic switching is an approach to low-power ‘igtal crcuts that fers fundamentally from other practical low-power tchniques. When adlabaiie switching is used, the signal energies stored on circuit capacitances may be recycled in- ‘sted of dsipated as heat. We describe the fundamental adiabatic amplifier circuit and analyze Its performance. The dissipation ‘of the adiabatic amplifier Is compared to that of convention ‘switching circuits, both for the case of fixed voage swing land the care when the voltage swing can be scaled to reduce over dissipation. We show bow combinational and sequential ‘Mlabaticwitehing logic ircults may be constructed and de- seribe the timing restrictions required for adiabatic operation. ‘Small chip-bulldng experiments have been performed to validate the techniques and to analyse the associated crcult overhead. Index Terms— Adiabatic amplification, adiabatic charging, ‘adiabatic switching, low-power CMOS, reversible computation, ‘Stching energy reduction with preserved signal energies. HE IMPORTANCE of reducing power dissipation in dig- itl systems is increasing asthe range and sophistication ‘of applications in portable and embedded computing continues to increase. System-level issues such as batery life, weight and size ae directly affected by power dissipation. Inrouds into reducing power dissipation ofthe digital systems only serves to improve the performance and capabilities ofthese systems, (CMOS has prevailed as the technology of choice for imple- menting low-power digital systems. One ofthe most important reasons isthe reduction in switching energy per device caused by the continually shrinking feature sizes. Another important reason is the almost ideal switch characteristics of the MOS. transistor, which translates into a negligible static power dssi- pation compared (othe switching (transient) power dissipation ‘Basic enerpy and charge conservation principles canbe used to derive the switching energy and power dissipation for sai, fully restoring CMOS logic. Throughout this ance, we will frequently refer to such CMOS logic as “conventional” logic Consider the generic CMOS gate shown in Fig. 1. A load ‘cepactance Cy, representing the input capacitance ofthe next logie stage and any parasitic capacitances, is connected tothe ‘de supply voltage Vaz through a pull-up block composed of | FET's and to ground through a pull-down block of nFET"s ‘With the pulldown network tied andthe poll-up network cut, Manip recived Due 15. 1994 Avge 23.1996, Ti wor wat “The tutes a wi he iran Scene ie, Unvrly of Souter Calor, Maro et ay, CA SD USA TERE Log Number 908867 gene, conentnea CMOS igi ate wih pala and paltdown retorts the output is discharged to ground. When the inputs change s0 that the pull-up network is ted ad the pull-down network cu, charge will Now out of Vaz and into the Toad capacitance ntl the output reaches Vi Inthe process of charging the output, @ charge of size Q = Cagis delivered to the load. The power supply most supply this charge at voltage Vas, $0 the enery supplied is Q" Vas = Cr: Vip. The energy stored on 8 capacitance Cx charged t0 Vacs only half ofthis 0 (1/2) CVE Because energy is conserved, the other half must be disipated by the pFET's in the pullup network The same amount of energy is dissipated, regardless of the make-up of the network, the resistance of the pPET's, and the time taken to complete the charging. Similarly, when the inputs change gain causing the output to discharge, al of the signal enerey Sored onthe capacitance is inevitably dissipated in the pll- down network, because no energy can enter the ground rail (Q Vena = 9-0 = 0), "Thu, from an energy conservation perspective, the conven: tional case represents maximum of wastefulness. All charge is inpot to the circuit at vokage Vag and exists at voltage 0. The energy of the charge upon entry is Ct Vas» Vag. The nergy of the charge upon exit i 0. Energy dissipation from delivery to removal ofthe charge is CV. All of this eneray 4s dissipated as heat. Since the energy dissipated when a signa capacitance is cycled is fined at twice the signal energy, the only way to reduce the energy dissipation in a conventional CMOS gate is to reduce the signal energy. This increases the seasivily 0 background noise and ths the probability of malfunction. ‘Switching energy can be made to be considerably less than signal energy. From the theory of charge contol (13) charges an be distinguished as either contlling or conoid chargeFor MOSFETs, the controling charge is on the gat, while the controled charge flows through the channel, Dissipation js caused by the resistance encountered by the contolled charge If charge wanspot is slowed down, energy that would ‘otherwise be dissipated in the channel can be conserved for Inter reuse. The enerey advantage can be readily understood by assuming @ constant curent source that delivers the charge Cag over a time period 7. The dissipation though the chanel resistance 2s then (2) Bag = PT = PRT = uation (1) shows that its possible to charge and discharge 2 eapactance through a resistance while siating less han Cig of energy. Rabo suggests that Wis posible 10 rede the dissipation fo an arbitrary depres by increasing the switching time to everlamger values. We refer to this as the pipe of adiabatic charging, We se the tem Staiabate™ to indicate that all charge taste is (0 cur witout generating hea. As i he typical usage of he erm in thermodynamics fully adiabatic peaton san idea eondon that i ssymploiclly approached as the process is slowed tlown To thebestof oar knowledge, Sit nd o-workers (1 sree the fist to formulate the relationship of (1) and 0 se the eflcc in practical dig eit Switching cuits that charge end change their Toad capuitance adabataly are said (9 use adiabatic switching This ante describes and analyzes the power sipaton and performance of ada awiehng lie circus bal i CMOS. The circuits rely on special power supplies that provide accurate pulsedpower delivery. Iv is important 10 ote that aba switching techniques canbe an aactive flemative to ther low power design approaches ony ft Supplies cen deliver power efiently an reyee the power fed ack o them, The cites deserbed here ae compasble bith enegy-ficicnt. resonant power supplies that we have Aeveloped and prtesypet [2 ‘Many factor must considered when detemining the ondiins for which adiabatic swtehing oes superior lw poner operation to her approaches. When signa-vlige Swing i significantly greater than the threshold volages of the CMOS devices, the advantages can be eal determined from he analysis othe adabaicapifer whichis dncssed in dealin Section I On the other hand, when signa-voltage Swing can he scaled downto reduce power dissipation, th Advantages of adiabatic amplification rpily diminish for fut the slowest applications, 8 shown in Section I “The adiabatic smpier and the simple gate strctre 00 wwii based canbe sraihtorvardyeneraized so hat in addition to amplieaton or buleing. it can implement ibiary logic function. Section TV describes the tanston fom combrntonal logic to sequent Tope. The tansiton Contes tuning poi, since conventional trae elements annot fe mae fully adiabat. Reversbelgic techies imay be ised to Noid sorage clemen’s and thus make ponible to build fully adiabatic sequential systema. To this o ‘end, we have developed techniques for constructing reversible Togie pipelines similar in organization to those developed and demonstrated by Younis and Knight [9]. Section 1V also includes a description of a design exercise, where the reversible pipeline stricture is used (0 construct & highly Pipelined adder, The results of this exercise indicate that for reversible logic 10 be @ competitive approach to low-power ‘CMOS, either the premium on reducing the energy dissipated per operation must be extremely high, or logic styles and synthesis procedures need tobe invented which result in iret designs with much less logical overhead 1, ADIABATIC AMPLIFICATION The adiabatic amplifier, which is the fundamental circuit to our approach, is @ simple buffer circuit that uses adiabatic charging to drive a capacitive load, It is useful in a stand- lone configuration, and also as a part of more sophisticated circuits In this section, we analyse it efficiency and deseribe its stand-alone use as a line driver for an address bus on a ‘memory board ‘Equation (1) assumes that Cr is charged or discharged through a constant resistance. Conventional gates, suc that in Fig. 1, use pull-up and pulldown networks composed of nonlinear FET devices. Fortunately, a switch network can be linearized to a first approximation by replacing each FET with a fully restoring CMOS wansmission gate (T-gate). Tre T- gate is built from an nFET and a pPET connected in paral. ‘To tie the T-gate with minimal on-resistance, the gate of the FET is prounded and the gate of the nFET is ted 10 Vag. For 4 small voltage drop across the T-gate, which isthe intended region for adiabatic ctcuts, we may model the conductances, Gy, and Gof the FET'S as a . Gy = Fela ~ Ya) @ Ca yy Vi Gy = FE (Vas ~ Ven ~ Va) eo Gp and Cy are the gate capacitances of the FET's, Vin is the threshold voltage of the nFET, and Ky, and Ky present ‘racess constants independent of gate capacitance and voltage. Vis the average channel voltage. We assume thatthe channel length is held constant so tht the gate capacitance is directly ‘proportional to the channel width, These equations do not take ito eccount body effects or the difference in threshold voltage between nFETs and pFET"s, Accuracy is therefore limited to a factor of 10. By selecting the widths of the wo FET"s such that Ky /Cpy = K,/Cp. we may simplify the sum of the two conductances 46, itera ayy FEW Vax Vn + Neu Vi) Cn eee Me) “ ‘The on-resstance of the T-gate isthe reciprocal of this sum: o