eZdspTM F2812

Technical
Reference

2003 DSP Development Systems

 eZdspTM F2812
Technical Reference

506265-0001 Rev. F
September 2003

SPECTRUM DIGITAL, INC.

12502 Exchange Dr., Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: 281.494.5310
sales@spectrumdigital.com www.spectrumdigital.com
 IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware, products described herein are not intended for use in life-support appliances,
devices, or systems. Spectrum Digital does not warrant, nor is it liable for, the product described
herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user, at his own expense, will
be required to take any measures necessary to correct this interference.

TRADEMARKS

eZdsp is a trademark of Spectrum Digital, Inc.

Copyright © 2003 Spectrum Digital, Inc.

 Contents

1 Introduction to the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Provides a description of the eZdspTM F2812, key features, and board outline.
1.0 Overview of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1 Key Features of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

2 Operation of the eZdspTM F2812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Describes the operation of the eZdspTM F2812. Information is provided on the DSK’s various
interfaces.
2.0 The eZdspTM F2812 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1 The eZdspTM F2812 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 eZdspTM F2812 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 eZdspTM F2812 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.3.1 P1, JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.2 P2, Expansion Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.3 P3, Parallel Port/JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.4 P4,P8,P7, I/O Interface ................................................ 2-9
2.3.5 P5,P9, Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.6 P6, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.7 Connector Part Numbers .............................................. 2-14
TM
2.4 eZdsp F2812 Jumpers ............................................... 2-14
2.4.1 JP1, XMP/MCn Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.4.2 JP4, JP5, Voltage Jumpers ............................................ 2-16
2.4.2.1 JP4, +3.3/5 Volts for P8, P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.4.2.2 JP5, +3.3/5 Volts for P4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.4.3 JP7,JP8,JP11,JP12, Boot Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.4.4 JP9, PLL Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.5 LEDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.6 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

A eZdspTM F2812 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1

Contains the schematics for the socketed and unsocketed versions of the eZdspTM F2812

B eZdspTM F2812 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Contains the mechanical information about the socketed and unsocketed versions of the eZdspTM
F2812
 List of Figures

Figure 1-1, Block Diagram eZdspTM F2812 ..................................... 1-3

TM
Figure 2-1, eZdsp F2812 PCB Outline ...................................... 2-2
Figure 2-2, eZdspTM F2812 Memory Space ................................... 2-4
TM
Figure 2-3, eZdsp F2812 Connector Positions ................................ 2-5
Figure 2-4, Connector P1 Pin Locations ....................................... 2-6
Figure 2-5, Connector P2 Pin Locations ........................................ 2-7
Figure 2-6, Connector P4/P8/P7 Connectors ................................... 2-9
Figure 2-7, Connector P5/P9 Pin Locations ................................... 2-11
Figure 2-8, Connector P6 Location .......................................... 2-13
TM
Figure 2-9, eZdsp F2812 Power Connector .................................. 2-13
Figure 2-10, eZdspTM F2812 Jumper Positions ................................ 2-15
TM
Figure 2-11, eZdsp F2812 Voltage Jumper Positions(Bottom side) .............. 2-16

List of Tables

Table 2-1, External Chip Select and Usages ................................... 2-3

TM
Table 2-2, eZdsp F2812 Connectors ....................................... 2-5
Table 2-3, P1, JTAG Interface Connector ...................................... 2-6
Table 2-4, P2, Expansion Interface Connector .................................. 2-8
Table 2-5, P4/P8, I/O Connectors .......................................... 2-10
Table 2-6, P7, I/O Connector .............................................. 2-11
Table 2-7, P5/P9, Analog Interface Connector ................................. 2-12
Table 2-8, Connector Part Numbers ........................................ 2-14
Table 2-9, eZdspTM F2812 Jumpers .......................................... 2-14
Table 2-10, JP1, XMP/MCn Select ........................................... 2-15
Table 2-11, JP4, +3.3/5 Volts for P8, P2 ...................................... 2-17
Table 2-12, JP5, +3.3/ Volts for P4 ........................................... 2-17
Table 2-13, JP7,JP8, JP11, JP12, Boot Mode Select ........................... 2-18
Table 2-14, JP9, PLL Disable .............................................. 2-18
Table 2-15, LEDs ........................................................ 2-19
Table 2-16, Test Points ................................................... 2-19
About This Manual

This document describes board level operations of the eZdspTM F2812 based on the
Texas Instruments TMS320F2812 Digital Signal Processor.

The eZdspTM F2812 is a stand-alone module permitting engineers and software

developers evaluation of certain characteristics of the TMS320F2812 DSP to
determine processor applicability to design requirements. Evaluators can create
software to execute onboard or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The “eZdspTM F2812” will sometimes be referred to as the “eZdsp”.

“eZdsp” will include the socketed or unsocket version

Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.

equations
!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.

This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.

Related Documents

Texas Instruments TMS320C28x DSP CPU and Instruction Set Reference Guide,
literature #SPRU430
Texas Instruments TMS320C28x Assembly Language Tools Users Guide,
literature #SPRU513
Texas Instruments TMS320C28x Optimizing C/C++ Compiler User’s Guide,
literature #SPRU514
Texas Instruments Code Composer Studio Getting Started Guide,
literature #SPRU509
 Chapter 1

Introduction to the eZdspTM F2812

This chapter provides a description of the eZdspTM for the TMS320F2812

Digital Signal Processor, key features, and block diagram of the circuit
board.

Topic Page
1.0 Overview of the eZdspTM F2812 1-2
1.1 Key Features of the eZdspTM F2812 1-2
1.2 Functional Overview of the eZdspTM F2812 1-3

1-1
Spectrum Digital, Inc

1.0 Overview of the eZdspTM F2812

The eZdspTM F2812 is a stand-alone card--allowing evaluators to examine the

TMS320F2812 digital signal processor (DSP) to determine if it meets their application
requirements. Furthermore, the module is an excellent platform to develop and run
software for the TMS320F2812 processor.

The eZdspTM F2812 is shipped with a TMS320F2812 DSP. The eZdspTM F2812
allows full speed verification of F2812 code. Two expansion connectors are provided
for any necessary evaluation circuitry not provided on the as shipped configuration.

To simplify code development and shorten debugging time, a C2000 Tools Code
Composer driver is provided. In addition, an onboard JTAG connector provides
interface to emulators, operating with other debuggers to provide assembly language
and ‘C’ high level language debug.

1.1 Key Features of the eZdspTM F2812

The eZdspTM F2812 has the following features:

• TMS320F2812 Digital Signal Processor

• 150 MIPS operating speed

• 18K words on-chip RAM

• 128K words on-chip Flash memory

• 64K words off-chip SRAM memory

• 30 MHz. clock

• 2 Expansion Connectors (analog, I/O)

• Onboard IEEE 1149.1 JTAG Controller

• 5-volt only operation with supplied AC adapter

• TI F28xx Code Composer Studio tools driver

• On board IEEE 1149.1 JTAG emulation connector

1-2 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

1.2 Functional Overview of the eZdspTM F2812

Figure 1-1 shows a block diagram of the basic configuration for the eZdspTM F2812.
The major interfaces of the eZdsp are the JTAG interface, and expansion interface.

A
N
A
L
O
G
30 Mhz.
XTAL1/OSCIN
E
ANALOG TO X
DIGITAL P
P A
A
CONVERTER N
R PARALLEL S
A I
L PORT/JTAG JTAG O
L CONTROLLER N
E
L TMS320F28xx
P XZCS6AND7n 64K x 16
O SRAM
R
T
EXTERNAL I
JTAG /
O

E
X
P
A
N
S
I
O
N

Figure 1-1, BLOCK DIAGRAM eZdspTM F2812

1-3
Spectrum Digital, Inc

1-4 eZdspTM F2812 Technical Reference

 Chapter 2

Operation of the eZdspTM F2812

This chapter describes the operation of the eZdspTM F2812, key

interfaces and includes a circuit board outline.

Topic Page
2.0 The eZdspTM F2812 Operation 2-2
2.1 The eZdspTM F2812 Board 2-2
2.1.1 Power Connector 2-3
2.2 eZdspTM F2812 Memory 2-3
2.2.1 Memory Map 2-4
2.3 eZdspTM F2812 Connectors 2-5
2.3.1 P1, JTAG Interface 2-6
2.3.2 P2, Expansion Interface 2-7
2.3.3 P3, Parallel Port/JTAG Interface 2-9
2.3.4 P4,P8,P7, I/O Interface 2-9
2.3.5 P5,P9, Analog Interface 2-11
2.3.6 P6, Power Connector 2-13
2.3.7 Connector Part Numbers 2-14
2.4 eZdspTM F2812 Jumpers 2-14
2.4.1 JP1, XMP/MCn Select 2-15
2.4.2 JP4, JP5 Voltage Jumpers 2-16
2.4.2.1 JP4, +3.3/5 Volts for P8, P4 2-17
2.4.2.2 JP5, +3.3/5 Volts for P2 2-17
2.4.3 JP7,JP8,JP11,JP12, Boot Mode Select 2-18
2.4.4 JP9, PLL Disable 2-18
2.5 LEDs 2-19
2.6 Test Points 2-19

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Spectrum Digital, Inc

2.0 The eZdspTM F2812 Operation

This chapter describes the eZdspTM F2812, key components, and operation.
Information on the eZdsp’s various interfaces is also included. The eZdspTM F2812
consists of four major blocks of logic:

• Analog Interface Connector

• I/O Interface Connector
• JTAG Interface
• Parallel Port JTAG Controller Interface

2.1 The eZdspTM F2812 Board

The eZdspTM F2812 is a 5.25 x 3.0 inch, multi-layered printed circuit board, powered
by an external 5-Volt only power supply. Figure 2-1 shows the layout of both the
socketed and unsocketed version of the F2812 eZdsp.

Figure 2-1, eZdspTM F2812 PCB Outline

2-2 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

2.1.1 Power Connector

The eZdspTM F2812 is powered by a 5-Volt only power supply, included with the
unit. The unit requires 500mA. The power is supplied via connector P6. If expansion
boards are connected to the eZdsp, a higher amperage power supply may be
necessary. Section 2.3.6 provides more information on connector P6.

2.2 eZdspTM F2812 Memory

The eZdsp includes the following on-chip memory:

• 128K x 16 Flash
• 2 blocks of 4K x 16 single access RAM (SARAM)
• 1 block of 8K x 16 SARAM
• 2 blocks of 1K x 16 SARAM

In addition 64K x 16 off-chip SRAM is provided. The processor on the eZdsp can be
configured for boot-loader mode or non-boot-loader mode.

The eZdsp can load ram for debug or FLASH ROM can be loaded and run. For larger
software projects it is suggested to do a initial debug with on eZdsp F2812 module
which supports a total RAM environment. With careful attention to the I/O mapping in
the software the application code can easily be ported to the F2812.

The table below shows the external chip select signal and its use.

Table 1: External Chip Select and Usage

Chip Select
Use
Signal
XZCS0AND1n Expansion header
XZCS2n Expansion Header
XZCS6AND7n External SRAM

2-3
Spectrum Digital, Inc

2.2.1 Memory Map

The figure below shows the memory map configuration on the eZdspTM F2812.

Figure 2-2, eZdspTM F2812 Memory Space

Note: The on-chip flash memory has a security key which can prevent visibility when
enabled.

2-4 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

2.3 eZdspTM F2812 Connectors

The eZdspTM F2812 has five connectors. Pin 1 of each connector is identified by a
square solder pad. The function of each connector is shown in the table below:

Table 2: eZdspTM F2812 Connectors

Connector Function
P1 JTAG Interface
P2 Expansion
P3 Parallel Port/JTAG
Controller Interface
P4/P8/P7 I/O Interface
P5/P9 Analog Interface
P6 Power Connector

The diagram below shows the position of each connector

P1
P2

P3

P5/P9
P4/P8/P7

P6
Figure 2-3, eZdspTM F2812 Connector Positions

2-5
Spectrum Digital, Inc

2.3.1 P1, JTAG Interface

The eZdspTM F2812 is supplied with a 14-pin header interface, P1. This is the
standard interface used by JTAG emulators to interface to Texas Instruments DSPs.

The positions of the 14 pins on the P1 connector are shown in the diagram below as
viewed from the top of the eZdsp.

P1
13 11 9 7 5 3 1 1
14 12 10 8 4 2 2

JTAG
Fig 2-4, P1 Pin Locations

The definition of P1, which has the JTAG signals is shown below.

Table 3: P1, JTAG Interface Connector

Pin # Signal Pin # Signal

1 TMS 2 TRST-
3 TDI 4 GND
5 PD (+5V) 6 no pin
7 TDO 8 GND
9 TCK-RET 10 GND
11 TCK 12 GND
13 EMU0 14 EMU1

2-6 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

WARNING !
The TMS320F2812 supports +3.3V Input/Output levels
which are NOT +5V tolerant. Connecting the eZdsp to
a system with +5V Input/Output levels will damage the
TMS320F2812. If the eZdsp is connected to another
target then the eZdsp must be powered up first and
powered down last to prevent lactchup conditions.

2.3.2 P2, Expansion Interface

The positions of the 60 pins on the P2 connector are shown in the diagram below as
viewed from the top of the eZdsp.

P2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59

Figure 2-5, Connector P2 Pin Locations

2-7
Spectrum Digital, Inc

The definition of P2, which has the I/O signal interface is shown below.

Table 4: P2, Expansion Interface Connector

Pin # Signal Pin # Signal

1 +3.3V/+5V/NC * 2 +3.3/+5V/NC *
3 XD0 4 XD1
5 XD2 6 XD3
7 XD4 8 XD5
9 XD6 10 XD7
11 XD8 12 XD9
13 XD10 14 XD11
15 XD12 16 XD13
17 XD14 18 XD15
19 XA0 20 XA1
21 XA2 22 XA3
23 XA4 24 XA5
25 XA6 26 XA7
27 XA8 28 XA9
29 XA10 30 XA11
31 XA12 32 XA13
33 XA14 34 XA15
35 GND 36 GND
37 XZCS0AND1n 38 XZCS2n
39 XREADY 40 10K Pull-up
41 XRnW 42 10K Pull-up
43 XWE 44 XRDn
45 +3.3V 46 XNMI/INT13
47 XRSn/RSn 48 No connect
49 GND 50 GND
51 GND 52 GND
53 XA16 54 XA17
55 XA18 56 XHOLDn
57 XHOLDAn 58 No connect
59 No connect 60 No connect

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp
with JP5.

2-8 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

2.3.3 P3, Parallel Port/JTAG Interface

The eZdspTM F2812 uses a custom parallel port-JTAG interface device. This device
incorporates a standard parallel port interface that supports ECP, EPP, and
SPP8/bidirectional communications. The device has direct access to the integrated
JTAG interface. Drivers for C2000 Code Composer tools are shipped with the eZdsp
modules

2.3.4 P4/P8/P7, I/O Interface

The connectors P4, P8, and P7 present the I/O signals from the DSP. The layout of
these connectors are shown below.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P4
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
5
P8
1 3 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

1 2 3 4 5 6 7 8 9 10 P7

Figure 2-6, P4/P8/P7 Connectors

2-9
Spectrum Digital, Inc

The pin definition of P4/P8 connectors are shown in the table below.

Table 5: P4/P8, I/O Connectors

P4 P8 P8
P4 Signal P8 Signal P8 Signal
Pin # Pin # Pin #
1 +3.3V/+5V/NC * 1 +3.3V/+5V/NC * 2 +3.3V/+5V/NC *
2 XINT2/ADCSOC 3 SCITXDA 4 SCIRXDA
3 MCLKXA 5 XINT1n/XBIOn 6 CAP1/QEP1
4 MCLKRA 7 CAP2/QEP2 8 CAP3/QEPI1
5 MFSXA 9 PWM1 10 PWM2
6 MFSRA 11 PWM3 12 PWM4
7 MDXA 13 PWM5 14 PWM6
8 MDRA 15 T1PWM/T1CMP 16 T2PWM/T2CMP
9 No connect 17 TDIRA 18 TCLKINA
10 GND 19 GND 20 GND
11 CAP5/QEP4 21 No connect 22 XINT1N/XBIOn
12 CAP6/QEPI2 23 SPISIMOA 24 SPISOMIA
13 T3PWM/T3CMP 25 SPICLKA 26 SPISTEA
14 T4PWM/T4CMP 27 CANTXA 28 CANRXA
15 TDIRB 29 XCLKOUT 30 PWM7
16 TCLKINB 31 PWM8 32 PWM9
17 XF/XPLLDISn 33 PWM10 34 PWM11
18 SCITXDB 35 PWM12 36 CAP4/QEP3
19 SCIRXDB 37 T1CTRIP/PDPINTAn 38 T3CTRIP/PDPINTBn
20 GND 39 GND 40 GND

* Default is No Connect (NC). User can jumper to +3.3V or +5V on backside of eZdsp
with JP4.

2-10 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

The pin definition of P7 connector is shown in the table below.

Table 6: P7, I/O Connector

P7
P7 Signal
Pin #
1 C1TRIPn
2 C2TRIPn
3 C3TRIPn
4 T2CTRIPn/EVASOCn
5 C4TRIPn
6 C5TRIPn
7 C6TRIPn
8 T4CTRIPn/EVBSOCn
9 No connect
10 GND

2.3.5 P5/P9, Analog Interface

The position of the 30 pins on the P5/P9 connectors are shown in the diagram below
as viewed from the top of the eZdsp.

P5 ANALOG
1 2 3 4 5 6 7 8 9 10
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 17 19
P9

Figure 2-7, Connector P5/P9 Pin Locations

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Spectrum Digital, Inc
The definition of P5/P9 signals are shown in the table below.

Table 7: P5/P9, Analog Interface Connector

P5 P9 P9
Signal Signal Signal
Pin # Pin # Pin #
1 ADCINB0 1 GND 2 ADCINA0
2 ADCINB1 3 GND 4 ADCINA1
3 ADCINB2 5 GND 6 ADCINA2
4 ADCINB3 7 GND 8 ADCINA3
5 ADCINB4 9 GND 10 ADCINA4
6 ADCINB5 11 GND 12 ADCINA5
7 ADCINB6 13 GND 14 ADCINA6
8 ADCINB7 15 GND 16 ADCINA7
9 ADCREFM 17 GND 18 VREFLO *
10 ADCREFP 19 GND 20 No connect

* Connect VREFLO to AGND or VREFLO of target system for proper ADC operation.

2-12 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc
2.3.6 P6, Power Connector

Power (5 volts) is brought onto the eZdspTM F2812 via the P6 connector. The
connector has an outside diameter of 5.5 mm. and an inside diameter of 2 mm. The
position of the P6 connector is shown below.

TP1

POWER
Figure 2-8, Connector P6 Location

The diagram of P6, which has the input power is shown below.

+5V
P6 Ground
PC Board

Front View
Figure 2-9, eZdspTM F2812 Power Connector

2-13
Spectrum Digital, Inc

2.3.7 Connector Part Numbers

The table below shows the part numbers for connectors which can be used on the
eZdspTM F2812. Part numbers from other manufacturers may also be used.

Table 8: eZdspTM F2812 Suggested Connector Part Numbers

Connector Male Part Numbers Female Part Numbers

P1 SAMTEC TSW-1-10-07-G-T SAMTEC SSW-1-10-01-G-T
P2 SAMTEC TSW-1-20-07-G-T SAMTEC SSW-1-20-01-G-T

*SSW or SSQ Series can be used

2.4 eZdspTM F2812 Jumpers

The eZdspTM F2812 has 8 jumpers available to the user which determine how
features on the eZdspTM F2812 are utilized. The table below lists the jumpers and their
function. The following sections describe the use of each jumper.

Table 9: eZdspTM F2812 Jumpers

Position As
Jumper # Size Function Shipped From
Factory
JP1 1x3 XMP/MCn 2-3
JP4 1x3 +3.3/5 Volts to P8,P4 Not connected
JP5 1x3 +3.3/5 Volts to P2 Not Connected
JP7 1x2 Boot Mode 3 2-3
JP8 1x3 Boot Mode 2 2-3
JP9 1x3 PLL Disable 1-2
JP11 1x3 Boot Mode 1 1-2
JP12 1x3 Boot Mode 0 2-3

WARNING!
Unless noted otherwise, all 1x3 jumpers must
be installed in either the 1-2 or 2-3 position

2-14 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc
The diagram below shows the positions of six jumpers on the component side of the
eZdspTM F2812.

JP9 JP8 JP7

DS2 JP1

DS1 JP11

JP12

TP1 TP2

Figure 2-10, eZdspTM F2812 Jumper Positions

2.4.1 JP1, XMP/MCn Select

Jumper JP1 is used to select the XMP/MCn option. The 1-2 selection allows the DSP to
operate in the Microcontroller mode. The 2-3 selection allow the DSP to operate in the
Microprocessor mode. The positions are shown in the table below.

Table 10: JP1, XMP/MCn Select

Position Function
1-2 Microprocessor mode
2-3 * Microcomputer mode

* as shipped from factory

2-15
Spectrum Digital, Inc

2.4.2 JP4, JP5 Voltage Jumpers

Jumpers JP4 and JP5 are an unpopulated jumpers on the bottom side of the board that
provide either +3.3 volts or +5 volts to pins on the expansion connectors. These
jumpers are shipped uninstalled to prevent accidental damage by connecting wires or
circuitry to the expansion connector. The user may connect these jumpers by installing
a jumper wire or zero ohm resistor. The position of these jumpers are shown in the
figure below.

JP5

JP4
TM
Figure 2-11, eZdsp F2812 Voltage Jumper Positions (Bottom Side)

2-16 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

2.4.2.1 JP4, +3.3/5 Volts for P8, P4

Jumper JP4 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 of
expansion connector P8, and pin 1 of P4. The settings for this jumper are shown in the
table below

Table 11: JP4, +3.3/5 Volts for P8, P4

Position Function Jumper Position

Connect +5 Volts 3.3V
5V
1-2 to P8, pins 1,2,
and P4 pin1 JP4
Connect +3.3 3.3V
5V
2-3 Volts to P8, pins
1,2, and P4 pin1 JP4

5V 3.3V
No connect *
JP4

* As shipped from factory

2.4.2.2 JP5, +3.3/5 Volts for P2

Jumper JP5 allows the user to provide either +3.3 or +5 volts to pins 1 and 2 of
expansion connector P2. The settings for this jumper are shown in the table below.

Table 12: JP5, +3.3/5 Volts for P2

Position Function Jumper Position

Connect +5 Volts to P2, pins JP5
1-2 1,2
5V 3.3V

Connect +3.3 Volts to P2, JP5

2-3 pins 1,2
5V 3.3V

JP5
No connect *
5V 3.3V

* As shipped from factory

2-17
Spectrum Digital, Inc

2.4.3 JP7, JP8, JP11, JP12, Boot Mode Select

Jumpers JP7, JP8, JP11, JP12 are used to determine what mode the DSP will use for
bootloading on power up. To set a signal high, place the jumper in the 1-2 position.
For a low signal, use the 2-3 position.The options are shown in the table below.

Table 13: JP7, JP8, JP11, JP12, Boot Mode Select

JP7, BOOT3 JP8, BOOT2 JP11, BOOT1 JP12, BOOT0

MODE
SCITXDA MDXA SPISTEA SPICLKA
1 X X X FLASH
0 1 X X SPI
0 0 1 1 SCI
0 0 1 0 H0 *
0 0 0 1 OTP
0 0 0 0 PARALLEL

* factory default

2.4.4 JP9, PLL Disable

Jumper JP9 is used to enable/disable the use of the Phase Lock Loop (PLL) logic on
the DSP. The selection of the 1-2 position enables the use of the PLL. If the 2-3
position is used the PLL is disabled. This signal is latched at reset and may be used as
XF after reset. The positions are shown in the table below.

Table 14: JP9, PLL Disable

Position Function
1-2 * PLL Enabled
2-3 PLL disabled

* as shipped from the factory

2-18 eZdspTM F2812 Technical Reference

 Spectrum Digital, Inc

2.5 LEDs

The eZdspTM F2812 has two light-emitting diodes. DS1 indicates the presence of
+5 volts and is normally ‘on’ when power is applied to the board. DS2 is under software
control and is tied to the XF pin on the DSP through a buffer. These are shown in the
table below.

Table 15: LEDs

LED # Color Controlling Signal

DS1 Green +5 Volts
DS2 Green XF bit (XF high = on)

2.6 Test Points

The eZdspTM F2812 has two test points. The signals they are tied to are shown in the
table below.

Table 16: Test Points

Test Point Signal

TP1 Ground
TP2 Analog Ground

2-19
Spectrum Digital, Inc

2-20 eZdspTM F2812 Technical Reference

 Appendix A
eZdspTM F2812
Schematics

The schematics for the eZdspTM F2812 can be found on the CD-ROM that
accompanies this board. The schematics were drawn on ORCAD.

The schematics are correct for both the socketed and unsocketed version
of the eZdspTM.

WARNING !
The TMS320F2812 supports +3.3V Input/Output levels
which are NOT +5V tolerant. Connecting the eZdsp to
a system with +5V Input/Output levels will damage the
TMS320F2812. If the eZdsp is connected to another
target then the eZdsp must be powered up first and
powered down last to prevent lactchup conditions.

Design Notes:

1. The TMS320F2812 X1/CLKIN pin is +1.8 volt input. The clock input is
buffered with a SN74LVC1G14 whose supply is +1.8 volts. This provides
+3.3 volts to the +1.8 volt clock translation. Refer to sheet 4 of the
schematics.

A-1
 5 4 3 2 1

REVISIONS

A-2
REV DESCRIPTION DATE APPROVED

A PROTOTYPES 04-April-2002

B PRODUCTION RELEASE 07-June-2002

D D
C UPDATE PER SPRS174G 20-Jan-2003
Spectrum Digital, Inc

C C

The TMS320F2812 EzDSP design is based on

preliminary information(SPRS174G) for the
TMS320F2812 device. This schematic is subject to
change without notification. Spectrum Digital Inc.
assumes no liability for applications assistance,
customer product design or infringement of patents
described herein.
B B

DWN DATE
REVISION STATUS OF SHEETS
CHK DATE
A A
REV
ENGR DATE
SH
ENGR-MGR DATE
REV
SPECTRUM DIGITAL INCORPORATED
QA DATE Title
SH TMS320F2812 EzDSP
MFG DATE
REV C C B C C C NEXT ASSY USED ON Size Document Number Rev
RLSE DATE B 506262 C
SH 1 2 3 4 5 6 APPLICATION
Date: Wednesday, June 04, 2003 Sheet 1 of 6
5 4 3 2 1

eZdspTM F2812 Technical Reference

 5 4 3 2 1

3.3V
(4,6) 1.8V
XA[0..18] (3,4)
(3,4,5,6) GND
(6) VDD3VFL
XD[0..15] (3,4)

XA10
XA11
XA12
XA13
XA14
XA15
XA16
XA17
XA18

XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
(3,4,5,6) AGND
U8

69
31
64
81
114
145
23
37
56
75
100
112
128
143
154
18
43
80
85
103
108
111
118
121
125
130
132
138
141
144
148
152
156
158

XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
D (4) ADCINA0 174 ADCINA0 D

XA10
XA11
XA12
XA13
XA14
XA15
XA16
XA17
XA18

VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
173 21 XD0

VDD10
(4) ADCINA1 ADCINA1 XD0

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
172 24 XD1

VDD3VFL
(4) ADCINA2 ADCINA2 XD1
171 27 XD2
(4) ADCINA3 ADCINA3 XD2
170 30 XD3
(4) ADCINA4 ADCINA4 XD3
169 33 XD4
(4) ADCINA5 ADCINA5 XD4
168 36 XD5
TAIYO YUDEN EMK325F106ZH-T (4) ADCINA6 ADCINA6 XD5
167 39 XD6
(4) ADCINA7 ADCINA7 XD6
2 54 XD7
(4) ADCINB0 ADCINB0 XD7
3 65 XD8
(4) ADCREFM (4) ADCINB1 ADCINB1 XD8 XD9

FLASH - 3.3V
(4) ADCREFP (4) ADCINB2 4 68
ADCINB2 XD9 XD10
5 73

VDD I/0 -3.3V

VDD CORE - 1.8V
(4) ADCINB3 ADCINB3 XD10
6 74 XD11
(4) ADCINB4 ADCINB4 XD11
10UF CERAMIC LOW ESR 7 96 XD12
(4) ADCINB5 ADCINB5 XD12
C35 8 97 XD13
(4) ADCINB6 ADCINB6 XD13
9 139 XD14
(4) ADCINB7 ADCINB7 XD14
147 XD15
10UF CERAMIC LOW ESR XD15
11
C36 ADCREFP
10 ADCREFM
16 44 RN2A 1
ADCRESEXT XZCS0AND1n A B 16 XZCS0AND1n (4)
R26 12 88 RN2B 2 33 15
AVSSREFBG XZCS2n A B XZCS2n (4)
24.9K VDDA1 13 133 RN2C 3 33 14
AVDDREFBG XZCS6AND7n A B XZCS6AND7n (3)
TP3 175 84 RN2D 4 33
ADCLO XWEn A B 13 XWEn (3,4)
ADCBGREFIN 164 42 RN2E 5 33
ADCBGREFIN XRDn A B 12 XRDn (3,4)
C
51 RN2F 6 33 11 C
XRnW A B XRnW (4)
TP 161 33 XREADY (4)
XREADY
XMP/MCn 17 XMP_MCn (4)
159 XHOLDn (4)
XHOLDn
(4) PWM1 92 82 XHOLDAn (4)
GPIOA0-PWM1 XHOLDAn
(4) PWM2 93 GPIOA1-PWM2 XRSn 160 XRSn (5)
(4) PWM3 94 GPIOA2-PWM3
(4) PWM4 95 77 X1_CLKIN (4)
GPIOA3-PWM4 X1/XCLKIN
(4) PWM5 98 76
GPIOA4-PWM5 X2
(4) PWM6 101 GPIOA5-PWM6 XCLKOUT 119 XCLKOUT (4)
(4) T1PWM_T1CMP 102 GPIOA6-T1PWM_T1CMP
(4) VREFLO 104 134
(4) T2PWM_T2CMP GPIOA7-T2PWM_T2CMP TESTSEL XTESTSEL (3,4,5,6)
(4) CAP1_QEP1 106 GPIOA8-CAP1_QEP1 TEST1 67
(4) CAP2_QEP2 107 GPIOA9-CAP2_QEP2 TEST2 66
(4) CAP3_QEPI1 109
GPIOA10-CAP3_QEPI1
(4) TDIRA 116 135 C28_TRSTn (5)
GPIOA11-TDIRA TRSTn
(4) TCLKINA 117 GPIOA12-TCLKINA TCK 136 C28_TCK (5)
(4) C1TRIPn 122 GPIOA13-C1TRIPn TMS 126 C28_TMS (5)
(4) C2TRIPn 123 131 C28_TDI (5)
GPIOA14-C2TRIPn TDI
(4) C3TRIPn 124 127 C28_TDO (5)
GPIOA15-C3TRIPn TDO
EMU0 137 C28_EMU0 (5)
(4) PWM7 45 GPIOB0-PWM7 EMU1 146 C28_EMU1 (5)
(4) PWM8 46
GPIOB1-PWM8
(4) PWM9 47 GPIOB2-PWM9 GPIOF0-SPISIMOA 40 SPISIMOA (4)
B (4) PWM10 48 GPIOB3-PWM10 GPIOF1-SPISOMIA 41 SPISOMIA (4) B

(4) PWM11 49 34 SPICLKA (4)

GPIOB4-PWM11 GPIOF2-SPICLKA
(4) PWM12 50 35 SPISTEA (4)
GPIOB5-PWM12 GPIOF3-SPISTEA
(4) T3PWM_T3CMP 53 GPIOB6-T3PWM_T3CMP
(4) T4PWM_T4CMP 55 GPIOB7-T4PWM_T4CMP GPIOF8-MCLKXA 28 MCLKXA (4)
(4) CAP4_QEP3 57 25 MCLKRA (4)
SINGLE POINT CONNECTION GPIOB8-CAP4_QEP3 GPIOF9-MCLKRA
(4) CAP5_QEP4 59 26 MFSXA (4)
TP2 GPIOB9-CAP5_QEP4 GPIOF10-MFSXA
1 (4) CAP6_QEPI2 60 GPIOB10-CAP6_QEPI2 GPIOF11-MFSRA 29 MFSRA (4)
(4) TDIRB 71 GPIOB11-TDIRB GPIOF12-MDXA 22 MDXA (4)
AGND 72 20
(4) TCLKINB GPIOB12-TCLKINB GPIOF13-MDRA MDRA (4)
(4) C4TRIPn 61 GPIOB13-C4TRIPn
(4) C5TRIPn 62 GPIOB14-C5TRIPn GPIOF4-SCITXDA 155 SCITXDA (4)
(4) C6TRIPn 63 157 SCIRXDA (4)
GPIOB15-C6TRIPn GPIOF5-SCIRXDA
ADC

L4 110 90
GPIOD0-T1CTRIP_PDPINTAn GPIOG4-SCITXDB SCITXDB (4)
( 1.8V ) (4) T1CTRIP_PDPINTAn 115 91
GPIOD1-T2CTRIPn_EVASOCn GPIOG5-SCIRXDB SCIRXDB (4)
1.8V VDD1 (4) T2CTRIPn_EVASOCn 79 GPIOD5-T3CTRIP_PDPINTBn
(4) T3CTRIP_PDPINTBn 83 87
GPIOD6-T4CTRIPn_EVBSOCn GPIOF6-CANTXA CANTXA (4)
BLM21P221SN (4) T4TRIPn_EVBSOCn
1.8V

GPIOF7-CANRXA 89 CANRXA (4)

C2 C58 C56 149
1uF (4) XINT1n_XBIOn GPIOE0-XINT1_XBIOn
.1uF .001uF 151 140 XF_XPLLDISn (4)
(4) XINT2n_ADCSOC GPIOE1-XINT2_ADCSOC GPIOF14-XF-XPLLDISn
150
VDDA2
VSSA1
VSSA2
VDD1
VSS1
VDDAIO
VSSAIO
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16

(4) XNMIn_XINT3 GPIOE2-XNMI_XINT13

3.3V L3
14 VDDA1
166
15
165
162
163
1
176
19
32
38
52
58
70
78
86
99
105
113
120
129
142
153

A
( 3.3V ) A
VDDA1 TMS320F2812PGF
DSP
BLM21P221SN
C3 C57 C38 C37 SPECTRUM DIGITAL INCORPORATED
1uF .1uF .1uF .001uF
Title
TMS320F2812 EzDSP

Size Document Number Rev

LOCATE NEAR DSP B 506262 C

Date: Wednesday, June 04, 2003 Sheet 2 of 6

5 4 3 2 1

A-3
Spectrum Digital, Inc
 5 4 3 2 1

A-4
D D
Spectrum Digital, Inc

XA[0..18] (2,4)

C XD[0..15] (2,4) C

3.3V

C22 C10
0.1uF 0.1uF

11
33
U4

VDD1
VDD2
XA0 1 7 XD0
XA1 A0 D0 XD1
2 8
XA2 A1 D1 XD2
3 A2 D2 9
XA3 4 10 XD3
A3 D3
XA4 5 13 XD4
XA5 A4 D4 XD5
18 14
XA6 A5 D5 XD6
19 A6 D6 15
XA7 20 16 XD7
XA8 A7 D7 XD8
21 29
XA9 A8 D8 XD9
B 24 A11 D9 30 B
XA10 25 31 XD10
A12 D10
XA11 26 32 XD11
XA12 A13 D11 XD12
27 35
XA13 A14 D12 XD13
42 A15 D13 36
XA14 43 37 XD14
A16 D14
XA15 44 38 XD15
A17 D15
XA16 22
XA17 A9
23 A10
NC 28
(2) XZCS6AND7n 6
CS
(2,4) XWEn 17
64Kx16 and 256Kx16 WE
(2,4) XRDn 41 OE
Compatible
40
BHE
39 BLE
VSS1
VSS2
IS61LV6416-12T 12
34

A A

SPECTRUM DIGITAL INCORPORATED

ASRAM Title
TMS320F2812 EzDSP
(2,4,5,6) GND
Size Document Number Rev
B 506262 B

Date: Wednesday, June 04, 2003 Sheet 3 of 6

5 4 3 2 1

eZdspTM F2812 Technical Reference

 8 7 6 5 4 3 2 1

JP5 Make a solder connection on JP4

3.3V +5V 3.3V +5V
JP4 and/or JP5 to the
3 1 3 1

B
B
C A appropriate power supply. C A T M S3 2 0 F2 8 1 2 s up p o r t s 3 .3 V XF_XPLLDISn (2)
JUMPER3_SMT JUMPER3_SMT

2
2
i n p u t /o u t p u t l e v e l s w h i c h a re PLLDISn

P2 P8 N OT 5 V t o l e r a n t . Co n n e c t i n g R42 10K 1 JP9

3.3V
1 2 1 2 2
t he eZdsp t o a s yst em w it h 5V R41 2.2K 3
(2,3) XD0 3 4 XD1 (2,3) (2) SCITXDA 3 4 SCIRXDA (2)
D (2,3) XD2 5 6 XD3 (2,3) (2) XINT1n_XBIOn 5 6 CAP1_QEP1 (2) 3.3V D
JUMPER3B
(2,3) XD4 7 8 XD5 (2,3) (2) CAP2_QEP2 7 8 CAP3_QEPI1 (2) i n p u t /o u t p u t l e v e l s w i l l d a m a g e
(2,3) XD6 9 10 XD7 (2,3) (2) PWM1 9 10 PWM2 (2)
DS2
(2,3) XD8 11 12 XD9 (2,3) (2) PWM3 11 12 PWM4 (2) t h e T M S3 2 0 F2 8 1 2 . If t h e e Z d s p LTST-C150GKT
(2,3) XD10 13 14 XD11 (2,3) (2) PWM5 13 14 PWM6 (2) GREEN
(2,3) XD12 15 16 XD13 (2,3) (2) T1PWM_T1CMP 15 16 T2PWM_T2CMP (2) i s c o n n e c t e d t o a n o t h e r t a rg e t
(2,3) XD14 17 18 XD15 (2,3) (2) TDIRA 17 18 TCLKINA (2)
C62
(2,3) XA0 19 20 XA1 (2,3) 19 20 3.3V
t h e n t h e e Zd s p m u s t b e .1uF
(2,3) XA2 21 22 XA3 (2,3) 21 22 XINT1n_XBIOn (2)
(2,3) XA4 23 24 XA5 (2,3) (2) SPISIMOA 23 24 SPISOMIA (2)
pow ered up first and pow ered U12 R43
5

(2,3) XA6 25 26 XA7 (2,3) (2) SPICLKA 25 26 SPISTEA (2)

SN74AHC1G14 XF
(2,3) XA8 27 28 XA9 (2,3) (2) CANTXA 27 28 CANRXA (2) 220
(2,3) XA10 29 30 XA11 (2,3) (2) XCLKOUT 29 30 PWM7 (2) d o w n l a s t t o p r e v e n t l a t c hu p
(2,3) XA12 XA13 (2,3) PWM9 (2) 2 4
31 32 (2) PWM8 31 32
(2,3) XA14 33 34 XA15 (2,3) (2) PWM10 33 34 PWM11 (2) condi t ion s .
35 36 (2) PWM12 35 36 CAP4_QEP3 (2) XF
(2) XZCS0AND1n 37 38 XZCS2n (2) (2) T1CTRIP_PDPINTAn 37 38 T3CTRIP_PDPINTBn (2)
3

ISn
(2) XREADY 39 40 STRBn 39 40
(2) XRnW 41 42 3.3V
(2,3) XWEn 43 44 XRDn (2,3)
3.3V 45 46 XNMIn_XINT3 (2)
DSP_RSn XTESTSEL
(5) DSP_RSn 47 48
49 50 XTESTSEL (2,3,5,6)
51 52
C (2,3) XA16 XA17 (2,3) P4 P7 C
53 54
(2) XA18 55 56 XHOLDn (2) 1 1 C1TRIPn (2)
1 JP1 XMPNMC
(2) XHOLDAn 57 58 (2) XINT2n_ADCSOC 2 2 C2TRIPn (2)
59 60 (2) MCLKXA 3 3 C3TRIPn (2) 2 XMP_MCn (2)
(2) MCLKRA T2CTRIPn_EVASOCn (2) 3
4 4 JUMPER3B
HEADER 30X2 (2) MFSXA C4TRIPn (2)
5 5
(2) MFSRA 6 6 C5TRIPn (2)
R39 10K 1 JP12 BOOT-0
(2) MDXA 7 7 C6TRIPn (2)
(2) MDRA T4TRIPn_EVBSOCn (2) 2 SPICLKA (2)
8 8 R36 2.2K
9 9 3
P9 10 10
JUMPER3B
1 2 ADCINA0 (2) (2) CAP5_QEP4 11
3 4 ADCINA1 (2) (2) CAP6_QEPI2 12 R38 10K 1 JP11 BOOT-1
5 6 ADCINA2 (2) (2) T3PWM_T3CMP 13
7 8 ADCINA3 (2) (2) T4PWM_T4CMP 14 2
R35 2.2K 3 SPISTEA (2)
9 10 ADCINA4 (2) (2) TDIRB 15
11 12 ADCINA5 (2) (2) TCLKINB 16 JUMPER3B
13 14 ADCINA6 (2) (2) XF_XPLLDISn 17
15 16 ADCINA7 (2) (2) SCITXDB 18
R40 10K 1 JP8 BOOT-2
17 18 VREFLO (2) (2) SCIRXDB 19
BOOT MODE

19 20 20 2 MDXA (2)
R37 2.2K 3
Connect VREFLO to AGND or
JUMPER3B
to VREFLO of target system
B P5 B
for proper ADC operation. R31 10K 1 JP7 BOOT-3
1 ADCINB0 (2)
ADCINB1 (2) 2 SCITXDA (2)
2 R30 2.2K
ADCINB2 (2) 3
3
4 ADCINB3 (2)
JUMPER3B
5 ADCINB4 (2)
L1 3.3V
6 ADCINB5 (2)
7 ADCINB6 (2)
8 ADCINB7 (2) (2,6) 1.8V BOOT-3 BOOT-2 BOOT-1 BOOT-0 MODE
9 ADCREFM (2)
BLM21P221SN SCITXDA MDXA SPISTEA SPICLKA
10 ADCREFP (2)
C43

U14 1 X X X FLASH
0.1uF

5
0 1 X X SPI
R1 SN74LVC1G14 U11
Tie off unused F24xx
4 2 8 1 0 0 1 1 SCI
compatible signals. (2) X1_CLKIN VCC OFFn
100
2

JP3 R29 0 0 1 0 H0
R6
B

1 3 5 4
A C CLK GND

3
ISn 100 0 0 0 1 OTP
3.3V
10K JUMPER3_SMT C42 NO-POP 0 0 0 0 PARALLEL
A R5 Schematic change from version A
STRBn 33 pF
A/B to C. F2812 clkin is 1.8V SMT/4PIN DIP
10K input.
GND
(5) MCLK OPTIONAL
GND (2,3,5,6)
Title
TMS320F2812 EzDSP
AGND (2,3,5,6)
Size Document Number Rev
B 506262 C

8 7 6 5 4 3 Date: 2
Wednesday, June 04, 2003 Sheet 4 1 of 6

A-5
Spectrum Digital, Inc
 5 4 3 2 1

R16
U5

A-6
10K
XPPD7 RN4A 1 16 33 2 18 RN3A 1 16 33 R14
XPPD6 RN4B A B 33 A1 B1 RN3B A B 33 C52
2 A B 15 3 A2 B2 17 2 A B 15
XPPD5 RN4C 3 14 33 4 16 RN3C 3 14 33
A B A3 B3 A B 33pf C53 10K
XPPD4 RN4D 4 13 33 5 15 RN3D 4 13 33 R13
XPPD3 RN4E A B 33 A4 B4 RN3E A B 33
5 A B 12 6 A5 B5 14 5 A B 12 33pf
XPPD2 RN4F 6 11 33 7 13 RN3F 6 11 33 C54
XPPD1 RN4G A B 33 A6 B6 RN3G A B 33 10K
7 A B 10 8 A7 B7 12 7 A B 10 33pf
XPPD0 RN4H 8 9 33 9 11 RN3H 8 9 33 C55
A B A8 B8 A B PPTRSTn
C33 33pf
PPBUSENn 19 20 5V 3.3V
PPBUSDIR G VCC P1 R17
1 DIR 33pf
10 C50 C51 C32 PPTMS
GND PPTDI 1 2
.1uF .001uF C31 33pf 5V 3 4 10K
74ABT245PW PPTDO 5 6 EMUOFF
D D
33pf C29 PPTCK 7 8
P3 9 10
U2 33pf DB25_SHIELD 11 12
PPEMU0
XPPS4 RN1A 33 PPSLCT 13 14
2 A1 B1 18 1 A B 16 13
XPPS5 3 17 RN1B 2 15 33 25
A2 B2 A B HEADER 7X2
XPPS7n 4 16 RN1C 3 14 33 PPPE 12
XPPS3 A3 B3 RN1D A B 33 PPEMU1
5 A4 B4 15 4 A B 13 24
6 14 RN1E 5 12 33 PPBSY 11
A5 B5 RN1F A B 33
7 A6 B6 13 6 A B 11 23
8 12 RN1G 7 10 33 PPACKn 10 XDS510PP EMULATION HEADER
A7 B7 RN1H A B 33
9 A8 B8 11 8 A B 9 22
PPD7 9
19 20 5V 21
5V G VCC PPD6
1 DIR 8
10 C27 C28 20
GND PPD5 7
.1uF .001uF 19
PPEMU0/1 CONNECT DIRECTLY TO F2812 FOR
Spectrum Digital, Inc

74ABT245PW PPD4 6
18 EMULATOR WAIT-IN-RESET SUPPORT
PPD3 5
PPSELn 17
PPD2 4
PPINITn 16
PPD1 3
XPPC3n PPERRn 15
PPD0 2 PONRSnIN PONRSnIN (6)
XPPC2 PPALEn 14
PPSTRBn 1 B
XPPC1n XTRSTn
C28_TRSTn (2)

A
XPPC0n PLACE NEAR EACH MOUNTING HOLE XTMS
C28_TMS (2)
XTDI C28_TDO (2) CROSS COUPLE IN TO OUT
3.3V
XTDO C28_TDI (2)
R19 R47 XTCK C28_TCK (2)
C C16 C67 C
R11 XEVNT0
C28_EMU0 (2)
1M .001uF 1M .001uF
R12 10K XEVNT1
R20 C28_EMU1 (2)
R25 C34 10K
100
100 33pf R22 TPOWLOSSn
R24 C30 10K

100 33pf
R15 C15
R8 33 XTCK
100 33pf
R10 33 PPTCK R18 C17
100 33pf
R9 33 PPTDO 3.3V

C14 C25 C26 C49

0.1uF 0.1uF 0.1uF 0.1uF

Locate R7,R54, C70 at the DSP XRSn pin

FPGA_VCCA
EMUOFF

3.3V

XEVNT0
XTRSTn
PPTRSTn
XTDI
GND
XTCKI
XTMS
PPTMS
XTDO
PPTDI

VCCR
GND
JCLK
for best EMI/ESD noise immunity.

IPPTCK
3.3V
3.3V R49

100
99
98
97
96
95
94
93 IPPTDO
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
U6 0
XRSn is logical AND of PONRSnIN and
U13
emulator controlled reset. Power on default

GND

XTDI
VCCI

JCLK

VCCA
XTMS
XTDO
FPGA_VCCA

XTCKI
PPTDI
1 5

RSV10
is PONRnIN controls XRSn.

PPTCK
PPTDO
PPTMS
IN OUT

XTRSTn

XEVNT0
R7

PPEMU0
PPTRSTn
ODEMU0n
ODEMU1n

VCCR_NC
1.5K 2

EMUOFF_1
B
R54 GND R50 B

ODEMU0_SRC
ODEMU1_SRC

RSV13_TCK_IO
RSV11_PRA_IO
GND 1 75 DSP_RSn OPEN-DRAIN 3 4 C45 C23 C24 C11 C68
GND DSP_RSn XRSn (2) EN NC/FB 0.1uF 0.1uF 0.1uF 0.1uF 1uF
2 74 100 41.2K 1%
3.3V RSV1_TDI_IO MCLKOUT GND IF U13 IS INSTALLED THEN
3 EMUOFF MCLKOUTEN 73 TPS72201
3.3V XEVNT1 4 72 C70 REMOVE R49 AND R48.
XEVNT1 MCLKOUT2 GND 22nF
5 71
PPEMU1 MCLKOUT2EN 3.3V
6 RSV2 EXTERN_RSTn 70
R23 7 69 GND R51
3.3V RSV3_TMS_IO GND GND
10K 8 VCCI GND 68
GND 9 67 FPGA_VCCA DSP_RSn (4) 40.2K 1%
XPPD0 GND VCCA
10 XPPD0 SPECTRUM DIGITAL I NC. XBITOUT0 66
XPPD1 11 65 To/from expansion header
XPPD2 XPPD1 XBITOUT1
12 EMBEDDED PP JTAG CON TROLLER 64
XPPD3 XPPD2 XBITOUT2 +5V
13 XPPD3 XBITOUT3 63
XPPD4 14 62 GND R48
XPPD4 506053-000 1B XBITIN0
XPPD5 15 61 GND VCCR
XPPD6 XPPD5 EXT_VER 00110-001 XBITIN1 GND 0
16 60
XPPD7 XPPD6 XBITIN2 GND
17 XPPD7 XBITIN3 59
18 58 3.3V
RSV4 VCCI
19 57 FPGA_VCCA C47 C13
3.3V RSV5 VCCA 0.1uF 0.1uF
20 VCCI VBUS_ENn 56
XPPS3 21 55
XPPS4 XPPS3 VPOWER_BLEED
22 XPPS4 VPOWER_ONn 54
XPPS5 23 53 3.3V
XPPS5 EXT_VER0 GND
24 XPPS6 EXT_VER1 52
XPPS7n 25 51 GND
XPPS7n GND

PPBUSENn
RSV6
PPBUSDIR
RSV7
XPPC3n
XPPC2
XPPC1n
XPPC0n
RSV8_PRB_IO
VCCA
GND
VCCR_NC
ALT_MCLK
HCLK
RSV9
PONRSn
TPOWLOSSn
VFUNC_EN
VCCI
EXT_VER7
EXT_VER6
EXT_VER5
EXT_VER4
EXT_VER3
EXT_VER2
L2 3.3V

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
506053-0001B

BLM21P221SN
A A
C48

GND
VCCR
GND
3.3V
GND
GND
3.3V
3.3V
GND
GND

FPGA_VCCA

PPBUSENn
PPBUSDIR
XPPC3n
XPPC2
XPPC1n
XPPC0n
0.1uF 5V
+5V

MCLK
PONRSnIN
TPOWLOSSn

ALT_MCLK
3.3V 3.3V
U10 GND
GND (2,3,4,6)
8 VCC OFFn 1
R32
SPECTRUM DIGITAL INCORPORATED
(4) MCLK 5 CLK GND 4
33 Title
TMS320F2812 EzDSP
C46 30 MHz
Size Document Number Rev
NO-POP CBLV-3C-30.000 C 506262 C

Date: Wednesday, June 04, 2003 Sheet 5 of 6

5 4 3 2 1

eZdspTM F2812 Technical Reference

 5 4 3 2 1

+5V
18.2K 1.899V
P6 U9 16.9K 1.848V
5 28 15.0K 1.773V
1IN 1RESET 13.7K 1.722V
6
C66 1IN
R44 + CT2 1.8VONn 4 23
+5V Max 220 47uF 1EN 1OUT 1.8V (2,4)
0.1uF 24
1OUT R33
25 C64
1FB/SENSE 16.9K, 1% + CT3
3
1GND 22uF 0.1uF
D D
R45 30.1K, 1%
DS1 11 22
LTST-C150GKT 2IN 2RESET
12 2IN
GREEN C65 3.3V
10 17
2EN 2OUT
0.1uF 18
2OUT
2SENSE 19
9 C63
R46 2GND + CT4
10K 22uF 0.1uF
1 NC NC 15
3.3V 2 16 R52
NC NC
7 20 VDD3VFL (2)
NC NC 0
U16 8 NC NC 21
13 NC NC 26
1 R53 14 27 3.3V C1 C7

THERMAL_PAD
CT NC NC 1uF
5 .1uF

D
VDD 1.5K 1% TPS767D301
2 Q3
GND
4 G BSS138
RESETn R2

S
3 MRn 10K
R34
C
TIE TPS767D301 POWER PAD TO GND C
TPS3838K33DBV 2.0K 1%
PLANE (TI-SLMA002)
PONRSnIN (5)
RESETn of TPS3838 is open-drain.
U16 was added for testing but not
populated on production boards.

1.8V (2,4)

+ CT6 + CT5 C19 C18 C5 C8 C21 C41 C40 C61 C59

22uF 22uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

3.3V

B B

+ CT1
22uF C20 C6 C9 C39 C60
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
TP1
1
GND

(2,3,4,5) GND

POWER ON SEQUENCE NOTES TPS767D301 RATINGS

3.3V THEN 1.8V 3.3V SUPPLY, VDDIO MAX Iout PER CHANNEL IS 1A
VDD3VFL, VDDA1,VDDA2
PONRSnIN, GOES HIGH > 200ms AFTER ALL POWER TPS767D301 PD = (Vin-Vout)*Iout
IS STABLE. 2.2V Q3
VOLTAGE SUPPLY MAX CURRENT TPS767D301 PD

SET Q3 TO TURN ON WHEN 3.3V SUPPLY IS 1.8V SUPPLY 1.8V 333mA 1065mW
A
GREATER THEN 2.2 VOLTS. REGULATOR A

TURN ON DELAY AND RAMP RATE WILL 3.3V 307mA 521mW

ENSURE THAT 3.3V SUPPLY IS AT 2.5 VOLTS
1586mW Total
OR HIGHER BEFORE THE 1.8V SUPPLY 140ms-280ms
REACHES 0.3 VOLTS. PD(max) = (Tj(max) - Ta)/Rja
SPECTRUM DIGITAL INCORPORATED
Title
U16 WILL TURN OFF THE 1.8V SUPPLY WHEN PONRSnIN = (125 - 35)/27.9 TMS320F2812 EzDSP
INPUT POWER FALLS BELOW 2.94V. THIS SPEEDS
UP THE 1.8V SUPPLY TURN OFF. = 3255mW Size Document Number Rev
B 506262 C

Date: Wednesday, June 04, 2003 Sheet 6 of 6

5 4 3 2 1

A-7
Spectrum Digital, Inc
Spectrum Digital, Inc

A-8 eZdspTM F2812 Technical Reference

 Appendix B
eZdspTM F2812
MechanicaI Information

This appendix contains the mechanical information about the socketed and
unsocketed versions of the eZdspTM F2812

B-1
Spectrum Digital, Inc

This drawing is not to scale

B-2 eZdspTM F2812 Technical Reference

 This drawing is not to scale

B-3
Spectrum Digital, Inc
Spectrum Digital, Inc

B-4 eZdspTM F2812 Technical Reference

Printed in U.S.A., September 2003
506265-0001 Rev. F