decoder1.

vhd Sun Oct 03 20:03:20 2010

1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 19:29:02 10/03/2010
6 -- Design Name:
7 -- Module Name: decoder1 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25 ---- Uncomment the following library declaration if instantiating
26 ---- any Xilinx primitives in this code.
27 --library UNISIM;
28 --use UNISIM.VComponents.all;
29
30 entity decoder1 is
31 Port ( a : in STD_LOGIC_VECTOR (2 downto 0);
32 y : out STD_LOGIC_VECTOR (7 downto 0));
33 end decoder1;
34
35 architecture Behavioral of decoder1 is
36
37 begin
38 y<="00000001" when a="000" else
39 "00000010" when a="001" else
40 "00000100" when a="010" else
41 "00001000" when a="011" else
42 "00010000" when a="100" else
43 "00100000" when a="101" else
44 "01000000" when a="110" else
45 "10000000" when a="111" ;
46 end Behavioral;
47
48

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