CPF
Pushing power forward
with Common Power Format
By Dr. Chi-Ping Hsu
Chief Strategist
Product and Technology
Cadence Design Systems
Necessity, the mother of
invention
It is no news flash that power
has moved to centre stage for
design teams working at 90
nanometres (nm) and below. As
figure 1 shows getting sufficient
power to these devices is getting
more complex and costly, as is
managing the heat they dissi-
pate. Scaling of supply voltages,
the most common method of
controlling power, is running up
against the limits of the ability
to control process variability and
is beginning to affect reliability
and to create unrealistic strain
on design-closure practices.
Further, the voltage scaling has
negated the performance scaling
that used to be counted on for
performance boosts to old archi-
tectures. In other words, process
scaling is stalling and it is stalling
because of power.
With no heir apparent to bulk
CMOS process technology that
will solve the power problem
using device physics in sight,
design-based methods must be
employed to control the power
hydra that assaults costs, sched-
ules and profitability.
In the spring of 2005, while
the finishing touches of the
core technology support for
multi-supply voltage, dynamic
voltage and frequency scal-
ing, and power shut-off design
techniques in the front-end
design process were being
completed, it became clear
that there was a huge problem.
The guardians of the design
automation infrastructure had
fallen asleep. The constraint
and library formats, along
with the hardware description
languages had fallen way be-
hind the design community’s
Figure 1: Left) Power dissipation in advanced CMOS process nodes now rivals where the industry was with Bipolar
technology around 1990; Right) voltage scaling has helped reduce power, but with a mounting performance
penalty and is reaching device physics limitations
innovations with respect to
their ability to support the now
critical low-power design tech-
niques. “Low-power design”
had been relegated to a back-
end, physical-design process.
Lack of abstraction in the
physical-design process, adds
further complexity to the already
complicated deployment of
low-power design techniques.
Further, deferring the represen-
tation of power-saving tech-
niques until near the end of
the project schedule leads to
surprises, exacerbates schedule
pressure, and leaves no room
for exploration of alternative
strategies.
Figure 2 depicts the mature
state of the infrastructure for
functional design versus the
chaotic state of the infrastruc-
ture support for advanced low-
power design techniques.
This state of chaos is an in-
dustry problem, which needs
an industry-wide solution.
As such, every effort is being
made to advance as rapidly as
possible, using and open and
inclusive approach. The design
community “needed this yes-
terday” as they say.
With the necessity clear,
architects within the Cadence
R&D organization began to
meet to devise a solution.
After considerable internal de-
bate and consultation with its
biggest customers, Cadence
decided that this effort to for-
mulate a solution needed to
be on the fast track to indus-
try standardization. Thus, the
Power Forward Initiative came
into being. It was also clear that
a fresh approach was needed;
the haphazard duct-tape and
bailing-wire-like extensions
to the existing infrastructure
were described by one design
lead as “cancerous.” A clean
slate, with a fresh start was
required -- an architecture that
addressed the issue of power
in a comprehensive and holistic
manner.
As partners from every con-
ceivable stake-holding view-
point were being recruited, the
Cadence R&D team began flesh-
EE Times-India | November 2006 | eetindia.com
ing out a detailed specification
from which the initiative body
could work. While necessity
has proven to be the mother of
invention, the task of creat-
ing a complete and consistent
Common Power Format (CPF)
proved to be quite a challenge.
The current draft of the
CPF represents over 100-man
years of effort and includes
more than 500 modifications
over the past six months that
include input from:
• Semiconductor manufactur-
ing equipment
• Semiconductor manufactur-
ing (foundry)
• IDM (system design through
silicon manufacturing)
consumer, computing, net-
working
• Processor design
• High-end graphics process-
ing
• Cell phone design
• Automotive
• EDA
• Intellectual Property (core
processors & peripherals)
• Library provider

Requirements
The result of the paucity of
power-design support in the
industry infrastructure is a gap in
the design techniques needed to
control power dissipation and the
ability of the design environment
to support those techniques in
a safe and efficient manner. The
specification must be architected
to supply the infrastructure needs
to support the state of the art in
low-power design styles and
techniques such that risk is dra-
matically reduced, as is the effort
in their realization.
The broad participation
in creating the requirements
specification has ensured that a
comprehensive solution could
be architected, and that the
resultant architecture would be
holistic in nature. The primary
attributes requirements of the
solution are:
• Easy to adopt to overcome
cost, time and risk-deploy- Figure 2: Left) Mature and orderly state of functional design infrastructure enabled by standard hardware
ment issues description languages such as Verilog, VHDL and SystemVerilog. Right) Relative state of chaos created because of
• Incremental to existing in- lack of infrastructure support for advanced low power design techniques.
frastructure; overlay on top
of methods in place ysis has led to an initial scope of
• Non-intrusive to existing support for a digital RTL to sign-
practices, methodologies off solution. Although limited in
and flows scope, the solution is quite broad
• Serves IP/re-use method- in terms of design-automation
ologies with a minimal incre- technology inclusion:
mental effort • RTL/gate simulation
• Consolidated view of the • Hardware simulation accel-
power strategy for a design eration
into a single entity • Hardware emulation
• Comprehensive in capabili- • Formal analysis (assertion-
ties to support the most ad- based verification)
vanced existing low-power • Design analysis & rule
design techniques, across checking
the entire continuum of de- • Formal verification
sign automation • Synthesis & optimization
• Extensible to new low- • Floorplanning
power design techniques • Silicon virtual prototyping
and to broader design- • Power analysis
flow scope (up to system- • Physical synthesis / place-
level and into analogue ment
mixed signal in particular) • Clock tree synthesis
• Power grid design
Scope and content • Power integrity analysis
While the broad spectrum of • Design for Test
perspectives and viewpoints pre- • Automatic test pattern gen-
sented above ensured complete- eration
ness from a chip-design team • Constraint generation
and supply-chain standpoint, in • Constraint verification Figure 3: Driven by Common Power Format, the design environment can be
the end, it is all about automating • Design project management automated to eliminate risks specific to the use of low-power design tech-
the design process. To that end, a • Design IP niques, and to automate the full scope of design, verification and implemen-
bottom-up approach to the anal- • Verification IP tation tool technologies.

 eetindia.com | November 2006 | EE Times-India

 The CPF is modelled after the
syntax of Tcl (Tool Command
Language). As such, it is light
in overhead, easy to learn, and
extensible by nature. CPF com-
mands cover the specification
of both the design requirements
and the binding to the technol-
ogy capabilities of the target
process. CPF includes the explicit
capture of the following ele-
ments related to the low-power-
design strategy with respect to
design requirements:
1. Power domain
• Logical: hierarchical mod-
ules as domain members
• Physical: power/ground
nets and connectivity
• Analysis view: timing
library sets for power do-
mains
2. Power Logic Figure 4:. Block diagram of processor that will implement power shut-down with state retention for key state informa-
• Level Shifter Logic tion. Design is to have four switchable power domains.
• Isolation Logic
• State-Retention logic The result of adopting the tional verification to validate • Increased productivity and
• Switch Logic & Control Common Power Format into power-related operation reduced cost of using those
Signals standard design flows will have • Higher design quality with power-saving methods
3. Power modes some fundamental benefits to fewer functional failures
• Mode definitions those that deploy it along with • Reduced risk in applying What’s a user to do?
• Mode transition expres- industry-leading tool solutions: state-of-the-art, low-power With the design-environment-
sions • Enablement of RTL func- design techniques infrastructure chasm bridged by
the Common Power Format, de-
signers can immediately deploy
the most advanced low-power
techniques with minimal effort
and risk. The first and most vis-
ible place for a design team to
begin is with RTL simulation. CPF
enables functional verification of
the power-related behaviour in
chip design. Figure 4 depicts a
design that will implement pow-
er shut-off modes, and will use
state-retention cells to minimize
wake-up time.
Logic design teams then
need to describe the sequence
of signal behaviours for power
management. Below, a simple
power-control sequence in
Verilog is shown.

else if (decode &&

opcode == matchDN) //
POWER DOWN SEQUENCE
case (counter) // ISO,
SRPG, PWR
4’D3: ps[`ISO] <= 1;
Figure 5:. Power sequence error detected during RTL simulation driven with the addition of the Common Power 4’D5: ps[`PWR] <= 1;
Format specification. Shows that power-control signal prior to state-retention initiation causes latching of unknown 4’D9: ps[`SRPG] <= 1;
values instead of desired present operating state information. endcase

EE Times-India | November 2006 | eetindia.com 

 Formerly, there was then a
disconnect between the further
implementation of the power
structures in the design and the
simulation of the power control
signals. This gap is bridged by
CPF. It enables design teams to
discover very quickly that the
above control sequence is actu-
ally erroneous. Figure 5 shows
the user environment for the de-
signer to detect very efficiently
that a coding-specification error
has been made.
Future of the common
power format
The pragmatic approach of
limiting the scope of the first
Common Power Format through
the standardization should yield
the benefit of a faster path to
ratification, and faster availability
of tools and flows that support
that standard. Once in place,
this infrastructure immediately
 eetindia.com | November 2006 | EE Times-India
enables new levels of automa-
tion in design, verification and
implementation. On top of that
infrastructure there are exciting
new classes of products being
planned surrounding analysis,
exploration, and optimization.
Notwithstanding those ben-
efits, there is more work to be
completed. Specifically, there
is high-value work that needs
to be attacked with an equal
sense of urgency in the support
of analogue and mixed signal
design, as well as pushing up to
the system level. In many sys-
tem-on-chip designs today the
analogue components of the
chip consume a very significant
amount of the power budget. To
create a global power view for
design exploration and trade-
off analysis, these components
need to be modelled along with
their digital counterparts. As was
the case for the digital portion
of the design-environment in-
frastructure, there is a gap that
needs to be filled. Extensions to
CPF are a natural vessel for this
information.
System-design extensions to
CPF will enable a higher-level
view of computation-energy
trade-offs between software and
hardware alternatives to perfor-
mance and function. Because
these sorts of architectural de-
cisions can have a tremendous
impact on the overall energy
consumption profile, design-au-
tomation support in this area is
of great value. Again, in order to
provide automation at this level
for exploration and analysis, the
industry infrastructure gap
needs to be addressed.
Appreciating the effort
Driving forward to solve the crisis
in industry infrastructure support
for low-power design has been
a monumental task requiring fo-
cus and dedication. Recognizing
the problem, stepping up to do
something about it, and commit-
ting to an open and inclusive pro-
cess has been done in a manner
that merits recognition of true
industry leadership, in the real
sense of world leadership.
CPF has been a labour of love
for those that have participated
so far in its conceptualization
and realization. Looking forward,
this is an effort that should pay
significant dividends to the de-
sign community for decades to
come. We should thank those
conscientious R&D engineers
across the industry for their
labours that cumulatively total
over 100-man years for the cre-
ation of this work. Take some
time to appreciate the toil and
sweat that went into the cre-
ation of this work.