Professional Documents
Culture Documents
Sequential Design
Sequential Design
Inputs: 1 1 1 0 01 1 0 1 00 1 00 1 1 0 …
Outputs: 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 …
Here, one input and one output bit appear every clock cycle.
• This requires a sequential circuit because the circuit has to “remember”
the inputs from previous clock cycles, in order to determine whether or
not a match was found.
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
1/1
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
0/0 1/1
State Meaning
A None of the desired pattern (1001) has been input yet.
B We’ve already seen the first bit (1) of the desired pattern.
C We’ve already seen the first two bits (10) of the desired pattern.
D We’ve already seen the first three bits (100) of the desired pattern.
0/0 1/1
Present Next
State Input State Output
Remember how the state diagram A 0 A 0
arrows correspond to rows of the
A 1 B 0
state table:
B 0 C 0
B 1 B 0
present input/output next C 0 D 0
state state
C 1 B 0
D 0 A 0
D 1 B 1
Present Next
Present Next State Input State Output
State Input State Output Q1 Q0 X Q1 Q0 Z
A 0 A 0 0 0 0 0 0 0
A 1 B 0 0 0 1 0 1 0
B 0 C 0 0 1 0 1 0 0
B 1 B 0 0 1 1 0 1 0
C 0 D 0 1 0 0 1 1 0
C 1 B 0 1 0 1 0 1 0
D 0 A 0 1 1 0 0 0 0
D 1 B 1 1 1 1 0 1 1
Present Next
State Input State Flip flop inputs Output
Q1 Q 0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1
J K Q(t+1) Operation
0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Complement
Present Next
State Input State Flip flop inputs Output
Q 1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 0 0 0
1 1 1 0 1 1
Present Next
State Input State Flip flop inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0 x 0 x 0
0 0 1 0 1 0 x 1 x 0
0 1 0 1 0 1 x x 1 0
0 1 1 0 1 0 x x 0 0
1 0 0 1 1 x 0 1 x 0
1 0 1 0 1 x 1 1 x 0
1 1 0 0 0 x 1 x 1 0
1 1 1 0 1 x 1 x 0 1
Present Next
State Input State Flip flop inputs Output
Q1 Q0 X Q1 Q0 J1 K1 J0 K0 Z
0 0 0 0 0 0 x 0 x 0 J1 = X’ Q0
0 0 1 0 1 0 x 1 x 0 K1 = X + Q 0
0 1 0 1 0 1 x x 1 0
0 1 1 0 1 0 x x 0 0 J0 = X + Q 1
1 0 0 1 1 x 0 1 x 0
K0 = X’
1 0 1 0 1 x 1 1 x 0
1 1 0 0 0 x 1 x 1 0
1 1 1 0 1 x 1 x 0 1 Z = Q1Q0X
J1 = X’ Q0
K1 = X + Q 0
J0 = X + Q1
K0 = X’
Z = Q1Q0X
J1 = X’ Q0
K1 = X + Q 0
J0 = X + Q1
K0 = X’
Z = Q1Q0X
1 2 3 4
CLK
Q1
Q0
D1 = Q1 Q0’ X’ + Q1’ Q0 X’
D0 = X + Q1 Q0’
Z = Q1 Q0 X
D1 = Q1 Q0’ X’ + Q1’ Q0 X’
D0 = X + Q1 Q0’