Valid Chips Truth Table Pin Diagram

KEY
The numbers of chips that
are identical in function for
this lab appear here.
The Truth Table for the Gate(s) on the A diagram of the chip
chip appears here. appears here.
Pin Type (Gate Number & Gate
In/Output Identification)

Chip Pin Number

1A 1 14 Vcc
1B 2 13 3A
1Y 3 12 3B
2A 4 11 3Y
2B 5 10 4A
2Y 6 9 4B
GND 7 8 4Y

Gate Diagrams

7400 Quadruple 2-Input NAND Gates

N7400N N74H00N 1A 1 14 Vcc
Input Input Output
N74S00N N74LS00N A B Y
1B 2 13 3A
N7400F N74H00F 1Y 3 12 3B
L L H
L H H 2A 4 11 3Y
N74S00F N74LS00F 2B 5 10 4A
H L H
H H L 2Y 6 9 4B
GND 7 8 4Y

7402 Quadruple 2-Input NOR Gates

N7402N 1Y 1 14 Vcc
N74S02N N74LS02N Input Input Output 1B 2 13 3Y
A B Y 1A 3 12 3B
N7402F L L H 2Y 4 11 3A
N74S02F N74LS02F L H L 2B 5 10 4Y
H L L
2A 6 9 4B
H H L
GND 7 8 4A

7404 Six Inverters

N7404N N74H04N
Input Output
N74S04N N74LS04N A Y 1A 1 14 Vcc
N7404F N74H04F L H 1Y 2 13 6A
N74S04F N74LS04F H L 2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y

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 Valid Chips Truth Table Pin Diagram

7408 Quadruple 2-Input AND Gates

N7408N N74H08N
N74S08N N74LS08N 1A 1 14 Vcc
N7408F N74H08F Input Input Output 1B 2 13 3A
A B Y 1Y 3B
N74S08F N74LS08F L L L
3 12
2A 4 11 3Y
L H L
H L L 2B 5 10 4A
H H H 2Y 6 9 4B
GND 7 8 4Y

7410 Triple 3-Input NAND Gates

N7410N N74H10N Input Input Input Output 1A 1 14 Vcc
N74S10N N74LS10N A B C Y
1B 2 13 1C
L L L H
N7410F N74H10F L L H H 2A 3 12 1Y
N74S10F N74LS10F L H L H 2B 4 11 3A
L H H H 2C 5 10 3B
H L L H 2Y 6 9 3C
H L H H
GND 7 8 3Y
H H L H
H H H L

7411 Triple 3-Input AND Gates

N7411N N74H11N
Input Input Input Output
N74S11N N74LS11N A B C Y 1A 1 14 Vcc
N7411F N74H11F L L L L 1B 2 13 1C
L L H L 2A 3 12 1Y
N74S11F N74LS11F
L H L L 2B 4 11 3A
L H H L 2C 5 10 3B
H L L L 2Y 6 9 3C
H L H L GND 7 8 3Y
H H L L
H H H H

7420 Double 4-Input NAND Gates

N7420N N74H20N
Input Input Input Input Output
N74S20N N74LS20N A B C D Y 1A 1 14 Vcc
N7420F N74H20F L L L L H 1B 2 13 2A
N74S20F N74LS20F L L L H H 3 12 2B
L L H L H 1C 4 11
L L H H H 1D 2C
5 10
L H L L H
1Y 6 9 2D
L H L H H
L H H L H GND 7 8 2Y
L H H H H
H L L L H
H L L H H
H L H L H
H L H H H
H H L L H
H H L H H
H H H L H
H H H H L

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 Valid Chips Truth Table Pin Diagram

7421 Double 4-Input AND Gates

N7421N N74H21N
Input Input Input Input Output
N74LS21N A B C D Y
N7421F N74H21F L L L L L 1A 1 14 Vcc
L L L H L 1B 2 13 2A
N74LS21F 2B
L L H L L 3 12
L L H H L 1C 4 11
L H L L L 1D 5 10 2C
L H L H L 1Y 2D
6 9
L H H L L
GND 7 8 2Y
L H H H L
H L L L L
H L L H L
H L H L L
H L H H L
H H L L L
H H L H L
H H H L L
H H H H H

7425 Double 4-Input NOR Gates w/Enable

N7425N
Input Input Input Input Output
N7425F A B C D Y
1A 1 14 Vcc
L L L L H
L L L H L 1B 2 13 2A
L L H L L 1En 3 12 2B
L L H H L 2C 4 11 2En
L H L L L 1D 5 10 2C
L H L H L 1Y 6 9 2D
L H H L L GND 7 8 2Y
L H H H L
H L L L L
H L L H L
H L H L L
H L H H L
H H L L L
H H L H L
H H H L L
H H H H L

7427 Triple 3-Input NOR Gates

N7427N N74LS27N
Input Input Input Output
N7427F N74LS27F A B C Y
1A 1 14 Vcc
1B 2 13 1C
L L L H
2A 3 12 1Y
L L H L
L H L L 2B 4 11 3A
L H H L 2C 5 10 3B
H L L L 2Y 6 9 3C
H L H L GND 7 8 3Y
H H L L
H H H L

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 Valid Chips Truth Table Pin Diagram

7430 8-Input NAND Gate

N7430N
Input Input Input Input Input Input Input Input Output
N74H30N A B C D E F G H Y 1A 1 14 Vcc
N74LS30N H H H H H H H H L 1B 2 13
All Other Cases H 1C 3 12 1G
N7430F 1D 1H
4 11
N74H30F 1E 5 10
N74LS30F 1F 6 9
GND 7 8 1Y

7432 Quadruple 2-Input OR Gates

N7432N N74H32N 1A 1 14 Vcc
N74S32N N74LS32N 1B 2 13 3A
N7432F N74H32F Input Input Output 1Y 3 12 3B
A B Y 2A 4 11 3Y
N74S32F N74LS32F L L L 2B 5 10 4A
L H H
2Y 6 9 4B
H L H
H H H GND 7 8 4Y

7473 Dual JK Master-Slave Flip-Flop

N7473N N74H73N
N74LS73N N7473F Input Input Clear Output Output
J K Q(t+1) Q’(t+1)
N74H73F N74LS73F X X 0 0 1 1CP 1 J Q’
14 1J
>CP
0 0 1 Q(t) Q(t)’ 1R 2 K Q 13 1Q’
R
0 1 1 0 1 1K 3 ^ 12 1Q
1 0 1 1 0 Vcc 4 11 GND
1 1 1 Q(t)’ Q(t) 2CP 5 K Q 10 2K
>CP
Q(t) Input Input Output Output 2R 6 J Q’ 9 2Q
R
J K Q(t+1) Q’(t+1) ^
2J 7 8 2Q’
0 0 X 0 1
0 1 X 1 0
1 X 1 0 1
1 X 0 1 0
X = Don’t Cares
Note: In order for this
flip-flop to work, clock
should start low,
transition to high, and
then back to low while all
inputs remain the same.
7483 4-Bit Full Adder
N7483N N74LS83N
N7483F N74LS83F Carry Input Input Output Output A4 1 16 B4
Ci Ai Bi Σi Ci+1 Ε3 2 15 Ε4
0 0 0 0 0 A3 3 14 Cout
0 0 1 1 0 B3 4 13 Cin
0 1 0 1 0 Vcc 5 12 GND
0 1 1 0 1
Ε2 6 11 B1
1 0 0 1 0
B2 7 10 A1
1 0 1 0 1
1 1 0 0 1 A2 8 9 Ε1
1 1 1 1 1
i=0 through 3
Note: Cin should be set to
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 Valid Chips Truth Table Pin Diagram

low when no carry in is

intended and 1 when
subtracting.

74107 Dual JK Master-Slave Flip-Flop

N74107N N74LS107N
N74107F N74LS107F Input Input Clear Output Output
J K Q(t+1) Q’(t+1)
X X 0 0 1 1J 1 14 VCC
0 0 1 Q(t) Q(t)’ 1Q’ 2 13 1R
0 1 1 0 1 1Q 3 12 1CP
1 0 1 1 0 1K 4 11 2K
1 1 1 Q(t)’ Q(t) 2Q 2R
5 10
Q(t) Input Input Output Output 2Q’ 2CP
6 9
J K Q(t+1) Q’(t+1)
GND 7 8 2J
0 0 X 0 1
0 1 X 1 0
1 X 1 0 1
1 X 0 1 0
X = Don’t Cares J Q
Note: In order for this >CP
flip-flop to work, clock K Q’
should start low, R
transition to high, and ^
then back to low while all
inputs remain the same.
74138 3X8 Decoder
N74138N N74LS138N
S0 1 16 Vcc
N74138F N74LS138F Input Output
S0 S1 S2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 S1 2 15 Y0
0 0 0 0 1 1 1 1 1 1 1 S2 3 14 Y1
0 0 1 1 0 1 1 1 1 1 1 E1 4 13 Y2
0 1 0 1 1 0 1 1 1 1 1 E2 5 12 Y3
0 1 1 1 1 1 0 1 1 1 1 E3 6 11 Y4
1 0 0 1 1 1 1 0 1 1 1
Y7 7 10 Y5
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1 GND 8 9 Y6
1 1 1 1 1 1 1 1 1 1 0
Note: E1 & E2 are active O
I 3x8 Y0
low enable. E3 is active Decoder Y1 u
n
high enable Y2 t
p S0 Y3
S1 Y4 p
u S2 Y5 u
t Y6
E1 E2 E3 Y7 t
s
s

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 Valid Chips Truth Table Pin Diagram

74148 3X8 Encoder

N74148N N74148F I4 1 16 Vcc
Output Input I5 2 15 E0
Y0 Y1 Y2 I0 I1 I2 I3 I4 I5 I6 I7 I6 3 14 GS
0 0 0 0 1 1 1 1 1 1 1 I7 4 13 I3
0 0 1 1 0 1 1 1 1 1 1 EI 5 12 I2
0 1 0 1 1 0 1 1 1 1 1 Y2 I1
6 11
0 1 1 1 1 1 0 1 1 1 1
Y1 7 10 I0
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1 GND 8 9 Y0
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
Note: EI is active low I I0 8x3
I1 Encoder
enable. GS and EO are not n I2
used in this lab. p I3 Y0 O
I4 Y1
u I5 Y2 u
t I6 t
I7 EI
s

74151 8-Input Multiplexer

N74151N
N74S151N Select Input Output
S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 Y Y’
N74LS151N 0 0 0 0 X X X X X X X 0 1
I3 1 16 Vcc
I2 2 15 I4
N74151F 0 0 0 1 X X X X X X X 1 0
I1 I5
0 0 1 X 0 X X X X X X 0 1 3 14
N74S151F I0 4 13 I6
0 0 1 X 1 X X X X X X 1 0
N74LS151F 0 1 0 X X 0 X X X X X 0 1 Y 5 12 I7
0 1 0 X X 1 X X X X X 1 0 Y’ 6 11 S0
0 1 1 X X X 0 X X X X 0 1 E’ 7 10 S1
0 1 1 X X X 1 X X X X 1 0 GND 8 9 S2
1 0 0 X X X X 0 X X X 0 1
1 0 0 X X X X 1 X X X 1 0
1 0 1 X X X X X 0 X X 0 1
1 0 1 X X X X X 1 X X 1 0 I0 8 Input
1 1 0 X X X X X X 0 X 0 1 I1 Mux
1 1 0 X X X X X X 1 X 1 0 I2
1 1 1 X X X X X X X 0 0 1 I3
1 1 1 X X X X X X X 1 1 0 I4 Y
X = Don’t Cares I5 Y’
I6
Note: E is active low enable. I7 S2 S1 S0

74153 Dual 4-Input Multiplexer

N74153N N74S153N
N74LS153N N74153F Select Input Output AE’ 1 16 Vcc
S0 S1 E’ I0 I1 I2 I4 Y S1 2 15 BE’
N74S153F X X 1 X X X X 0 AI3 3 14 SO
N74LS153F 0 0 0 0 X X X 0 AI2 4 13 BI3
0 0 0 1 X X X 1 AI1 5 12 BI2
0 1 0 X 0 X X 0
AI0 6 11 BI1
0 1 0 X 1 X X 1
AY 7 10 BI0
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1 GND 8 9 BY
1 1 0 X X X 0 0
1 1 0 X X X 1 1

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 Valid Chips Truth Table Pin Diagram

X = Don’t Cares
Note: E is active low
enable. AI0 AE’
AI1
AI2
AI3 AY

S0 2x4 Input
S1 Mux

BI0 BY
BI1
BI2
BI3 BE’

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