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cn

CMOS IC DESIGN FOR

RELIABILITY: A REVIEW

By W. Kuang
Associate Processor
Department of Electrical Engineering
Univ. of Texas – Pan American
Email: wkuang2003@ieee.org

ABSTRACT - The negative bias temperature instability (NBTI), gate oxide breakdown (BD), and HCI
(hot carrier injection) are the major wear-out effects on the Complementary Metal Oxide
Semiconductor (CMOS) integrated circuit reliability as the CMOS device becomes smaller, especially
in the nanoscale size. This paper summarizes much of the recently developed research about the CMOS
integrated circuit (IC) design for reliability: from physical level to the circuit level. The tools and
algorithm for the CMOS IC design for reliability are also summarized in this paper. It surveys the
crucial topics of the CMOS IC design for reliability and the technology to improve the circuit
robustness to the wear-out effects.
K EYWORDS - CMOS IC, reliability, NBTI, TDDB, HCI, simulation, wear-out effects.

I. I NTRODUCTION

C MOS is a very promising technology in integrated circuits because of the low power
consumption, high integration density, and high operation speed. With the device scaling
down to improve the circuit operation speed, integration, density, power consumption, and
layout size, the reliability becomes critical, especially in nanoscale range. The research inside
recent ten years pointed out that the HCI, gate-oxide breakdown, and the NBTI are the three
major wear-out effects on the CMOS integrated reliability for the long-term operation [1]-[16].
The performances and life-time of integrated circuits based on such the CMOS devices are
thus affected by the life-time of the MOS device itself. To satisfy the production quality, cost,
the CMOS devices for the integrated circuits must have their wear-out effects well understood.

Many researches have investigated on the physical analysis of the wear-out effects, such as
the HCI, gate-oxide breakdown, and NBTI [1]-[6]. It is known that the hot carrier injection
comes from the hot carriers with sufficiently high energies injected from the semiconductor into
the surrounding dielectric films for the smaller size CMOS devices. The presence of such
carriers in the oxides triggers physical damage processes that can drastically change the
device characteristics over prolonged periods. The accumulation of damage can eventually
cause the circuit to fail with the critical parameters shifts, such as threshold voltage, and
mobility [1], [8], [9]. The accumulation of damage results in the degradation in device behavior,
and thus the CMOS integrated circuits. During the field operation, the high-performance
integrated circuits can have hot spots, leading to large temperature gradients across a chip.
The temperature at the terminals of the devices is over 550 K for the silicon-on-insulator circuit
from the simulation [6]. The high temperature will result in a key instability issue for pMOSFET
– negative bias temperature instability. The pMOSFET structure is obtained by growing a layer
of silicon dioxide (SiO2) on top of a silicon substrate and depositing a layer of polycrystalline
silicon. The NBTI degradation is due to generation of interface traps, which are unsaturated
silicon dangling bonds, at the interface between the silicon dioxide and the silicon substrate at
high operation temperature. The unsaturated silicon dangling bonds affect the pMOSFET

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behaviors, such as the threshold voltage shifting, mobility degradation. Another major
wear-out effect is called the time-dependent dielectric breakdown (TDDB), which is caused by
formation of a conducting path through the gate oxide to substrate due to electron tunneling
current [2]-[5]. The TDDB induced the gate leakage current and degrades the CMOS
integrated circuit performances. The NBTI, HCI, and TDDB are the three major wear-out
effects on the CMOS integrated circuit performance and life-time.

To assure that integrated circuits manufactured with minimal geometry devices will not have
their life-time impaired, the life-time of the component MOS devices must have their NBTI,
HCI, and TDDB induced performance degradations well understood [13]. Failure to accurately
characterize NBTI, HCI, and TDDB effects on the circuit performance can affect business
costs such as warranty and support costs and impact marketing and sales promises for a
foundry or IC manufacturer. An accurate and efficient failure equivalent circuit model for the
circuit performance evaluation due to these effects is necessary to detect the circuit failure,
understand the wear-out effects mechanisms, and used for life-time evaluations.

This paper reviews the present state of the research about the CMOS device reliability, the
device failure models, the integrated circuit designs with reliability considerations, and the
insights for the future.

II. R ECENT R ESEARCH ON M ODELING FOR IC R ELIABILITY S IMULATIONS

As described in the above section, the shrinking MOSFET physical geometries have raised
many new challenges in the CMOS integrated circuit reliability, special in the nanoscale sizes.
If care is not taken to understand these issues, timing-degradation-dependent paths can lead
to accelerated circuit failures during burn-in or field operations. Detection of these failures may
become difficult due to circuit complexity, and lead to erroneous data or output conditions [6].
Predictions of the integrated circuit performance degradation and the circuit life time due to
these wear-out effects with an accurate device failure models becomes necessary at the initial
design stage before the fabrication. On anther hand, the integrated circuit design for reliability
requires the accurate device failure models, which can combined with the existing tools and
assist the circuit design with consideration of wear-out effects to make the integrated circuit
more reliable. The long-term wear-out introduced effects can be identified and properly get
eliminated through the simulation with the models at the initial design stage. From the
commercial point of view, these steps could achieve a shorter time-to-market objective,
reduce the following debugging period, increase the production reliability, and reduce the
produce cost.

In recent 10 years, various kinds of models have been proposed for the MOSFET integrated
circuit reliability simulations. Among these models, the failure equivalent circuit models
become more important, because of it’s high compatibility with the current simulation tools and
easy extraction from the experiments. A promising complete failure equivalent circuit model
was developed by Dr. C. Yu et al., “MOS RF reliability subject to dynamic voltage stress –
modeling and analysis”, published by IEEE Transactions on Electron Devices 2005 [12]. Dr
Yu’s model includes the core BSIM model and the surrounding components. The BSIM core is
extracted from the measured device DC characteristics from the on-wafer experiments. Dr. Yu
et al. used the BSIM core to model the DC performance degradations due to the wear-out
effects. The surrounding components account for the RF characteristics shifting of the devices
due to the wear-out effects. It includes two terminal resistors, which are used to account for
the leakage current flowing through the breakdown path due to the TDDB. The
substrate-network-equivalent resistance and the junction capacitances were used to simulate
the RF performance degradations due to the wear-out effects. They extracted the components
for the RF performance degradation simulation from the S-parameter degradations with the
network analyzer in the voltage and temperature stress acceleration experiments. Dr. Yu’s

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model is more complete and significantly contributes to the integrated circuit performance
degradation and lifetime simulation due to the wear-out effects. It comprised the wear-out
effects from HCI, NBTI, and gate-oxide breakdown. This model can be used for both analog
integrated circuit reliability and digital circuit for DC and AC operations. Dr. Yu’s model forms
the solid basis for many CMOS integrated circuit reliability research, such as Dr. Tang et al. at
VLSI Technology Laboratory, National Cheng Kung University, “Investigation and Modeling of
Hot Carrier Effects on Performance of 45- and 55-nm NMOSFETs with RF Automatic
Measurement”, published at IEEE Transactions on Electron Devices, 2008 [13]. The project of
“Design Reliable Asynchronous Circuits” at the Microelectronics Research Lab, University of
Texas - Pan American, employed Dr. Yu’s failure equivalent circuit model to evaluate the new
architectures for the functionality with the wear-out effects, which was published at the
international journal - Microelectonics and Reliablity, 2008 [14]. Dr. Yu’s model gives the
accurate DC and AC performance degradations due to the wear-out effects for the VLSI
circuits with the new architectures. By comparing the simulated performance degradations
with different architectures, the researchers can select the best one, which is more stable to
the wear-out effects.

The analytical models for the physical level of the HCI, NBTI, and TDDB were proposed in
several researches [15]-[23]. Dr. Wu, et al. at IBM gave the failure time equation due to the
TDDB as a function of device area, cumulative failure percentile at use conditions, and the
bias conditions for the nMOSFET. Dr. Zafar et al at IBM proposed a NBTI lifetime model
equation [22], [23], which is based on the physics and statistics model for the pMOSFET.
These models can quickly be used to calculate the circuit normalized lifetime with some
degree of accuracy.

III. R EVIEW OF R ELIAB ILITY S IMULATION TOOLS

The computer-aided-design (CAD) tools have been developed in the recent twenty years to
simulate the CMOS integrated circuit performances, such as the CADENCE. Some of the
general simulation tools can be used to predict the wear-out effects on the circuit
performances combined the developed device failure models [24]-[28]. These tools were
being used analyze, simulate, validate, and optimize the robustness and performance of
CMOS integrated circuit to the wear-out effects. They can also be used to predict the life-time
for the CMOS integrated circuits. In the future, the software tools will be major providers of
information to help support design teams in the CMOS integrated circuit designs for reliability.

The SPICE-like simulators are the general used simulation tools for integrated circuit
performance. However, it does not integrate the wear-out effects simulation capability usually.
In this case, other tools, such as the RelXpert, can be used to combine with the SPICE-like
simulators to simulate the wear-out degradation on the CMOS integrated circuits. RelXpert is
developed by the Celestry and is an industry standard simulation tool for simulating the effect
of HC and NBTI degradation on circuit performances [29]. This tool can work either
stand-alone or combined with Cadence's Analog Artist environment. RelXpert simulates the
age of the devices based upon actual circuit operating waveforms using degraded or "aged"
models. Degraded circuit performance waveforms can then be calculated and used to optimize
the circuits with the SPICE netlist. Combined with the Analog Artist environment, RelXpert can
“pick up” the key devices, which were responsible for circuit degradation [29]. The designer
can specific the devices inside the integrated circuit, which can be redesigned to improve the
CMOS IC reliability. RelXpert can generate the netlist allowing an aged circuit simulation.
RelXpert can also be used to drive the commercial SPICE-like simulator for the lifetime and
degradation simulations.

Another simulation tool is the Cadence Virtuoso UltraSim, which offers the advantage of being
a FastSPICE isomorphic simulator [17], [18]. Because of it’s fast simulation speed, the

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UltraSim can easily simulate the larger scale circuits for mixed-signal and digital applications.
The HCI/NBTI circuit simulation has already been built in for the Virtuoso UltraSim. UltraSim is
a fast and multi-purpose single engine, hierarchical simulator, designed for the verification of
analog, mixed signal, and digital circuits. UltraSim can be used for functional verification of
billion-transistor memory circuits, as well as for high-precision simulation of complex analog
circuits. Because of its true hierarchical simulation approach, UltraSim is faster and uses less
memory than traditional circuit simulators, while maintaining near SPICE accuracy. UltraSim
can also support the RelXpert, as well as HSPICE and Spectre. The UltraSim can simulate
most of the Figure of Merit for the CMOS integrated circuit, such as timing, power, noise, and
reliability.

Another fast timing digital CMOS circuit simulator ILLIADS uses the new generic circuit
primitive and analytical nonlinear state equations [24], [25]. ILLIADS can simulate the charge
sharing effect and the channel length modulation effect accurately. ILLIADS has been able to
simulate the large scale integrated circuit in short time, e.g. a combinational circuit consisting
of 235,000 transistors in 10.5-min real time in a workstation environment. Meanwhile, it has
been shown faster speed and more accuracy, compared to other fast MOS timing simulators.

The Eldo is another circuit simulator, which is developed by Mentor Graphics, delivers all the
capability and accuracy of SPICE-level simulation for complex analog circuits and SoC
designs. Reliability simulation due the HCI effects in Eldo selects the threshold voltage,
transconductance, the drain current degradation as the key parameters to be monitored. The
criteria for the device lifetime are that the concerned parameters or performances have 10%
degradation.

IV. CMOS IC D ESIGN C ONSIDERAT IONS FOR R ELIABILITY

Usually, the design with reliability consideration flow is defined by rules for many companies.
The reliability rules defined the reliability constraints that cannot be violated by designers. The
reliability of HCI/NBTI simulation is performed on the finished chip after the first prototype is
broken. If failure occurs, the design to fix the reliability issue must be re-done. That will
definitely delay the time-to-market. Some new flow introduced by the reliability researches [13]
[24], which consider the reliability circuit simulation in the circuit design phase.

Dr. Li, et al. in his publication “A new SPICE reliability simulation method for deep
submicrometer CMOS VLSI circuits”, IEEE Transactions on TDMR, proposed a new and
useful MaCRO reliability evaluation algorithm [13] [17], which can be used for different
purposes of reliability analyses. The failure equivalent model and the lifetime model
parameters are obtained from experiments. Usually, the wear-out effects on the MOSFET
integrated circuit in the normal voltage and temperature conditions is really slow. It may take
several months for the MOSFET to have visible performance degradations. With the stress
acceleration experiments, the device will have the visible performance degradations inside
several hours. The performance degradation time point in real operation conditions can be
predicted by the reliability extrapolation model with the conditions of the stress acceleration
experiments. It saves the experiment time. By accurate extraction of the related device model
parameters and applying the parameters in the circuit lifetime analytical models, the device
and circuit life-time can be properly predicted, if the circuit lifetime is of primary interest. If the
circuit functionality is of primary interest, the extracted device models combined with the
simulators can simulate circuit operations and check functionality at any interested time. The
weak devices and circuit blocks can be identified and the designers can obtain the insight for
the circuit re-designs for reliability. If the CMOS integrated circuit does not satisfy the reliability
requirements, the design should be re-done or optimized.

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V. S UMMARY

The physical mechanisms of the HCI, NBTI, and TDDB have been investigated for many
years. It is clear that all these wear-out effects degrade the CMOS integrated circuit
performance and short the life-time in the practical operation. The simulation models and CAD
tools could be used to evaluate the wear-out effects and assist the circuit designers to optimize
the circuit topology to be stable to the wear-out effects. These considerations can improve the
circuit robust and reduce the production development cost due to failures and debugging
caused by the wear-out effects. In the future, the device sizes will become even smaller –
32nm or 20 nm scale, that will introduce more reliability issues due to the HCI, NBTI, and time
dependent BD problems. For the new type of MOS devices, such as the high-k devices, the
reliability issues need more concern [26] [27]. The CMOS integrated circuit design for
reliability is a promising research for the future scaling CMOS technology.

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：
Author Brief Introduction：
Dr. W. Kuang is currently an Associate Professor in the Department of Electrical Engineering,
University of Texas - Pan American. He is the director of the Microelectronics Research Lab of the
University of Texas. Dr. Kuang’s research includes fault tolerance in digital VLSI circuits, low power
integrated circuit design, asynchronous digital circuits, and network-on-chip. He has received
nationally recognized science and technology awards five times in signal processing and radar systems.
He is an IEEE member, IEEE Solid-State Circuit Society.