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Mother III 810e
Mother III 810e
Title Page
Cover Sheet 1 ** Please note these schematics are subject to change.
Block Diagram 2
SC242 Connector 3,4 THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES
Clock Synthesizer 5 WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS
82810e 6, 7, 8 FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING
Display Cache 9 OUT OF PROPOSAL, SPECIFICATION OR SAMPLES.
System Memory 10, 11
ICH 12, 13 Information in this document is provided in connection with Intel products. No license,
FWH 14 express or implied, by estoppel or otherwise, to any intellectual property rights is
Super I/O granted by this document. Except as provided in Intel's Terms and Conditions of Sale
A
15 for such products, Intel assumes no liability whatsoever, and Intel disclaims any
A
PCI Connectors 16, 17 express or implied warranty, relating to sale and/or use of Intel products including
ULTRA-ATA66 IDE Connectors 18 liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products
USB Connectors 19 are not intended for use in medical, life saving or life sustaining applications.
Parallel Port 20
Serial Port/COM Headers 21
Intel may make changes to specifications and product descriptions at any time,
Kybrd / Mse / F. Disk / Gme Connectors 22 without notice.
Digital Video Out 23
Video Connectors 24 The Intel® Celeron(tm) processor and Intel® 810e chipset may contain design defects or
Audio/Modem Riser 25 errors known as errata which may cause the product to deviate from published
LAN 26, 27 specifications. Current characterized errata are available on request.
Voltage Regulators 28
Copyright (c) Intel Corporation 1999.
Processor Voltage Regulator (VRM8.4 rev 1.5) 29
System 30, 31
Pullup Resistors and Unused Gates 32 * Third-party brands and names are the property of their respective owners.
DRAM, Chipset,and Bulk Power Decoupling 33
Block Diagram
ADDR
CTRL
DATA
Term
ADDR
CTRL
DATA
Display Cache
Memory
2 DIMM
GMCHE Modules
Digital Video
Out Device
IDE Primary
UltraDMA/66
PCI CONN 1
PCI CONN 2
PCI CONN 3
IDE Secondary PCI CNTRL
ICH
A
PCI ADDR/DATA A
USB Port 1
USB
USB Port 2
LPC Bus
SIO
FirmWare
Hub
J20A
SC242
CONNECTOR
Part 1 6 HD#[63:0] HD#0 B72
HD#0
HD#1 A73
HD#1
HD#2 B71
HD#2 B98 HA#3 HA#[31:3] 6
HD#3 A72 HA#3
HD#3 A100 HA#4
HD#4 B70 HA#4
HD#4 A97 HA#5
HD#5 A71 HA#5
HD#5 B99 HA#6
HD#6 B68 HA#6
HD#6 B96 HA#7
HD#7 B67 HA#7
HD#7 B95 HA#8
HD#8 A69 HA#8
HD#8 A99 HA#9
HD#9 A68 HA#9
HD#9 A96 HA#10
HD#10 A65 HA#10
HD#10 B92 HA#11
HD#11 A64 HA#11
HD#11 B94 HA#12
HD#12 B66 HA#12
HD#12 A93 HA#13
HD#13 A63 HA#13
HD#13 A95 HA#14
HD#14 A67 HA#14
HD#14 B90 HA#15
HD#15 B64 HA#15
HD#15 A92 HA#16
HD#16 A61 HA#16
HD#16 B91 HA#17
HD#17 B63 HA#17
HD#17 A91 HA#18
HD#18 B60 HA#18
HD#18 A89 HA#19
HD#19 B59 HA#19
HD#19 B86 HA#20
HD#20 B62 HA#20
HD#20 B87 HA#21
HD#21 A60 HA#21
HD#21 A85 HA#22
HD#22 B58 HA#22
HD#23 A59
HD#22
HD#23
SC242 HA#23
A87 HA#23
HD#24 HA#24
B83 HA#24
A57
HD#24 B88 HA#25
HD#25 B56 HA#25
HD#25 B82 HA#26
HD#26 B55 HA#26
HD#26 A84 HA#27
HD#27 A56 HA#27
HD#27 B84 HA#28
HD#28 B52 HA#28
HD#28 B80 HA#29
HD#29 B54 HA#29
HD#29 A81 HA#30
HD#30 A55 HA#30
HD#30 A83 HA#31
HD#31 A53 HA#31
A
HD#31 B79
A
SLOT 1 VCC2_5
VCC3_3
VTT1_5
220
VTT1_5 VCC5
VCCVID VCC3_3
1
1
R184A R185A R243 R244
1 2
1K 150 150 330 1k
J27A
B105
B109
B113
B117
B121
4N642
B13
B17
B25
B29
B33
B37
B45
B49
B53
B57
B65
B69
B73
B77
B85
B89
B93
B97
J20B 4N937
2
2
A1
A3
B5
B9
ITP30RA 1K JP19A
R188A ITP_RST 1K
VTT1
VTT2
VTT3
VTT4
1 2
VCC3_1
VCC3_2
VCC3_3
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCC5
6 CPURST#
240 R189A R_DBRST# 3 4 JP19A is a Test Option Only.
1
31 DBRESET#
R_TCK 0K 5 6
R_TMS 7 8 TDI A9
TDI A117
ITP_PON 9 10 TDO A11 AP0#
TDO B116
TRST# B11 AP1#
11 12 TRST#
R190A A101 BNR# 6
13 14 R_TCK TCK B7 BNR#
TCK A103 BPRI# 6
R_TMS
R191A 47 TMS B10 BPRI#
15 16 TMS A104 HTRDY# 6
17 18 R_ITPRDY# 47 TRDY#
ITPREQ# A105
A20 DEFER# DEFER# 6
19 20 PREQ# B106 HLOCK# 6
R192A B23 LOCK#
21 22 PRDY# B107 DRDY# 6
23 24 DRDY#
240 A109 HITM# 6
25 26 A25 HITM#
DEP#0 B110
A27 HIT# HIT# 6
27 28 DEP#1 A111
29 30 B26 DBSY# DBSY# 6
5 ITPCLK DEP#2 A115
A28 HADS# HADS# 6
DEP#3 B2 VCC3_3
B27 FLUSH# FLUSH# 32
DEP#4
A29 R193
DEP#5 A76 1 2
1
A31 BREQ0# R245
DEP#6 B75 10
B28 BREQ1# 220
DEP#7
B21 FREQSEL 5,8
2
B19 BSEL0
BP2# A14 R_REFCLK 5,8
A21 BSEL1
BP3#
SLOT1_B
A23
BPM0# A13
B24 TESTHI TESTHI 32
BPM1# A15
A24 THMTRP#
BINIT#
A5 A20M# 12,32
A
5 CPUHCLK A19 A20M# A
PICD0 B6
B22 STPCLK# STPCLK# 12,32
12,32 APICD1 PICD1 B8 CPUSLP# 12,32
5 APICCLK_CPU B18 CPUSLP#
PICCLK B3
SMI# SMI# 12,32
A17 INTR 12,32
5 CPUHCLK A75 LINT0
CLK B16
VCC2_5 LINT1 NMI 12
2
B4 INIT# 12,14,32
31 PWRGOOD A12 INIT#
PWRGOOD A7
B74 FERR# FERR# 12,32
6 CPURST# 1K RESET# A8 IGNNE# 12,32
IGNNE#
1
A4
B101 IERR#
SLOTCC# A77
BERR#
Do not stuff C339A R195 B118
1
1 2
B61 AERR#
680 R197 0 EMI_1
1 2 B100
R198 0 EMI_2 A16
Place site w / in 0.5" C339A R196 1 2 B81 RES0
1
0 EMI_5 A113
RES3
B76
RES4
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND0
GND1
GND2
GND4
GND5
GND6
GND7
GND8
GND9
A102
A106
A110
A114
A118
A10
A18
A22
A26
A30
A34
A38
A42
A46
A50
A54
A58
A62
A66
A70
A74
A78
A82
A86
A90
A94
A98
A2
A6
4N101
L21A
USBV3 1 2
C340A C341A
1
+
VCC3_3 22UF 0.1UF
2
VCC3_3
L23A L22A
1 2 1 2
Notes: PCIV3 MEMV3
- Place all decoupling caps as close to VCC/GND pins as possible
C347A C348A C349A C350A C351A C352A C342A C353A C354A C343A C344A C345A C346A C355A
1
- PCI_0/ICH pin has to go to the ICH.
+
(This clock cannot be turned off through SMBus) 22UF 0.1UF .001UF 0.1UF .001UF .1UF .001UF .001UF .1UF .001UF 0.1UF .001UF 0.1UF 22UF
2
- CPU_ITP pin must go to the ITP. It is the only
CPU CLK that can be shut off through the SMBUS interface.
R201A
U17A
8.2K
10
21
27
33
38
44
2
9
C356A
VDD3_3[0]
VDD3_3[1]
VDD3_3[2]
VDD3_3[3]
VDD3_3[4]
VDD3_3[5]
VDD3_3[6]
VDD3_3[7]
Y3A
12PF
2
4,8 R_REFCLK 1 2
XTAL_IN 3 55
R203A
10K XTAL_IN APIC_0 APIC_0
APICCLK_CPU 4
XTAL
APIC 54 APIC_1 33 R204A
APIC_1 APICCLK_ICH 12
R205A 33
1
C357A 14.318MHZ REF R206A
15 SIO_CLK14 X T AL_OUT 4 52 CPU_0_1
10 XTAL_OUT CPU_0 CPUHCLK 4
50 33 R207A
R208A 12PF CPU CPU_1 GMCHHCLK 6
REFCLK 1 49 CPU_2
R209A 33
13 ICH_CLK14 REF0 CPU_2/ITP ITPCLK 4
10 33
R210A R211A MEMCLK[7:0] 10,11
3V66_0 7 46 DRAM_0 MEMCLK0
13 ICH_3V66 3V66_0 SDRAM_0
R212A 223V66_1 8 3V66 45 DRAM_1
R213A 22 MEMCLK1
7 GMCH_3V66 3V66_1 SDRAM_1
22 43 DRAM_2 22 R214A MEMCLK2
A
12 PCLK_0/ICH
R215A
PCI_0 11
PCI_0/ICH
CK810e SDRAM_2
SDRAM_3
42 DRAM_3
R216A 22 MEMCLK3
A
PWRDWN# CK_PWRDN# 31
R228A 25 31
L24A 13 USBCLK USB_0 USB_0 SCLK CK_SMBCLK 24
SEL1 _PU
R229A USB
2
33 USB_1 26 30
8 DOTCLK USB_1 SDATA CK_SMBDATA 24
22 29 L25A
SEL1
28
1
1
C358A C359A 22
VDD_A
51
VDD2_5[0]
0.1UF .001UF 53 L_VCC2_5
VDD2_5[1]
23
VSS_A C360A C361A C362A
VSS3_3[0]
VSS3_3[1]
VSS3_3[2]
VSS3_3[3]
VSS3_3[4]
VSS3_3[5]
VSS3_3[6]
VSS3_3[7]
1
56
+
VSS2_5[1]
48
VSS2_5[0] .001UF 0.1UF 4.7UF
2
14
17
24
35
41
47
5
6
Minimize Stub Length from JP20A
CLK14 trace to
JP20A.
JP1
U18
B20
V17
V16
V15
V14
V10
F17
F16
F14
F10
U18A
P6
V9
V8
V7
F8
F7
Y5 HD#0 HD#[63:0] 3
VCC_CORE[10]
VCC_CORE[11]
VCC_CORE[12]
VCC_CORE[13]
VCC_CORE[0]
VCC_CORE[1]
VCC_CORE[2]
VCC_CORE[3]
VCC_CORE[4]
VCC_CORE[5]
VCC_CORE[6]
VCC_CORE[7]
VCC_CORE[8]
VCC_CORE[9]
VCC1_8[0]
VCC1_8[1]
VCC1_8[2]
R231A HD0#
75 HD1#
W5 HD#1
1% W8 HD#2
HD2#
HD3#
AA6 HD#3
GMCHGTLREF M5
GTLREFA AB6 HD#4
W13 HD4#
GTLREFB Y6 HD#5
C364A HD5#
R232A C363A AA5 HD#6
150 V6 HD6#
5 GMCHHCLK HTCLK AA9 HD#7
1% 0.1UF .001UF M2 HD7#
12,14,15,16,17,18,23,26 PCIRST# RESETB V5 HD#8
AB4 HD8#
4 CPURST# CPURST# AC7 HD#9
P5 HD9#
4 HLOCK# HLOCK# AB7 HD#10
R3 HD10#
4 DEFER# DEFER# AC8 HD#11
N3 HD11#
4
4
HADS#
BNR# T3
ADS#
BNR#
INTEL 82810E HD12#
AA7 HD#12
HD13#
Y8 HD#13
4 BPRI# T1
BPRI# W7 HD#14
M4 HD14#
4 DBSY#
N1
DBSY# PART1 HD15#
AC6 HD#15
4 DRDY# DRDY# W9 HD#16
P1 HD16#
4 HIT# HIT# AC9 HD#17
R1 HD17#
4 HITM#
N4
HITM# HOST INTERFACE HD18#
Y7 HD#18
4 HTRDY# HTRDY# AA10 HD#19
HD19#
3 HA#[31:3] HD20#
AB8 HD#20
HA#3 U5
HA3# AC10 HD#21
HA#4 U1 HD21#
HA4# AB13 HD#22
HA#5 V4 HD22#
HA5# AB10 HD#23
HA#6 V1 HD23#
HA6# AB9 HD#24
HA#7 T4 HD24#
HA7# AB11 HD#25
HA#8 U2 HD25#
HA8# Y10 HD#26
HA#9 U3 HD26#
HA9# AB16 HD#27
HA#10 W1 HD27#
HA10# AB12 HD#28
HA#11 U4 HD28#
HA11# Y11 HD#29
HA#12 W3 HD29#
HA12# Y9 HD#30
HA#13 W4 HD30#
A HA13# AC12 HD#31 A
HA#14 T5 HD31#
HA14# W11 HD#32
HA#15 W2 HD32#
HA15# AC11 HD#33
HA#16 V2 HD33#
HA16# W12 HD#34
HA#17 AC2 HD34#
HA17# AA11 HD#35
HA#18 AA2 HD35#
HA18# AA13 HD#36
HA#19 Y3 HD36#
HA19# Y13 HD#37
HA#20 AB3 HD37#
HA20# Y12 HD#38
HA#21 AA1 HD38#
HA21# AC14 HD#39
HA#22 AB2 HD39#
HA22# AA15 HD#40
HA#23 AC3 HD40#
HA23# AC15 HD#41
HA#24 AA3 HD41#
HA24# Y14 HD#42
HA#25 Y2 HD42#
HA25# AC13 HD#43
HA#26 AB5 HD43#
HA26# AA14 HD#44
HA#27 AC4 HD44#
HA27# AB14 HD#45
HA#28 Y1 HD45#
HA28# Y17 HD#46
HA#29 AC5 HD46#
HA29# Y15 HD#47
HA#30 Y4 HD47#
HA30# AC17 HD#48
HA#31 AB1 HD48#
HA31# AC16 HD#49
HD49#
3 HREQ#[4:0] HD50#
AA18 HD#50
HREQ#0 R4
HREQ0# AB15 HD#51
HREQ#1 T2 HD51#
HREQ1# W15 HD#52
HREQ#2 P4 HD52#
HREQ2# AB18 HD#53
HREQ#3 R2 HD53#
HREQ3# W17 HD#54
HREQ#4 R5 HD54#
HREQ4# AA17 HD#55
HD55#
3 RS#[2:0] HD56#
W18 HD#56
RS#0 N5
RS0# W16 HD#57
RS#1 P2 HD57#
RS1# AC19 HD#58
RS#2 N2 HD58#
RS2# Y16 HD#59
HD59#
HD60#
AB19 HD#60
HD61#
Y18 HD#61
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
HD62#
AC18 HD#62
HD63#
AB17 HD#63
M14
M13
M12
M11
M10
N22
C19
N14
N13
Y22
V18
Y19
E22
K14
K13
K12
K11
K10
L14
L13
L12
L11
L10
J22
G21
C11
C15
R18
F15
F18
L21
J18
R233A
G3
D4
C7
K6
B2
F9
F6
L3
U18B
40 SM_MD[63:0] 10,11
E17 SM_MD0
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
VCC3_3[15]
VCC3_3[0]
VCC3_3[1]
VCC3_3[2]
VCC3_3[3]
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
VCC3_3[7]
VCC3_3[8]
VCC3_3[9]
1% SMD0
10,11 SM_MAA[11:0] C16 SM_MD1
SM_MAA0 C9 SMD1
SMAA0 D15 SM_MD2
SM_MAA1 E7 SMD2
SMAA1 D17 SM_MD3
SM_MAA2 A9 SMD3
SMAA2 C17 SM_MD4
SM_MAA3 RP33A D7 SMD4
SMAA3 A17 SM_MD5
SM_MAA4 1 8 B8 SMD5
SMAA4 A16 SM_MD6
SM_MAA5 2 7 A8 SMD6
SMAA5 B16 SM_MD7
SM_MAA6 3 6 B7 SMD7
SMAA6 A15 SM_MD8
SM_MAA7 4 5 A7 SMD8
SMAA7 C14 SM_MD9
SM_MAA8 D6 SMD9
SMAA8 SM_MD10
SM_MAA9
SM_MAA10
10 C6
D5
SMAA9 INTEL 82810E SMD10
SMD11
B14
A14 SM_MD11
SMAA10 D13 SM_MD12
SM_MAA11 A5 SMD12
SMAA11 C13 SM_MD13
RP34A SMD13
SM_MD14
11 SM_MAB#[7:4] SM_MAB#4
SM_MAB#5
1
2
8
7
B6
A6
SMAB4# PART 2 SMD14
SMD15
A13
A12 SM_MD15
SMAB5# E1 SM_MD16
SM_MAB#6 3 6 B4 SMD16
SMAB6# F2 SM_MD17
SM_MAB#7 4 5 A4 SMD17
10,11 SM_DQM[7:0]
10
SMAB7#
SYSTEM MEMORY SMD18
G4
G1
SM_MD18
SM_MD19
SM_DQM0 C10 SMD19
SDQM0 D3 SM_MD20
SM_DQM1 A10 SMD20
SDQM1
SM_DQM2
SM_DQM3
B1
D1
SDQM2 AND SMD21
SMD22
H2
H1
SM_MD21
SM_MD22
SDQM3 J4 SM_MD23
SM_DQM4 B10 SMD23
SDQM4 J1 SM_MD24
SM_DQM5 SMD24
SM_DQM6
D9
C1
SDQM5
SDQM6
HUB INTERFACE SMD25
K2
K1
SM_MD25
SM_MD26
SM_DQM7 D2 SMD26
SDQM7 K3 SM_MD27
SMD27
10,11 SM_BS[1:0] L1 SM_MD28
SM_BS0 C5 SMD28
SBS0 L2 SM_MD29
SM_BS1 E5 SMD29
SBS1 M3 SM_MD30
SMD30
A
10,11 SM_CS#[3:0] K4 SM_MD31 A
SM_CS#0 C4 SMD31
SCS0# D16 SM_MD32
SM_CS#1 C3 SMD32
SCS1# E15 SM_MD33
SM_CS#2 B3 SMD33
SCS2# D14 SM_MD34
SM_CS#3 C2 SMD34
SCS3# E14 SM_MD35
SMD35
E13 SM_MD36
D8 SMD36
10,11 SM_RAS# SRAS# E12 SM_MD37
A11 SMD37
10,11 SM_CAS# SCAS# D12 SM_MD38
B11 SMD38
10,11 SM_WE# SWE# B15 SM_MD39
SMD39
10,11 SM_CKE[1:0] B12 SM_MD40
SM_CKE0 A3 SMD40
SCKE0 C12 SM_MD41
SM_CKE1 A2 SMD41
R238A SCKE1 D11 SM_MD42
SCLK E6 SMD42
5 DCLK_WR SCLK D10 SM_MD43
0K SMD43
E10 SM_MD44
D19 SMD44
C368A 5 GMCH_3V66 HLCLK E9 SM_MD45
HL0 C21 SMD45
HL0 E8 SM_MD46
22PF 12 HL[10:0] HL1 B23 SMD46
HL1 C8 SM_MD47
HL2 B22 SMD47
HL2 F3 SM_MD48
HL3 A23 SMD48
HL3 F1 SM_MD49
HL4 B19 SMD49
HL4 G2 SM_MD50
HL5 B18 SMD50
HL5 H3 SM_MD51
HL6 C18 SMD51
HL6 HUB I/F SMD52
E4 SM_MD52
HL7 A18
Place HUBREF Generation HL7 E3 SM_MD53
Circuit in middle of HL8 A22 SMD53
VCC1_8 HL8 F4 SM_MD54
GMCH and ICH HL9 C20 SMD54
HL9 J3 SM_MD55
HL10 A19 SMD55
HL10
1
F5 SM_MD56
R246 HUBREF D20 SMD56
301 1% HUBREF G5 SM_MD57
A21 SMD57
GHCOMP
R247 J5 SM_MD61
SMD61
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
C369A L5 SM_MD63
Place C369A as close
2
SMD63
AA12
AA16
W10
W14
AC1
AA4
AA8
N12
N11
N10
P14
P13
P12
P11
P10
W6
M1
R6
V3
P3
as possible to GMCH
L4
J2
0.1UF
C370A
Title: Intel® 810e Chipset Customer Reference Board REV.
18PF
82810E, Part 2: System Memory and Hub 1.0
Platform Components Division Last Revision Date:
6/14/99
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
7 of 33
A
A
L26A
AND VIDEO INTERFACE VCCDACA
C371A
68NH-0.3A
C372A
C373A
1
+
Use Surface Mount Caps
0.01UF
33UF
AC20
AB23
AB21
0.1UF
U18C placed as close as possible to
E19
U6
2
power pins with short,
VCCDACA1
VCCDACA2
VCCHA
VCCBA
VCCDA
wide direct connections
9 DC_CS# L20
LCS#
8
7
6
5
1
2
3
4
U20 SL_STALL 23
GRS_PU 28
GRS_PU 30
TVCLKIN/SL_STALL
GRS_PU31
DC_MA5 H19
JP21A LMA5 V21 FTCLK0 23
DC_MD31 DC_MA6
DC_MA7
H20
H18
LMA6
LMA7
PART3 CLKOUT0
CLKOUT1
V22
V20
FTCLK1 23
DC_MA8 G19 TVVSYNC FTVSYNC 23
JP22A LMA8 U19
DC_MD30 DC_MA9 F19 TVHSYNC FTHSYNC 23
DC_MD29
DC_MA10
DC_MA11
M20
L19
LMA9
LMA10 DISPLAY CACHE LTVCL
T19 3VFTSCL 23,24
LMA11 T20
LTVDA 3VFTSDA 23,24
JP23A 9 DC_MD[31:0] DC_MD0 M22
DC_MD28 LMD0
DC_MD1
DC_MD2
M21
L23
LMD1 AND
LMD2
DC_MD3 L22
LMD3
JP24A DC_MD4 K21
LMD4
A
DC_MD26 DC_MD5
DC_MD6
K23
R19
LMD5 VIDEO INTERFACE A
LMD6
DC_MD7 R20
LMD7
DC_MD8 R22
LMD8
DC_MD9 R21
LMD9
DC_MD10 P23
LMD10
DC_MD11 P22
LMD11
DC_MD12 N23
LMD12
Function Jumper Comment DC_MD13 N21
LMD13
DC_MD14 N20
XOR JP21A IN = XOR Tree LMD14
DC_MD15 M23
*OUT = Normal LMD15
DC_MD16 F23
Tri-state JP22A IN = Tri-state Mode LMD16
DC_MD17 E20
*OUT = Normal LMD17
DC_MD18 E21
System Reads System LMD18 W19
N/A DC_MD19 E23 DISPLAY CACHE DDCDA 3VDDCDA 24
Bus Freq. Bus Freq. LMD19 W20
DC_MD20 D22 DDCCL 3VDDCCL 24
IN = IOQ Depth of 1 LMD20
IOQ Depth JP23A DC_MD21 D23
*Out = IOQ Depth of 4 LMD21 AA21
DC_MD22 D21 DCLKREF DOTCLK 5 DOTCLK
LMD22 Y23
VCORE N/A Detects type of DC_MD23 C22 IWASTE
Detect Processor I/O Buffers LMD23 AA23 IREFPD C374A
DC_MD24 H21 IREF
LMD24 Do not Stuff C374A
RESVD JP24A TBD DC_MD25 H22 18PF
LMD25 AA20 Place site w / in 0.5"
DC_MD26 H23 VSYNC CRT_VSYNC 24
LMD26 GRAPHICS INTERFACE HSYNC
AB20 CRT_HSYNC 24
of clock ball (AA21).
DC_MD27 G20
LMD27 AC21
DC_MD28 G22 RED VID_RED 24
LMD28 AC22
DC_MD29 G23 GREEN VID_GREEN 24
LMD29 AC23
DC_MD30 F21 BLUE VID_BLUE 24
LMD30
DC_MD31 F22
LMD31
R240A Place as close as
R_LTCLK K22 R239A
9 DC_CLK LTCLK Possible to GMCH
22 174 and via straight to
R241A 1% VSS plane.
RCLK J20
LRCLK
0K J23
R242A LOCLK
OCLK_FB OCLK
VSSDACA
33
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSSHA
VSSDA
VSSBA
AA22
AB22
G18
E18
E11
B13
E16
B17
B21
K18
P18
T18
G6
E2
A1
B5
B9
T6
J6
C375A
Title: Intel® 810e Chipset Customer Reference Board REV.
22PF
Do Not Populate C375A 82810E, Part 3 : Display Cache and Video 1.0
Platform Components Division Last Revision Date:
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
8
6/14/99
of 33
A
A
4MB Display
Cache
VCC3_3 VCC3_3
U1A
U2A
25
13
38
44
1
7
25
13
38
44
1
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDD_1
VDD_2
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDD_1
VDD_2
DC_MA[11:0]
DC_MA0 21 2 DC_MD16 DC_MD[31:0] 8
8 DC_MA[11:0] DC_MA0 21 2 DC_MD0 A0 DQ0
A0 DQ0 DC_MA1 22 3 DC_MD17
DC_MA1 22 3 DC_MD1 A1 DQ1
A1 DQ1 DC_MA2 23 5 DC_MD18 DC_DQM[3:0] 8
VCC3_3 DC_MA2 23 5 DC_MD2 A2 DQ2
A2 DQ2 DC_MA3 24 6 DC_MD19
DC_MA3 24 6 DC_MD3 A3 DQ3
A3 DQ3 DC_MA4 27 8 DC_MD20
DC_MA4 27 8 DC_MD4 A4 DQ4
50-PIN TSOP
A4 DQ4 DC_MA5 28 9 DC_MD21
50-PIN TSOP
DC_MA5 28 9 DC_MD5 A5 DQ5
A5 DQ5 DC_MA6 29 11 DC_MD22
DC_MA6 29 11 DC_MD6 A6 DQ6
A6 DQ6 DC_MA7 30 12 DC_MD23
DC_MA7 30 12 DC_MD7 A7 DQ7
R1A A7 DQ7 DC_MA8 31 39 DC_MD24
SDRAM
DC_MA8 31 39 DC_MD8 A8 DQ8
SDRAM
4.7K A8 DQ8 DC_MA9 32 40 DC_MD25
DC_MA9 32 40 DC_MD9 A9 DQ9
A9 DQ9 DC_MA10 20 42 DC_MD26
DC_MA10 20 42 DC_MD10 A10 DQ10
A10 DQ10 DC_MA11 19 43 DC_MD27
DC_MA11 19 43 DC_MD11 A11 DQ11
A11 DQ11 45 DC_MD28
45 DC_MD12 DQ12
A
DQ12 DC_CLK 35 46 DC_MD29 A
VSSQ_4
VSSQ_3
VSSQ_2
VSSQ_1
37 NC_2
VSS_2
VSS_1
VSSQ_4
VSSQ_3
VSSQ_2
VSSQ_1
NC_2
VSS_2
VSS_1
10
41
47
26
50
4
10
41
47
26
50
4
VCC3_3SBY
J1A
6
18
26
40
41
90
102
110
124
49
59
73
84
133
143
157
168
7,11 SM_DQM[7:0]
7,11 SM_BS[1:0]
7,11 SM_MAA[11:0]
5,11 MEMCLK[7:0]
2 SM_MD0
DQ0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
3 SM_MD1
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
DQ1
MEMCLK0 42 4 SM_MD2
CLK0 DQ2
MEMCLK1 125 5 SM_MD3
CLK1 DQ3
MEMCLK2 79 7 SM_MD4
SYSTEM MEMORY
CLK2 DQ4
MEMCLK3 163 8 SM_MD5
CLK3 DQ5
9 SM_MD6
DQ6
SM_MAA0 33 10 SM_MD7
A0 DQ7
SM_MAA1 117 11 SM_MD8
A1 DQ8
SM_MAA2 34 13 SM_MD9
A2 DQ9
SM_MAA3 118 14 SM_MD10
A3 DQ10
SM_MAA4 35 15 SM_MD11
A4 DQ11
SM_MAA5 119 16 SM_MD12
A5 DQ12
SM_MAA6 36 17 SM_MD13
A6 DQ13
SM_MAA7 120 19 SM_MD14
A7 DQ14
SM_MAA8 37 20 SM_MD15
A8 DQ15
SM_MAA9 121 55 SM_MD16
A9 DQ16
SM_MAA10 38 56 SM_MD17
A10 DQ17
SM_MAA11 123 57 SM_MD18
A11 DQ18
126 58 SM_MD19
A12 DQ19
132 60 SM_MD20
A13 DQ20
7,11 SM_WE#
7,11 SM_RAS#
7,11 SM_CAS#
7,11 SM_CS#[3:0]
11,13,24,27,32 SMBDATA
7,11 SM_CKE[1:0]
11,13,24,27,32 SMBCLK
65 SM_MD21
DQ21
SM_BS0 122 66 SM_MD22
BA0 DQ22
SM_BS1 39 67 SM_MD23
BA1 DQ23
69 SM_MD24
DQ24
SM_DQM0 28 70 SM_MD25
DQMB0 DQ25
SM_DQM1 29 71 SM_MD26
DQMB1 DQ26
SM_DQM2 46 72 SM_MD27
DQMB2 DQ27
SM_DQM3 47 74 SM_MD28
DQMB3 DQ28
SM_DQM4 112 75 SM_MD29
DQMB4 DQ29
SM_DQM5 113 76 SM_MD30
DQMB5 DQ30
SM_DQM6 130 77 SM_MD31
DQMB6 DQ31
SM_DQM7 131 86 SM_MD32
DQMB7 DQ32
87 SM_MD33
DQ33
SM_CS#0 30 88 SM_MD34
S0# DQ34
SM_CS#1 114 89 SM_MD35
S1# DQ35
45 91 SM_MD36
A
A
S2# DQ36
129 92 SM_MD37
S3# DQ37
27 93 SM_MD38
WE# DQ38
111 94 SM_MD39
CAS# DQ39
168 PIN
115 95 SM_MD40
RAS# DQ40
97 SM_MD41
DQ41
SM_CKE0 128 98 SM_MD42
CKE0 DQ42
SM_CKE1 63 99 SM_MD43
CKE1 DQ43
100 SM_MD44
DQ44
DIMM SOCKET
82 101 SM_MD45
SMBDATA DQ45
83 103 SM_MD46
SMBCLK DQ46
104 SM_MD47
DQ47
147 139 SM_MD48
REGE DQ48
165 140 SM_MD49
SA0 DQ49
166 141 SM_MD50
SA1 DQ50
167 142 SM_MD51
SA2 DQ51
144 SM_MD52
81 DQ52
WP 149 SM_MD53
DQ53
24 150 SM_MD54
NC1 DQ54
25 151 SM_MD55
NC2 DQ55
31 153 SM_MD56
NC3 DQ56
44 154 SM_MD57
NC4 DQ57
48 155 SM_MD58
NC5 DQ58
50 156 SM_MD59
NC6 DQ59
51 158 SM_MD60
NC7 DQ60
61 159 SM_MD61
NC8 DQ61
62 160 SM_MD62
NC9 DQ62
SAO_PU
80 161 SM_MD63
NC10 DQ63
108 21
11
NC11 ECC0
109 22
NC12 ECC1
134 52
NC13 ECC2
135 53
NC14 ECC3
145 105
NC15 ECC4
146 106
NC16 ECC5
164 136
NC17 ECC6
137
ECC7
intel
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
R
1
12
23
32
43
54
64
68
78
85
96
107
116
127
138
148
152
162
Sheet:
10
Last Revision Date:
of
6/14/99
33
1.0
REV.
A
A
7,10 SM_MD[63:0]
VCC3_3SBY
SYSTEM MEMORY
J2A
6
18
26
40
41
90
102
110
124
49
59
73
84
133
143
157
168
7,10 SM_BS[1:0]
5,10 MEMCLK[7:0]
7,10 SM_MAA[11:0]
7,10 SM_DQM[7:0]
7 SM_MAB#[7:4]
2 SM_MD0
DQ0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
3 SM_MD1
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
DQ1
MEMCLK4 42 4 SM_MD2
CLK0 DQ2
MEMCLK5 125 5 SM_MD3
CLK1 DQ3
MEMCLK6 79 7 SM_MD4
CLK2 DQ4
MEMCLK7 163 8 SM_MD5
CLK3 DQ5
9 SM_MD6
DQ6
SM_MAA0 33 10 SM_MD7
A0 DQ7
SM_MAA1 117 11 SM_MD8
A1 DQ8
SM_MAA2 34 13 SM_MD9
A2 DQ9
SM_MAA3 118 14 SM_MD10
A3 DQ10
SM_MAB#4 35 15 SM_MD11
A4 DQ11
SM_MAB#5 119 16 SM_MD12
A5 DQ12
SM_MAB#6 36 17 SM_MD13
A6 DQ13
SM_MAB#7 120 19 SM_MD14
A7 DQ14
SM_MAA8 37 20 SM_MD15
A8 DQ15
SM_MAA9 121 55 SM_MD16
A9 DQ16
SM_MAA10 38 56 SM_MD17
A10 DQ17
SM_MAA11 123 57 SM_MD18
A11 DQ18
126 58 SM_MD19
A12 DQ19
132 60 SM_MD20
A13 DQ20
65 SM_MD21
DQ21
SM_BS0 122 66 SM_MD22
BA0 DQ22
SM_BS1 39 67 SM_MD23
BA1 DQ23
69 SM_MD24
DQ24
SM_DQM0 28 70 SM_MD25
DQMB0 DQ25
SM_DQM1 29 71 SM_MD26
DQMB1 DQ26
SM_DQM2 46 72 SM_MD27
DQMB2 DQ27
SM_DQM3 47 74 SM_MD28
DQMB3 DQ28
SM_DQM4 112 75 SM_MD29
DQMB4 DQ29
SM_DQM5 113 76 SM_MD30
DQMB5 DQ30
SM_DQM6 130 77 SM_MD31
A
A
DQMB6 DQ31
SM_DQM7 131 86 SM_MD32
DQMB7 DQ32
87 SM_MD33
7,10 SM_RAS#
7,10 SM_CAS#
7,10 SM_WE#
10,13,24,27,32 SMBCLK
10,13,24,27,32 SMBDATA
DQ33
7,10 SM_CKE[1:0]
7,10 SM_CS#[3:0]
30 88 SM_MD34
S0# DQ34
114 89 SM_MD35
S1# DQ35
SM_CS#2 45 91 SM_MD36
S2# DQ36
SM_CS#3 129 92 SM_MD37
S3# DQ37
27 93 SM_MD38
WE# DQ38
111 94 SM_MD39
CAS# DQ39
168 PIN
115 95 SM_MD40
RAS# DQ40
97 SM_MD41
DQ41
SM_CKE0 128 98 SM_MD42
CKE0 DQ42
SM_CKE1 63 99 SM_MD43
CKE1 DQ43
100 SM_MD44
DQ44
DIMM SOCKET
82 101 SM_MD45
SMBDATA DQ45
83 103 SM_MD46
SMBCLK DQ46
104 SM_MD47
DQ47
147 139 SM_MD48
REGE DQ48
165 140 SM_MD49
SA0 DQ49
166 141 SM_MD50
SA1 DQ50
167 142 SM_MD51
SA2 DQ51
144 SM_MD52
81 DQ52
WP 149 SM_MD53
DQ53
24 150 SM_MD54
NC1 DQ54
SAO_PU
25 151 SM_MD55
NC2 DQ55
31 153 SM_MD56
NC3 DQ56
44 154 SM_MD57
NC4 DQ57
48 155 SM_MD58
NC5 DQ58
SAO_PU 10
50 156 SM_MD59
NC6 DQ59
51 158 SM_MD60
NC7 DQ60
61 159 SM_MD61
NC8 DQ61
62 160 SM_MD62
NC9 DQ62
80 161 SM_MD63
NC10 DQ63
108 21
NC11 ECC0
109 22
NC12 ECC1
134 52
NC13 ECC2
intel
135 53
NC14 ECC3
R
145 105
NC15 ECC4
146 106
NC16 ECC5
164 136
NC17 ECC6
137
ECC7
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
2.2K
Sheet:
System Memory : DIMM1
VCC3_3SBY
11
Last Revision Date:
of
6/14/99
33
1.0
REV.
A
A
M14
G13
G15
U10
R13
C11
D16
N13
H14
H16
E13
K14
T16
L15
J16
G5
C8
N5
E3
P6
A5
E6
E5
U3A
T7
VCC3_3_10
VCC3_3_11
VCC3_3_12
VCC3_3_13
VCC3_3_14
VCC3_3_15
VCC3_3_16
VCC3_3_17
VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6
VCC3_3_7
VCC3_3_8
VCC3_3_9
VCC1_8_1
VCC1_8_2
VCC1_8_3
VCC1_8_4
VCC1_8_5
VCC1_8_6
VCC1_8_7
16,17,26 AD[31:0] AD0 G2 F13
AD0 A20M# A20M# 4,32
AD1 G4 E12
AD1 CPUSLP# CPUSLP# 4,32
AD2 F2 F15
AD2 FERR# FERR# 4,32
AD3 F3 B17
AD3 IGNNE# IGNNE# 4,32
AD4 F4 E15
AD4 INIT# INIT# 4,14,32
AD5 F5 E14
AD5 INTR INTR 4,32
AD6 E1
AD6
CPU NMI
B16 NMI 4
AD7 E2 F14
AD7 SMI# SMI# 4,32
AD8 D1 A17
AD8 STPCLK# STPCLK# 4,32
AD9 D3 A15 RCIN# 15,32
AD9 RCIN#
AD10 E4 B15
AD10 A20GATE A20GATE 15,32
AD11
AD12
C2
C1
AD11
AD12
INTEL 82801AA (ICH) HL0
D17 HL0 HL[10:0] 7
AD13 B1 E17 HL1
AD13 HL1
AD14 D4 F17 HL2
AD14 HL2 VCC1_8
AD15 C3 G16 HL3
AD15 HL3
AD16
AD17
A4
B4
AD16
AD17
PART 1 HL4
HL5
J15
K16
HL4
HL5
AD18 C5 K17 HL6 R3A
AD19 C6
AD18
AD19
HUB I/F HL6
HL7
L17 HL7 40
Place R3A
as close as
AD20 B5 H15 HL8 1% possible to ICH.
AD20 HL8
AD21 HL9
AD22
E7
A6
AD21 PCI HL9
J17
J14 HL10
AD22 HL10
AD23 B6 G17
AD23 HLSTB HLSTB 7
AD24 D7 H17
AD24 HLSTB# HLSTB# 7
A AD25 B8 M17 IHCOMP_PU A
AD25 HCOMP
AD26 A7 J13
AD26 HUBREF HUBREF 7
AD27 A8
AD27
AD28 B7 D10 C1A
AD28 PIRQ#A PIRQ#A 16,17,26,32
AD29 C9 A10
AD29 PIRQ#B PIRQ#B 16,17,32 Place C1A as close
AD30 D8 B10 0.1UF
AD30 PIRQ#C PIRQ#C 16,17,32 as possible to ICH.
AD31 C7 C10
AD31 PIRQ#D PIRQ#D 16,17,32
32 GNT#B/GPIO17 R5
GNT#B/GPIO17
R6A
VSS10
VSS11
VSS12
VSS13
0K
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
For Test/Debug
Don't Stuff R6A
G14
H10
K10
K15
J10
G3
R2
H8
H9
K8
K9
J8
J9
A
R8 CR1A R7A
CR2A C2A C3A 1K
10K U3B BAT17
A C R9
C15
SLP_S5#
1.0UF 0.1UF
G1
C
N1
L1
BAT17 10K
R10A
VCCRTC
VCCSUS2
VCCSUS1
5VREF
1K
32 THERM# D14
THRM#
C4A K3
28,31 SLP_S3# SLP_S3/GPIO24
1.0UF JP1A Config. K2
SLP_S5 N12
J3 PDCS#1 PDCS#1 18
1-2 Normal 27,28,31 PWROK PWROK L14
M2 SDCS#1 SDCS#1 18
2-3 Clear CMOS 30 PWRBTN# PWRBTN# U13 PDCS#3 18
L3 PDCS#3
VBATC 21 ICH_RI# RI# L16
F1 SDCS#3 SDCS#3 18
JP1A 27,31 RSMRST# RSMRST#
R11A
VBATC_DLY 1 L4
27 SUS_STAT# SUSSTAT#/GPIO25 R12 PDA0 PDA[2:0] 18
8.2K 2 RTCRST# PDA0
PDA1
C
T12
CR3A 3 J1 PDA1
10,11,24,27,32 SMBDATA SMBDATA
1
J2 PDA2
BAT17
2.2UF JP24_PD 10,11,24,27,32 SMBCLK
M1
SMBCLK
SYSTEM SDA0
M16 SDA0 SDA[2:0] 18
A
H2
CLK66 INTEL 82801AA (ICH) PDDACK#
SDDACK#
U12
M13
PDDACK# 18
SDDACK# 18
VBIAS R11
RTCX1 H3 PDIOR# PDIOR# 18
RTCX1 N16
RTCX2 H4 SDIOR# SDIOR# 18
VBAT
R14A
10M
R15A
RTCRST# H1
RTCX2
RTCRST# PART 2 PDIOW#
SDIOW#
T11
N15
PDIOW# 18
SDIOW# 18
N11 PIORDY 18
10M T1 PIORDY
25 AC_RST# AC_RST# N17
T3 SIORDY SIORDY 18
25 AC_SYNC AC_SYNC
Y1A 25 AC_BITCLK R3 PDD[15:0] 18
AC_BITCLK R10 PDD0
X1 PDD0
AC97
+
25 AC_SDOUT T2
1 2 AC_SDOUT N9 PDD1
U1 PDD1
A
25,32 AC_SDIN0 AC_SDIN0 R9 PDD2 A
P3 PDD2
32.768KHZ 25,32 AC_SDIN1 AC_SDIN1/GPIO9 PDD3
30 ICH_SPKR U3
SPKR
IDE PDD3
U9
R8 PDD4
Socketed C7A C8A PDD4
U8 PDD5
3vdc Lithium 18pF 18pF D11 PDD5
15,32 LPC_SMI# GPIO5 R7 PDD6
equivalent to E11 PDD6
15,32 LPC_PME# GPIO6 U7 PDD7
Rayovac BR2325 E9 PDD7
17,32 GPIO7 GPIO7 P7 PDD8
N4 PDD8
32 GPIO12 GPIO12 N7 PDD9
L2 PDD9
32 GPIO13 GPIO13 T8 PDD10
B14 PDD10
17,32 GPIO21
32 GPIO22 D13
GPIO21
GPIO22
GPIO PDD11
P8 PDD11
PDD12
T9
D15 PDD12
30 GPIO23_FPLED GPIO23 P9 PDD13
K4 PDD13
30 GPIO26_FPLED GPIO26 T10 PDD14
M5 PDD14
27 GPIO27 GPIO27 P10 PDD15
L5 PDD15
27 GPIO28 GPIO28
P15 SDD0 SDD[15:0] 18
R6 SDD0
14,15 LAD0/FWH0 LAD0/FWH0 R16 SDD1
U5 SDD1
14,15 LAD1/FWH1 LAD1/FWH1 T17 SDD2
T5 SDD2
JP2A Strap Speaker 14,15 LAD2/FWH2 LAD2/FWH2 U16 SDD3
SDD3
IN No Reboot on 2nd watchdog timeout
14,15 LAD3/FWH3 T4
U4
LAD3/FWH3 LPC SDD4
U15 SDD4
14,15 LFRAME#/FWH4 LFRAME#/FWH4 R14 SDD5
OUT Reboot on 2nd watchdog timeout T6 SDD5
15 LDRQ#0 LDRQ#0 P13 SDD6
N3 SDD6
32 LDRQ#1 LDRQ#1/GPIO8 T13 SDD7
JP3A Strap AC_SDOUT SDD7
U14 SDD8
R1 SDD8
IN Force CPU freq. strap to safe mode (1111) 19 USBP1P USBP1P T14 SDD9
P2 SDD9
OUT Use CPU freq. strap setting in ICH register. 19 USBP1N USBP1N P14 SDD10
P1 SDD10
19 USBP0P USBP0P
19 USBP0N N2
USBP0N
USB SDD11
T15
U17
SDD11
SDD12
M4 SDD12
OC#1 R15 SDD13
VCC3_3 M3 SDD13
JP2A 19 OC#0 OC#0 R17 SDD14
SDD14
ICH_SPKR P16 SDD15
SDD15
JP13_PD
R16A C9A
1K 18PF
R17A
10K Minimize Stub Length
JP14_PU
to Jumpers
Title: Intel® 810e Chipset Customer Reference Board REV.
JP3A
ICH, Part 2 1.0
AC_SDOUT Platform Components Division Last Revision Date:
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
6/14/99
of 33
13
A
A
VCC3_3
VCC3_3
FGPI4_PD
FGPI3_PD
FGPI2_PD
R19A IC_PD
WPROT
JP4A CONFIG 4.7K
IN Unlocked
4
3
2
1
4
3
2
1
TBLK_LCK
OUT Locked Default
RP1A 0K RP2A
8.2K
RP2A for
R20A
5
6
7
8
5
6
7
8
Test/Debug
4.7K
Notes:
VCC5 VCC3_3
VCC3_3
44
18
53
65
93
U4A
VTR
VREF
VCC1
VCC2
VCC3
Decoupling
13,14 LFRAME#/FWH4 24 66 PAR_INIT# 20
VCC3_3 VCC5 LFRAME# INIT#
13,14 LAD3/FWH3 23 67 SLCTIN# 20
LAD3 SLCTIN#
13,14 LAD2/FWH2 22
Place near LAD2
21 75 PDR7 PDR[7:0] 20
13,14 LAD1/FWH1 LAD1 PD7
C20A
C16A
C19A
C21A
VREF pin
C18A
C17A
20 74 PDR6
13,14 LAD0/FWH0 LAD0 PD6
U
LPC I/F
1
25 73 PDR5
+
SUSSTAT_P
13 LDRQ#0 LDRQ# PD5
2.2UF
PDR4
0.1UF
0.1UF
0.1UF
26 72
0.1UF
0.1UF
6,12,14,16,17,18,23,26 PCIRST# LRESET# PD4
2
27 71 PDR3
LPCPD# PARALLEL PORT I/F PD3
17 70 PDR2
13,32 LPC_PME# PME# PD2
30 69 PDR1
12,17,32 SERIRQ SERIRQ PD1
Place 1 0.1UF cap near each power pin 5 PCLK_1 29
PCI_CLK SIO PD0
SLCT#
68
77
PDR0
SLCT# 20
22 KDAT 56 78 PE 20
KDAT PE
22 KCLK 57
KCLK
LPC47B27X BUSY
79 BUSY 20
22 MDAT 58 80 ACK# 20
MDAT ACK#
22 MCLK 59 81 ERROR# 20
MCLK KYBD/MSE I/F ERROR#
12,32 RCIN# 63 82 ALF# 20
KBDRST ALF#
12,32 A20GATE 64 83 STROBE# 20
A20GATE STROBE#
30 IRRX 61 54 PWM2 30
IRRX2/GP34 FAN2/GP32
62 INFRARED I/F 55
30 IRTX IRTX2/GP35 FAN1/GP33 PWM1 30
84 28 SIO_GP43
C22A 21 RXD#0 RXD1 FDC_PP/DDRC/GP43
C23A
21 TXD0 85
TXD1
470PF 470PF 86
21 DSR#0 DSR1#
21 RTS#0 87
RTS1#
88 SERIAL PORT 1 Test/Debug Header
21 CTS#0 CTS1# Unused GPIOs
A
21 DTR#0 89 J3A A
DTR1#
21 RI#0 90 1 2
RI1#
21 DCD#0 91 3 4
DCD1#
5 6
21 RXD#1 95
RXD2_IRRX
21 TXD1 96
TXD2_IRTX
21 DSR#1 97
DSR2#
21 RTS#1 98
RTS2# SERIAL PORT 2
99 48 SIO_GP60
21 CTS#1 CTS2# GP60/LED1
100 49 SIO_GP61
21 DTR#1 DTR2# GP61/LED2
21 RI#1 92 50 LPC_SMI# 13,32
RI2# GP27/IO_SMI#
21 DCD#1 94 51 TACH2 30
DCD2# GP30/FAN_TACH2
52 TACH1 30
GP31/FAN_TACH1
22 DRVDEN#1 2 46 MIDI_IN 22
DRVDEN1 GP25/MIDI_IN
22 DRVDEN#0 1 47 MIDI_OUT 22
DRVDEN0 GP26/MIDI_OUT
22 MTR#0 3
MTR0#
22 DS#0 5 32 J1BUTTON1 22
DS0# GP10/J1B1
22 DIR# 8 33 J1BUTTON2 22
DIR# GP11/J1B2
22 STEP# 9 34 J2BUTTON1 22
STEP# GP12/J2B1
22 WDATA# 10 35 J2BUTTON2 22
WDATA# GP13/J2B2
11 FDC I/F 36
22 WGATE# WGATE# GP14/J1X JOY1X 22
22 HDSEL# 12 37 JOY1Y 22
HDSEL# GP15/J1Y
22 INDEX# 13 38 JOY2X 22
INDEX# GP16/J2X
22 TRK#0 14 39 JOY2Y 22
TRK0# GP17/J2Y
22 WRTPRT# 15 41 KEYLOCK# 30
WRTPRT# GP20/P17
16 42 SIO_GP21
22 RDATA# RDATA# GP21/P16
4 43 SIO_GP22
22 DSKCHG# DSKCHG# GP22/P12
AVSS
R22A
4.7K
31
60
76
40
7
VCC12-
VCC5
VCC3_3SBY VCC5
J4A VCC12
VCC3_3 VCC3_3 PCI3_CON
VCC12-
VCC5 B1 A1 PTRST#
VCC5
J5A VCC12 PTCK B2 A2
VCC3_3 P CI3_CON
B3 A3 PTMS
B1 A1 PTRST# 17 PTDI
B4 A4
17 PTCK B2 A2
B5 A5
B3 A3 PTMS 17,32 PIRQ#B
B6 A6
B4 A4 PTDI 17,32 PIRQ#C PIRQ#D
B7 A7
B5 A5 PIRQ#A B8 A8
B6 A6 PIRQ#A 12,17,26,32
17 PRSNT#21 B9 A9
12,17,32 PIRQ#B B7 A7 PIRQ#C 12,17,32 B10 A10
12,17,32 PIRQ#D B8 A8
17 PRSNT#22 B11 A11
17 PRSNT#11 B9 A9
B12 A12
B10 A10
B13 A13
17 PRSNT#12 B11 A11
B14 A14
B12 A12 PCIRST#
B15 A15
B13 A13
5 PCLK_3 B16 A16
B14 A14
B17 A17 PGNT#1 12,32
B15 A15 PCIRST# 6,12,14,15,17,18,23,26 12,32 PREQ#1 B18 A18
5 PCLK_2 B16 A16 PCI_PME#
B19 A19
B17 A17 AD[31:0]
PGNT#0 12,32 AD31 B20 A20 AD30
B18 A18 AD[31:0]
12,32 PREQ#0 AD29 B21 A21
B19 A19 PCI_PME# 12,17,26 AD28
B22 A22
12,17,26 AD[31:0] AD31 B20 A20 AD30
AD[31:0] AD27 B23 A23 AD26
AD29 B21 A21 AD25 B24 A24
B22 A22 AD28
B25 A25 AD24
AD27 B23 A23 AD26 C_BE#[3:0] R23A
C_BE#3 B26 A26 R_AD17 AD17
AD25 B24 A24 AD23 B27 A27 100
B25 A25 AD24
R24A B28 A28 AD22
12,17,26 C_BE#[3:0] C_BE#3 B26 A26 R_AD16
AD16 12,17,26 AD21 B29 A29 AD20
AD23 B27 A27 100 AD19 B30 A30
B28 A28 AD22
B31 A31 AD18
A AD21 B29 A29 AD20 A
AD17 B32 A32 AD16
AD19 B30 A30 C_BE#2 B33 A33
B31 A31 AD18
B34 A34 FRAME#
AD17 B32 A32 AD16
IRDY# B35 A35
C_BE#2 B33 A33
B36 A36 TRDY#
B34 A34 FRAME# 12,17,26,32 DEVSEL# B37 A37
12,17,26,32 IRDY# B35 A35 STOP#
B38 A38
B36 A36 TRDY# 12,17,26,32 PLOCK# B39 A39
12,17,26,32 DEVSEL# B37 A37 PERR# B40 A40 SDONEP2 32
B38 A38 STOP# 12,17,26,32 B41 A41 SBOP2 32
12,17,32 PLOCK# B39 A39 SERR# B42 A42
B40 A40 SDONEP1 32 PAR
17,26 PERR# B43 A43
B41 A41 SBOP1 32 C_BE#1 AD15
B44 A44
B42 A42 AD14
12,17,26,32 SERR# B45 A45
B43 A43 PAR 12,17,26 AD13
B46 A46
C_BE#1 B44 A44 AD15
AD12 B47 A47 AD11
AD14 B45 A45 AD10 B48 A48
B46 A46 AD13
B49 A49 AD9
AD12 B47 A47 AD11
key
AD10 B48 A48
B49 A49 AD9
AD8 B52 A52 C_BE#0
AD7
key
B53 A53
B54 A54 AD6
AD8 B52 A52 C_BE#0 12,17,26 AD5 B55 A55 AD4
AD7 B53 A53 AD3 B56 A56
B54 A54 AD6
B57 A57 AD2
AD5 B55 A55 AD4
AD1 B58 A58 AD0
AD3 B56 A56
B59 A59
B57 A57 AD2
32 PU2_ACK64# B60 A60 PU2_REQ64# 32
AD1 B58 A58 AD0
B61 A61
B59 A59
B62 A62
32 PU1_ACK64# B60 A60 PU1_REQ64# 32
B61 A61
B62 A62
PCI Connector 2 Layout Note: Should be in Slot 0 Position (Outside Edge of Board Furthest from CPU)
VCC12- VCC5
C27A
R31A
C25A
C29A
C26A
C28A
C24A
B17 A17 PGNT#2 12,32 PCPCI_REQ#A 12,32
12,32 PREQ#2 B18 A18 0K
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
B19 A19 PCI_PME# 12,16,26 Do Not Stuff R31A
12,16,26 AD[31:0] AD31 B20 A20 AD30
AD[31:0] For Debug Only
AD29 B21 A21
B22 A22 AD28
AD27 B23 A23 AD26
AD25 B24 A24
B25 A25 AD24
12,16,26 C_BE#[3:0] R32A
C_BE#3 B26 A26 R_AD22 AD22
AD23 B27 A27 100
ULTRA-ATA66 IDE
CONNECTORS
VCC5
VCC5
R33A
1K PRIMARY R34A SECONDARY
IDE CONN. 1K IDE CONN.
13 PDD[15:0] 13 SDD[15:0]
J7A J8A
R35A R36A
PCIRST_BUF# R_RSTP# 1 2 PCIRST_BUF# R_RSTS# 1 2
PDD7 3 4 PDD8 33 SDD7 3 4 SDD8
33
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 20 19 20
13 PDREQ 21 22 13 SDREQ 21 22
For Host side 80-conductor Cable Detection:
23 24 23 24 For Host side 80-conductor Cable Detection:
13 PDIOW# Populate R37A and R40A, Depopulate C31A 13 SDIOW#
Populate R38A and R39A, Depopulate C30A
13 PDIOR# 25 26 For Drive side 80-conductor Cable Detection: 13 SDIOR# 25 26
For Drive side 80-conductor Cable Detection:
27 28 PRI_PD1 Populate C31A, Depopulate R37A and R40A 27 28 PRI_SD1
13 PIORDY 13 SIORDY Populate C30A, Depopulate R38A and R39A
13 PDDACK# 29 30 13 SDDACK# 29 30
12,32 IRQ14 31 32 12,32 IRQ15 31 32
R37A R38A
PDA1 33 34 R_P66DET SDA1 33 34 R_S66DET
P66DETECT 14 S66DETECT 14
PDA0 35 36 0K SDA0 35 36 0K
13 PDCS#1 37 38 PDCS#3 13 13 SDCS#1 37 38 SDCS#3 13
30 IDEACTP# 39 40 30 IDEACTS# 39 40
PDA2 SDA2
13 PDA[2:0] 13 SDA[2:0]
C30A
C31A
A A
R41A
R42A
R43A
R45A
R46A
R44A
R39A
R40A
0.047UF
15K
0.047UF
470
470
5.6K
10K
15K
5.6K
10K
VCC3_3
VCC3_3
14
R47A
VCC
8.2K
U5A
SN74LVC07A
7
USB Connectors
VCC3_3 VCC5
R48A
POLYSWITCH RUSB250 25 AC97_USB-
2
0K
F1A
R49A
2.5A 25 AC97_USB+
R50A
Do Not Stuff 0K
1
A L1A
330K
USBV5 1 2
C32A
C33A
1
+
25 AC97_OC#
R51A
68UF
0.1UF
2
470K
R52A
Place R53A, R55A, C35A, and C36A
0K within 1" of ICH
USBV0
Do Not Stuff
R53A R54A
R_USBP0N USBD0N
13 USBP0N
13 OC#0
15 0K R56A
R55A
R_USBP0P USBD0P
C34A R57A 13 USBP0P
15 0K
560K USBG0
.001UF
R58A R59A
C35A C36A 15K
2
15K C37A
47PF 47PF L2A
470PF J9A
USB-CON2
1
1 9
VCC0 GND
2
DATA0-
3 12
DATA0+ GND
4
GND0
2 - USB Stacked
L3A
5
1 2 VCC1
6 11
C38A
A DATA1- GND A
C39A
7
DATA1+
1
8 10
+
GND1 GND
0.1UF
68UF
2
C42A
C43A
C40A
C41A
within 1" of ICH0 USBV1
47PF
47PF
47PF
R60A
47PF
USBD1N
13 USBP1N
15 R61A
USBD1P Place CAPs as close as
13 USBP1P
possible to connector for
15
USBG1 EMI.
2
C44A C45A R62A R63A
15K 15K C46A L4A
47PF 47PF
470PF
1
Title: Intel® 810e Chipset Customer Reference Board REV.
USB Connectors 1.0
Platform Components Division Last Revision Date:
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
19
6/14/99
of 33
A
A
VCC5
CR4A
A C PARV5
1N4148
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
R64A RP3A RP4A RP5A RP6A
2.2K
2.2K 2.2K 2.2K 2.2K
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
15 ERROR#
RP7A
1 8 R_SLCTIN#
15 SLCTIN#
2 7 R_PARINIT#
15 PAR_INIT#
3 6 R_ALF#
15 ALF#
4 5 R_STROBE#
A
15 STROBE# A
33
15 PDR[7:0] RP8A J10A
PDR0 1 8 R_PDR0
1 2
PDR1 2 7 R_PDR1
3 4
PDR2 3 6 R_PDR2
5 6
PDR3 4 5 R_PDR3
7 8
33 9 10
RP9A
PDR4 1 8 R_PDR4 11 12
PDR5 2 7 R_PDR5 13 14
PDR6 3 6 R_PDR6 15 16
PDR7 4 5 R_PDR7 17 18
19 20
33
21 22
15 ACK# 23 24
25 26
15 BUSY
180PF
180PF
C55A
180PF
180PF
C49A
C51A
C54A
180PF
180PF
C47A
C48A
C50A
C52A
C53A
180PF
180PF
180PF
15 PE NOTE: J10A is pinned out for IDC (Flow
15 SLCT# Through) ribbon cable connector.
180PF
180PF
C56A
C62A
C58A
C59A
180PF
180PF
C57A
C60A
180PF
C63A
C61A
180PF
180PF
180PF
VCC5 VCC12
GD75232
20 1
VCC VCC12
19 2 DCD#0_C
15 DCD#0 RY0 RA0
18 3 RXD#0_C
15 RXD#0 RY1 RA1 J11A
17 4 DSR#0_C 1 2
15 DSR#0 RY2 RA2
16 5 DTR#0_C 3 4
15 DTR#0 DA0 DY0
15 6 TXD#0_C 5 6
15 TXD0 DA1 DY1
14 7 CTS#0_C 7 8
15 CTS#0 RY3 RA3
13 8 RTS#0_C 9 10
15 RTS#0 DA2 DY2
12 9 RI#0_C
15 RI#0 RY4 RA4
11 10
GND VCC-12
VCC3_3SBY
100PF
100PF
100PF
100PF
C67A
C64A
C66A
C65A
Place Close to Header COM1 and COM2 are 2x5 pin
Headers for a cabled port.
100PF
100PF
100PF
R65A
100PF
C68A
C69A
C70A
C71A
10K
13 ICH_RI#
Q1A
D
CR5A
2N70 02LT1
R67A BAT54C
1.0UF
47K
A A
C75A
100PF
C73A
C74A
C76A
100PF
100PF
100PF
Place Close to Header
C78A
C79A
C77A
C80A
100PF
100PF
100PF
100PF
F2A L5A
1 2 PS2V5_F 1 2
1.25A
PS2V5 VCC5
RP10A
8
7
6
5
1 8
RP11A 2 7
4.7K STACKED PS2 CONNECTOR 3 6
4 5
1
2
3
4
J13A
L6A 1K
1 2 L_KDAT 1
15 KDAT R68A
PS/2 Kybd
2
1K
3 J14A
L7A 4
1 2 L_KCLK 5 15 DRVDEN#0 2 1
15 KCLK
6 4 3
6 5
L8A 15 DRVDEN#1
1 2 L_MDAT 7 8 7
15 MDAT 15 INDEX#
8 17 PS2GND 10 9
15 MTR#0
PS/2 Mse
9 16 12 11
L9A 10 15 15 DS#0 14 13
1 2 L_MCLK 11 14 16 15
15 MCLK
12 13 15 DIR# 18 17
20 19
C81A
C82A
470PF C83A
C84A
C85A
15 STEP#
15 WDATA# 22 21
24 23
2
15 WGATE#
0.1UF
470PF
470PF
470PF 26 25
PS2_PD
L10A 15 TRK#0
15 WRTPRT# 28 27
15 RDATA# 30 29
1
32 31
2
A
15 HDSEL# A
15 DSKCHG# 34 33
L11A
1
C86A
C87A
C89A
C88A
NOTE: J15A is pinned out for IDC (Flow
2.2K
Through) ribbon cable connector.
VCC5
0.01UF
0.01UF
0.01UF
0.01UF
11
13
15
1
3
5
7
9
J15A
VCC5
8
7
6
5
10
12
14
16
2
4
6
8
RP13A
1K
1
2
3
4
R69A R70A
4.7K 4.7K J1BUTTON1 15
J1BUTTON2 15
J2BUTTON2 15
J2BUTTON1 15
R71A
C91A
C90A
C93A
C92A
15 MIDI_OUT R_MIDIOUT
R72A 47
R_MIDIIN
15 MIDI_IN
47PF
47PF
47PF
47PF
C94A
C95A
47
470PF
470PF
22 of 33
A
A
L12A L13A
2 1 FPP1V3 2 1
C96A
C97A
C98A
C99A
100PF C100A
C101A
C102A
FPDV3
1
+
1
+
100PF
100PF
10UF
10UF
100PF
100PF
VCC3_3
2
L14A
2 1 FPAV3
C103A
C104A
VCC1_8
C105A
1
+
100PF
10UF
100PF
R73A 2
1K R74A
400
FTVREF 1%
EXTRS_PU
U8A
29
23
49
18
33
12
C106A
Place C106A
C107A
1
near U8A pin 3
VREF
AVCC1
AVCC0
PVCC1
PVCC0
VCC2
VCC1
VCC0
1
+
R76A
100pF
1K 36
0.01UF
D23
2
37 21 TXC- 24
D22 TXC-
38 22 TXC+ 24
D21 TXC+
39
D20
40
D19
41 24 TX0- 24
D18 TX0-
42 25 TX0+ 24
D17 TX0+
43
44
D16/PFEN DFP
45
D15
D14
Flat Panel TX1-
27 TX1- 24
A
46
47
D13 Transmitter TX1+
28 TX1+ 24
A
8 FTD[11:0] D12
FTD11 50
D11
FTD10 51 30
D10 TX2- TX2- 24
FTD9 52 31
D9 TX2+ TX2+ 24
FTD8 53
D8
FTD7 54 19
D7 EXT_RS
FTD6 55
D6
FTD5 58 35
D5 DKEN PCIRST# 6,12,14,15,16,17,18,26
FTD4 59 34 TEST_PD
D4 TEST
FTD3 60 15
D3 BSEL/SCL 3VFTSCL 8,24
FTD2 61 14 3VFTSDA 8,24
FPDV3
D2 DSEL/SDA
FTD1 62 13
D1 ISEL/RST
FTD0 63 11
D0 MSEN SL_STALL 8
10
PD
8 FTCLK0 56 9 3VHTPLG 24
IDCLK- EDGE/CHG
57 R77A
8 FTCLK1 IDCLK+ 8 A1_PD
2 CTL1/A1/DK1
8 FTBLNK# DE 7 A2_PD 1K
4 CTL2/A2/DK2
8 FTHSYNC HS 6 A3_PD R78A
5 CTL3/A3/DK3
8 FTVSYNC VS
AGND2
AGND1
AGND0
1K
PGND
GND2
GND1
GND0
R79A R80A
4.7K
1K
32
26
20
17
64
48
16
Do Not Stuff
Video Connectors
VCC5
20 Pin Flat Panel Connector VGA Connector
VCC1_8
CR6A
2
2 F3A
BLM11B750S is rated at 2.5A
VCC5 1 3
VCC5 70Ohms at 100MHz
1
L15A R82A R81A
BAT54S
1 2 1K
CRT5V_F
8 VID_RED 1K
J16A
C
B L M 11B750S
C108A
C109A
CR7A -
Place R66A,R67A,&
23 TX1+ 1 11 TX2+ 23 R69A Close to VGA
1N5821 + Protection Circuit
R83A
2 12 TX2- 23 Connector 75
A
23 TX1-
3.3PF
3.3PF
2
3 13 for 20V Tolerance 1%
VCC1_8 L16A J17A
4 14
1
7 17 R84A L_RED 1 1 11
8 18 CON_HTPLG 1 5VHTPLG 1 3 MONOPU 11
0.01UF C111A
2.2K
C110A
9 19 R248 BAT54S 7
L17A
10 20 30k 1 2 L_GREEN 2
1
+
De-Bounce 8 VID_GREEN
12
2
10UF
Circuit B L M11B750S
C113A
C112A
2
8
CON_FTSDA
CON_FTSCL
R85A L_BLUE 3
3.3PF
3.3PF
75 L_HSYNC 13
1%
FUSE_5 9
R86A MON2PU 4
5VFTSDA
0K L_VSYNC 14
R87A
5VFTSCL 5VDDCDA 10 10
0K 5 5 15
R88A
P o p u l ate if DFP Device 5VHSYNC 15
A i s also populated. A
C114A
C115A
VCC5 0K
CR9A
5V to 3.3V Translation / Isolation
3.3PF
3.3PF
2
VCC5
CR10A 1 3
Do Not Stuff C114A and C115A
QS4_3V C A BAT54S
C116A
5VDDCCL
8
7
6
5
VCC5 0K
C117A
C118A
2.2K
1
2
3
4
U9A CR11A
C119A
C120A
C121A
C122A
3.3PF
3.3PF
QST3384 2
24
VCC
3 2 5VDDCDA 1 3
8 3VDDCDA 1A1 1B1
10PF
10PF
10PF
10PF
4 5 5VDDCCL
8 3VDDCCL 1A2 1B2 BAT54S Do Not Stuff C117A and C118A
7 6 5VHSYNC
8 CRT_HSYNC 1A3 1B3
8 9 5VVSYNC L18A
8 CRT_VSYNC 1A4 1B4 1 2
11 10 5VHTPLG 8 VID_BLUE
23 3VHTPLG 1A5 1B5
5VFTSDA B L M 11B750S
14 15
C123A
C124A
8,23 3VFTSDA 2A1 2B1
17 16 5VFTSCL VCC1_8
8,23 3VFTSCL 2A2 2B2 R91A CR12A
18 19 QSSDA R92A 75
5 CK_SMBDATA SMBDATA 10,11,13,27,32
3.3PF
3.3PF
2A3 2B3
21 20 QSSCL R93A 0K 1% 2
5 CK_SMBCLK 2A4 2B4 SMBCLK 10,11,13,27,32
22 23 0K
2A5 2B5 1 3
1 12
BEA# GND
13 BAT54S
BEB#
R94A
2.2K
R95A
2.2K
Do Not Populate Title: Intel® 810e Chipset Customer Reference Board REV.
AUDIO/MODEM RISER
VCC12
VCC5
VCC5 VCC12-
VCC3_3 VCC3_3SBY
J18A
B1 A1
AUDIO_MUTE# AUDIO_PWRDWN
B2 A2
GND[0] MONO_PHONE
30 AC97SPKR B3 A3
MONO_OUT/PC_BEEP RESV[5]
B4 A4
RESV[1] RESV[6]
B5 A5
RESV[2] RESV[7]
B6 A6
PRIMARY_DN# GND[7]
B7 A7
-12V +5VDUAL/5VSBY
B8 A8 AC97_OC# 19
GND[1] USB_OC
B9 A9
+12V GND[8]
B10 A10 AC97_USB+ 19
GND[2] USB+
B11 A11 AC97_USB- 19
+5VD USB-
KEY
AC'97_RISER KEY
AMR_CONNECTOR
KEY KEY
B12 A12
GND[3] GND[9]
A B13 A13 A
RESV[3] S/P_DIF_IN
B14 A14
RESV[4] GND[10]
B15 A15
+3.3VD +3VDUAL/3VSBY
B16 A16
GND[4] GND[11]
13 AC_SDOUT B17 A17 AC_SYNC 13
AC97_SDATA_OUT AC97_SYNC
13 AC_RST# B18 A18
AC97_RESET# GND[12]
B19 A19 AC_SDIN1 13,32
AC97_SDATA_IN3 AC97_SDATA_IN1
B20 A20
GND[5] GND[13]
B21 A21 AC_SDIN0 13,32
AC97_SDATA_IN2 AC97_SDATA_IN0
B22 A22
GND[6] GND[14]
B23 A23 AC_BITCLK 13
AC97_MSTRCLK AC97_BITCLK
VCC5
VCC3_3SBY VCC3_3SBY
LAN R96A
4.7K
VCC3_3SBY VCC3_3SBY
5% VCC3_3SBY
G13
U10A
K13
P12
A11
E12
K10
K11
L10
J10
J11
G5
G6
N8
N6
H5
H6
H7
H8
A3
A7
E1
K3
P2
K4
K5
K6
K7
K8
K9
L4
L5
L9
J5
J6
J7
J8
J9
VCCPT
VCCPL[0]
VCCPL[1]
VCCPL[2]
VCCPL[3]
VCCPP[0]
VCCPP[1]
VCCPP[2]
VCCPP[3]
VCCPP[4]
VCCPP[5]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[0]
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
12,16,17 AD[31:0] AD0 N7
AD0
AD1 M7
AD1
AD2 P6 A12
AD2 LILED LILED 27
LAN Decoupling AD3 P5 C11
AD3 ACTLED ACTLED 27
Distribute around Power AD4 N5 B11
VCC3_3SBY AD4 SPEEDLED SPEEDLED 27
AD5 M5 C13
Pins Close to 82559. AD5 TDP TDP 27
AD6 P4 C14
AD6 TDN TDN 27
AD7 N4 E13
C127A
C125A
C126A
0.1UF
0.1UF
AD10 N2 C5
AD10 CSTSCHG
AD11 M1 A6
AD11 PME# PCI_PME# 12,16,17
AD12 M2 J13
AD12 FLA0/PCIMODE# R97A
AD13 M3 J12 LANAPWR
AD13 FLA1/AUXPWR
VCC3_3SBY
AD14 L1 K14 3K
AD14 FLA2
AD15 L2 L14
AD15 FLA3
AD16 K1 L13
AD16 FLA4
C128A
C129A
C130A
AD17 E3 L12
AD17 FLA5
AD18 D1 M14
AD18 FLA6
AD19 D2 M13
0.1UF
0.1UF
0.1UF
AD19 FLA7
AD20
AD21
D3
C1
AD20
AD21
82559 FLA8/IOCHRDY
FLA9/MRST
N14
P13
VCC3_3SBY
AD22 B1 N13
AD22 FLA10/MRING#
AD23 B2 M12 U11A
VCC3_3SBY AD23 FLA11/MINT
8
AD24 B4 M11 93C46
AD24 FLA12/MCNTSM#
VCC
Place C131A/C132A AD25 A5 P10 EEDI 3
AD25 FLA13/EEDI EEDI
C131A
C132A
1
+
GND
AD28 C6 P9 1
AD28 FLA16 EECS
4.7UF
4.7UF
AD29 C7 F14
2
AD29 FLD0
AD30 A8 F13
5
AD30 FLD1
AD31 B8 F12
AD31 FLD2
A G12 A
FLD3
12,16,17 C_BE#[3:0] C_BE#0 M4 H14
C/BE0# FLD4 R98A
C_BE#1 L3 H13 FLD5_PD
C/BE1# FLD5 R99A
C_BE#2 F3 H12 FLD6_PD 619
C/BE2# FLD6
C_BE#3 C4 J14 619
C/BE3# FLD7 Do Not Stuff
P7 EECS
EECS
12,16,17,32 FRAME# F2 N9
FRAME# FLCS#
12,16,17,32 IRDY# F1 M8
IRDY# FLOE#
12,16,17,32 TRDY# G3 M9
TRDY# FLWE# R100A
H3 C8 LANCLKRUN
12,16,17,32 DEVSEL# DEVSEL# CLKRUN# R101A
H1 A13 LAN_TEST 62K
12,16,17,32 STOP# STOP# TEST
J1 D13 4.7K
12,16,17 PAR PAR TEXEC
12,16,17,32 PIRQ#A H2 D14
INTA# TCK
16,17 PERR# J2 D12
PERR# TI
12,16,17,32 SERR# A2 B12
R102A SERR# TO R103A
R_LANIDS A4 B14 RBIAS10
12,16,17 AD20 IDSEL RBIAS10 R104A
100 C3 B13 RBIAS100 549
12,32 PREQ#3 REQ# RBIAS100
J3 C12 619
12,32 PGNT#3 GNT# VREF
6,12,14,15,16,17,18,23 PCIRST# C2 D10
RST# NC11
5 PCLK_5 G1 G4
CLK NC10
A14
NC9
27 LAN_ISOLATE# B9 J4
ISOLATE# NC8
27 LAN_RST# A9 L7
ALTRST# NC7
P1
NC6
27 L_SMBCLK A10 D9
SMBCLK NC5
27 L_SMBD C9 L8
SMBD NC4
P14
NC3
VIO G2 H4
VIO NC2
A1
NC1
L AN_XTAL1 N11
X1
VSSPP[0]
VSSPP[1]
VSSPP[2]
VSSPP[3]
VSSPP[4]
VSSPP[5]
VSSPL[0]
VSSPL[1]
VSSPL[2]
VSSPL[3]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSSPT
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
Y2A
2
L AN_XTAL2 P11
X2
C133A
C134A
C135A
G14
G10
G11
N12
C10
D11
H10
H11
K12
E10
E11
F10
F11
L11
M6
G7
G8
G9
N1
D4
D5
D6
D7
D8
H9
P8
B3
B7
E2
K2
E4
E5
E6
E7
E8
E9
F4
F5
F6
F7
F8
F9
L6
25MHZ
1
22PF
22PF
0.1UF
LAN 1.0
Platform Components Division Last Revision Date:
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
26
6/14/99
of 33
A
A
LAN
VCC3_3SBY
VCC3_3SBY
JP11_PU
JP12_PU
JP7_PU
ACT_CR
J19A JP6A JP7A JP8A
10 RJMAG
R109A
26 TDP TD+ 15 LI_CR ACTLED
12 LA1
26 TDN TD- 330
9 16 LILED
26 RDP RD+ LC1
7
RJ-45
26 RDN RD- 26 LILED
13 26 ACTLED
5 LA2
R110A R111A R112A R113A RJ-4 26 SPEEDLED
Place Termination near 82559 50 6 14 SPEEDLED
50 50 50 RJ-5 LC2
3
RJ-7
4
RJ-8
SHLD1
SHLD2
TD_PD RD_PD
RDC
RXC
TDC
TXC
C137A
C136A
17
18
11
1
2
8
0.1UF
0.1UF
RDC
TDC
RJ45_PD
RJ78_PD
Do Not Stuff
RXC_PD
TXC_PD
R114A R115A R116A R117A C138A C139A VCC3_3SBY
75 75 75 75 0.1UF
A
0.1UF A
Do Not Stuff
R118A
RJMAG_CONN
4.7K
JP9A
C140A 1
10,11,13,24,32 SMBCLK R119A
Default Config: Note: Chassis Ground, JP8_SMBC
2 L_SMBCLK 26
Do Not Stuff 470PF-1500V use plane for this signal
For EST Testing 13 GPIO27 3 0K
Select JP9A/JP10A
R120A
4.7K
JP10A
10,11,13,24,32 SMBDATA 1
R121A
2 JP9_SMBD L_SMBD 26
R122A
13 GPIO28 3 0K
13 SUS_STAT#
0K
LAN_ISOLATE# 26
R123A
13,28,31 PWROK
0K
Do Not Stuff R123A LAN DISABLE - JP11A
NORMAL 1-2 Default
DISABLE 2-3
JP11A
13,31 RSMRST# 1
2 LAN_RST# 26
3
LAN 1.0
Note: This circuit is for debug purpose only. Platform Components Division Last Revision Date:
6/14/99
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
27 of 33
A
A
Voltage Regulators
V3SB
VCC3_3
VCC3_3SBY
1N5822
CR13A
1
C144A
+
C141A C142A C143A
This generates 3.3V Standby Power which is
47UF 47UF NDS356AP 1200uF 1200uF
2
on in S0,S1,S3,S4,&S5. It passes 3.3V from S D
the ATX supply in S0/S1, and 3.3VSB (generated
by VR4 below) in S3/S4/S5. VTT 1.5V VOLTAGE REGULATOR
Q2A
G
Do Not Populate
VCC12
NDS356AP VCC3_3 VTT1_5
VR1A
S D LT1587-1_5
2
VOUT
R124A 3
VIN
4.7K ADJ
1
Q3A
C145A
VCC5SBY
C146A
C147A
G
1
+
+
100UF
VCC5SBY Q4A
100UF
SI4410DY
1.0UF
R125A
2
VCC3_3SBY PLANE_CTL1 4 5
10K
14
3 6
C
U12A Q5A
VCC
U13A 2 7
3
14
R126A
MMBT3904LT1
13,31 SLP_S3# 1 1 8
A 3 PCTL_IN 1 2 PLANE_CTL0 V_GQ6 B
2 Y 1
13,27,31 PWROK B 7 0K
GND
2
74LS132 SN74LVC07A
E
7
VCC 3.3VSB Regulator VCC 1.8 VOLTAGE REGULATOR VCC 2.5 VOLTAGE REGULATOR
VCC1_8
VCC2_5
VCC5SBY V3SB VCC3_3 VCC5
VR2A
VR4A
VR3A LT1587ADJ
LT1587ADJ
LT1117-3_3 R127A R128A
2 301
VOUT 2 240
3 1% VOUT
3 2 VIN 3 1%
C148A
GND
IN OUT VIN
1
C149A
C151A
VR1_ADJ
C150A
Place C152A at
1
ADJ
C152A
+
Regulator
C154A
1
1
+
+
the Regulator
1
1
R129A
+
1
22UF
+
100UF
100UF
1.0UF
130 R130A
2
100UF
22UF
1% 2 240
0.1UF
2
2
1%
Processor Voltage
Regulator
(VRM 8.4 rev 1.5) VCC3_3 VCC5
VCC5 VCC12
1.0UH-6.8A
R133A R134A
R135A 220
L19A
5.6K
5.1
VRM_PWRGD 31
5VIN C155A
C156A
C158A
C157A
C160A
C159A
C161A
1.0UF
1
+
1200UF +
1200UF +
R136A
10UF
1200UF
1200UF
0.1UF
10K
2
C162A R137A
2.7K Q7A Q8A
0.01UF
5
6
7
8
5
6
7
8
PV12
D4
D3
D2
D1
D4
D3
D2
D1
SI4410DY
SI4410DY
VR5A Place CAPs
2
RP15A Close to FETs
PVCC
VCC
G1
G1
3 VID[4:0] OUTEN
S3
S2
S1
S3
S2
S1
19 7 IMAX
OUTEN IMAX
VID0 4 5 R_VID0 18 13 C163A C164A
VID0 PWRGD VCCVID
1.0UF 1.0UF
4
3
2
1
4
3
2
1
VID1 3 6 R_VID1 17 12 FAULT#_PU
VID1 FAULT#
VID2 2 7 R_VID2 16 20 G1
VID2 G1 L20A
VID3 1 8 R_VID3 15 8 R_VCCVID R138A L_VCCVID
VID3 IFB
VID4 1 20K 14 1 20 0.8UH-20A
SENSE
G2
Q9A
COMP
VID4 G2 Q10A
SGND
0
GND
11 VFB_PD
5
6
7
8
5
6
7
8
VFB
SS
D4
D3
D2
D1
D4
D3
D2
D1
SI4410DY
SI4410DY
10
LTC1753
6
The LTC1753 incorporates internal pull-ups on VID[4:0]. VRCOMP_PD
SS_PD
G1
G1
S3
S2
S1
S3
S2
S1
A If your VR IC does not incorporate these, they must A
4
3
2
1
4
3
2
1
JP15A
8.2K
JP13A
R_VRCOMP
C166A
C168A
C167A
C165A
220PF
0.1UF
150PF
0.01UF
C170A
C172A
C173A
C174A
C171A
C169A
1
+
+
+
+
+
0.1UF
2700UF
2700UF
2700UF
2700UF
2700UF
Do Not Stuff C169A
2
Refer to VR supplier for layout guildlines.
VCC3_3 VCC5
SYSTEM VCC3_3SBY
C175A
16V
No stuff. R141A
1
+
R142A 100K
ICH has internal pullup and debounce on PWRBTN# For test only
10UF
C176A
1M
2
0.1UF
R143A
13 PWRBTN# J21A
0K 15 IRRX
C177A 1
1.0UF 2
No stuff. 15 IRTX R144A
R_IRTX 3
For test only SW1 R145A 82 4 INFRARED
1 2 4.7K 5
VCC3_3 VCC3_3 KEY
3 4 6
7
VCC5 VCC5 VCC3_3
PBTN_IN 8
9 POWER SW.
R146A 10
R147A R148A
14
U5B 11
R149A 470
10K 10K 10K SN74LVC07A
VCC
12
13
14
KEY
3
A O
4 IDE_ACTIVE 14 H.D. LED
18 IDEACTP#
VCC
15
GND
VCC5
FP_PD
16 KEY
5 6 17
18 IDEACTS# A O
7
U5C
GND
18 POWER LED
SN74LVC07A R150A KEY
PWRLED 19
220 20
7
KEY
21
15 KEYLOCK#
22 KEYLOCK
23
24
KEY
25 SPEAKER VCC5
A 25 AC97SPKR R151A A
SPKR_IN R_SPKRIN 26
JP17A
VCC3_3 68
Q11A
C
1 FNT_PNL_CONN
R152A
3
2 R153A
13 ICH_SPKR SP1A
3 SPKR SPKR_Q1G B 68
2N3904
1 1+
C178A C179A C180A POS
2.2K SPKR_NEG 2
2
NEG
5
6
7
8
E
0.1UF 470PF 470PF
RP16A
4.7K
VCC3_3SBY
VCC12 VCC3_3SBY
VCC12 VCC3_3SBY
R155A
R154A
330
C181A
330
C182A
VCC3_3SBY VCC3_3SBY
0.1UF 0.1UF
J22A J23A R156A On-Board LED indicates the
1 1 14 U13B U13C 14
Standby Well is on to prevent
2 2 330
Hot-Swapping Memory. 13 GPIO23_FPLED 3 4 1 2 GP26LED 6 5 GPIO26_FPLED 13
3 3
V3SBLED
GP23LED
7 7
For Debug Only
SN74LVC07A SN74LVC07A
15 TACH1 15 TACH2 CR14A
R157A
VCC12
2
4.7K
VCC12 CR15A
1
C183A C184A
0.1UF
J24A J25A 0.1UF
1 1
2 2
3 3
Title: Intel® 810e Chipset Customer Reference Board REV.
15 PWM1 15 PWM2
SYSTEM 1.0
Platform Components Division Last Revision Date:
intel R
1900 Prairie City Road
Folsom, Ca. 95630
Sheet:
30
6/14/99
of 33
A
A
SYSTEM
Power Connector and Reset Control
ITP RESET CIRCUIT - FOR DEBUG ONLY
VCC3_3SBY
VCC3_3SBY
14
VCC5 SN74LVC08A
VCC5SBY
1
VCC5- 3 DBRST
VCC12 APOK_ST 2 VCC2_5
VCC12- VCC3_3 VCC3_3SBY
14
14
7
U15A U15B
VCC3_3SBY 1 2 ST23 3 4
R159A
R160A J26A 74LVC14A 74LVC14A 0K
14
7
7
4.7K U16A R161A
14
11 1
VCC
U16B 3_3V11 3_3V1 SN74LVC06A has 330
74LVC14A is 5V input 5V input tolerance
VCC
12 2
-12V 3_3V2 tolerant
13 3 1 2
GND13 GND3 A O PWRGOOD 4
3 4 5VPSON 14 4 VCC5SBY
13,28 SLP_S3# A O PS_0N ATX 5V4
GND
15 5 DBRPOK SN74LVC06A
GND15 GND5
GND
14
SN74LVC06A 16 6 U12B
SN74LVC06A is 5V output GND16 5V6
74LS132
VCC
7
17 7 VCC3_3SBY
tolerance GND17 GND7 R162A R163A
ATX_PWOK DBRPOK_DLY
7
18 8 4
-5V PW_OK A 6 PWROK#
19 9 5 Y
5V19 5VSB 0K 0K B VCC3_3SBY
GND
20 10 Do not stuff C185A
5V20 12V 1.0UF
14
R164A
7
Do not stuff U16C
4.7K
VCC
220 Ohm Pull-up to 3.3V is on VRM Sheet 5 6
A
A O PWROK 13,27,28 A
29 VRM_PWRGD
GND
SN74LVC06A
R165A
1M
7
Reset Button Do Not Stuff
For Debug Only
SW2
1 2
R166A
3 4 RST_PD
22
JP18A
1
+
1 2 C186A C187A
0.01UF 10UF
2
Place JP23A near front panal header (J20) Resume Reset Circuitry
Schmitt Trigger Logic
using a 22msec delay
VCC3_3SBY VCC3_3SBY VCC3_3SBY
14
14
8.2K R168A U15D
V3RSMRST
5 6 ST69 9 8 RSMRST# 13,27
VCC3_3SBY CK_PWRDN# 5 22K 74LVC14A
7
U14B
14
R169A
DBRPOK 4 R170A C188A
6 CK_PWRD 1.0UF 1M
5 Do Not Stuff
For Debug Only
0K
SN74LVC08A
7
2 7
14
U14C 13 GPIO22
9 3 6
VCC
14
10 4 5
13,17 GPIO21
11 10
VCC
SN74LVC08A
9 8
7
U5D A O 8.2K
74LVC14A
7
GND
9 8 U14D
14
A O SN74LVC06A VCC5
14
U15F 12
GND
11 RP31A
13 12 13 1 8
7
74LVC14A
7
12,18 IRQ15
VCC3_3SBY 150
8.2K
VCC
11 10
14
U5E A O
R179A
VCC
U13D 4 TESTHI
GND
11 10 SN74LVC06A 14 U12C
A O 9 100K
9 8 A 8
GND
10 Y
SN74LVC07A 7 B
7
GND
74LS132 R180A
SN74LVC07A 13,25 AC_SDIN0
7
10K
14
U13E
14
R181A
VCC
14 13,25 AC_SDIN1
VCC
U16F 11 10 10K
U5F
14
13 12 7 U12D
A O
VCC
13 12
A O SN74LVC07A
12
GND
GND
SN74LVC06A A 11
SN74LVC07A U13F 13 Y
14 B
GND
74LS132
13 12
7
7
GMCH Decoupling Display Cache Decoupling ICH Distribute near the Distribute near the
C270A
C269A
C268A
1
C238A C239A C240A C241A C243A C244A C245A C246A C249A C250A C251A
1
C242A C247A C248A C252A C253A C254A C255A C256A C257A C258A C259A C260A C261A C262A C263A C264A C265A C266A C267A
+
C237A
+ 2.2UF
10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF
10UF
10UF
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
2
2
GMCH Core Plane Decoupling:
Place 1 .1uF/.01uF pair in each corner,
and 2 on opposite sides close to component
if they fit.
VCC1_8
C279A
C283A
DIMM0 Decoupling:
C296A
C282A
C280A
C281A
C297A
C295A
A
C284A
A
C294A
C290A
22UF
22UF
1
2
VCC3_3SBY
+
+
Distribute near DIMM0 Power Pins.
2
C285A C286A C288A C289A
+
C291A C292A
0.1UF
0.1UF
22UF
0.1UF 0.1UF
22UF
C287A
+
0.1UF 0.1UF 0.1UF 0.1UF
+
22UF
C293A
2
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1
2
1
C298A
1
C299A C300A
+
DIMM1 Decoupling:
VCC3_3
Distribute near DIMM1 Power Pins.
VCC3_3SBY
C337A
C332A
C334A
C335A
C338A
C331A
C336A
22UF C333A
C311A C312A C313A C314A C315A C316A C317A C318A C319A C320A C321A C322A C323A C324A C325A C326A C327A C328A C329A C330A
1 +
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
2
33 of 33
A