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Compal confidential
Schematics Document Mobile Arrandale rPGA989 with Intel PCH(Ibex Peak-M) core logic
2009-11-05 REV 1.0
2006/03/10
Title
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 1 of 45
Compal confidential
Fan conn
Page 6
Mobile Arrandale
2C CPU + GMCH Socket-rPGA989
DDR3 SO-DIMM X2
BANK 0, 1, 2, 3
P17, 18
Dual Channel
CRT
page 20
UMA
DMI X4
FDI X4
USB conn x1 P29 Left side (ESATA) USB conn x2 Right side
USB2.0 X12
P29
2
P29
HDMI Conn.
page 22
Level Shifter
page 22
UMA
Intel PCH
Ibex Peak-M FCBGA 951
Page 11,12,13,14,15,16
P21
PCI-E BUS*4
P29
SATA Slave
Mini-Card
WWAN SPI
P29
Mini-Card
WLAN
P24
Mini-Card
TV-tuner
P24
New Card
P24
Audio CKT
Codec_IDT92HD80
P27
Audio Jack
LPC BUS
P30
P28
3
RJ45 CONN
P25
MDC
P27
ENE KB926
Version D2
P31
P23
P23
LED
P32
Int.KBD
P31
P32
P29
ACCELEROMETER ST
4
P23
4
P32
http://mycomp.su/x/
P33
A
P26
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 2 of 45
Symbol Note :
USB assignment:
USB-0 Left side(with ESATA) Right side Right side Dock Camera MiniCard(WLAN) X (HM55 don't support) X (HM55 don't support) MiniCard(WWAN) New Card USB-1 USB-2 USB-3
Voltage Rails
O MEANS ON
X MEANS OFF
@ : means just reserve , no build 45@ : means need be mounted when 45 level assy or rework stage. BATT @ : means need be mounted when 45 level assy or rework stage. CONN@ : means ME part PA@ : Only For PA (With Capacitor sensor) OPP@ : For POWER BUTTON (NO CAP SERSOR) DEBUG@ : For DEBUG
PCIe assignment:
PCIe-1 WWAN PCIe-2 WLAN PCIe-3 RTL8401 Combo PCIe-4 New card PCIe-5 X PCIe-6 X PCIe-7 X (HM55 don't support) PCIe-8 X (HM55 don't support)
O O O O O X
O O O O X X
O O O X X X
O O X X X X
SATA assignment:
SATA0 HDD SATA1 ODD SATA2 X (HM55 don't support) SATA3 X (HM55 don't support) SATA4 ESATA SATA5 Multi Bay
1
ADDRESS
10100000 10100100 11010010 00011101
X X X X X
VCCP
V X X X X
X X X X X
X X V X X
+3VS
X X V X X
+3VS
X X V X X
+3VS @+3VALW
X X V X X
+3VS @+3VALW
X X X X X
V X X X X
+3VL
X X V X X
+3VS
X X V X X
+3VS
+3VALW
CONNECTED
ZZZ ZZZ
DAZ0BI00400
OPP@
2006/03/10
Title
http://mycomp.su/x/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1A
+V_BATTERY INVPWR_B+
+3VAUX_BT +3VS_PEC
80mA 1.3A
Dock con
0.3A
DOCK_VIN
D
VL
+5VL
20mA
25mA
+3VL_EC CIR
EC
LVDS CON
AC
VIN
+3VALW
250mA 1A 1A
B++
169mA
500mA
C
USB-L(ESATA)
850mA
1A 7.7A
PCH
C
CPU
+5VALW
0.1A
LED
100mA
HDMI TRANS
6.1A
35mA
B+
20.67A 2.16A 13.3A
3A
8 A
+1.5V_B+
+1.5V
650mA
800Mhz 4G x2
650mA
1mA
+3VS_ACL
DDR3
60mA
60mA
+AVDD_CODEC INT_MIC CODEC PVDD ODD HDD Multi Bay +CRT_VCC +USB_CAM +5VS_LED
20mAx6 1A
3.7 X 3=11.1V
Mini card-WWAN
500mA
DC
BATT
+1.5VS_WLAN
1650mA
0.5A 650mA
+1.5VS
650mA
Mini card-WLAN
1.8A
+1.5VS_PEC
New card
1300mA 162mA
18.24A
+VCCP
18A 80mA
2.89A
VCCP_B+
25.24A
+1.05V_VCCP
7A
+1.05VS
7A
5.49A
CPU_B+
+VCC_CORE
48A/1.05V
CPU
Security Classification
http://mycomp.su/x/
5
1.72A
GFX_B+
4
+GFX_CORE
15A/1.05 V
CPU
3
Issued Date
2006/03/10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
2006/03/10
Title
http://mycomp.su/x/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
Layout rule 10mil width trace length < 0.5", spacing 20mil
R1 1 R3 1 R5 1 R7 1 2 20_0402_1% 2 20_0402_1% COMP3 COMP2 AT23 AT24 G16 AT26 AH24 AK14
CLOCKS
14
H_PECI
DDR3 MISC
T73 1 1 1
TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
AN28 AP28 AT27 AT29 AR27 AR29 AP29 AN25 AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
13 H_PM_SYNC H_CPUPWRGD
14 H_CPUPWRGD
38
VCCP_POK
1.5K_0402_1% 2
14 BUF_PLT_RST#
750_0402_1% Design guide 1.11update,PLTRST series resittor 1.5K, PL resistor 750 ohm
Processor Pullups
H_CATERR#
B
R35
1 1 2
1 2 5 6
1 C12 470P_0402_50V7K
1.5VSCPU_DRAM_PWRGD
@ R384 2
U57 Y 4
13 PM_DRAM_PWRGD
B A
VCCP_POK
2 1
PM_DRAM_PWRGD
R1218 750_0402_1%
A
NC7SZ08P5X_NL_SC70-5
http://mycomp.su/x/
+VCCP JCPU1B COMP3 COMP2 COMP1 COMP0 SKTOCC# CATERR# BCLK BCLK# BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# A16 B16 AR30 AT30 E16 D16 A18 A17 CLK_EXP CLK_EXP# CLK_EXP 12 CLK_EXP# 12 CLK_CPU_BCLK CLK_CPU_BCLK# CLK_CPU_BCLK 14 CLK_CPU_BCLK# 14
XDP Connector
XDP_TDI XDP_TMS
@ R2 1 @ R4 1
MISC
XDP_PREQ# @ R6 1 XDP_TDO R8 1
PAD
T1
eDP
SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PM_EXTTS#0 PM_EXTTS#1 R14 T63 PAD 2 0_0402_5%
THERMAL
R10
AT15
JTAG MAPPING
XDP_TDI_R R30 1 2 0_0402_5% XDP_TDI
PECI
40 H_PROCHOT#
AN26
PROCHOT#
XDP_TDO_M
@ R32
2 0_0402_5%
XDP_TDO
14 H_THERMTRIP#
H_THERMTRIP#
AK15
THERMTRIP#
PRDY# PREQ#
AT28 AP27
R34 0_0402_5%
@ R37
+3VS
PWR MANAGEMENT
XDP_TDO_R
R38
2 0_0402_5%
XDP_DBRESET#
13
XDP_TRST#
R39
2 51_0402_1%
H_PWRGD_XDP_R PLT_RST#_R
AM26 AL14
1.5K_0402_1% R28
IC,AUB_CFD_rPGA,R1P0 CONN@
+1.5V
1105_Add R597.
R597 0_0603_5% 1 2 1 C3 4.7U_0805_10V4Z 1 C295 0.1U_0402_16V4Z JP2 1 2 3 4 1 2 GND GND ACES_88231-02001 CONN@
DRAMRST#
17,18
+FAN
B
@ D49 RLZ5.1B_LL34
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
JCPU1A PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
B
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
A24 C23 B22 A21 B24 D23 B23 A22 D24 G24 F23 H23 D25 F24 E23 G23
DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]
B26 A26 B27 A25 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
EXP_ICOMPI EXP_RBIAS
R44 R45
1 1
13 13 13 13 13 13 13 13
D22 C21 D20 C18 G22 E20 F20 G19 F17 E17 C17 F18 D17
FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1]
RESERVED
13 13 13 13 13 13 13 13
IC,AUB_CFD_rPGA,R1P0 CONN@
*
A
CFG3-PCI Express Static Lane Reversal CFG3 1: Normal Operation 0: Lane Numbers Reversed 15 -> 0, 14 ->1, .....
WW33 WW41
http://mycomp.su/x/
5
Only temporary for early CFD samples (rPGA/BGA) Only for pre ES1 sample
4
CFG7
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18
AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86
RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 E15 F15 A2 D15 C15 AJ15 AH15
@ R48 @ R49
1 1
2 0_0402_5% 2 0_0402_5%
B19 A19 @ R50 @ R51 1 1 2 0_0402_5% 2 0_0402_5% A20 B20 U9 T9 AC9 AB9
RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 VSS
C1 A3
RSVD_NCTF_23 RSVD_NCTF_24
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 AP34
IC,AUB_CFD_rPGA,R1P0 CONN@
2009/05/11
Title
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 7 of 45
JCPU1D JCPU1C
17 DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
AA6 AA7 P7
18 DDR_B_D[0..63] M_CLK_DDR0 17 M_CLK_DDR#0 17 DDR_CKE0_DIMMA 17 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
W8 W9 M3 V7 V6 M2
Y6 Y5 P6
SA_CS#[0] SA_CS#[1]
AE2 AE8
DDR_CS0_DIMMA# 17 DDR_CS1_DIMMA# 17
SB_CS#[0] SB_CS#[1]
AB8 AD6
DDR_CS2_DIMMB# 18 DDR_CS3_DIMMB# 18
SA_ODT[0] SA_ODT[1]
AD8 AF9
M_ODT0 17 M_ODT1 17
SB_ODT[0] SB_ODT[1]
AC7 AD1
M_ODT2 18 M_ODT3 18
DDR_A_DM[0..7]
17
DDR_B_DM[0..7] 18
DDR_A_DQS[0..7]
17
DDR_A_DQS#[0..7]
17
DDR_B_DQS#[0..7]
18
DDR_B_DQS[0..7]
18
AC3 AB2 U7
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_MA[0..15] 17
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDR_B_MA[0..15] 18
2009/05/11
Title
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 8 of 45
+VCC_CORE JCPU1F
+GFX_CORE AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 C987 22U_0805_6.3V6M C988 22U_0805_6.3V6M C989 10U_0805_6.3V6M 10U_0805_6.3V6M C990 10U_0805_6.3V6M
JCPU1G VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VCC_AXG_SENSE VSS_AXG_SENSE
48A
D
18A
VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C40 10U_0805_6.3V6M C41 10U_0805_6.3V6M C42 10U_0805_6.3V6M
15A
SENSE LINES
RF request.
AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26
RF request.
VAXG_SENSE VSSAXG_SENSE
AR22 AT22
VCC_AXG_SENSE 41 VSS_AXG_SENSE 41
D
C79 1U_0603_10V4Z
C80 1U_0603_10V4Z
C81 2.2U_0603_6.3V4Z
to power
CPU VIDS
2 0_0402_5%
H_DPRSLPVR 40 to power
IC,AUB_CFD_rPGA,R1P0 CONN@
VTT_SELECT
G15
VTT_SELECT 38
C1357 10U_0805_10V4Z
C83 4.7U_0603_6.3V6K
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100
C48 10U_0805_6.3V6M
C49 10U_0805_6.3V6M
C50 10U_0805_6.3V6M
C51 10U_0805_6.3V6M
C52 10U_0805_6.3V6M
GRAPHICS VIDs
GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] GFX_VR_EN GFX_DPRSLPVR GFX_IMON
AM22 AP22 AN22 AP23 AM23 AP24 AN24 AR25 AT25 AM24
41 41 41 41 41 41 41
C991 22U_0805_6.3V6M
C993 22U_0805_6.3V6M
GRAPHICS
R43 1 2 249_0402_1% GFXVR_EN GFXVR_EN 41 GFXVR_DPRSLPVR GFXVR_DPRSLPVR 41 2 @ R128 2 @ R1176 1 10K_0402_5% GFXVR_IMON 1 1K_0402_5% GFXVR_IMON 41
2 @
2 @
+VCCP 1 +
C56 1U_0603_10V4Z
C57 1U_0603_10V4Z
C58 1U_0603_10V4Z
C59 1U_0603_10V4Z
- 1.5V RAILS
+ 2
C61 10U_0805_6.3V6M
C62 10U_0805_6.3V6M
C63 22U_0805_6.3V6M
POWER
3A
+1.5VS_CPU C65 22U_0805_6.3V6M C327 47P_0402_50V8J C328 47P_0402_50V8J C329 47P_0402_50V8J C330 47P_0402_50V8J Rev 1.0 Sheet
1
1 + 2
C64 220U_D2_2VY_R15M
C66 22U_0805_6.3V6M
C60 1U_0603_10V4Z
C995 330U_D2_2VY_R9M
+VCCP +VCCP VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 C67 10U_0805_6.3V6M C68 10U_0805_6.3V6M C69 22U_0805_6.3V6M C70 22U_0805_6.3V6M J24 J23 H25 VTT1_45 VTT1_46 VTT1_47
DDR3
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18
FDI
1.1V
C74 10U_0805_6.3V6M
C73 22U_0805_6.3V6M
C75 10U_0805_6.3V6M
C76 22U_0805_6.3V6M
C77 22U_0805_6.3V6M
to power PSI# AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR_R R58 H_PSI# 40 H_VID[0..6] 40
POWER
0.6A
1.8V
C78 22U_0805_6.3V6M
C82 10U_0805_6.3V6M
SENSE LINES
R59 R60
1 1
2 2
0_0402_5% 0_0402_5%
VCCSENSE 40 VSSSENSE 40
C333 C334
1 1
2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
B15 A15
VSS_SENSE_VTT R203 1
Near Processor
2 0_0402_5%
VTT_SENSE 38
2N7002DW-7-F_SOT363-6
VCCSENSE VSSSENSE
http://mycomp.su/x/
IC,AUB_CFD_rPGA,R1P0 CONN@
5 4
RF request.
C71 10U_0805_6.3V6M C72 10U_0805_6.3V6M VTT0_59 VTT0_60 VTT0_61 VTT0_62 P10 N10 L10 K10 +VCCP
+VCCP 2 0_0603_5% 2 0_0603_5% 1 +VCCP K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 2
+VCCP
+1.8VS
CPU
ISENSE
AN35
C331 C332
1 1
2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
+1.5VS_CPU
R1183 330K_0402_5%
R1182 220_0402_5%
C1358 0.1U_0402_16V4Z
Near Processor
+VCC_CORE VCCSENSE VSSSENSE R61 R62 1 1 2 100_0402_1% 2 100_0402_1%
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 9 of 45
+VCC_CORE JCPU1H AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 JCPU1I C84 22U_0805_6.3V6M C85 22U_0805_6.3V6M C86 22U_0805_6.3V6M
CPU CORE
C87 22U_0805_6.3V6M C88 22U_0805_6.3V6M C89 10U_0805_6.3V6M C90 10U_0805_6.3V6M C91 10U_0805_6.3V6M C92 10U_0805_6.3V6M C93 10U_0805_6.3V6M C94 10U_0805_6.3V6M 1 1 1 1 1 1 1 1 1 1 1 C95 10U_0805_6.3V6M
VSS
K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9
VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233
Inside cavity
D
C96 10U_0805_6.3V6M
C97 10U_0805_6.3V6M
C98 10U_0805_6.3V6M
C99 22U_0805_6.3V6M
C100 22U_0805_6.3V6M
C101 10U_0805_6.3V6M
C102 10U_0805_6.3V6M
C103 10U_0805_6.3V6M
C104 10U_0805_6.3V6M
C105 10U_0805_6.3V6M
C106 22U_0805_6.3V6M
C108 330U_D2_2VM_R9M
C109 330U_D2_2VM_R9M
1 + 2
1 + 2
1 + 2
C110 330U_D2_2VM_R9M
C114 22U_0805_6.3V6M
C115 22U_0805_6.3V6M
C116 22U_0805_6.3V6M
C117 10U_0805_6.3V6M
C118 10U_0805_6.3V6M
C119 22U_0805_6.3V6M
C120 10U_0805_6.3V6M
47P_0402_50V8J
C121 22U_0805_6.3V6M
1 + 2
C982
VSS
C
+VCC_CORE C314 47P_0402_50V8J C315 47P_0402_50V8J C316 47P_0402_50V8J C317 47P_0402_50V8J VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 VSS_NCTF1_R VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R
NCTF
RF request.
IC,AUB_CFD_rPGA,R1P0 CONN@
IC,AUB_CFD_rPGA,R1P0 CONN@
2009/05/11
Title
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 10 of 45
+RTCVCC
+3VS
R65 R66
1 1
2 1M_0402_5%
SM_INTRUDER#
R64
2 10K_0402_5%
SIRQ
2 330K_0402_5% PCH_INTVRMEN
@ R67
Y1 32.768KHZ_12.5PF_Q13MC14610002
C122 18P_0402_50V8J
OSC
OSC
C123 18P_0402_50V8J
2 1K_0402_5%
SB_SPKR
NC
NC
RTC
LPC
1 C125 1U_0603_10V4Z
27 27 27 27
1 1 1 1 27
2 2 2 2
1 R1163 1 R78
IHDA
1 1
2 22P_0402_50V8J 2 22P_0402_50V8J
HDA_BITCLK_CODEC HDA_SDOUT_CODEC R81 R82 @ R670 1 2 33_0402_5% 2 33_0402_5% 2 100K_0402_5% PAD HDA_SDOUT ME_EN# T16
27 HDA_SDOUT_MDC 27 HDA_SDOUT_CODEC
1 1
AH3 AH1 AF3 AF1 AD9 AD8 AD6 AD5 AD3 AD1 AB3 AB1 AF16 AF15
SATA
SATA_TXN4_C SATA_TXP4_C
M3 K3 K1 J2 J4
SATA_TXN5_C SATA_TXP5_C
JTAG
SATAICOMPO SATAICOMPI
R89
SPI_CLK_PCH SPI_SB_CS#
SPI_CLK_PCH SPI_SB_CS#
R654 1
2 15_0402_5%
SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISO SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19 T3 Y9 V1 PCH_GPIO21 PCH_GPIO19 R91 1 2 10K_0402_1% +3VS SATA_LED# 32
1 1
2 10K_0402_5% 2 10K_0402_5%
SPI_SB_CS# SPI_SO_R
30
30 30
SPI_SI SPI_SO_R
SPI_SI SPI_SO_R
R655 1
2 15_0402_5%
AY1 AV1
SPI
+3VS 1
HDA_SDO HDA_SYNC
This signal has a weak internal pull down. H=>On Die PLL is supplied by 1.5V L=>On Die PLL is supplied by 1.8V This signal has a weak internal pull down. This signal can't PU
1 R90
PCH_JTAG_TCK 2 51_0402_5%
RefDes ES1 R86 No Install No Install 200ohm 100ohm 200ohm 100ohm 51ohm 20Kohm 10Kohm ES2 200ohm 100ohm 200ohm 100ohm 200ohm 100ohm 51ohm 20Kohm 10Kohm No Install No Install No Install No Install No Install No Install No Install No Install 20Kohm 10Kohm 51ohm No Install No Install 51ohm
A
Enable iTPM=Stuff
PCH_JTAG_TDO
HDA_DOCK_EN#
ME debug mode , this signal has a weak internal PU
+RTCVCC
+3VL
BATT1.1
R684 R84 CR2032 RTC BATTERY PCH_JTAG_TMS R683 R85 PCH_JTAG_TDI R685 PCH_JTAG_TCK PCH_JTAG_RST# R88 R90 R87
31
2 G 3 S
JBATT1
W=20mils
1 2 3 4
SPI_MOSI
This signal has a weak internal pull down.
Enable iTPM=Stuff
+3VS
PCH_GPIO21 PCH_GPIO19
R92 R93
2 2
1 10K_0402_5% 1 10K_0402_5%
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
http://mycomp.su/x/
SI
Reserve GPIO19
@ C54
U1A ICH_RTCX1 ICH_RTCX2 ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN B13 D13 C14 D17 A16 A14 RTCX1 RTCX2 RTCRST# FWH4 / LFRAME# SRTCRST# INTRUDER# INTVRMEN LDRQ0# LDRQ1# / GPIO23 SERIRQ FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 D33 B33 C32 A32 C34 A34 F34 AB9 LDRQ0# LDRQ1# SIRQ T13 T14 PAD PAD SIRQ 31 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 24,31 24,31 24,31 24,31 24,31
LPC_FRAME#
HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0 HDA_SDIN1 SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA0RXN SATA0RXP SATA0TXN SATA0TXP
AK7 AK6 AK11 AK9 AH6 AH5 AH9 AH8 AF11 AF9 AF7 AF6
SATA_TXN0_C SATA_TXP0_C
C126 C127
1 1
2 0.01U_0402_50V7K 2 0.01U_0402_50V7K
HDD
SATA_TXN1_C SATA_TXP1_C
C130 C131
1 1
2 0.01U_0402_50V7K 2 0.01U_0402_50V7K
ODD
C128 C129
1 1
2 0.01U_0402_50V7K 2 0.01U_0402_50V7K
C296 C297
1 1
2 0.01U_0402_50V7K 2 0.01U_0402_50V7K
2 37.4_0402_1%
+1.05VS
+3VALW
+3VALW
+3VALW
+3VALW
R684 @ 100_0402_1%
R683 @ 100_0402_1%
R88 @ 10K_0402_5%
1 1 1 1 1
+3VALW +3VS +3VS +3VS R105 2.2K_0402_5% Q1A SMBDATA Q1B SMBCLK 3 5 6 2 R106 2.2K_0402_5%
D
SML1CLK SML1DATA
SMB_DATA_S3
SMB_DATA_S3
17,18,19,23
SMB_CLK_S3
U1B 24 24 24 24 24 24 24 24 25 25 25 25 24 24 24 24 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 PCIE_RXN1 PCIE_RXP1 PCIE_C_TXN1 PCIE_C_TXP1 PCIE_RXN2 PCIE_RXP2 PCIE_C_TXN2 PCIE_C_TXP2 PCIE_RXN3 PCIE_RXP3 GLAN_C_TXN GLAN_C_TXP PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4 BG30 BJ30 BF29 BH29 AW30 BA30 BC30 BD30 AU30 AT30 AU32 AV32 BA32 BB32 BD32 BE32 BF33 BH33 BG32 BJ32 +3VS +3VALW +3VS +3VALW R677 1 R405 1 R411 1 R415 1 2 2 2 2 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% CLKREQ_LAN# CLKREQ_WWAN#_R CLKREQ_WLAN# CLKREQ_EXP#_R BA34 AW34 BC34 BD34 AT34 AU34 AU36 AV36 BG34 BJ34 BG36 BJ36 CLK_PCIE_WWAN#_R CLK_PCIE_WWAN_R AK48 AK47 P9 AM43 AM45 U4 R111 1 R112 1 2 0_0402_5% 2 0_0402_5% CLK_PCIE_LAN#_R CLK_PCIE_LAN_R CLKREQ_LAN# R114 1 R115 1 R83 1 2 0_0402_5% 2 0_0402_5% CLK_PCIE_EXP#_R CLK_PCIE_EXP_R AM47 AM48 N4 AH42 AH41 A8 AM51 AM53 +3VALW R503 1 2 10K_0402_5% PCIECLKREQ4# M9 AJ50 AJ52 H6 AK53 AK51 P13 PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 SMBALERT# / GPIO11 SMBCLK SMBDATA SML0ALERT# / GPIO60 SML0CLK B9 H14 C8 J14 C6 G8 M14 E10 G12 T13 T11 T9 EC_LID_OUT# SMBCLK SMBDATA SML0ALERT# EC_LID_OUT# SMBCLK 24 SMBDATA 24 31
2N7002DW-7-F_SOT363-6
WLAN
C135 1 C136 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
SML0CLK SML0DATA SML1ALERT# SML1CLK R215 0_0402_5% 0_0402_5% SMB_EC_CK2 SMB_EC_DA2 31 31 @ 2 1 C326 12P_0402_50V8J 1
SMBus
LAN+Cardreader
C137 1 C138 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
New Card
C139 1 C140 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
SML1DATA R231
PCI-E*
Controller
Link
PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE0N CLKOUT_PCIE0P
H1 AD43 AD45 AN4 AN2 AT1 AT3 AW24 BA24 AP3 AP1 F18 E18 AH13 AH12 P41 J42 AH51 AH53 AF38 T45 P43 T42 N50
PEG_CLKREQ# R102 1
2 10K_0402_5%
PEG
CLKOUT_DMI_N CLKOUT_DMI_P
OK
OK
WWAN
2 0_0402_5% 2 0_0402_5%
CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKIN_DMI_N CLKIN_DMI_P CLKIN_BCLK_N CLKIN_BCLK_P CLKIN_DOT_96N CLKIN_DOT_96P CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P REFCLK14IN CLKIN_PCILOOPBACK XTAL25_IN XTAL25_OUT XCLK_RCOMP CLKOUTFLEX0 / GPIO64
PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56
CLK_DMI# 19 CLK_DMI 19 CLK_BUF_BCLK# 19 CLK_BUF_BCLK 19 CLK_BUF_DOT96# 19 CLK_BUF_DOT96 19 CLK_BUF_CKSSCD# CLK_BUF_CKSSCD CLK_14M_PCH CLK_PCI_FB XTAL25_IN XTAL25_OUT R116 1 2 90.9_0402_1% 19 14
OK OK
XTAL25_IN
OK
WLAN
R109 1 R110 1
OK OK OK OK
19 19
2 100_0402_5% CLKREQ_EXP#_R
+1.05VS
T59 T60
Clock Flex
PCIECLKREQ5#
T61 T62
PEG_B_CLKRQ#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
http://mycomp.su/x/
WWAN
C133 1 C134 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
WLAN
WWAN
New card
PCH
SMBCLK
@ R501 2.2_0402_5%~D
RF request.
XTAL25_OUT
R113 1
2 1M_0402_5%
B
Y2 1 2
1019_Stuff R113, Y2, C141 and change C142 from 0 ohm to 18pF.
2009/05/11
Title
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
2N7002DW-7-F_SOT363-6
SMB_CLK_S3
17,18,19,23
R770 1 U1C 7 7 7 7 7 7 7 7
D
ENBKL
EDID_CLK and EDID_DATA single end and keep 30 mil with other LVDS signal avoid noise
U1D T48 T47 Y48 L_BKLTEN L_VDD_EN L_BKLTCTL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 SDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P T51 T53 SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP BJ46 BG46 BJ48 BG48 BF45 BH45
100K_0402_5% FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT FDI_FSYNC0 FDI_FSYNC1 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 BJ14 BF13 BH13 BJ12 BG14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_INT 7 7 7 7 7 21 21 21 LVDS_A0+ LVDS_A1+ LVDS_A2+ 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 31 ENBKL 21 I_ENAVDD 21,31 LVDS_INV_PWM R890 2 21 LVDS_EDID_CLK 21 LVDS_EDID_DATA +3VS R773 1 PAD 1 1 R771 R772 ENBKL I_ENAVDD 1 0_0402_5% DPST_PWM
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
BC24 BJ22 AW20 BJ20 BD24 BG22 BA20 BG20 BE22 BF21 BD20 BE18 BD22 BH21 BC20 BD18 BH25
DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP DMI_ZCOMP DMI_IRCOMP
LVDS_EDID_CLK AB48 LVDS_EDID_DATA Y45 2 AB46 2 10K_0402_5% V48 10K_0402_5% 2 2.37K_0402_1% AP39 AP41 T69 AT43 AT42 LVDS_ACLKLVDS_ACLK+ LVDS_A0LVDS_A1LVDS_A2LVDS_A0+ LVDS_A1+ LVDS_A2+ AV53 AV51 BB47 BA52 AY48 AV47 BB48 BA50 AY49 AV48 AP48 AP47
SDVO
7 7 7 7 7 7 7 7 +1.05VS
Display Port B
LVDS
BG44 BJ44 AU38 BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 Y49 AB49
DMI
FDI
R118 1
2 49.9_0402_1%
DMI_IRCOMP
BF25
FDI_LSYNC0 FDI_LSYNC1
R120 2
PM_PWROK
31
M_PWROK
31 PWRBTN_OUT# 31
R125 1
P5 P7 A6 F14
K8 N2 BJ10 F6
AD48 AB51
DAC_IREF CRT_IRTN
EC_ACIN
H_PM_SYNC
6 2
31 SUS_PWR_ACK
SUS_PWR_ACK
M_BLUE M_GREEN
@ R133 R129
1 1
2 10K_0402_5% 2 8.2K_0402_5%
M_RED
PM_CLKRUN#
CRT
http://mycomp.su/x/
5
Display Port C
J12 Y1
ICH_PCIE_WAKE# PM_CLKRUN#
ICH_PCIE_WAKE#
24,25
BE44 BD44 AV40 BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 U50 U52 BC46 BD46 AT38 BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36 HDMID_CTRLCLK HDMID_CTRLDATA
P8 F3 E4 H7 P12
PM_SUS_STAT# SUS_CLK
T17 T18 SLP_S5# 31 SLP_S4# 31 SLP_S3# 31 20 20 CRT_HSYNC CRT_VSYNC 20 I_DDCCLK 20 I_DDCDATA CRT_HSYNC CRT_VSYNC 1 R774 1 R775 2 2 0_0402_5% HSYNC VSYNC 0_0402_5% V51 V53 Y53 Y51 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC 20 20 20 M_BLUE M_GREEN M_RED M_BLUE M_GREEN M_RED AA52 AB53 AD53
HDMID_CTRLCLK 22 HDMID_CTRLDATA 22
Display Port D
TMDS_B_HPD#
TMDS_B_HPD#
22
SUS_PWR_DN_ACK / GPIO30
Place the 3 resistors close to IBEX +3VALW R134 R136 R137 R138 1 1 1 2 2 8.2K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 1 8.2K_0402_5%
Check PM_SLP_LAN#
R1215 1 0_0402_5% 2 +RTCVCC
+RTCVCC
1K_0402_5%
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
+3VS RP3 PCI_DEVSEL# PCI_SERR# PCI_REQ0# PCI_PIRQB# 1 2 3 4 8 7 6 5 8.2K_0804_8P4R_5% RP4 PCI_REQ1# PCI_FRAME# PCI_TRDY# PCI_PIRQH#
D
U1E H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 J50 G42 H47 G34 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3# PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# G38 H51 B37 A44 F51 A46 B45 M53 F48 K45 F36 H53 B41 K53 A36 A48 K6 PCI_SERR# PCI_PERR# PCI_IRDY# E44 E50 A42 H44 F46 C46 D49 D41 C48 M7 PLT_RST# R_CLK_PCI_FB R_CLK_PCI_EC R_CLK_DEBUG_PORT_1 D5 N52 P53 P46 P51 P48 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# PIRQA# PIRQB# PIRQC# PIRQD# REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PCIRST# SERR# PERR# IRDY# PAR DEVSEL# FRAME# PLOCK# USBRBIAS# STOP# TRDY# PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 BD82HM55 QMNT B3_FCBGA1071 R_CLK_PCI_FB R_CLK_PCI_EC R_CLK_DEBUG_PORT_1 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 USBRBIAS NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 NV_DQS0 NV_DQS1 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 NV_ALE NV_CLE NV_RCOMP AY9 BD1 AP15 BD8 AV9 BG8 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 BD3 AY6 AU2 AV7 AY8 AY5 AV11 BF5 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 B25 D25 N16 J16 F16 L16 E14 G16 F12 T15
GPIO8
U1F +3VS R140 1 2 1K_0402_1% PCH_GPIO0 PCH_GPIO1 Y3 C38 D37 J32 F10 K9 T7 AA2 F38 Y7 H10 AB12 V13 M11 V6 AB7 AB13 V3 P3 H3 F1 AB6 AA4 F8 BMBUSY# / GPIO0 TACH1 / GPIO1 TACH2 / GPIO6 TACH3 / GPIO7 GPIO8 LAN_PHY_PWR_CTRL / GPIO12 GPIO15 SATA4GP / GPIO16 TACH0 / GPIO17 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM3 AM1 BG10 T1 BE10 BD10 H_THERMTRIP#_L PCH_PECI_R KB_RST# CLK_CPU_BCLK# CLK_CPU_BCLK R144 1 KB_RST# 31 H_CPUPWRGD 1 R146 6 H_THERMTRIP# 6 6 2 0_0402_5% H_PECI 6 6 A20GATE U2 GATEA20 GATEA20 31
D
CLKOUT_PCIE6N CLKOUT_PCIE6P
AH45 AH46
T19 T20
PAD PAD
8.2K_0804_8P4R_5% RP5 PCI_REQ3# PCI_PIRQF# PCI_PERR# PCI_LOCK# 1 2 3 4 8 7 6 5 8.2K_0804_8P4R_5% +3VS RP6 PCI_PIRQA# PCI_PIRQD# PCI_PIRQG# PCI_PIRQC# 1 2 3 4 8 7 6 5 8.2K_0804_8P4R_5% RP7 PCI_PIRQE# PCI_STOP# PCI_IRDY# PCI_REQ2# 1 2 3 4 8 7 6 5 8.2K_0804_8P4R_5%
NVRAM
24
XMIT_OFF
XMIT_OFF
GPIO
Check list Rev0.8 section1.23.2 If not implemented, the Braidwood interface signals can be left as No Connect (NC).
NV_ALE NV_CLE +3VS R145 1
CPU
1 R147 56_0402_5% 2
PCI
NV_RB# NV_WR#0_RE# NV_WR#1_RE# NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P
On-Die PLL Voltage Regulator This signal has a weak internal pull up
*
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5
H L
T70 PAD
NCTF
RSVD
23
ACCEL_INT
ACCEL_INT 31 31
USB
PCI_SERR#
Low=Configures DMI for ESI compatible operation(for servers only.Not for mobile/desktops)
USBRBIAS
12 31
CLK_PCI_FB CLK_PCI_EC
PCI_GNT0# PCI_GNT1#
@ R163 1 @ R164 1
2 1K_0402_5% 2 1K_0402_5%
24 CLK_DEBUG_PORT_1
NV_ALE
@ R174 1
2 1K_0402_5%
0 1 1
1 0 1
R179 1
DMI Termination Voltage Set to Vcc when HIGH NV_CLE Set to Vss when LOW
Weak internal PU,Do not pull low
NV_CLE @ R184 1 +3VS
4 3 2 1
5 6 7 8
2 0_0402_5% +3VS
2 1K_0402_5%
A
IN1 IN2
1 2
A16 swap overide Strap/Top-Block Swap Override jumper Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default *
5
PLT_RST#
@ R185 100K_0402_5% 2
SN74AHC1G08DCKR_SC70-5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
http://mycomp.su/x/
1 2 3 4
8 7 6 5
CR_WAKE#
SCLOCK / GPIO22
MISC
CLKOUT_PCIE7N CLKOUT_PCIE7P
AF48 AF47
T21 T22
PAD PAD
2 54.9_0402_1%
SATACLKREQ# / GPIO35 SATA2GP / GPIO36 SATA3GP / GPIO37 SLOAD / GPIO38 SDATAOUT0 / GPIO39 PCIECLKRQ6# / GPIO45 PCIECLKRQ7# / GPIO46 SDATAOUT1 / GPIO48 SATA5GP / GPIO49 GPIO57 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 BA22 AW22 BB22 AY45 AY46 AV43 AV45 AF13 M18 N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39 P6 C10 EC_SCI# PCH_GPIO1 KB_RST# PCH_GPIO36 PCH_GPIO6 VGA_PRSNT_L# PCH_GPIO16 WWAN_DETECT# GATEA20
GPIO27
24 WWAN_DETECT# 32 HDDHALT_LED#
VGA_PRSNT_L# WWAN_DETECT# HDDHALT_LED# PCIECLKREQ6# USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 29 29 29 29 29 29 26 26 21 21 24 24
+VCCP
+3VS
6 PCH_DDR_RST
PCH_DDR_RST PCHGPIO48
2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5%
C
31 PCH_TEMP_ALERT#
PCH_TEMP_ALERT# PCH_GPIO57
EHCI 1
A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31
TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5 INIT3_3V# TP24
PCH_TEMP_ALERT# R181 1 HDDHALT_LED# PCHGPIO48 CR_WAKE# PCH_GPIO17 R169 1 R170 1 R168 1 R874 1
R155 1
2 22.6_0402_1%
INIT3_3V
WXMIT_OFF#
RF request.
Close PCH
T48
PAD
+3VALW
EC_SMI# PCH_GPIO15
*
+1.8VS
PCH_GPIO12
2009/05/11
Title
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
+VCCP_VCCA_CLK +1.05VS AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 C144 1U_0402_6.3V6K C143 10U_0805_6.3V6M U1G C146 10U_0603_6.3V6M
POWER
VCCADAC[1] C147 0.01U_0402_25V7K C148 10U_0805_6.3V6M AE50 AE52 AF53 AF51 2 1
U1J AP51 AP53 AF23 AF24 VCCACLK[1] VCCACLK[2] VCCLAN[1] VCCLAN[2] DCPSUSBYP VCCME[1]
+1.05VS VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] C150 1U_0402_6.3V6K V24 V26 Y24 Y26 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 U23
C145 1U_0402_6.3V6K
POWER
0.052A
VCC CORE
0.344A
2 C152 Y20 0.1U_0402_16V4Z +1.05VS AD38 AD39 C153 1U_0402_6.3V6K 1 AD41 AF43 AF41 AF42 V39 V41
VCCME[2] VCCME[3] VCCME[4] VCCME[5] VCCME[6] VCCME[7] VCCME[8] VCCME[9] VCCME[10] VCCME[11] VCCME[12]
C159 10U_0805_6.3V6M
1.998A
C162 10U_0805_6.3V6M
C163 10U_0805_6.3V6M
C161 1U_0402_6.3V6K
VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] 0.163A VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27] VCCSUS3_3[28] VCCIO[56]
VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] 1.524A VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15]
0.069A
C149 0.1U_0402_16V4Z
CRT
+3VS
0.030A
VCCALVDS VSSA_LVDS
AH38 AH39 R779 1 2 0_0603_5% AP43 AP45 AT46 AT45 +1.8VS 0.01U_0603_16V7K 0.01U_0603_16V7K 10U_0805_6.3V6M
+1.05VS +3VALW +1.05VS_APLL @ R188 1 0_0603_5% 1 2 BJ24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 AN30 AN31 AN35 AT22 BJ18 AM23 AK24 VCCIO[24]
0.059A
USB
C157 0.1U_0402_16V4Z
C158 0.1U_0402_16V4Z
LVDS
C998
C999
C1000
0.042A VCCAPLLEXP
VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53] VCCIO[54] VCCIO[55] VCC3_3[1] VCCVRM[1] VCCFDIPLL VCCIO[1]
HVCMOS
VCC3_3[4]
+1.05VS
+1.8VS
C164 1U_0402_6.3V6K
V23 F24
C165 1U_0402_6.3V6K
+1.05VS ICH_V5REF_SUS
VCCVRM[2]
AT24
C
DMI
>1mA
V5REF_SUS
C166 1
VCCDMI[2]
PCI/GPIO/LPC
+1.8VS
AU24 BB51 BB53 BD51 BD53 AH23 AJ35 AH35 AF34 AH34 AF32
VCCVRM[3]
PCI E*
0.035A 0.072A
VCCADPLLA[1] VCCADPLLA[2]
>1mA
V5REF
C168 1U_0402_6.3V6K
C169 1U_0402_6.3V6K
VCC3_3[8] VCC3_3[9]
C170 10U_0603_6.3V6M
2 VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9] AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
0.073A
VCCADPLLB[1] VCCADPLLB[2] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[2] VCCIO[3]
C167 1U_0402_6.3V6K
+VCCRTCEXT 2 0.1U_0402_16V4Z
V9
DCPRTC
0.061A
VCCDMI[1]
AT16 AU16
+VCCP
C172 0.1U_0402_16V4Z
0.357A
VCC3_3[10]
R671 @ R672
1 1
2 0_0402_5% 2 0_0402_5%
0.156A
+1.8VS +3VS
NAND / SPI
C173 1U_0402_6.3V6K
C174 1U_0402_6.3V6K
C175 1U_0402_6.3V6K
3.208A
VCC3_3[14]
+3VS C176 1 2 0.1U_0402_16V4Z +1.05VS @ R189 1 2 0_0603_5% +1.05VS C682 1 2 0.1U_0402_16V4Z +1.8VS +1.05VS_VCCFDIPLL
0.035A 6mA
1 C177 1
B
C180 1U_0402_6.3V6K
2 0.1U_0402_16V4Z
+VCCSST
V12
DCPSST
0.032A
FDI
VCCSATAPLL[1] VCCSATAPLL[2]
0.085A
1 Y22 DCPSUS VCCIO[9] P18 U19 VCCSUS3_3[29] VCCVRM[4] AH22 2 AT20 AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22 AD22 AA34 Y34 Y35 AA35 L30 +PCH_VCC1_1_20 +PCH_VCC1_1_21 +PCH_VCC1_1_22 +PCH_VCC1_1_23 1 C184 1U_0402_6.3V6K +1.8VS
C181 10U_0805_6.3V6M
C179
2 @
C178 0.1U_0402_16V4Z
C182 +3VS
U20 U22
VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCME[13] VCCME[14] VCCME[15] VCCME[16]
VCCSUS3_3[31] VCCSUS3_3[32]
2 +1.05VS R191 1 2 0_0603_5% +1.05VS_L +V1.05S_VCCA_A_DPL_L R192 L6 1 2 1 2 0_0603_5% 10UH_LB2012T100MR_20%_0805 @ 1 R194 R195 R198 R200 1 1 1 1 2 2 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
1 C185
C187 1U_0402_6.3V6K
2 +1.05VS
C186 220U_B_2.5VM_R15M
2 0.1U_0402_16V4Z +VCCP
AT18 AU18
C189 0.1U_0402_16V4Z
C188 4.7U_0603_6.3V6K
C190 0.1U_0402_16V4Z
CPU
V_CPU_IO[1] V_CPU_IO[2]
RTC
HDA
VCCRTC
VCCSUSHDA
1 C193 1U_0402_6.3V6K 1 @ 2
C191 220U_B_2.5VM_R15M
+RTCVCC
A12
2mA
6mA
+3.3A_1.5A_VCCPAZSUS
C192 1U_0402_6.3V6K
R196 100_0402_5% 2 1
D4 RB751V_SOD323
R197 100_0402_5% 2 1
D5 RB751V_SOD323 ICH_V5REF_RUN
+V1.05S_VCCA_B_DPL 1 + 2
ICH_V5REF_SUS
+3VALW
20 mils
1 C194 1U_0402_6.3V6K 1
C183 10U_0805_6.3V6M
2 0.1U_0402_16V4Z
PCI/GPIO/LPC
VCCSUS3_3[30]
SATA
C196 0.1U_0402_16V4Z
C197 0.1U_0402_16V4Z
Close PCH
http://mycomp.su/x/
VCCIO[4]
+1.05VS
+1.05VS
@ R190 1 2 0_0603_5%
+1.05VS_VCCFDIPLL
20 mils
C195 1U_0402_6.3V6K
A
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
U1I AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42 VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366] H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14 AB16 AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28
U1H VSS[0] VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] BD82HM55 QMNT B3_FCBGA1071 VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
http://mycomp.su/x/
+VREF_DQ_DIMMA
+1.5V
+1.5V
JDIMM1 +VREF_DQ_DIMMA C1057 0.1U_0402_10V6K C1058 C1058 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z DDR_A_D0 DDR_A_D1 DDR_A_DM0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
CONN@ VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 DRAMRST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 1 @ C1441 0.1U_0402_16V4Z
R884 1
V_DDR_CPU_REF 0_0402_5%
+V_DDR_CPU_REF0
R205 1K_0402_1% 2 1
2
D
DRAMRST#
6,18
+1.5V
C
8 DDR_CKE0_DIMMA 8 DDR_A_BS2
C214 2.2U_0402_6.3V6M
C213 0.1U_0402_16V4Z
C215 1U_0402_6.3V6K
C216 1U_0402_6.3V6K
C217 1U_0402_6.3V6K
C218 1U_0402_6.3V6K
DDR_A_DQS#4 DDR_A_DQS4
B
DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3 +0.75VS
C202 10U_0805_6.3V6M
DDR_A_D32 DDR_A_D33
DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 1 R207 2 10K_0402_5% +3VS C219 2.2U_0402_6.3V6M
A
C220 0.1U_0402_16V4Z
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205
R208 10K_0402_5%
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G2
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206
DDR_CKE1_DIMMA
8 C44 47P_0402_50V8J C45 47P_0402_50V8J C201 10U_0603_6.3V6M C203 10U_0603_6.3V6M C204 10U_0603_6.3V6M C205 10U_0603_6.3V6M C206 10U_0603_6.3V6M C207 10U_0603_6.3V6M C208 10U_0603_6.3V6M C209 0.1U_0402_16V4Z C210 0.1U_0402_16V4Z C211 0.1U_0402_16V4Z C212 0.1U_0402_16V4Z 1 + C200 330U_D2_2V_Y 2
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_ODT1 +VREF_CA DDR_A_D36 DDR_A_D37 1 1 M_CLK_DDR1 8 M_CLK_DDR#1 8 DDR_A_BS1 8 DDR_A_RAS# 8 DDR_CS0_DIMMA# M_ODT0 8 M_ODT1 8 8
+0.75VS
http://mycomp.su/x/
V57.0@A56.0
V5.1@A3
+VREF_CA PM_EXTTS#1_R 6,18 SMB_DATA_S3 12,18,19,23 SMB_CLK_S3 12,18,19,23
+1.5V
R206 1K_0402_1%
2 @
2 @
2009/05/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1
+1.5V
+1.5V
+VREF_DQ_DIMMB JDIMM2 +VREF_DQ_DIMMB C221 2.2U_0402_6.3V6M C1059 0.1U_0402_10V6K DDR_B_D0 DDR_B_D1 DDR_B_DM0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR_B_DM1 DRAMRST# DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31 1 @ C1442 0.1U_0402_16V4Z
2
D
8 DDR_CKE2_DIMMB 8 DDR_B_BS2
C46 47P_0402_50V8J
C47 47P_0402_50V8J
C223 10U_0603_6.3V6M
C224 10U_0603_6.3V6M
C225 10U_0603_6.3V6M
C226 10U_0603_6.3V6M
C227 10U_0603_6.3V6M
C228 10U_0603_6.3V6M
C229 10U_0603_6.3V6M
C230 10U_0603_6.3V6M
C231 0.1U_0402_16V4Z
C232 0.1U_0402_16V4Z
C233 0.1U_0402_16V4Z
2 @
+VREF_CA
C235 0.1U_0402_16V4Z
DDR_B_DQS#4 DDR_B_DQS4
B
C1060 2.2U_0603_6.3V4Z
DDR_B_D32 DDR_B_D33
DDR_B_D36 DDR_B_D37
DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 1 R210 2 10K_0402_5% +3VS C241 2.2U_0402_6.3V6M
A
+0.75VS
C237 1U_0402_6.3V6K
C238 1U_0402_6.3V6K
C239 1U_0402_6.3V6K
DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3 PM_EXTTS#1_R 6,17 SMB_DATA_S3 12,17,19,23 SMB_CLK_S3 12,17,19,23 +0.75VS
C242 0.1U_0402_16V4Z
R211 1 2 10K_0402_5%
C240 1U_0402_6.3V6K
DDR_B_DQS#5 DDR_B_DQS5
C234 0.1U_0402_16V4Z
G1 +0.75VS CONN@
G2
http://mycomp.su/x/
V57.0@A56.0
8 DDR_B_DQS[0..7] 8 DDR_B_MA[0..15]
R885 1 @ R899 1
2 0_0402_5% 2 0_0402_5%
DRAMRST#
6,17
+1.5V
2009/05/11
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 1.0 18 of 45
Sheet
80mA
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CLK_14M_PCH @ C808 1
2 10P_0402_50V8J
250mA OK
D
DOT96
12 CLK_BUF_DOT96 12 CLK_BUF_DOT96#
CLK_BUF_DOT96 CLK_BUF_DOT96#
R213 2 R214 2
1 1
NC
CLK_DMI CLK_DMI# CLK_BUF_CKSSCD CLK_BUF_CKSSCD# R221 1 R223 1 R219 1 R220 1 2 2 2 2 33_0402_5% L_CLK_DMI 33_0402_5% L_CLK_DMI# 33_0402_5% L_CLK_BUF_CKSSCD 33_0402_5% L_CLK_BUF_CKSSCD# CPU_STOP#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDD_DOT VSS_DOT DOT_96 DOT_96# 96MHz VDD_27 27MHZ 27MHZ_SS VSS_27 VSS_SATA SRC_1/SATA SRC_1#/SATA#100MHz VSS_SRC SRC_2 SRC_2# 100MHz VDD_SRC_IO CPU_STOP#
SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD# VDD_CPU CPU_0
CLK_14M_PCH 12
14M OK
D
VGATE
13,40
OK OK
CKSSCD
DMI12
12
CLK_DMI CLK_DMI#
133MHz CPU_0#
CLK_BUF_BCLK 12 CLK_BUF_BCLK# 12
BCLK OK
12 CLK_BUF_CKSSCD 12 CLK_BUF_CKSSCD#
TGND
Near pin5
Near pin29
33
ICS9LRS3197AKLFT MLF_QFN32_5X5
C245 10U_0805_10V4Z
C247 0.1U_0402_16V4Z
250mA
SLG8SP585 SLG8SP587 pin8 is GND (for DELL HP) pin8 is 48MHz (For ABO or 030)
Number 2 1 1 1 1 1 1
C259 22P_0402_50V8J 1 1 Y3 2 1 14.318MHZ_16PF_7A14300083 C260 22P_0402_50V8J CLK_XTAL_OUT CLK_XTAL_IN
Place close to U3
+1.05VS_CK505 R218 1 2 0_0805_5% 1
C
C252 10U_0805_10V4Z
C253 0.1U_0402_16V4Z
C254 0.1U_0402_16V4Z
CKPWRGD
PIN 30 0(default) 1
CPU_1 133MHz
CPU_STOP#
100MHz
R234 1
2 10K_0402_5%
+1.5VS_CK505
R228 0_0603_5% 1 2 1 2 C248 0.1U_0402_16V4Z C246 0.1U_0402_16V4Z @ R229 @R229 0_0603_5% C249 0.1U_0402_16V4Z
2
B
C250 0.1U_0402_16V4Z 1 2
SI
2006/03/10
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Near pin24
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 1.0 19 of 45
Sheet
+5VS D9
+RCRT_VCC F1 1
+CRTVDD
CRT Connector
26 26 26 26 +5VS C267 0.1U_0402_16V4Z 1 2 +5VS C268 0.1U_0402_16V4Z 1 2 R815 2 5 1 1 10K_0402_5% 26 RED GREEN D_HSYNC BLUE D_VSYNC RED GREEN BLUE
1 RB491D_SC59-3
W=40mils
1 0.1U_0402_16V4Z C266 JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
1.1A_6VDC_FUSE
DAN217T146_SC59-3
+3VS
16 17 +CRTVDD +3VS
P OE#
13
CRT_HSYNC
CRT_HSYNC
U5 SN74AHCT1G125GW_SOT353-5 HSYNC_G_A 4 5 1
R269 1
2 0_0603_5%
P OE#
R271 4.7K_0402_5% 2 2
R272 2.2K_0402_5% 2 2
R273 2.2K_0402_5%
13
CRT_VSYNC
CRT_VSYNC
VSYNC_G_A
R274 1
2 0_0603_5% 1
6 Q2A
1 5
I_DDCDATA
U6 SN74AHCT1G125GW_SOT353-5
I_DDCDATA 13
2N7002DW-7-F_SOT363-6 3 Q2B
I_DDCCLK
I_DDCCLK 13
2006/07/26
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Calpella_UMA_LA4106P
Thursday, November 12, 2009
E
Rev 1.0 20 of 45
Sheet
+3VS
+LCDVDD INVPWR_B+
6 2
C278 680P_0402_50V7K
C279 680P_0402_50V7K
C319 47P_0402_50V8J
C318 47P_0402_50V8J 2 1
RF request.
1
RF request.
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2
2 G
C281
R279 1M_0402_5%
1 C283 4.7U_0805_10V4Z
JLVDS1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ LVDS_ACLKLVDS_ACLK+ LVDS_A2LVDS_A2+ LVDS_A1LVDS_A1+ LVDS_A0LVDS_A0+ 13 13 13 13 13 13 2 C302 5P_0402_50V8C @ LVDS_ACLK- 13 LVDS_ACLK+ 13 C303 5P_0402_50V8C 13
RF request.
R280 2
1 C284 0.047U_0402_16V7K
100K_0402_5%
14 14
USB20_P4 USB20_N4
1 @ DMIC_DAT DMIC_CLK +3V_LOGO LVDS_INV_PWM BKOFF# DAC_BRIG R281 1 100_0805_5% DMIC_DAT 27 DMIC_CLK 27 +5VS LVDS_INV_PWM 13,31 BKOFF# 31 DAC_BRIG 31 LVDS_EDID_CLK 13 LVDS_EDID_DATA 13 LVDS_INV_PWM BKOFF# 1 1 C286 1 2 2 680P_0402_50V7K 2 @ R202 2.2_0402_5%~D 2
LVDS_EDID_CLK LVDS_EDID_DATA
+USB_CAM
ACES_88242-4001 CONN@
C294 680P_0402_50V7K
2 @ R282 10K_0402_5% 1
C321 12P_0402_50V8J
EMI request.
1 @
B+
INVPWR_B+
2 +3VS
IO2 GND
PRTR5V0U2X_SOT143-4
L12 1 2 FBMA-L11-201209-221LMA30T_0805
RF request.
B
RF request.
2 R285 2.2K_0402_5% 1
USB Camera
+5VS
+USB_CAM
2 3
C289 10U_0805_6.3V6M
C320 47P_0402_50V8J
G916-390T1UF_SOT23-5
2 2
2 R287 100K_0402_1%
+USB_CAM=1.25(1+R1091/R1093)
C981 47P_0402_50V8J
RF request.
U7 1 IN OUT 5
1 R286 215K_0603_1%
2006/07/26
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 1.0 21 of 45
Sheet
ST
R833
8171 X X
Asmedia 1442 X 0 ohm X X X 0 ohm X 0 ohm X X 0 ohm X 0 ohm 0 ohm X 0 ohm X 0 ohm X 0.1uF X X 4.7K ohm
C2 C4 C6 C7 C8 C9 C10 C11
1 1 1 1 1 1 1 1
TMDS_CLK TMDS_CLK# +3VS_LS TMDS_DATA0 TMDS_DATA0# TMDS_DATA1 TMDS_DATA1# TMDS_DATA2 TMDS_DATA2# +3VS_LS 1 TMDS_DATA0# TMDS_DATA0 TMDS_CLK# TMDS_CLK +3VS_LS +3VS_LS +3VS TMDS_DATA1 TMDS_DATA1# 1
0 ohm 4.7K ohm 4.7K ohm 4.7K ohm X X 2.2uF X 4.7K ohm 4.7K ohm X 4.7K ohm X X 4.7K ohm 4.7K ohm X X 4.7K ohm 1uF X X
1 C1050
1 C1051
TMDS_DATA2 TMDS_DATA2#
46
48
45
42
40
43
39
47
44
41
IN_D4-
IN_D3-
IN_D2-
IN_D4+
IN_D3+
IN_D2+
IN_D1+
VCC3V
VCC3V
IN_D1-
GND
GND
R850 C1052 R853 R855 R857 R858 R851 R854 R843 R844 R839 R834 R841 R835 C667
C
U47
38
37
@ R834 2 @ R835 2 GND 36 35 34 33 32 31 30 29 28 27 26 25 +3VS_LS HDMI_DETECT HDMIDAT HDMICLK @ R851 2 R854 1 R839 2 R841 2 R843 @ R844 R845 @ R846 2 2 2 2
1 4.7K_0402_5% +3VS_LS 1 4.7K_0402_5% +3VS_LS 1 0_0402_5% 1 0_0402_5% 1 1 1 1 0_0402_5% 0_0402_5% 4.7K_0402_5% 0_0402_5% +3VS_LS +3VS_LS
1 2 3 4
GND VCC3V FUNCTION1 FUCNTION2 GND ANALOG1(REXT) HPD_SOURCE SDA_SOURCE SCL_SOURCE ANALOG2 VCC3V OUT_D4+ OUT_D3+ OUT_D2+ OUT_D1+ GND thm_pad OUT_D4OUT_D3OUT_D2OUT_D1-
FUNCTION4
PC0 PC1
FUNCTION3 VCC3V DDC_EN GND HPD_SINK SDA_SINK SCL_SINK GND VCC3V OE* GND
R847 2.2K_0402_5% 2 2
5 6 7 8 9
10 11 12 49
R856 2
VCC3V
VCC3V
GND
R862 R867
1 HDMI_DETECT ASM1442 QFN 48P HDMI SHIFTER 2 G HDMI_TX_0+3VS_LS 1 @ R861 1 2 68_0402_5% @C1054 @C1054 HDMI_TX_0+ 0.5P_0402_50V8B @ R862 20K_0402_5% R865 2 1 @ R867 7.5K_0402_1% 2 2 13 TMDS_B_HPD# 0_0402_5% +5VS 22N_0402_16V7K +5VS_HDMI 3
@ R857 1 R858 1
2 4.7K_0402_5% 2 0_0402_5%
13
14
15
16
17
18
19
20
21
22
23
24
S Q31 2N7002_SOT23-3
HDMICLK+
HDMICLK+ HDMICLK-
@C1053 @C1053
+3VS_LS
+3VS_LS
0_0402_5% 2 0_0402_5% HDMI_R_TX0HDMI_R_TX0+ HDMI_TX_2+ HDMI_TX_2@ R863 @R863 1 2 68_0402_5% 0.5P_0402_50V8B HDMI_TX_1@ R864 @C1056 @C1056 HDMI_TX_1+ 1 2 68_0402_5% 0.5P_0402_50V8B
HDMI_TX_0HDMI_TX_0+
1 TMDS_B_HPD
HDMI_TX_1B
HDMI Connector
1 2 C665 @ 2
HDMI_TX_1+
HDMI_TX_2HDMI_TX_2+
0_0402_5%
JHDMI1 HDMIDAT L32 R579 FBML10160808121LMT_0603HDMICLK HDMI_HPD 1 2 1 2 1 10K_0402_1% R580 100K_0402_1% 2 C668 330P_0402_50V7K 1 HDMI_R_CLKHDMI_R_CLK+ HDMI_R_TX0HDMI_R_TX0+ HDMI_R_TX1HDMI_R_TX1+ HDMI_R_TX2HDMI_R_TX2+ 18 16 15 19 12 10 9 7 6 4 3 1 +5V SDA SCL HP_DET CKCK+ D0D0+ D1D1+ D2D2+ CEC Reserved 13 14 2 5 8 11 20 21 22 23 17
HDMI_DETECT 1
D35 SKS10-04AT_TSMA
A
SUYIN_100042MR019S153ZL CONN@
2006/03/10
Title
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 22 of 45
HDD Connector
JP3 GND A+ AGND BB+ GND V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SATA_TXP0 SATA_TXN0 SATA_RXN0 C466 2 SATA_RXP0 C467 2 1 0.01U_0402_50V7K 1 0.01U_0402_50V7K SATA_RXN0_C SATA_RXP0_C SATA_TXP0 11 SATA_TXN0 11 SATA_RXN0_C 11 SATA_RXP0_C 11
C469 10U_0805_6.3V6M
C468 0.1U_0402_16V4Z
ACCELEROMETER (ST)
+3VS PA@ D10 2 1 1 +3VS_ACL PA@ R364 2 0_0603_5% +3VS_ACL_IO PA@ 2 1
+3VS_ACL
PA@
+5VS +5VS 1
RB751V_SOD323
0.4mA
C462 10U_0805_10V4Z
SMB_CLK_S3
SMB_CLK_S3 12,17,18,19
SUYIN_127072FR022G523_RV CONN@
SCL / SPC
14
PA@ U15
0011101b
13 12 11 10 9 8
SMB_DATA_S3 12,17,18,19
0_0402_5%
C
0_0402_5%
C
CD-ROM Connector
JP5 GND A+ AGND BB+ GND DP V5 V5 MD GND GND 13 12 11 10 9 8 7 6 5 4 3 2 1
ACCEL_INT 14
SATA_TXP1 SATA_TXN1 SATA_RXN1 SATA_RXP1 OPP@ C473 2 C474 2 OPP@ 1 0.01U_0402_50V7K 1 0.01U_0402_50V7K SATA_RXN1_C SATA_RXP1_C
R368 2 PA@
1 10K_0402_5%
2 SUYIN_127382FR013GX09ZR CONN@
OPP@
OPP@
OPP@
OPP@
CS HP302DLTR8_LGA14_3x5
Multi Bay
+5VS +5VS JP12 2 4 6 8 10 12 14 16 18 20 VCC5 VCC5 VCC5 VCC3 VCC3 VCC3 GND GND GND G2 GND TX+ TXGND RXRX+ GND GND GND G1 1 3 5 7 9 11 13 15 17 19 SATA_TXP5 SATA_TXN5 PA@ SATA_RXN5 C255 2 SATA_RXP5 C256 2 PA@ SATA_TXP5 11 SATA_TXN5 11 1 1 SATA_RXN5_C SATA_RXP5_C SATA_RXN5_C 11 SATA_RXP5_C 11
PA@ 1 C263 2
PA@ 1 C264 2
PA@ C265
1 + 2
1 + 2
0.01U_0402_16V7K 0.01U_0402_16V7K
CONN@ TYCO_2023087-3
2006/03/10
Title
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 23 of 45
CW7 @
CW8
CW9
CW12
1 0.1U_0402_16V4Z CW13
ACES_88266-07001 CONN@
2 0.1U_0402_16V4Z
RF request.
RF request.
+3VS
RW2 1
0_0805_5%
+3VS_WLAN
RF request.
@ CW17 @ CW18
@ JP7 ICH_PCIE_WAKE# CLKREQ_WLAN# CLK_PCIE_WLAN# CLK_PCIE_WLAN PLT_RST# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 GND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 GND2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 +3VS_WLAN RW3 RW4 RW5 RW6 RW7 +1.5VS_WLAN 1 2 1 2 1 2 1 2 1 2 0_0402_5% DEBUG@ 0_0402_5% DEBUG@ 0_0402_5% DEBUG@ 0_0402_5% DEBUG@ 0_0402_5% DEBUG@
39P_0402_50V8J 39P_0402_50V8J 1 1 1 1 +1.5VS_WWAN UIM_PWR UIM_DATA UIM_CLK UIM_RST UIM_VPP M_WXMIT_OFF# PLT_RST# @ RW9 @RW9 1 RW11 1 SMBCLK SMBDATA CW15 @ CW16
47P_0402_50V8J 39P_0402_50V8J
LPC_FRAME# 11,31 LPC_AD3 11,31 LPC_AD2 11,31 LPC_AD1 11,31 LPC_AD0 11,31
12 12
PCIE_RXN1 PCIE_RXP1 12 12
PCIE_C_RXN2 PCIE_C_RXP2
2 0_0805_5% 2 0_0805_5%
14 WWAN_DETECT# +3VS_WWAN
PCIE_TXN2 PCIE_TXP2
+3VS_WLAN +1.5VS_WWAN +3VS_WWAN 31 31 @ RW19 1 2 UIM_DATA 47K_0402_5% EC_UTX EC_URX RW25 1 RW27 1 2 33_0402_5% 2 33_0402_5%
FOX_AS0B226-S40N-7F CONN@ +3VS_WWAN @ RW22 1 2 0_0603_5% 2 M_WXMIT_OFF# +3VALW RB751V_SOD323 2 G 31 WWAN_POWER_OFF 3 S 1 D @ RW23 1 2 0_1206_5%
UIM_PWR
FOX_AS0B226-S40N-7F CONN@
+3VS_WLAN
RF request.
@ CW22 @ CW23
39P_0402_50V8J 39P_0402_50V8J 1 1 1 1 +3VS UIM_CLK 1 CW11 @ 18P_0402_50V8J 14 XMIT_OFF 1 DW2 2 XMIT_OFF# 47P_0402_50V8J 39P_0402_50V8J RB751V_SOD323 CW20 @ CW21
DW1 14 WXMIT_OFF# 1
QW1 SI2305ADS-T1-GE3_SOT23-3
New Card
PA@ C1308 1 2 0.1U_0402_16V4Z +1.5VS
Close to JEXP
14 14 11 13 3 5 15 19 8 16 7 PERST# 12 CLKREQ_EXP# 12 CLK_PCIE_EXP# 12 CLK_PCIE_EXP 12 12 12 12 PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 CLK_PCIE_EXP# CLK_PCIE_EXP PCIE_RXN4 PCIE_RXP4 PCIE_TXN4 PCIE_TXP4 +1.5VS_PEC 12 SMBCLK 12 SMBDATA +3VS_PEC 13,25 ICH_PCIE_WAKE# +3V_PEC R1110 PA@ 1 2 0_0402_5% +1.5VS_PEC +1.5VS_PEC +3V_PEC +3VS_PEC CLKREQ_EXP# CPPE# SMBCLK SMBDATA PCIE_PME#_R PERST# USB20_N9 USB20_P9 R1108 R1109 PA@ 1 1 PA@ 2 0_0402_5% 2 0_0402_5% USB9USB9+ CPPE# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
+3VS PA@ C1311 1 PA@ C1312 1 +3VALW 14,25 PLT_RST# 31,32,33,37 SYSON 27,31,33,35,38,39 SUSP# +3VALW 14 EXP_CPPE# 1 2 0_0402_5% PA@ R1210 @ PLT_RST# SYSON SUSP# R1111 1 2 100K_0402_5% CPPE#
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
+1.5VS_PEC
6 20 1 10 9 18
+3V_PEC
internal pull high to 3.3Vaux-in EC need setting at Hi-Z & output Low
PA@
SANTA_130801-5_LT CONN@
2006/07/26
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Calpella_UMA_LA4106P
Thursday, November 12, 2009
E
Rev 1.0 24 of 45
Sheet
+HV33 +DVDD33 LAN_ACTIVITY# C1261 1 2 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 46 47 48 14 44 45 19 33 26 XTAL1 XTAL2 1 RSET/AVDD Y8 2 27P_0402_50V8J CL13 0.1U_0402_16V4Z 1 8 2 26 RJ45_MIDI1RJ45_MIDI17 6 5 4 26 RJ45_MIDI1+ 26 CL14 0.1U_0402_16V4Z LAN_SK_LAN_LINK# 2 RJ45_MIDI0RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+ +3V_LAN 1 2 1 LANLED_LINK# 3 2 1 11 12 RL2 300_0402_5% 2 1 +3V_LAN LANLED_ACT# 13 14
LAN Conn.
JRJ45 Yellow LED+ Yellow LEDSHLD1 PR4DETECT PIN1 PR4+ PR2PR3PR3+ PR2+ PR1DETCET PIN2 PR1+ SHLD1 Green LED+ Green LEDFOX_JM36113-P1122-7F CONN@ LANGND LANLED_LINK# 3 2 1 CL17 0.1U_0402_16V4Z 1 CL18 4.7U_0805_10V4Z 10 15
D
U9
16 9
ICH_PCIE_WAKE# ISOLATEB PCIE_PTX_IRX_P3_R PCIE_PTX_IRX_N3_R PLT_RST# CLKREQ_LAN# LAN_ACTIVITY# LAN_SK_LAN_LINK# LED2/EEDI CR_LED# EECS
C1265 C1264
1 1
2 0.1U_0402_16V7K 2 0.1U_0402_16V7K
35 36 17 18 20 21 15 16 37 38 43 42 41 40 39 28 29 31 32
LANWAKEBPIN ISOLATEBPIN REFCLK_P REFCLK_M HSOP HSON HSIP HSIN PERSTBPIN CLKREQBPIN LEDPIN0 LEDPIN1/EESK LEDPIN2/EEDI LEDPIN3/EEDO EECSPIN MDIP0 MDIN0 MDIP1 MDIN1
DVDD3
CKXTAL1 CKXTAL2 IBREF(REST) XD_CE#/SD_D1 XD_CLE/SD_D0/MS_D7 XD_ALE/SD_D7/MS_D3 XD_WE#/SD_CD# XD_WP#/SD_D6/MS_D6 XD_D0/SD_CLK/MS_D2 XD_D1/SD_D5/MS_D0 XD_D2/SD_CMD XD_D3/SD_D4/MS_D4 XD_D4/SD_D3/MS_D1 XD_D5/SD_D2/MS_D5 XD_D6/MS_BS XD_D7 XD_CD# XD_RDY/SD_WP#/MS_CLK XD_RE#/MS_INS# EVDD3 CARD_3V3 VDD3_IN VDDTX CTRL12D CTRL12A
25MHz_20pF_6X25000017
C1260 1 2 27P_0402_50V8J 2 1 R1044 2.49K_0402_1%
8401
+3VS LAN_MDI0+ LAN_MDI0LAN_MDI1+ LAN_MDI1R1047 1K_0402_5% 2 2 ISOLATEB GNDTX R1048 15K_0402_5% 1 EECS LED2/EEDI @ R1046 1 R1049 2 2 1K_0402_5% 1 3.6K_0402_5% EPAD
XDCE#_SDD1 XDCLE_SDD0 XDALE_SDD7_MSD3 XDWE#_SDCD# XDWP#_SDD6 SD_CLK 0_0402_5% XDD0_SDCLK_MSD2 1 R1179 2 XDD1_SDD5_MSD0 XDD2_SDCMD XDD3_SDD4_MSD4 XDD4_SDD3_MSD1 XDD5_SDD2_MS_D5 XDD6_MSBS XD_D7 XD_CD# MS_CLK 1 R1178 2 0_0402_5% XDDRY_SDWP_MSCLK XDRE#_MSINS# +VCC_4IN1_R +EVDD +D3V3 +EVDD12_8401 CTRL12 CTRL12A R1033 2 C322 1 C1272 C1258 1 1 1 0_0603_5% 2 0.1U_0402_16V4Z +VCC_4IN1
26 RJ45_MIDI0+
GND(GPO)
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
@ R823 1
2 0_0805_5%
80 mils
S D 3 R824 100K_0402_5% 1 2 C485 0.1U_0402_16V4Z 2 1 +3V_LAN
C
49
22
30
RTL8401-GR_QFN48_6X6
+3V_LAN
@ R382 1
Q15 SI2301BDS-T1-E3_SOT23-3
R1043
31 LAN_POWER_OFF 1 +EVDD 1
2 0_0402_5%
close pin 27
C1251 0.1U_0402_16V4Z
+3V_LAN
2 0_0402_5%
close pin 14
C1259 0.1U_0402_16V4Z R369 300_0402_5% 1 2 1 C480 0.1U_0402_16V4Z
0_0402_5%
LANLED_ACT#
R1036
+3V_LAN
DL2 +5VS RL16 1 2 1.2K_0402_5% 2 1 CR_LED#
2 0_0402_5%
close pin 45
C1254 1U_0402_6.3V6K
+3V_LAN
2 0_0402_5%
close pin 34
C1263 0.1U_0402_16V4Z
2 HT-F196BP5_WHITE
White
10/100 Transformer
U17 1 2 3 4 5 6 7 8 RD+ RDCT NC NC CT TD+ TDNS681680 RX+ RXCT NC NC CT TX+ TX16 15 14 13 12 11 10 9 RJ45_MIDI0+ RJ45_MIDI0RJ45_CT0 RJ45_CT1 RJ45_MIDI1+ RJ45_MIDI1C1041 1 C1039 1 2 0.01U_0603_100V7-M RJ45_CT0_C 2 0.01U_0603_100V7-M RJ45_CT1_C 1 1 R822 75_0402_1% 2 2 R821 75_0402_1%
7 IN 1 CONN
SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 SD-CMD SD-CD-SW SD-WP-SW MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS
C323 0.1U_0402_16V4Z
C324 0.1U_0402_16V4Z
C325 0.1U_0402_16V4Z
C1042 1 C1046 1
2 0.01U_0402_16V7K 2 0.01U_0402_16V7K
RJ45_GND C1045 1
1000P_1206_2KV7K
41 42
2006/10/06
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
Rev 1.0
http://mycomp.su/x/
DOCK_PWR_ON Spec 0V = Notebook S4/S5, Dock off 2.5V = Notebook S3, Dock on 4V = Notebook S0, Dock on
+5VS +3VALW R1093 1 PA@ R1094 1 PA@ 2 1K_0402_5% 2 1K_0402_5% 2
38 40 34 36 30 32 26 28 22 24 18 20 14 16 10 12 6 8 2 4
33,39
SYSON#
2 G PA@Q89 2N7002_SOT23-3
CRT_Red CRT_Green CRT_Blue DDC_DATA DDC_Clock Hsync Vsync USBUSB+ Digital gnd MDI3MDI3+ MD2IMDI2+ MDI1MDI1+ MDI0MDI0+ Battery out Battery out
Digital gnd TV Luma TV chroma TV composite TV ground CIR input PWR_ON Mute_LED Sleep Botton Jack Detect VOL_up VOL_down SPDIF Audio Output gnd Right headphone Left headphone Mic_Right Mic_Left Mic gnd Dock_present GND GND GND GND
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 41 42 43 44
R1185 10K_0402_5% VGA_GND CIR_IN CIR_IN 28,31 DOCK_PWRON D_MUTE_LED R1089 1 PA@ 2 33_0402_5% D_DOCK_SLP_BTN# R1090 1 PA@ 2 33_0402_5% JACK_DET# R_VOL_UP# R1091 1 PA@ 2 200_0402_5% R_VOL_DWN# R1092 1 PA@ 2 200_0402_5% SPDIFO_L AUDIO_OGND GNDA DOCK_LOUT_C_R DOCK_LOUT_C_R 27 DOCK_LOUT_C_L DOCK_LOUT_C_L 27 DOCK_MIC_R_C DOCK_MIC_L_C AUDIO_IGND GNDA DOCK_PRESENT R1096 1 2 2K_0402_5% @ +DOCKVIN
1 2
R1186 10K_0402_5%
DOCK_VOL_UP# 31 DOCK_VOL_DWN# 31
B+
@ 1
45 46
GND GND
CONN@ FOX_QL1122L-H212AR-7F
Dock PRESENT
31 CONA#
+3VL 2
GNDA
R1097 10K_0402_5% 1
MIC_Dock
1000P_0402_50V7K
DOCK_PRESENT
R1098 PA@ 2 1
D Q90 DMN5L06K-7_SOT23-3 L64 PA@ FBM-11-160808-601-T_0603 DOCK_MIC_R_C 1 2 1 2 L65 PA@ FBM-11-160808-601-T_0603 PA@ C1303 220P_0402_50V7K DOCK_MIC_L_C 1 1 PA@ C1304 220P_0402_50V7K PA@ C1301
0.01U_0402_16V7K
22_0402_5%
27 DOCK_MIC_R 27 DOCK_MIC_L
GNDA
GNDA
+3VS
GNDA GNDA
SENSE_B# 27
2 G 3 S PA@
2 B 3 E
Q92 MMBT3904_NL_SOT23-3
GNDA
E 2 PA@ C1306 1
1U_0603_10V6K
2006/03/10
Title
http://mycomp.su/x/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009
1102_Reserve LDO power for Codec. 1105_Reserve the others +5VS power for Codec.
+3VS R437 BLM18BD601SN1D_0603 2 1 C976 0.1U_0402_16V4Z +3VS_HDA 2 0_0603_5% C551 0.1U_0402_16V4Z 1 1 1 +3VS_DVDD +AVDD_CODEC C553 1U_0402_6.3V6K C1443 4.7U_0805_10V4Z 2 1 1 U22 C1065 2 1 10U_0805_10V4Z 1 9 @ R441 @R441 2 1 47_0402_5% HDA_BITCLK_CODEC R444 1 2 HDA_SDIN0_CODEC 33_0402_5% HDA_SDOUT_CODEC HDA_SYNC_CODEC HDA_RST#_CODEC 3 6 8 5 10 11 DVDD_CORE DVDD DVDD_IO HDA_BITCLK HDA_SDI HDA_SDO HDA_SYNC HDA_RST# HP1_PORT_B_L HP1_PORT_B_R PORT_C_L PORT_C_R VREFOUT_C DMIC_CLK/GPIO1 DMIC0/GPIO2 DMIC1/GPIO0/SPDIF_OUT_1 SPDIF_OUT_0 EAPD SPKR_PORT_D_RSPKR_PORT_D_R+ PORT_E_L PORT_E_R PORT_F_L PORT_F_R PC_BEEP CAP+ MONO_OUT 7 HDA_RST#_CODEC 1 C1433 0.01U_0402_25V7K 2 2 1 C1434 100P_0402_50V8J 33 30 26 42 49 DVSS AVSS AVSS AVSS PVSS DAP 92HD80B1X5NLGXYD38_QFN48_7X7~D CAP2 VREFFILT VVREG 22 21 34 37 C1071 4.7U_0603_6.3V6M 2 C1072 10U_0805_10V4Z C563 10U_0805_10V4Z 1 2 C564 1U_0603_10V6K SPKR_PORT_D_L+ SPKR_PORT_D_LHP0_PORT_A_L HP0_PORT_A_R VREFOUT_A_or_F PVDD PVDD SENSE_A SENSE_B AVDD AVDD 27 38 39 45 13 14 28 29 23 31 32 19 20 24 40 41 43 44 15 16 17 18 12 25 SENSE_A SENSE_B DOCK_LOUT_L DOCK_LOUT_R +VREFOUT_EXTMIC HP_OUT_L HP_OUT_R MIC_INL MIC_INR +VREFOUT_INMIC SPKL+ SPKLSPKRSPKR+ PA@1U_0603_10V6K DOCK_MICL_C C1317 1 PA@ R1114 1 2 DOCK_MICR_C C1318 1 PA@ R1115 1 2 PA@ 1U_0603_10V6K MIC_EXTL MIC_EXT_L C1326 1 2 2.2U_0603_6.3V4Z MIC_EXTR MIC_EXT_R C1327 1 2 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z MONO_INR 2 MONO_IN 1 C561 DOCK_MICL DOCK_MICR OPP@ C1328 1 C1329 1 OPP@ 2 2.2U_0603_6.3V4Z 2 2.2U_0603_6.3V4Z MIC_IN_L MIC_IN_R 2 R904 2 C1063 0.1U_0402_16V4Z C1064 1U_0402_6.3V6K 1 0_0805_5% 2 1 +5VS +5VS 1 @ R1229 0_0805_5% 2 @ R1226 @R1226 0_0805_5% 2 1
+VREFOUT_EXTMIC +AVDD_CODEC
+VDDA_CODEC
MIC_EXT_R MIC_EXT_L
+3VS
1
1102_Reserve 4.7uF.
1105_Reserve 1230.
R1227 MCK2012102YZF_0805
R907 1
C1066 0.1U_0402_16V4Z
C1068 10U_0805_10V4Z
C1067 1U_0402_6.3V6K
@ C554 2 1 33P_0402_50V8K
SENSE_A SENSE_B
R438 PA@R439 PA@R439 R598 R440 C556 R254 PA@R257 PA@R257 R256 C555
1 1 1 1 1 1 1 1 1
2.49K_0402_1% +AVDD_CODEC 39.2K_0402_1% JACK_DET# JACK_DET# 26 20K_0402_1% HP_DET# HP_DET# 28 10K_0402_1% INTMIC_DET# INTMIC_DET# 28 1000P_0402_50V7K 2 2 2.49K_0402_1% +AVDD_CODEC 2 39.2K_0402_1% SENSE_B# SENSE_B# 26 2 20K_0402_1% EXTMIC_DET# EXTMIC_DET# 28 1000P_0402_50V7K 2 2 2 2 2
92HD80 port define Port A DOCK HP Port B Port C Port D Port E Port F DM0 HP INT. MIC SPKR DOCK MIC EXT. MIC Digital MIC
+VREFOUT_INMIC
C546 1 1 1
R434 4.7K_0402_5%
150U_Y_6.3VM 1 2 1 2 + + 150U_Y_6.3VM
DOCK_LOUT_C_L 26 DOCK_LOUT_C_R 26 HP_OUT_L 28 HP_OUT_R 28 MIC_IN_L 28 MIC_IN_R 28 SPKL+ SPKLSPKRSPKR+ 2 10K_0402_5% 2 10K_0402_5% MIC_EXT_L 28 MIC_EXT_R 28 28 28 28 28
Dock HP Jack
DOCK_MICL_C DOCK_MICR_C
HP Jack
1 1
Int. MIC
21 21
2 4 46 48
+VREFOUT_INMIC 28
Internal SPKR
2 10K_0402_5% 47
DOCK_MIC_L 26 DOCK_MIC_R 26
DOCK_MIC
+3VS 1
28,31 EC_MUTE#
92HD80 Resistor define SENSE_B Resistor SENSE_A 39.2K 20.2K 10.0K 5.11K 2.49K Port A Port B Port C SPDIFOUT0 PU to AVDD HP1 Port E Port F DMIC0 SPDIFOUT1 PU to AVDD
35 36
CAP-
Ext MIC
+AVDD_CODEC 2 2 1 1 MONO_IN R447 2 1 47K_0402_5% C1070 1 2 0.1U_0402_16V4Z D C562 0.1U_0402_16V4Z 2 1 R909 10K_0402_5%
W=40Mil
C1444 1
+VDDA_CODEC
C1445 2.2U_0805_16V4Z
R449 10K_0402_5%
1 @ R1228 0_0402_5%
24,31,33,35,38,39
SUSP#
Q38 2N7002_SOT23-3 S
2 G
SB_SPKR
SB_SPKR 11
3
CODEC POWER
(4.75V) 300mA
G9191-475T1U_SOT23-5 2
1 1
C1446 0.1U_0402_16V4Z
1 1 1 1
2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0_0603_5% 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z GNDA 26,28
GND
GNDA
CONN@ 1 1
4
13 14 15 16 17 18
H12 HOLEA
H14 HOLEA
MDC Standoff
Security Classification Issued Date 2007/08/28
2006/07/26
Title
Codec_IDT92HD80
Size Document Number Custom Date:
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Calpella_UMA_LA4106P
Sheet
E
Rev 1.0 of 45
27
SPEAKER
1
@ C1447 0.1U_0402_16V4Z 1 2
JP60 6 5 27 27 27 27 SPKRSPKR+ SPKLSPKL+ SPKRSPKR+ SPKLSPKL+ R454 R455 R456 R457 1 1 1 1 2 2 2 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% C569 330P_0402_50V7K 1 1 2 2 3 2 SPK_RSPK_R+ SPK_LSPK_L+ 4 3 2 1 GND2 GND1 4 3 2 1 ACES_88231-04001 CONN@ 27 +VREFOUT_INMIC +VREFOUT_INMIC 2 OPP@ R1125 1 1 OPP@ +AVDD_CODEC C1323 1U_0603_10V4Z 1 2 OPP@ OPP@ R1126 R1128 10K_0402_5% 4.7K_0402_5% 1 2 JP51 1 2 3 4 5 6 OPP@ Q20B 1 2 3 4 GND1 GND2 ACES_88231-04001 CONN@
2
C570 330P_0402_50V7K
C571 330P_0402_50V7K
C572 330P_0402_50V7K
INTMIC IN
D15 @ PSOT24C_SOT23-3 1
D16 @ PSOT24C_SOT23-3 1
R401 OPP@1
27 27
0_0402_5%
2N7002DW-7-F_SOT363-6 1 6
27
INTMIC_DET# MIC_IN_L
OPP@ Q20A
Audio connector
3 2
MIC_IN_R
5 MIC_EXT_R MIC_EXT_L 3 2
Q28A 2N7002DW-7-F_SOT363-6 1 6
Q32A 2N7002DW-7-F_SOT363-6
HP de pop circuit
HP_OUT_L
HP_OUT_R
@ D61 PACDN042_SOT23~D 1
+5VALW
2 1
Q28B 2N7002DW-7-F_SOT363-6 3 4
Q32B 2N7002DW-7-F_SOT363-6
R76 10K_0402_5% @ 2
2N7002DW-7-F_SOT363-6 Q39A
15 16
3
27,31 EC_MUTE#
3
2 1
26,31
ACES_87213-1400G CONN@
2006/07/26
Title
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Calpella_UMA_LA4106P
Sheet
E
Rev 1.0 of 45
28
USB20_N0 USB20_P0
R479 1 R480 1
2 0_0402_5% 2 0_0402_5%
USB20_N0_R USB20_P0_R
C599 4.7U_0805_10V4Z
11 SATA_RXN4_C 11 SATA_RXP4_C
GND A+ ESATA AGND BB+ GND GND GND GND GND TYCO_1759576-1 CONN@
R481
2 10K_0402_5%
+5VALW D21 USB20_N0 USB20_P0 WCM-2012-900T_0805 1 1 2 2 4 4 @ L11 3 3 D20 +5VALW 4 VIN IO1 2 1 USB20_P0_R USB20_N0_R 3 +5VALW SATA_TXN4 USB20_N0_R USB20_P0_R 4 3 VIN IO1 2 1 SATA_TXP4
IO2 GND
PRTR5V0U2X_SOT143-4
IO2 GND
Finger printer
EMI request
C
PRTR5V0U2X_SOT143-4
ESD request
C
+3VS R1113 1 1 C301 <BOM Structure> 0.1U_0402_16V4Z JP24 1 2 3 4 5 6 7 8 1 2 3 4 5 6 GND GND ACES_85201-06051 CONN@ 2 0_0603_5%
BT Connector
9
2 R248 14 14 USB20_N11 USB20_P11 1 1 R599 2 0_0402_5% 2 0_0402_5% 3 2 USB20_N11_R USB20_P11_R @ R548 1 2 0_0402_5%
4 3
VIN
IO1
2 1
USB20_P12_R
IO2 GND
PRTR5V0U2X_SOT143-4
0_0603_5% S S
3 1
D D
1 C293 2 1U_0603_10V4Z 2
@ R1123 100K_0402_5%
C298
C299
C300
2 4.7U_0805_10V4Z
C292 1 2 0.1U_0402_16V4Z
11 12
2006/07/26
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 1.0 29 of 45
Sheet
+3VL U25 20mils C610 0.1U_0402_16V4Z SPI_FSEL# SPI_CLK_R SPI_FWR# 1 8 3 7 1 6 5 VCC W HOLD S C D Q 2 SPI_SO 1 R498 VSS 4
&U25
Close to EC
31 31 31 FSEL# SPI_CLK FWR# 1 2 R495 0_0402_5% 1 2 R496 0_0402_5% 1 2 R497 0_0402_5%
MX25L8005M2C-15G SOP 8P
@
FRD# 2 33_0402_5%
FRD#
31
MX25L2005CMI-12G SOP 8P
SA00003GM00 (WINBOND)
Close to PCH
R661 11 SPI_SB_CS# SPI_SB_CS# 1 2
11 SPI_CLK_PCH 11 SPI_SI
SA000021A00 (MXIC)
http://mycomp.su/x/
5 4
SA000031Q00 (ATMEL)
SA00003GK00 (MXIC)
S IC FL 2M MX25L2005CMI-12G SOP 8P
C391 2 22P_0402_50V8J
S IC FL 2M W25X20AVSNIG SOIC 8P
SPI_WP# SPI_HOLD#
3 7 1 6 5
SPI_SO_R
SPI_SO_R 11
AT25DF321-SU SOIC 8P
2006/07/26
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 1.0 30 of 45
Sheet
+3VL_EC +3VL_EC 1 0.1U_0402_16V4Z 1 1 C613 C614 0.1U_0402_16V4Z 1 C615 2 2 1000P_0402_50V7K C616 2 1000P_0402_50V7K 1 C617 +3VL R511 1 +3VL_EC +EC_AVCC OPP@ R386 2
VCC R1223
R1223 100K_0402_5% BDID PA@ R386 0_0402_5%
3.3V+/-5% 100K+/-5% R386 0 8.2K+/-5% 18K+/-5% 33K+/-5% V AD_BID min 0V 0.216V 0.436V 0.712V V AD_BID typ 0V 0.250V 0.503V 0.819V V AD_BID max 0V 0.289V 0.538V 0.875V
+3VL_EC
Board ID
Blade UMA Blade SG Bee. UMA Bee. DIS
2 2 0.1U_0402_16V4Z
0 1 2 3
2 0_0805_5%
18K_0402_1%
2 AVCC VCC VCC VCC VCC VCC VCC U27 SMB_EC_DA1 SMB_EC_CK1 R512 R513 1 1 2 2.2K_0402_5% 2 2.2K_0402_5% GATEA20 KB_RST# SIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 CLK_PCI_EC PCI_RST# ECRST# 1 2 R518 0_0402_5% KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 TP_BTN# CONA# SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 1 2 3 4 5 7 8 10 12 13 37 20 38 67 +3VL_EC 9 22 33 96 111 125
@ C623 1
@ R516 2 1 2 33_0402_5%
14 GATEA20 14 KB_RST# 11 SIRQ 11,24 LPC_FRAME# 11,24 LPC_AD3 11,24 LPC_AD2 11,24 LPC_AD1 11,24 LPC_AD0
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC &
LVDS_INV_PWM ME_EN
ACOFF C624
35 1
0.01U_0402_16V7K ECAGND 2
PCI_RST#
BDID KSO11 R1224 KSO14 2 SUS_PWR_ACK 13 KSO13 KSO12 +5V_TP KSO3 KSO6 KSO8 KSO7 KSO4
2 C630
1 0.1U_0402_16V4Z
+3VS
SYSON 2 1
SUSP# 1
PCI_RST# 2
R526 10K_0402_5% 2
R525 10K_0402_5%
R521 8.2K_0402_5% 1 2
R522 8.2K_0402_5% 2
R523 100K_0402_5%
LID_SW#
TP_BTN#
33
1.05VS_ON 32
+3VL_EC
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 77 78 79 80
DA Output
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47
DAC_BRIG VCTRL IREF AC_SET EC_MUTE# USB_EN# I2C_INT MUTE_LED TP_CLK TP_DATA R524 DOCK_VOL_UP# DOCK_VOL_DWN#
0_0402_5%
R519 1 R520 1
PS2 Interface
2 0_0402_5%
AC_LED# 34
DOCK_VOL_UP# 26 DOCK_VOL_DWN# 26
1 1 1 R530
2 2 2 1
30 30 30 30
KSO5 KSI3 KSI2 KSO0 KSI5 C612 KSI4 1 KSO9 KSI6 KSI7 KSI1
@ R531 10K_0402_5% 1 2
R532 10K_0402_5%
GPIO SM Bus
14 PCI_PME# 32 WL_BLUE_BTN
2 0_0402_5% 2 0_0402_5%
EC_PME# EC_PME# 13 13 14 32 SLP_S3# SLP_S5# EC_SMI# LID_SW# SLP_S3# SLP_S5# EC_SMI# LID_SW# ESB_CLK_R ESB_DAT_R EC_PME# EC_ACIN 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
CIR_IN PCH_TEMP_ALERT# FSTCHG STD_ADP CAPS_LED# BAT_LED# ON/OFFBTN_LED# SYSON VR_ON AC_IN
2 10K_0402_5% CIR_IN 26,28 PCH_TEMP_ALERT# 14 FSTCHG 35 STD_ADP 35 CAPS_LED# 32 BAT_LED# 32 ON/OFFBTN_LED# 32 SYSON 24,32,33,37 VR_ON 40
BATT_OVP
100P_0402_50V8J
26 DOCK_SLP_BTN#
13 ON/OFFBTN
EC_ACIN
WWAN_POWER_OFF EC_UTX EC_URX ON/OFFBTN DIM_LED 33 DIM_LED NUM_LED# 2 4.7K_0402_5%32 NUM_LED# C647 15P_0402_50V8J 1 2 Y6 3 2 NC NC OSC OSC 4 1 2 1
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 V18R AGND
R534 EC_RSMRST# 100 EC_RSMRST# 13 101 R535 1 2 EC_LID_OUT# 12 EC_ON 0_0402_5% 102 EC_ON 36 R536 WL_BLUE_LED# 103 WL_BLUE_LED# 32 PM_PWROK_R 104 1 2 PM_PWROK 13 100_0402_5% 105 BKOFF_R# 2 1 BKOFF# BKOFF# 21 M_PWROK R504 22_0402_5% 106 M_PWROK 13 TP_LED# 107 PV PWROK sequence issue TP_LED# 32 108 110 112 114 115 116 117 118 124 1 C648 4.7U_0603_6.3V6K R540 10K_0402_5% D25 NMI_DBG# 2 1 +3VL_EC 2 PCI_SERR# RB751V_SOD323 PCI_SERR# 14 RB751V_SOD323 1 SLP_S4# SLP_S4# 13 ENBKL ENBKL 13 EAPD_CODEC R543 EAPD_CODEC 27 R_LAN_POWER_OFF 2 1 SUSP# 0_0402_5% SUSP# 24,27,33,35,38,39 PWRBTN_OUT# PWRBTN_OUT# 13 NMI_DBG# +3VL_EC ADP_ID 2
1 10K_0402_5%
For EMI
GPI
CRY2
122 123
11 24 35 94 113
69
@ R539 20M_0402_5%
KB926QFB0_LQFP128_14X14
L26 0_0603_5% 2
1 C650 +3VL_EC +3VS 1 1 1 PA@ R1219 4.7K_0402_5% PA@ @ R1220 R544 4.7K_0402_5% 4.7K_0402_5% +3VS 1 @ R545 4.7K_0402_5% PA@ R546 R547 1 1 PA@ 2 0_0402_5% 2 0_0402_5% ESB_CLK_R ESB_DAT_R
2 0.1U_0402_16V4Z
AC_IN
2 2 100P_0402_50V8J RB751V_SOD323
ACIN
35 R388 1 R389 1
+3VL_EC
2 47K_0402_5% 2 47K_0402_5%
2006/07/26
32 32
ESB_CLK ESB_DAT
http://mycomp.su/x/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Calpella_UMA_LA4106P
Thursday, November 12, 2009 Sheet 31 of 45
Rev 1.0
TP ON/OFF
+5V_TP 1 R1139 @ 10K_0402_5% 2
D51
1
White
2 1
31
BAT_LED#
TP_BTN# 31
White
11 SATA_LED# 14 HDDHALT_LED#
PA
+5VS_LED +3VS +5VS_LED D54 PA@
OPP
4 2 4
1 3
2 4
1 1
AMBER
White
White White
Amber
White
Amber Amber
AMBER
R1150 10K_0402_5%
3 TP_LED# TP_LED# 31
QSMF-C16E_AMBER-WHITE 1 D
D53 ON/OFFBTN_LED# 1
White
2 1
2 D58 PSOT24C_SOT23-3
+5V_TP
31 WL_BLUE_BTN 31 ON/OFFBTN_LED# 31,34 SMB_EC_CK1 31 ESB_CLK 31 ESB_DAT 31 I2C_INT 31 NUM_LED# 31,34 SMB_EC_DA1 31 ON/OFFBTN
WL_BLUE_LED#
OPP@ OPP@
1 1 1 1 1 1
2 0_0402_5% 2 0_0402_5% 2 2 2 2
1 1 C1347 0.1U_0402_16V4Z
ENE
SMB_EC_DA1 OPP@
5 6
R1151 R1152
1 PA@ 1
G1 G2
Cypress
ESB_CLK 1 @ @ R1153 2 33_0402_5% C1342 2 1
1 2 2 2
24,31,33,37 SYSON
4.7U_0603_6.3V6K C1343
SYSON 2 G
1 @ C1349 100P_0402_50V8J
+3VS
3
R1154 10K_0402_5% 2
G1 G2
ACES_85201-04051 CONN@
ACES_85201-04051 CONN@
5 6
R1156 100K_0402_5% 2
24
WL_LED# WW_LED#
D56 1 1 D57
24
+3VALW JP11 1 2 3 4 1 2 3 4
4
31
G1 G2
5 6
ACES_85201-04051 CONN@
2006/07/26
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
HT-F196BP5_WHITE
2 G Q98 S 2N7002_SOT23-3
TP_DATA TP_CLK
15P_0402_50V8J
0_0805_5%
0_0805_5%
@ @
Calpella_UMA_LA4106P
Thursday, November 12, 2009
E
Rev 1.0 32 of 45
Sheet
+5VS B+
+1.5VS
C671 0.1U_0402_16V4Z
C673 0.1U_0402_16V4Z
C672 10U_0805_10V4Z
R596 330K_0402_5% 2
1 4
C679 0.1U_0402_16V4Z
C680 10U_0805_10V4Z
2 1
RUNON_5VS
SUSP
1 1
C677 4700P_0402_25V7K
C770 0.1U_0402_16V4Z @
+VCCP B+ +1.5VS_CPU
C
+1.05VS
@ R1164 330K_0402_5%
1 4
C1352 0.1U_0402_16V4Z
+1.5VS_CPU
+1.8VS
2N7002DW-7-F_SOT363-6
2 @
@ 31 1.05VS_ON
Q103A
1.05VS_ON 2 1
Discharge circuit
+5VS 1 +3VS 1 1 R588
B
1021_Change R593 from 470 ohm to 22 ohm. 1105_Change R592 from 470 ohm to 22 ohm.
+1.5VS +VCCP 1 +1.5V 1 +0.75VS 1 +1.05VS 1
R591 470_0402_5% 2
@ R1166
B
470_0402_5% 2
470_0402_5% 2 2N7002DW-7-F_SOT363-6
@ Q8B SUSP 5 4
Q7B SUSP 5 4
Q103B
2 G
1.05VS_ON 5 4
Q10B 2N7002DW-7-F_SOT363-6
2N7002_SOT23-3
DIM LED
+5VS
C1353 10U_0805_10V4Z
+1.5VS
+5VS
+3VL
+3VL
SUSP
9,39
31
DIM_LED
DIM_LED
2 G 3 S
24,31,32,37 SYSON
2 1
SUSP#
24,27,31,35,38,39 2 DIM_LED#
H1 HOLEA
H2 HOLEA
H3 HOLEA
H4 HOLEA
H5 HOLEA
H6 HOLEA
H7 HOLEA
H8 HOLEA
H9 HOLEA
H10 HOLEA
H15 HOLEA
H16 HOLEA
H17 HOLEA
H18 HOLEA
H19 HOLEC
FM1 1 FM3 1
FM2 FM4
2006/07/26
http://mycomp.su/x/
1 1 1 1 1 1 1
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Q6A
Q6B G
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 1.0 33 of 45
Sheet
+3VALW
PQ3 TP0610K-T1-E3_SOT23-3 +3VL
1 PR9 2 100K_0402_5%
1
BATT
1
340K_0402_1% PR1 1 2
+5VALW
0.01U_0402_25V7K PC1
ADP_ID 31
2 1 1 1
PC12
ACES_88334-057N
RLZ3.6B_LL34
ADP_SIGNAL
0.01U_0402_25V7K PC6
105K_0402_1% PR6 1 2
5 4 3 2 1
PJP1
5 4 3 2 1
ADPIN
PL1 SMB3025500YA_2P 1 2
PL2 SMB3025500YA_2P 2 1
+ -
1 2 PR3 10K_0402_5%
PR2 10K_0402_5%
VIN
+DOCKVIN
499K_0402_1% PR4 1 2
PR8 2K_0402_5%
PD4
@1000P_0402_50V7K
3 2 1
0 4 G
PR5 10K_0402_5% 2 1
BATT_OVP 31
2 1 PC2 100P_0402_50V8J
PU1A LM358ADT_SO8
PC5 1000P_0402_50V7K 2 1
PJSOT24CW _SOT323
PD1
PC3 1000P_0402_50V7K
PC4 100P_0402_50V8J 2 1
8 7 6 5 4 3 2 1 GND GND
3
8 7 6 5 4 3 2 1 9 10
1
EC_SMD EC_SMC PD2 PJSOT24CW _SOT323
1 2
PH1 under CPU botten side : CPU thermal protection at 90 +-3 degree C
PR7 604K_0402_1% 1 2
3
PC8 1000P_0402_50V7K
3 2 1
SUYIN_200275MR008GXOLZR
CPU
1
PH1 10K_TH11-3H103FT_0603_1%
PR13 100_0402_5%
PR14 100_0402_5%
SMB_EC_DA1 SMB_EC_CK1
PR10 200K_0402_1% 1 2
EN0_TRIP 36
5 6 1 + P
D PQ1 SSM3K7002FU_SC70-3
0 4
2 G 3
S
BAT_ID
35 PC10 0.22U_0603_10V7K
PU1B LM358ADT_SO8
PR16 6.49K_0402_1% 1 2
+3VL
PR15 150K_0402_1%
PC11 1000P_0402_50V7K
Security Classification
Issued Date
2008/05/29
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Calpella_UMA_LA4106P
Thursday, November 12, 2009
D
Rev 0.3 34 of 45
Sheet
P4
B+
BATT
VIN P2 PQ102 FDS6675BZ_SO8
1
PC132 @1000P_0402_50V7K
1000P_0402_50V7K
2 1 PC129 470P_0402_50V7K 2 1
PC103 4.7U_0805_25V6-K
PC104 4.7U_0805_25V6-K
PC130 270P_0402_50V7K
PQ101 SI4835DDY-T1-E3_SO8 1 2 3
1 2 3
CHG_B+
PQ103 SI4459ADY
PL101 HCB2012KF-121T50_0805 2
1 2 3
8 7 6 5
PR103 47K_0402_5% 1 2 1
VIN
31 PC106 0.1U_0603_25V7K 2 1 1
AC_SET
PC108 0.1U_0603_25V7K
2 PR106 200K_0402_5%
PC107 @0.01U_0402_16V7K
PR140 100K_0402_5%
PR107 47K_0402_1% 1 2
PQ104 DTA144EUA_SC70-3
2 5 6 7 8
ACOFF
31
ACN
PQ105 DTC115EUA_SC70-3
CHGEN
ACDET
ACSET
LPREF
LPMD
ACP
SUSP# PC128 1 2
PQ109A 2 2N7002KDW-2N_SOT363-6 1
PR110 0_0402_5% 1 2
TP PVCC BTST
3 PQ108 AO4466L_SO8 0.1U_0402_10V7K PL102 10U_LF919AS-100M-P3_5.3A_20% 1 2 1 PR141 4.7_1206_5% PC113 4.7U_0805_25V6-K 2 1 PC114 4.7U_0805_25V6-K 2 2 1
8 9
IADSLP AGND VREF VDAC VADJ EXTPWR ISYNSET DPMDET IADAPT SRSET CELLS SRN SRP BAT PU101 BQ24740RHDR_QFN28_5X5
PQ106 DTC115EUA_SC70-3
BQ24740VREF 10 +3VL 11
PACIN_1
PR111 3K_0402_1% 1 2 PD101
2
BATT
PR112 1 2 4 3 0.015_1206_1% PC131 @1000P_0402_50V7K PC115 4.7U_0805_25V6-K 2 1 PC116 4.7U_0805_25V6-K 2 1 PC136 4.7U_0805_25V6-K 2 1
2
VADJ
12 13 14
REGN DL_CHG
1 RLS4148_LL34-2
ACOFF#
2 1SS355_SOD323-2 31 VCTRL
5 6 7 8
PACIN
PD102
3 2 1
3 2 1
PC117 0.1U_0603_16V7K
15
16
17
18
19
20
21
PQ110 AO4468L_SO8
PC118 0.1U_0402_10V7K
Charge Detector
31 ADP_I
PC120 0.22U_0603_10V7K 2 1
PR118 10K_0402_5% 1 2
IADAPT
BQ24740VREF 1
PC121 100P_0402_50V8J 2 1
SRP SRN
PC124 0.1U_0603_25V7K
VIN 2 1
PR121 200K_0402_1% 2
PC123 0.1U_0402_10V7K
PR120 2 1 133K_0402_1%
IREF
31
PC122 @0.1U_0603_25V7K
PR122 681K_0402_1% 1 2
3
1VIN_1
VIN 1
PR124 1K_0402_5% 1 2
ACIN
31
PR129 10K_0402_1% 2 1
5 6
+ -
VIN
PR130 2.15K_0402_1% 1 2
PR131 133K_0402_1% 2 8
1 PR134 10K_0402_5% 2
PC125 0.1U_0603_25V7K
CHGEN#
PC126 0.047U_0402_16V7K
PR133 10K_0603_0.1% 2 2
3 1 2 PR135 10K_0603_0.1% 2
+ -
VIN_1
1.24VREF 31 FSTCHG
STD_ADP 31
1
4
2 1
ACDET 22P_0402_50V8J
1.24VREF
PR137 20K_0402_1%
LMV431ACM5X_SOT23-5
Security Classification
http://mycomp.su/x/
A B
Issued Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Calpella_UMA_LA4106P
Thursday, November 12, 2009
D
Rev 0.3 35 of 45
Sheet
2VREF_51125
PC302 1U_0603_16V7
B+ PL301 HCB2012KF-121T50_0805
B++
B++
2
PC301 2200P_0402_50V7K 2 1 PC316 0.1U_0402_25V6 PC303 4.7U_0805_25V6-K
ENTRIP2
PC304 2200P_0402_50V7K
PC306 10U_0805_6.3V6M
PQ301
PC305 4.7U_0805_25V6-K 2 1
PR305 100K_0402_1% 1 2
ENTRIP1
+3VLP
1 1
PR306 140K_0402_1% 2
ENTRIP2
D1 D1 G2 S2
ENTRIP1
TONSEL
1 2 3 4
8 7 6 5
VFB2
VREF
VFB1
UG1_3V
PU301
5 6 7 8
PQ302 AO4466L_SO8
25 7
PR307 2 1 2 0_0402_5% PC307 0.1U_0402_10V7K LX_3V
AO4932_2N_SO8
8
BST_3V UG_3V
PGOOD VBST1 DRVH1 LL1 DRVL1 SKIPSEL VREG5 VCLK GND EN0
23 22 21 20 19
+3VALWP
10 11 12
3 2 1
PL303 10U_LF919AS-100M-P3_5.3A_20% 1 2
UG1_5V
VO1
24
5 6 7 8
+5VALWP
1
PC310 150U_D_6.3VM
1
PC309 220U_6.3VM_R15 +
13
14
15
16
17
18
PR309 1 2 1M_0402_1%
VIN
B++
RT8205AGQW
2
PC315 680P_0603_50V8J
PC314 @680P_0603_50V7K
PR311 191K_0402_1% 2
VL
1
PC311 10U_0805_10V6K
3 2 1
34
EN0_TRIP
PQ304 AO4712L_SO8
6 ENTRIP1
3ENTRIP2
2 PC312 0.1U_0603_25V7K
B++
PR318 1 2 0_0805_5%
+3_5V PWR_OK 13
2VREF_51125
PQ305B
2 1
5 4
2N7002KDW -2N_SOT363-6
VL
PJP304
+5VL
2 1
PAD-OPEN 2x2m
PJP302
VL
+5VALW P
2
PAD-OPEN 4x4m PJP303
+5VALW
S
4
+3VL
2 1
PAD-OPEN 2x2m
+3VALW P
2
PAD-OPEN 4x4m
+3VALW
EC_ON
100K_0402_5% PR314
31
Security Classification
Issued Date
2008/05/29
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
Calpella_UMA_LA4106P
Thursday, November 12, 2009 Sheet
E
Rev 0.3 36 of 45
1.5V_B+
PL402 HCB1608KF-121T30_0603 2 1
B+
PR404
24,31,32,33 SYSON
1
2200P_0402_50V7K PC407 PC406 @0.1U_0402_10V7K
0_0402_5%
PC402 4.7U_0805_25V6-K
PC403 4.7U_0805_25V6-K
UG1_1.5V
4
PQ401 AON7408L_DFN8-5
15
14
EN_PSV
DRVH LL TRIP
13 12 11 10 9
UG_1.5V LX_1.5V
PR407 0_0402_5% 1 2
TP
VBST
3 2 1
1 PR408
PR401
2 0_0402_5%
FB_1.5V
3 4
PL401 2.2UH_PCMC063T-2R2MN_8A_20% 1 2
PC408 0.1U_0402_25V6
+1.5VP
C
2
+1.5VP
PR403
14.3K_0402_1%
GND
1 2
PC411 1U_0603_10V6K
PGND
PC410 4.7U_0805_10V6K
PR402 10K_0603_0.1%
TPS51117RGYR_QFN14_3.5x3.5
3 2 1
PC412 220P_0603_50V8J
PC405 4.7U_0805_6.3V6K
PGOOD
DRVL
PC401
10.2K_0603_0.1%
LG_1.5V
220U_B2_2.5VM_R25M
PR409 316_0402_1%
5 6 7 8
V5DRV
+5VALW
+5VALW
PQ402 AO4712L_SO8
PR410 4.7_1206_5%
PJP401 +1.5VP
2
PAD-OPEN 4x4m
+1.5V
Security Classification
Issued Date
2008/05/29
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009 Sheet
1
Rev 0.3 37 of 45
B+
2 1 PC704 4.7U_0805_25V6-K
2 1 PC705 4.7U_0805_25V6-K
2 1 PC706 4.7U_0805_25V6-K
2 1 PC718 4.7U_0805_25V6-K
+3VS
+VCCP
PR705 1K_0402_5%
1
DH_VCCP LX_VCCP
2 PR708 2.2_0603_5%
+5VALW
1 2 PR707 2 0_0603_5%
PC709 0.22U_0603_16V7K
VCCP_POK
DH_VCCP1
16
15
PU701
17
PGOOD
GND
PHASE
UG
14
BOOT
13
PR709 0_0402_5%
PR710 2.2_0603_5% 1 2
5 6 7 8
PQ701 AO4474L_SO8
+6269_VCC
4 PVCC 12 1 2
PC710 2.2U_0603_6.3V6K
1
+6269_VCC
VIN
2
2
VCC
ISL6269ACRZ-T_QFN16_4X4
LG
11
DL_VCCP
3 2 1
PC711 2.2U_0603_6.3V6K
PR711 0_0402_5% 1 2
PL701 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 2 +VCCP 330U 2V Y D2 LESR9M PR712 4.7_1206_5% + PC703 330U 2V Y D2 LESR9M PC702 330U 2V Y D2 LESR9M PC701 PC719 220U_B2_2.5VM_R25M
+1.05V_VCCP
1 1
+
FCCM
PGND
10 5 1
COMP
24,27,31,33,35,39 SUSP#
1
PR713 0_0402_5%
EN FSET VO FB
ISEN
SE_VCCP 1
2 PR704 10.5K_0402_1%
PQ702
1
+
1
+
4 2
PR714 22.6K_0402_1% 2 1
FB_VCCP
PC712 @0.1U_0402_10V7K
+1.05V_VCCP
S TR AON6718L 1N DFN
PC713 680P_0603_50V7K
3 2 1
PC715 22P_0402_50V8J
2 1 PC716 6800P_0603_50V7K
PR715 49.9K_0402_1% 2
2 1 PC714 0.01U_0402_16V7K
PJP701 +1.05V_VCCP
2
PAD-OPEN 4x4m PJP702
+VCCP
9 VTT_SELECT
2 PR701 35.7K_0402_1%
2 PR702 1.58K_0402_1% 1
2
PAD-OPEN 4x4m
2 PR717 0_0402_5%
VTT_SENSE 9
PJP703 +1.05V_VCCP
@0.1U_0402_10V7K
2
PAD-OPEN 4x4m
+1.05VS
Security Classification
Issued Date
2009/09/15
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Calpella_UMA_LA4106P
Thursday, November 12, 2009
D
Rev 0.3 38 of 45
Sheet
+1.5V
VCNTL NC NC NC TP
6 5 1 7 8 2 9
+5VALW
1
2 1 3 PR601 1K_0402_1% 2 4
PC601 10U_0805_10V6K
VCNTL
5 4 3 2 9 1 2 1 PC610 22U_0805_6.3V6M
2 1 PC604 0.1U_0402_16V7K
+0.75VSP
GND
D 2
PR602 1K_0402_1%
24,27,31,33,35,38 SUSP#
PC605 10U_0805_6.3V6M
SUSP#
PR605 0_0402_5%
2 1
EN
FB TP
PR603 1
PR604 1
SSM3K7002FU_SC70-3
@0_0402_5%
PR608 0_0402_5%
@0_0402_5%
@0.1U_0402_10V7K
PC612 @0.1U_0402_10V7K
PR607 12K_0402_1%
C
26,33
9,33 SYSON#
SUSP
+1.8VS
6 1.5VSCPU_DRAM_PWRGD
2 G
PC606
PR606 15K_0402_1%
PQ602
PC609 @0.1U_0402_10V7K
PC611 150P_0402_50V8J
PC608 10U_0805_10V6K
+1.8VSP
2007/11/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009
1
Rev 0.3 39 of 45
Sheet
http://mycomp.su/x/
+VCCP 1 PR201 2 @1K_0402_1% 1PR202 2 1K_0402_1% 1PR203 2 @1K_0402_1% 1 PR204 2 @1K_0402_1% 2 1PR206 2 @1K_0402_1% 1PR207 2 @1K_0402_1%
CPU_B+
1PR205 1K_0402_1%
PC211 2200P_0402_50V7K 2 1
PC205 4.7U_0805_25V6-K 2 1
PC206 4.7U_0805_25V6-K 2 1
PC207 4.7U_0805_25V6-K 2 1
PC208 4.7U_0805_25V6-K 2 1
PC212 0.1U_0402_25V6 2 1
PC209 @100U_25V_M
1 + 2
PC210 100U_25V_M
B+
1 + 2
H
9 9 9 9 9 9 9 31
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PR211 VR_ON 0_0402_5% 1 2 PR217 2 1 1K_0402_1% PR219 0_0402_5% 1 2 2 PR220 1 @1K_0402_1% H_VID1 H_VID2 H_VID3
H_VID0
5 6 7 8 2 2 1 PR208 @1K_0402_1% 1 PR209 1K_0402_1% 1 PR210 2 1K_0402_1% 4 2 2 2 2 1 PR212 1K_0402_1% 1 PR213 @1K_0402_1% 1 PR214 1K_0402_1% 1PR216 1K_0402_1% BOOST_CPU2 UGATE_CPU2 PHASE_CPU2 5 PR215 2.2_0603_5% 2 1 <BOM Structure> PC213 0.22U_0603_10V7K 1 2 PR218 0_0603_5% 2 1 3 2 1
0.36UH +-20% MPO104F-R36H1 PL202 4 LF2 PR223 3.65K_0603_1% 2 1 10K_0402_1% PQ204 TPCA8036-H_SOP-ADV8-5 1 1 PR221 4.7_1206_5% 2 3 1 2 1 V2N PR225 1_0402_5% 2 +VCC_CORE
G
+VCCP 9 H_DPRSLPVR
+3VS
19
CLK_EN#
LGATE_CPU2
13,19
F
PC214 680P_0603_50V7K 2 1
PR227 0_0402_5% 1
3 2 1
PR226 1.91K_0402_1%
PR224 2
PR222 1.91K_0402_1% 1
CLK_EN#
VSUM-
ISEN2 VSUM+
F
2 PR231 147K_0402_1% +VCCP PU201 40 39 38 37 36 35 34 33 32 31 CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0 BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP PWM3 LGATE1 VSSP1 PHASE1 1 1 PR233 0_0402_5% 1 2 3 4 5 6 7 8 9 10 41 PR232 2 68_0402_5% 2
6 H_PROCHOT#
PC218 2 1
AGND
1U_0603_10V6K
PC216 22P_0402_50V8J
+5VALW
E
11 12 13 14 15 16 17 18 19 20
1 2 PC220 10P_0402_50V8J
D
PR238 1 PR239 1 PR241 1 1 PC222 1U_0603_10V6K 2 1 PC223 0.22U_0603_25V7K 0_0402_5% 2 CPU_B+ 1_0402_5% 2 +5VALW 1
1 PC221 150P_0402_50V8J
CPU_B+
PC227 2200P_0402_50V7K 2 1
PC201 4.7U_0805_25V6-K 2 1
PC202 4.7U_0805_25V6-K 2 1
PC203 4.7U_0805_25V6-K 2 1
VSSSENSE
PQ201 AO4406AL 1N SO8 UGATE_CPU1 PR244 2.2_0603_5% 2 1 <BOM Structure> PR243 0_0603_5% 2 1 PC229 0.22U_0603_10V7K 1 2
PC225 2 1
VSUMC
PC204 4.7U_0805_25V6-K 2 1
PC228 0.1U_0402_25V6 2 1
5 6 7 8 BOOST_CPU1
PR242 10.5K_0402_1%
VSUM+
3 2 1
0.047U_0603_16V7K
0.22U_0603_10V7K
PR245 82.5_0402_1% 1 1 0.01U_0402_25V7K 2 PC230 0.022U_0402_16V7K 1 VCCSENSE PR249 2 1 0_0402_5% PC233 330P_0402_50V7K
PR246 2.61K_0402_1% 2 1
4 3
1 2 1 V1N
+VCC_CORE
PR248 3.65K_0603_1% 2
PC231
PC232
PC237 330P_0402_50V7K
PC234
PC235 680P_0603_50V7K 2 1
PR255 11K_0402_1% 2 1
3 2 1
VSUMB
PR253 1.3K_0402_1% 1 2
PH201 10KB_0603_5%_ERTJ1VR103J 2
ISEN1 VSUM+
PC238 1 @1200P_0402_50V7K
PC239 0.1U_0402_16V7K
LGATE_CPU1
10K_0402_1%
PQ203 TPCA8036-H_SOP-ADV8-5
PR251 1_0402_5%
PR250 2
Security Classification
http://mycomp.su/x/
8 7 6 5
Issued Date
2008/05/29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4 3 2
Calpella_UMA_LA4106P
Thursday, November 12, 2009 Sheet
1
Rev 0.3 40 of 45
B+
PC805 2200P_0402_50V7K
2 1 PC801 4.7U_0805_25V6-K
2 1 PC802 4.7U_0805_25V6-K
2 1 PC803 4.7U_0805_25V6-K
2 1 PC804 4.7U_0805_25V6-K
PC806 0.1U_0402_25V6
GFX_B+
2 1 PR803 22.6K_0402_1%
1 1
GFXVR_IMON
5 6 7 8
BST_GFX 1
PR804 10_0402_5% 1 2
1 2 PC810 1000P_0402_50V7K 1 2
2 4
29
12
10
ISUM
AGND
IMON
VDD
RTN
VIN
ISUM+
BOOT
7 6 5 4
PR813 10.2K +-1% 0402 PR814 825K_0402_1% PC815 1000P_0402_50V7K PR808 47K_0402_1%
UGATE
PU801 ISL62881HRZ-T_QFN28_4X4 PHASE
3 2 1
PC812 330P_0402_50V7K
11
13
14
PC813 330P_0402_50V7K
PR805 2.2_0603_5%
PC811 0.22U_0603_16V7K
PL801
+GFX_CORE
4 3
1 5 2 1
PR810 2.2_1206_5%
VSSP LGATE VCCP VID0 VID1 VR_ON VID6 VID5 VID4 VID3 VID2
1 3 2
2 1
1 1
+GFX_CORE
PQ802
3 2 1
PC816 2.2U_0603_6.3V6K
PR811 3.65K_0805_1%
1
PR812 0_0402_5%
AON6718L 1N DFN
2
10KB_0603_5%_ERTJ1VR103J
28
27
26
25
24
23
22
2
PC818 150P_0402_50V8J
1 2
1
PR817 8.06K_0402_1%
PR816 17.8K_0402_1%
2 1 PR819 @1.91K_0402_1%
1 PR820 @10K_0402_1%
PH801
GFXVR_PW RGD GFXVR_CLKEN# 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1
GFXVR_VID_0 9 GFXVR_VID_1 9 GFXVR_VID_2 9 GFXVR_VID_3 9 GFXVR_VID_4 9 GFXVR_VID_5 9 GFXVR_VID_6 9 GFXVR_EN 9 GFXVR_DPRSLPVR 9 ISUM+ ISUM-
2
PR823 @100_0402_1%
2
PC823 @180P 50V J NPO 0402
Security Classification
Issued Date
2009/10/31
Title
http://mycomp.su/x/
5 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3 2
Size Document Number Custom Calpella_UMA_LA4106P Date: Thursday, November 12, 2009 41 of 45
Title
PWR-3.3VALWP/5VALWP
PWR-CPU_CORE PWR-CPU_CORE PWR-0.75VP/1.8VSP
Solution Description
Add PC313,PC305 from 1206 to 0805 and parallel PC313 Change PR253 from 1.1K to 1.3K,Change PR242 from 8.25K to 10.5K Change PR237 from 2.43K to 3.01K
Change PQ201 PQ202 from AO4474L to AO4406AL Change PU602 from APL5915 to APL5930
Note
DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 DB to PV1 PV1 to PV2 PV1 to PV2
2 1
1 2 3 4 5 6 7 8 9 10
36 40 40 39 35 38 37 38 40 38 38 41 39
Change PR113 from 143K to 140K, Change PC117 from 1u to 0.1u, Add PR114 Add PR705 connect to 3VS, remove PR706 PR403 from 8.45K to 14.3K PR703 from 8.25K to 10.5K Add PC230 PQ702 from TPCA8028-H to AON6718L Delet PC717 Add PR833 connet to GFXVR_IMON and PU801 13pin
Add 1.5VSCPU_DRAM_PWRGD add PR608 connect to PQ601 pin 2 and Delet PR604
11 12 13
http://mycomp.su/x/
A B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C D
2008/08/02
Title
Rev 0.3 42 of 45
Item 01 02 03 04 05 06
D
PAGE 22 26 31 13 31 32 22 22 31 31 31 31 32 33 33 14 31 21 32 27 6 25 26 27 6 25 28 32 14 32
Fixed Issue Fix Volum up/down cannot work on Docking. Remove double pull high resistor. Per EMI request. Modify correct pull high resistor value. Modify LVDS PWM connection. Fix cannot hot plug if use Asmedia level shifter. Add series for Express card delete signal between Express card power swtich and PCH For Board ID. Change LAN power off control pin to U27 pin115. Change LID switch power rail from +3VL to +3VALW. Delete useless parts. Change LID switch power rail from +3VL to +3VALW. For Cost down. Try to use +1.5VS to replace +1.8VS power rail. Modify prevent S3 leakage issue circuit. Modify prevent S3 leakage issue circuit. Fix LCD panel no display issue. Change Cap. board power rail from +3VL to +3VS. Swap Audio port A and F. Delete XDP connector Conecto Q15 to +3V_LAN. Modify Audio circuit near docking side. Per EMI/ESD request. Modify prevent S3 leakage issue circuit. Follow DIS. Per ESD request. Change cap. board power rail from +3VL to +3VS. Make sure PLT_RST# level is stable. Reserve +3VL power rail for cap. board.
Modify List Add R1185, R1186 and pull high to +3VS. Delete R660. Change R679 from 33 ohm to 100 ohm. Change R512 and R513 from 4.7K to 2.2K ohm. Connect R890 to PCH and R505(reserve) to EC. Remove R862 and R867. Add R1210 Add R386 and pull low to GND. Connect U27 pin115 and add series resistor R543 to LAN power control circuit. Pull high R526 to +3VALW. Delete R542 because already connect EC_UTX to MINI PCIE connector Change JP11 pin 1 to +3VLALW. Reserve U30, R596, R650, R590, C681, C770, C679, C680, Q8; add PJ2 to connect +1.5VS_CPU and +1.5VS power plan. Add and reserve PJ3 to short +1.8VS and +1.5VS_CPU power plan. Connect PCH_DDR_RST from EC GPIO48 to PCH GPIO46. Delete R386 Connect JLVDS1 pin27 to +3VS. Reserve R1211 and connect to +3VS. Swap port A and port F. Detail please see audio circuit. Delete JP1, R13, R17, R18, R19, R22, R25, C1 Delete R1031 and connect Q15 pin1 to +3V_LAN directly. Connect Q91 pin3 to GNDA and move it near Codec. Add R1212/C1433 for HDA_RST#_CODEC. Add C1434. Change R132/R135/R139 to C1435/C1436/C1437. Change U57 from reset IC to AND gate; add R1218 and reserve R383; add voltage divider(R1216/R1217) for VTTPWRGOOD. Change Y8 material. Add D61, D62 for OPP sku. Pull high R544 and R545 to +3VS power rail. Stuff R185. Add and reserve R1219/R1220 to +3VL.
Date 7/20. 7/20. 7/20. 7/20 7/20 7/24 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/13 8/17 8/17 8/17 8/17 8/17 8/19 8/19 8/19 8/20 8/20 8/21
Note DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1 DB --> PV-1
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Fixed Issue Make sure +1.5VS can ramp up early than +0.75VS. ME fuction control enable/disable. For support ME function. HM55 disable USB port6/port7. To solve no Vref out when external MIC change from port A to port F. Delete EC_BEEP from EC because useless. Delete ANA_MIC_DET net to EC.because useless. HM55 disable USB port6/port7. Board ID is not enough when use pin81. ME fuction control enable/disable. For support ME function. Chagne ENE cap. board ESB bus power rail from +3VS to +3VL. Chagnge Cap. board power rail from +3VS to +3VL.
Modify List Connect 1.5VSCPU_DRAM_PWRGD to enable PU601. Add Q106, R1221, R1222 and connect to EC pin26. Connect SUS_PWR_ACK to EC pin76. Change Bluetooth port6 to port12, change Fingerprinter port7 to port11. Reserve R431, add R and connect to +AVDD_CODEC. Delete EC_BEEP to EC. Delete ANA_MIC_DET to EC. Change Bluetooth port6 to port12, change Fingerprinter port7 to port11. Swap TP_BTN# and BDID, then add pull high resistor R1223 for BDID. Remove EC_BEEP and change to ME_EN, then connect ME_EN to Q106. Remove ANA_MIC_DET and change to SUS_PWR_ACK, then connect SUS_PWR_ACK to PCH. Reserve R544/R545 and stuff R1219/R1220. Reserve R1211 and stuff R1140.
Date 9/11 9/11 9/11 9/11 9/11 9/11 9/11 9/11 9/11 9/11 9/11 9/11 9/11
Note PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2 PV-1 --> PV-2
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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Fixed Issue To solve RTL8401 cause BSOD 0xD1 issue. To solve HDMI signal jitter fail issue. To solve time too fast in DOS mode. To solve RTL8401 cause BSOD 0xD1 issue. To solve cannot power on when no CPU insert in ATE test. To meet Intel power down sequence spec. To meet Intel power down sequence spec. Follow Intel schematic checklist rev2.0 change. To solve audio noise issue. To solve ESD test fail. To solve ESD test fail. To solve ESD test fail. To solve ESD test fail. To solve EMI test fail. To solve EMI test fail. To solve audio noise issue. Reserve ref. power for external MIC. To solve GFX power spike when S0 to S3/S5. To meet Intel power down sequence spec. To reduce powr noise from FAN.
Request by HW Intel HW HW HW HW HW HW HW ESD ESD ESD ESD EMI EMI EMI HW Intel HW HW
Modify List Change RTL8401 PCIE port from port3 to port5 (follow Rhett2.0), new add series resistor R506/0 ohm. Add Y2, R131, C141. Change C142 from 0 ohm to 18pF. Change R259 and R260 from 18pF to 22pF. Change RTL8401 PCIE port from port3 to port5 (follow Rhett2.0) Add pull high resistro R13 to +3VL_EC for EC pin21. Change R593 from 470 ohm to 22 ohm. Change R1182 from 470 ohm to 220 ohm. Change R137 from 1K ohm to 10K ohm. Add and reserve U59, R1228, C1443, C1444, C1445, C1446, R1226, R1227. Add and reserve C1438, C1439, C1440 near Q104. Add and reserve C1441 near JDIMM1. Add and reserve C1442 near JDIMM2. Add and reserve C1447 between GND and GNDA near internal MIC connector. Change R1148 from 0 ohm to bead (SM01000CY00), move C652 to near JP59. Move C652 to near JP59. Move C652 to near JP59. Reserve R1230 to connect +VREFOUT_INMIC. Change R43 from 4.7K ohm to 249 ohm. Change R592 from 470 ohm to 22 ohm. Add R597.
Date 10/19 10/19 10/19 10/19 10/20 10/21 10/21 10/21 11/02 11/03 11/03 11/03 11/03 11/03 11/03 11/03 11/05 11/05 11/05 11/05
Note Delete this item in 10/26. PV-2 --> MV PV-2 --> MV Delete this item in 10/26. PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV PV-2 --> MV
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THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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