Computer Communication

&
Networking

Data Link Control

Sudipta Mahapatra

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 Serial and Parallel
Data Transmission
• Serial Transmission: Data are transferred
using a single communication path or a
single bit at a time.
• Parallel Transmission: A parallel set of lines
are used to transfer data; examples include
I/O transfers, internal computer signal paths.
• Serial data transmission can be further
subdivided into asynchronous and
synchronous transmissions.

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 Synchronization
• One of the key tasks in data
communication is synchronization of
the transmitter and receiver.
• The receiver can correctly recognize
the transmitted bits if:
- the clock frequencies of the
transmitter and receiver agree.
- the receiver recognizes the beginning
and end of a block of data bits.
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 Asynchronous transmission
• Data transmitted one character at a time
– 5 to 8 bits
• Timing information is embedded within each
character
• Resynchronization takes place for each
character

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Source: William Stallings. Data and Computer Comn. 7th Edition
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 Characteristics of asynchronous
transmission
• In a steady stream, interval between
characters is uniform (length of stop
element)
• In idle state, receiver looks for transition
from 1 to 0
• Then samples next seven intervals (char
length)
• Then looks for next 1 to 0 for next char
• Simple and Cheap
• Overhead of 2 or 3 bits per char (~20%)
• Good for data with large gaps (keyboard)
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 Synchronous Transmission

• Block of data transmitted without start or

stop bits
• Clocks must be synchronized
• Can use separate clock line
– Good over short distances
– Subject to impairments
• Embed clock signal in data
– Manchester encoding
– Carrier frequency (analog)

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Synchronous Transmission (Contd.)

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Synchronous Transmission (Contd.)

• Need to indicate start and end of block

• Use preamble and postamble
– e.g. series of SYN (hex 16) characters
– e.g. block of 11111111 patterns ending in
11111110
• More efficient (lower overhead) than
asynchronous transmission

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 Signal Encoding Schemes

• Nonreturn to Zero-Level (NRZ-L)

• Nonreturn to Zero Inverted (NRZI)
• Bipolar -AMI
• Pseudoternary
• Manchester
• Differential Manchester

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 NRZ-L

• Two different voltages for 0 and 1 bits

• Voltage constant during bit interval
– no transition, I.e. no return to zero voltage
• e.g. Absence of voltage for zero, constant
positive voltage for one
• More often, negative voltage for one value
and positive for the other

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 NRZ-I (Non return to zero inverted)

• Nonreturn to zero inverted on ones

• Constant voltage pulse for duration of bit
• Data encoded as presence or absence of signal
transition at beginning of bit time
• Transition (low to high or high to low) denotes a
binary 1
• No transition denotes binary 0
• An example of differential encoding
– Transition detection vs. threshold value comparison

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 NRZ – Pros and Cons
• Pros
– Easy to engineer
– Make good use of bandwidth
• Cons
– dc component
– Lack of synchronization capability
• Used for magnetic recording
• Not often used for signal transmission
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 Manchester

Uses Return to zero (RZ) encoding

• Transition in middle of each bit period
• Transition serves as clock and data
• Low to high represents one
• High to low represents zero
• Used by IEEE 802.3

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Source: William Stallings. Data and Computer Comn. 7th Edition
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 Differential Manchester

Also, an RZ code
• Mid-bit transition serves as the clock
• Transition at start of a bit period represents
zero
• No transition at start of a bit period represents
one
• Note: this is a differential encoding scheme
• Used by IEEE 802.5

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Source: William Stallings. Data and Computer Comn. 7th Edition
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 Errors in data communication
• An error occurs when a bit is altered between
transmission and reception
• Single bit errors
– One bit altered
– Adjacent bits not affected
– White noise
• Burst errors
– Length B
– Contiguous sequence of B bits in which first, last, and any
number of intermediate bits are in error
– Impulse noise
– Fading in wireless channels
– Effect greater at higher data rates
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 Error Handling
• Should we go for error detection or error
correction?
• Forward Versus Backward Error Correction?
• Error Detection Techniques
– Parity checks
– Longitudenal redundancy check
Add a second set of parity bits for each column of a
block of data.
– Cyclic Redundancy Check

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 Error Detection Process

Source: William Stallings. Data and Computer Comn. 7th Edition 21

 Error Detection Mechanism
• Additional bits added by transmitter for
error detection code
• Parity
– Value of parity bit is such that character has
even (even parity) or odd (odd parity) number
of ones
– Even number of bit errors goes undetected

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 Error Detection Mechanism
(Contd.)
•Longitudenal redundancy check: Add a
second set of parity bits for each column
of a block of data.

•Cyclic Redundancy Check (CRC)

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 Cyclic redundancy check
• k-bit data frame: M(x)=ak-1xk-1+ ak-2xk-2+…+ a0x0
• Select a generator polynomial G(x) of degree
r < k-1.
• Append r zero bits to M(x) to form xr M(x).
• Divide xr M(x) by G(x) using modulo-2 arithmetic.
• Subtract remainder from xr M(x) (Modulo-2
arithmetic) to generate T(x).
• Transmit T(x) as the frame with checksum.
• Receiver divides the received data frame by the
same generator polynomial to check for errors.
Example:
M(x)=1101011011, G(x)= x4 +x+ 1=10011, r=4
xr M(x)/G(x)= 11010110110000/10011
Quotient =? Reminder =?
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 Example
Send • Receive
M(x) = 110011
x5+x4+x+1 (6 bits)
P(x) = 11001
x4+x3+1 (5 bits, n = 4) 11001 1100111001

4 bits of redundancy
11001
Form xnM(x)
110011 0000

x9+x8+x5+x4 11001
Divide xnM(x) by P(x) to find C(x)
11001
100001 00000
11001 1100110000
11001 No remainder
10000
Accept
11001
1001 = C(x)
Send the block 110011 1001

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 When CRC fails?
• Sent F(x), but received F′(x) = F(x)+E(x)

When will E(x)/P(x) have no remainder, CRC will fail to

detect an error.

1. Single Bit Error
E(x) = xi

If P(x) has two or more terms, P(x) will not divide E(x)
2. Isolated Single Bit Errors (double errors)
E(x) = xi+xj, i>j
E(x) = xj(xi-j+1)
Provided that P(x) is not divisible by x, a sufficient
condition to detect all double errors is that P(x) does
not divide (xt+1) for any t up to i-j (i.e., block length)

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 When CRC fails?
3. Odd Number of Bit Errors
If x+1 is a factor of P(x), all odd number of bit errors
are detected

Proof:
Assume an odd number of errors has x+1 as a factor.
Then E(x) = (x+1)T(x).
Evaluate E(x) for x = 1

E(x) = E(1) = 1 since there are odd number of terms
(x+1) = (1+1) = 0
(x+1)T(x) = (1+1)T(1) = 0
∴ E(x) ≠ (x+1)T(x)

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 When CRC fails?
4. Short Burst Errors
(Length t ≤ n, number of redundant bits)
E(x) = xj(xt-1+…+1)
Length t, starting at bit position j
If P(x) has an x0 term and t ≤ n, P(x) will not divide E(x)
∴All errors up to length n are detected
5. Long Burst Errors (Length t = n+1)
Undetectable only if burst error is the same as P(x)
P(x) = xn+ … + 1 n-1 bits between xn and x0
E(x) = 1 + … + 1 must match
Probability of not detecting the error is 2-(n-1)
6. Longer Burst Errors (Length t > n+1)
Probability of not detecting the error is 2-n

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 CRC Polynomials
– CRC-12 = x12+x11+x3+x2+x+1
CRC-16 = x16+x15+x2+1
CRC-CCITT = x16+x12+x5+1
– CRC-16 and CRC-CCITT catch all
• Single and double errors
• Odd number of bit errors
• Bursts of length 16 or less
• 99.997% of 17-bit error bursts
• 99.998% of 18-bit and longer error bursts

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 Shift Register Implementation
• Size of shift register q=r
Use feedback at positions corresponding to terms of G(x).

G(x)=x4+x+1
di
C3 C2 C1 C0

G(x)=x4+x2+1 30
 Example

- Remainder = 0011 – This is sent after the data

frame as the checksum.
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 Error correction
• Correction of detected errors usually requires
data block to be retransmitted (see chapter 7)
• Not appropriate for wireless applications
– Bit error rate is high
• Lots of retransmissions
– Propagation delay can be long (satellite) compared
with frame transmission time
• Would result in retransmission of frame in error plus many
subsequent frames
• Need to correct errors on basis of bits received

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 Error correction mechanism

Source: William Stallings. Data and Computer Comn. 7th Edition 33

 Error correction process
• Each k bit block mapped to an n bit block (n>k)
– Codeword
– Forward error correction (FEC) encoder
• Codeword sent
• Received bit string similar to transmitted but may contain
errors
• Received code word passed to FEC decoder
– If no errors, original data block output
– Some error patterns can be detected and corrected
– Some error patterns can be detected but not corrected
– Some (rare) error patterns are not detected
• Results in incorrect data output from FEC

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Error correction process (Contd.)
• Add redundancy to transmitted message
• Can deduce original in face of certain level of
error rate
• For example, block error correction code
– In general, add (n – k ) bits to end of block
• Gives n bit block (codeword)
• All of original k bits included in codeword
– Some FEC map k bit input onto n bit codeword such
that original k bits do not appear

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 Interfacing
• Data processing devices (or data terminal
equipment, DTE) usually do not include data
transmission facilities
• Need an interface called data circuit terminating
equipment (DCE) for transmitting data
– e.g. modem, NIC
• DCE transmits bits on medium
• DCE communicates data and control information
with DTE
– Done over interchange circuits
– Clear interface standards required

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Interfacing (Contd.)

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 Characteristics of Interface
• Mechanical
– Connection plugs
• Electrical
– Voltage, timing, encoding
• Functional
– Data, control, timing, grounding
• Procedural
– Sequence of events

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