Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal(M.P.

)
Scheme of Examination
Second Semester- Master of Engineering
( Embedded System and VLSI Design,Micro electronics and VLSI Design)
S.No. Subject Subject Name Periods per Credits Maximum Marks Maximum Marks Total
Code week (Theory Slot) (Practical Slot) Marks
End. Tests Assign End. Practical
Sem. (Two) ments Sem. Record/A
Exam. /Quiz Practical/ ssignmen
L T P
Viva t/Quiz/Pr
esentatio
n
1. MEVD- VLSI Technology 3 1 - 4 100 30 20 - - 150
201
2. MEVD- Real Time 3 1 - 4 100 30 20 - - 150
202 Operating System
3. MEVD- Microelectronics 3 1 - 4 100 30 20 - - 150
203
4. MEVD- Embedded 3 1 - 4 100 30 20 - - 150
204 Computing System
Design
5. MEVD- Opto-Electronics 3 1 - 4 100 30 20 - - 150
205 Integrated Circuits
6. MEVD- Lab-III - - 6 6 - - - 75 50 125
206 Real Time
Operative System
7. MEVD- Lab-IV - - 6 6 - - - 75 50 125
207 VLSI Technology
Total 15 5 12 32 500 150 100 150 100 1000

L: Lecture - T: Tutorial - P: Practical w.e.f. July-2010