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    Pankaj Garg
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    This document contains a homework assignment for a digital VLSI design course. It provides information about the school, faculty member, course details, date of assignment, and consists of 6 questions split into two parts. Part A contains 3 questions about static RAM cells, dynamic RAM timing parameters, and implementing Boolean functions with a PAL. Part B contains 3 additional questions that are not described. The document requires signatures from the faculty member, Head of Department, and Head of School.

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    12695_ECE419HW2H68T1

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    This document contains a homework assignment for a digital VLSI design course. It provides information about the school, faculty member, course details, date of assignment, and consists of 6 questions split into two parts. Part A contains 3 questions about static RAM cells, dynamic RAM timing parameters, and implementing Boolean functions with a PAL. Part B contains 3 additional questions that are not described. The document requires signatures from the faculty member, Head of Department, and Head of School.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    14 views2 pages

    Ece419hw2h68t1

    Uploaded by

    Pankaj Garg
    This document contains a homework assignment for a digital VLSI design course. It provides information about the school, faculty member, course details, date of assignment, and consists of 6 questions split into two parts. Part A contains 3 questions about static RAM cells, dynamic RAM timing parameters, and implementing Boolean functions with a PAL. Part B contains 3 additional questions that are not described. The document requires signatures from the faculty member, Head of Department, and Head of School.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    of 2

    MODEL HOME WORK: 2

    School: LIE-LEET Department: ECE


    Name of the faculty member: Ms. Navjot Kaur Course No: ECE419
    Course Title :Digital VLSI Design:
    Class: B.Tech LEET ECE Term: 2 Section: H68T1 Batch:2007
    Max. Marks: 5 Date of Allotment: 6/2/11 Date of Submission:19/2/11

    PART-A
    Q1.

    Q2. a) How does static RAM cell differ from a dynamic RAM?
    b) What RAM timing parameters determines its operating speed?

    Q3. Implement the following two Boolean functions with a PAL


    F1(Q3,Q2,Q1) =Σ(0,1,2,4)
    F2(Q3,Q2,Q1) =Σ(0,5,6,7).

    PART-B
    Q4.
    Q5.

    Q6. Reduce the following state table to a minimum number of states


    Present state Next state Output
    X= 0 X=1 X=0 X=1
    A B G 0 1
    B C D 1 1
    C F G 0 1
    D H A 0 0
    E G C 0 0
    F C D 1 1
    G G E 0 0
    H G D 1 1

    12695
    Date: 6/2/11 Sig. of Faculty member

    Remarks by HOD (Mandatory)


    Sig. of HOD with date

    Remarks by HOS (Mandatory)


    Sig. of HOS with date

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