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MT 8870
MT 8870
Integrated DTMF Receiver
Bias
PWDN Circuit VRef
Buffer
Q1
Chip Chip
Power Bias High Group Digital Code
Filter Detection Converter
Algorithm and Latch Q2
IN + Dial
Tone Zero Crossing
Filter Detectors Q3
IN -
GS Low Group
Filter Q4
to all St Steering
Chip
Clocks GT Logic
4-11
MT8870D/MT8870D-1 ISO2-CMOS
4-12
ISO2-CMOS MT8870D/MT8870D-1
Functional Description
VDD
Following the filter section is a decoder employing Before registration of a decoded tone pair, the
digital counting techniques to determine the receiver checks for a valid signal duration (referred
frequencies of the incoming tones and to verify that to as character recognition condition). This check is
they correspond to standard DTMF frequencies. A performed by an external RC time constant driven by
complex averaging algorithm protects against tone ESt. A logic high on ESt causes vc (see Figure 4) to
simulation by extraneous signals such as voice while rise as the capacitor discharges. Provided signal
0 AA
AAAA
AA
AAA
AAA
AA
AAAA AAAA
AAAAAAAA
AAAAAAAA
AAAAAAA
AA
AAAA
AAAAAA
AAAAA
AAA
AAA
AAAAAA PRECISE
AA
AAA
AA
AAA
A AAAA
AAA
AAAAA
AAAA
AAA
AAA
AAAA AAAA
AAAAAA
AAAAAAA
AA
AA
AAA
DIAL TONES
AA
AAA
AA AAA
AA
AA
AAA
AA
AAA
AAAA
AAA
A
AAA AAAA
AAA
AAA
AA
AAA
AAAA
AAA
AAAA
AA
AAA AAAA
AA
AAA X=350 Hz
10 AAA
AA
AA
AAA
A
AAA AAAA
AAA
AA
AA
AA
AA Y=440 Hz
AA
AA
AAA
AAAA
AAA
AA DTMF TONES
AA
20 AAA
AA
AA
AAA
AA A=697 Hz
ATTENUATION AA
AAA
AA
(dB) AA
AAA
AA B=770 Hz
AA
AAA
AA C=852 Hz
30 AA D=941 Hz
AAA
AA
AA
AAA
AA
AA E=1209 Hz
AA
AA
AA F=1336 Hz
AA AA
AAA
AA G=1477 Hz
40 AAAAAAA
AAAAA
AA
AAA
AAAA
AAA AA
AAA
AAA
AA
AAAAAA
AAA
AA A A AA
AAA
AA
AAA
AA AA
AAA H=1633 Hz
AAA
AAA
AAA
AA AAAA
AAA
AAA AA
AAAAA
AA
AAA
AAA AAAA
AAA AA
AAA
AA AAAAAAA
AAA AA
AA
AAA
AA
AAA AA
AAA AA
AAAA
AAA
AAA
A
AAAA
A
AAA
AA
AA
AAA
AAAAA
AA
AAA
AAA
AA
AAA AAA
AA
50 AA
AAA
A
AA
AA A AA
AA
1kHz
X Y A B C D E F G H
FREQUENCY (Hz)
Figure 3 - Filter Response
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MT8870D/MT8870D-1 ISO2-CMOS
R2
R1
ESt
b) decreasing tGTA; (tGTP>tGTA)
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ISO2-CMOS MT8870D/MT8870D-1
Power-down and Inhibit Mode
Crystal Oscillator
Figure 6 - Differential Input Configuration
The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single- To OSC1 of next
Ended Input Configuration). However, it is possible C MT8870D/MT8870D-1
to configure several MT8870D/MT8870D-1 devices X-tal
employing only a single oscillator crystal. The OSC1 OSC2
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices OSC2 OSC1
are connected in a similar fashion. Refer to Figure 7
C
for details. The problems associated with
unbalanced loading are not a concern with the
C=30 pF
arrangement shown, i.e., precision balancing X-tal=3.579545 MHz
capacitors are not required.
Figure 7 - Oscillator Connection
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MT8870D/MT8870D-1 ISO2-CMOS
Applications
VDD
C1
DTMF C2
Input R1 MT8870D-1
IN+ VDD
IN- St/GT
GS ESt R3
R2 VRef StD
INH Q4
PWDN Q3
OSC 1 Q2 NOTES:
X1 R1 = 102KΩ ± 1%
OSC 2 Q1
VSS TOE R2 = 71.5KΩ ± 1%
R3 = 390KΩ ±1 %
C1,C2 = 100 nF ± 5%
X1 = 3.579545 MHz ± 0.1%
VDD = 5.0V ± 5%
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ISO2-CMOS MT8870D/MT8870D-1
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter Sym Min Typ‡ Max Units Test Conditions
DC Electrical Characteristics - VDD=5.0V± 5%, VSS=0V, -40°C ≤ TO ≤ +85°C, unless otherwise stated.
Characteristics Sym Min Typ‡ Max Units Test Conditions
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MT8870D/MT8870D-1 ISO2-CMOS
MT8870D AC Electrical Characteristics - VDD =5.0V ±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using Test Circuit shown in
Figure 10.
* NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5 %± 2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Guaranteed by design and characterization.
4-18
ISO2-CMOS MT8870D/MT8870D-1
MT8870D-1 AC Electrical Characteristics - VDD =5.0V±5%, VSS=0V, -40°C ≤ TO ≤ +85°C , using Test Circuit shown in
Figure 10.
* NOTES
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all DTMF tones.
3. Tone duration= 40 ms, tone pause= 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ±1.5 %± 2 Hz.
7. Bandwidth limited (3 kHz ) Gaussian noise.
8. The precise dial tone frequencies are (350 Hz and 440 Hz) ± 2 %.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
12. Referenced to Fig. 10 input DTMF tone level at -25dBm (-28dBm at GS Pin) interference frequency range between 480-3400Hz.
13. Guaranteed by design and characterization.
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MT8870D/MT8870D-1 ISO2-CMOS
AC Electrical Characteristics - VDD=5.0V±5%, VSS=0V, -40°C ≤ To ≤ +85°C , using Test Circuit shown in Figure 10.
Characteristics Sym Min Typ‡ Max Units Conditions
*NOTES:
1. Used for guard-time calculation purposes only.
2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums
are recommendations based upon network requirements.
3. With valid tone present at input, tPU equals time from PDWN going low until ESt going high.
VDD
C1
DTMF
Input C2
R1
MT8870D/MT8870D-1
IN+ VDD
IN- St/GT R3
GS ESt
R2
VRef StD
INH Q4
PDWN Q3
OSC 1 Q2 NOTES:
X-tal OSC 2 Q1 R1,R2=100KΩ ± 1%
R3=300KΩ ± 1%
VSS TOE
C1,C2=100 nF ± 5%
X-tal=3.579545 MHz ± 0.1%
4-20
ISO2-CMOS MT8870D/MT8870D-1
EVENTS A B C E F G
TONE TONE
Vin TONE #n #n + 1 #n + 1
tDP AA
AA
AA tDA
AA
ESt
tGTP tGTA
VTSt
St/GT
tPQ
tQStD
HIGH IMPEDANCE
Q1-Q4 DECODED TONE # (n-1) #n # (n + 1)
tPSrD
StD
tPTE
tPTD
TOE
EXPLANATION OF EVENTS
A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED.
B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS
C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMIAN LATCHED UNTIL NEXT VALID
TONE.
D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE.
E) TONE #n + 1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY
HIGH IMPEDANCE).
F) ACCEPTABLE DROPOUT OF TONE #n + 1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED.
G) END OF TONE #n + 1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT
VALID TONE.
EXPLANATION OF SYMBOLS
Vin DTMF COMPOSITE INPUT SIGNAL.
ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES.
St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT.
Q1 -Q 4 4-BIT DECODED TONE OUTPUT.
StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE
REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL.
TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q1-Q4 TO ITS HIGH IMPEDANCE STATE.
tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECED AS VALID
tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION
tID MAXIMUM TIME BETWEEN VALID DTMF SIGNALS.
tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL.
tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS.
tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS.
tGTP GUARD TIME, TONE PRESENT.
tGTA GUARD TIME, TONE ABSENT.
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MT8870D/MT8870D-1 ISO2-CMOS
NOTES:
4-22