Yamaha Htr-5940-Au

AV RECEIVER/AV AMPLIFIER
RX-V459/HTR-5940/DSP-AX459
HTR-5935
SERVICE MANUAL
IMPORTANT NOTICE
This manual has been provided for the use of authorized YAMAHA Retailers and their service personnel.
It has been assumed that basic service procedures inherent to the industry, and more specifically YAMAHA Products, are already
known and understood by the users, and have therefore not been restated.
WARNING: Failure to follow appropriate service and safety procedures when servicing this product may result in personal
injury, destruction of expensive components, and failure of the product to perform as specified. For these reasons,
we advise all YAMAHA product owners that any service required should be performed by an authorized
YAMAHA Retailer or the appointed service representative.
IMPORTANT: The presentation or sale of this manual to any individual or firm does not constitute authorization, certification or
recognition of any applicable technical capabilities, or establish a principle-agent relationship of any form.
The data provided is believed to be accurate and applicable to the unit(s) indicated on the cover. The research, engineering, and
service departments of YAMAHA are continually striving to improve YAMAHA products. Modifications are, therefore, inevitable
and specifications are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please
contact the distributor's Service Division.
WARNING: Static discharges can destroy expensive components. Discharge any static electricity your body may have
accumulated by grounding yourself to the ground buss in the unit (heavy gauge black wires connect to this buss).
IMPORTANT: Turn the unit OFF during disassembly and part replacement. Recheck all work before you apply power to the unit.
■ CONTENTS
HTR-5935
TO SERVICE PERSONNEL ...................................... 2–3 DISPLAY DATA ..................................................... 39–40
FRONT PANELS ........................................................ 3–5 IC DATA ................................................................. 41–50
REAR PANELS .......................................................... 5–9 PIN CONNECTION DIAGRAM .............................. 51–52
REMOTE CONTROL PANELS .................................... 10 BLOCK DIAGRAMS .............................................. 53–55
SPECIFICATIONS / 参考仕様 ................................ 11–12 PRINTED CIRCUIT BOARDS ................................ 56–68
INTERNAL VIEW ......................................................... 13 SCHEMATIC DIAGRAMS ...................................... 69–75
DISASSEMBLY PROCEDURES / 分解手順 ......... 14–15 REPLACEMENT PARTS LIST .............................. 77–95
SELF DIAGNOSIS FUNCTION (DIAG) / REMOTE CONTROL .............................................. 96–97
自己診断機能（ダイアグ）........................................ 16–37 ADVANCED SETUP .................................................... 98
AMP ADJUSTMENT / アンプ部調整 ........................... 38 REPLACEMENT PARTS LIST FOR CARBON RESISTORS .... 99
100998 2006 All rights reserved.

This manual is copyrighted by YAMAHA and may not be copied or
redistributed either in print or electronically without permission.
P.O.Box 1, Hamamatsu, Japan
'06.02
HTR-5935
■ SELF DIAGNOSIS FUNCTION (DIAG)／自己診断機能（ダイアグ） No. MAIN MENU

9. XM Tone / 32k
SUB MENU
10. ISO Tone / 32k

This unit has self diagnosis functions that are intended for 本機には、検査、測定、不良個所の発見を目的にした自己診断機 11. XM / DT Bus Power : OFF
inspection, measurement and location of faulty point. 能（ダイアグ）があります。 13 iPod 1. DOCK : OK/NG
There are 23 DIAG menu items, each of which has sub- ダイアグメニューは23個あり、そのそれぞれにサブメニューがあ
menu items. ります。（ダイアグのメニュー操作は本体で行います。）下表は 16 IF STATUS 1. DSP STATUS (5Byte)
Listed in the table below are menu items and sub-menu メニュー一覧です。 2. DECODE MODE (2Byte) (Not applied to these models / このモデルには適用されません)
items. 下表の全メニュー項目が、このサービスマニュアル記載のモデル 3. DIR INFO (5Byte) (Not applied to these models / このモデルには適用されません)
4. Pc (2Byte) (Not applied to these models / このモデルには適用されません)
Note that not all menu items listed will apply to the models に適用されるとは限りません。
5. CHS 1 (5Byte) (Not applied to these models / このモデルには適用されません)
covered in this service manual. 6. CHS 2 (1Byte) (Not applied to these models / このモデルには適用されません)
7. DEC INFO (5Byte) (Not applied to these models / このモデルには適用されません)
No. MAIN MENU SUB MENU 8. BSI 1 (5Byte) (Not applied to these models / このモデルには適用されません)
1 BYPASS 1. ANALOG BYPASS 9. BSI 2 (5Byte) (Not applied to these models / このモデルには適用されません)
2. DSP BYPASS 10. BSI 3 (5Byte) (Not applied to these models / このモデルには適用されません)
2 RAM THR 1. RAM MARGIN 11. BSI 4 (5Byte) (Not applied to these models / このモデルには適用されません)
2. RAM FULL BIT 12. BSI 5 (5Byte) (Not applied to these models / このモデルには適用されません)
3 PRO LOGIC 1. Pro Logic 13. BSI 6 (5Byte) (Not applied to these models / このモデルには適用されません)
4 SPEAKERS SET 1. FRONT : SMALL 0dB 14. BSI 7 (5Byte) (Not applied to these models / このモデルには適用されません)
2. CENTER : NONE 15. BSI 8 (1Byte) (Not applied to these models / このモデルには適用されません)
3. LFE/B : FRNT 16. Mute Trigger (5Byte) (Not applied to these models / このモデルには適用されません)
4. Pres Mix : 5ch 17. Digital Info (5Byte) (Not applied to these models / このモデルには適用されません)
5. Front GAIN 1 17 DSP BUS CHECK 1. TI (DSP) BUS CHECK
6. Front GAIN 2 2. RDS IC CHECK
7. SURR B Check 18 SWFR CUT OFF 1. L CUT OFF
5 XCH-INPUT 1. XCH_INPUT_6 (HTR-5935 model) 2. H CUT OFF
2. XCH_INPUT_8 19 PROTECTION SETTING 1. PS L
3. LIMIT SET (Not applied to these models / このモデルには適用されません) (Not applied to these models / このモ 2. PS H
6 MIC CHECK (Not applied to these 1. MIC CHECK --dB デルには適用されません) 3. DC L
models / このモデルには適用されません) 4. DC H
7 DISPLAY CHECK 1. STRAIGHT (Initial display) 5. TEMP
2. VFD DISP OFF 6. PL_J_8_L
3. VFD DISP ALL 7. PL_J_8_H
4. VFD DIMMER 8. PL_U_8_L
5. CHECK PATTERN 9. PL_U_8_H
8 MANUAL TEST 1. TEST ALL 10. PL_U_N_L
2. TEST FRNT L 11. PL_U_N_H
3. TEST CENTER 12. PL_G_8_L
4. TEST FRNT R 13. PL_G_8_H
5. TEST SURR R 14. PL_G_N_L
6. TEST SB R (Not applied to these models / このモデルには適用されません) 15. PL_G_N_H
7. TEST SB L 20 PROTECTION HISTORY 1. HISTORY 1
8. TEST SURR L 2. HISTORY 2
9. TEST PRES L (Not applied to these models / このモデルには適用されません) 3. HISTORY 3
10. TEST PRES R (Not applied to these models / このモデルには適用されません) 4. HISTORY 4
11. TEST LFE 21 SOFT SW 1. SW MODE : PCB/MODEL/FNC
9 FACTORY PRESET 1. PRESET INHI (memory initialization inhibited) 2. MODEL : 759SE-5935
2. PRESET RSRV (memory initialized) 3. DEST. : J/UC/R/T/K/A/BGE/L
10 AD DATA CHECK 1. PS1/PS2 4. TUNER DEST : J/UC/ATKBG/RL
2. DC/TH 5. TUNER TYPE : NRM/RDS/XM
3. IMP SW/POWER LIMITER DISP 6. VIDEO FORMAT : NTSC/PAL
4. PANEL KEY 7. ZONE2 EXIST : EXIST/NOT
11 VIDEO 1. I2C Read Check 8. AAC EXIST : EXIST/NOT
(Not applied to these models / このモ 2. DIGITAL THR CVBS 9. TUNER EXIST : EXIST/NOT
デルには適用されません) 3. DIGITAL THR Y/C 10. ZONE2 AMP EXIST : EXIST/NOT
4. ANALOG BYPASS 11. OSD EXIST : EXIST/NOT
5. TEST PATTERN 12. YPAO EXIST : EXIST/NOT
6. LOOP BACK CVBS 22 ROM VER / SUM / PORT 1. MICROPROCESSOR VERSION
7. LOOP BACK Y/C 2. SUM ALL / PROGRAM
12 XM STATUS 1. 1k -1dB / 44.1k 3. OPE / DSP / XM VERSION
(U,C models) 2. 1k -61dB / 44.1k 4. PORT
3. Mute / 44.1k 5. TI (DSP) FLASH VERSION
4. XM Tone / 44.1k 6. TI (DSP) FLASH SUM
5. ISO Tone / 44.1k 7. EEPROM SUM
6. 1k -1dB / 32k 23 TI (DSP) BOOT ( Not applied to 1. TI (DSP) FLASH BOOT
7. 1k -61dB / 32k these models / このモデルには適用されません)
8. Mute / 32k
16
HTR-5935
• Starting DIAG ● ダイアグの起動

Press the “STANDBY/ON” key while simultaneously 本体の下図に示すキーを同時に押しながら“STANDBY/ON”
pressing those two keys of the main unit as indicated in the キーを押すと、ダイアグが起動します。
figure below.
Keys of main unit / 本体キー
Turn on the power while pressing these keys.

これらのキーを同時に押しながら、パワーオンする。
• Starting DIAG in the protection cancel ● プロテクション解除モードでの起動

mode プロテクションが動作することにより、故障箇所の診断に支障を
If the protection function works and causes hindrance to きたすような場合は、次の方法によりプロテクションを解除した
trouble diagnosis, cancel the protection function as 状態でダイアグモードに入ることができます。
（過電流検出以外の
described below, and it will be possible to enter the DIAG プロテクション動作を解除する）
mode. (The protection functions other than the excess 上図のキーを同時に押しながら“STANDBY/ON”キーを押しま
current detect function will be disabled.) す。このとき、上図のキーを3秒以上押し続けてください。
Press the “STANDBY/ON” key while simultaneously このモードでは本体FLの“SLEEP”セグメントが点滅し、プロテ
pressing those two keys indicated in the figure above. At クションを解除した状態でのダイアグモードであることを知らせ
this time, keep pressing those two keys for 3 seconds or ます。
longer.
In this mode, the “SLEEP” segment of the FL display of the

main unit flashes to indicate that the mode is DIAG mode
with the protection functions disabled.
注意！
CAUTION! プロテクションを解除した状態でのダイアグモードは、危険な
Using this product with the protection function disabled 状態でもプロテクションが作動しないため、動作させると、機
may cause damage to itself. Use special care for this point 器を破壊することがあります。このモードを使用する場合は十
when using this mode. 分注意してください。
HTR-5935
• Canceling DIAG ● ダイアグの解除
1 Before canceling DIAG, execute setting for FACTORY ① ダイアグを解除する前に、ダイアグメニューN o . 9 の
PRESET of DIAG menu No.9 (Memory initialization FACTORY PRESET（メモリーの初期化禁止/またはメモ
inhibited or Memory initialized). リーの初期化）の設定をします。
* In order to keep the user memory stored, be sure to ※ ユーザーメモリーを保持したい場合は、必ずP R E S E T
select PRESET INHIBITED (Memory initialization INHIBITED（メモリー初期化禁止）を選択してください。
inhibited). ② 本体の“STANDBY/ON”キーを押し、パワーオフにします。
2 Turn off the power by pressing the “STANDBY/ON”
key of the main unit.
17
HTR-5935
• Display provided when DIAG started ● ダイアグ起動時の表示

On the FL display of the main unit, an opening message 本体FLディスプレイには、オープニング（プロテクション履歴／
(including the version and the protection history) appears バージョン）が表示され、数秒後にダイアグメニュー表示（1 .
for a few seconds followed by the diagnostic menu display ANALOG BYPASS）となります。
(1. ANALOG BYPASS).
When there is no history of protection function: プロテクション履歴が無い場合：
Opening message / オープニング表示 DIAG menu display / ダイアグメニュー表示
When there is no protection history After a few seconds

プロテクション履歴が無い場合
数秒後
NO PROTECT A 1.ANALOG BYPAS
Version (1 alphabet)
バージョン（英 1 文字）
When there is a history of protection function: プロテクション履歴がある場合：

The FL display appears as shown below depending on the プロテクションの種類によって下記の表示が現れます。
type of the protection function.
The protection function worked due to ex- スピーカーをショートさせた時などが原因で、プ

I PROTECT A
cessive current through the amplifier. ロテクションが働いたことを示します。
Causes could be a short at the speaker ter-
minal or a defect in the amplifier. The pro-
tection function activates immediately to
turn off the power, with no history display at
turn-on, if the amplifier is defective.
The protection function worked due to a 電源電圧による原因で、プロテクションが働いた

PS1 PRT:000 A
defect or overload in the power supply. If ことを示します。異常状態のままパワーオンする
or
the power is turned on with the abnormality と、約1秒後にプロテクションが掛かり、電源が
unsolved, the protection function works in PS2 PRT:000 A 切れます。
about 1 second to turn off the power.
HTR-5935
The protection function worked due to a DC アンプの故障でスピーカーに直流電圧が掛かるな

DC PRT:000 A
voltage appearing at the speaker terminal. どが原因で、プロテクションが働いたことを示し
A cause could be a defect in the amplifier. If ます。異常状態のままパワーオンすると、約3秒
the power is turned on with the abnormality 後にプロテクションが掛かり、電源が切れます。
unsolved, the protection function works in
about 3 seconds to turn off the power.
18
HTR-5935
The protection function worked due to the 温度制限を越えた原因で、プロテクションが働い

TMP PRT:000 A
temperature limit being exceeded. Causes たことを示します。異常状態のままパワーオンす
could be poor ventilation or a defect related ると、約1秒後にプロテクションが掛かり、電源
to the thermal sensor. If the power is turned が切れます。
on with the abnormality unsolved, the pro-
tection function works in about 1 second to
turn off the power.
For detection of each protection function (except I-PRO- 各プロクテクションの検出に関しては、後述のダイアグメニュー

TECT) , refer to DIAG MENU No.10 AD DATA. No. 10 AD DATAを参照してください。
History of protection function プロテクションの履歴

When the protection function has worked, its history is プロテクションが働いた場合、履歴をバックアップして記憶し
stored in memory with a backup. Even if no abnormality ています。サービスのときに異常が認められなくても、バック
is noted while servicing the unit, an abnormality which アップが残っていれば、お客様のところで起きた異常を区別で
has occurred previously can be defined as long as the きます。
backup data has been stored. ダイアグメニュー No.9 で PRESET RESERVED（メモリー
The history of the protection function is cleared when の初期化）を選んでダイアグを解除した場合、またはバック
DIAG is cancelled by selecting PRESET RESERVED アップが消えた場合に、プロテクションの履歴はクリアされま
(Memory initialized) of DIAG menu No.9 or when the す。
backup data is erased.
• Display during menu operation ● メニュー動作中の表示

During the DIAG operation, the menu list described in the ダイアグ中、モニター画面には起動画面の項で説明したメニュー
section of the startup screen appears on the monitor 一覧が表示されます。本体のFL ディスプレイには動作中の機能が
screen and the function at work is indicated on the FL indi- 表示されます。機能動作中の表示内容については、後述の機能詳
cator. The contents displayed during the function opera- 細で記述します。
tion are described later in the “Details of DIAG menu” sec-
tion.
• Operation procedure of DIAG menu and ● ダイアグメニューとサブメニューの操作

SUB-MENU ダイアグにはNo.1∼23のメニューがあり、そのそれぞれにサブ
There are 23 MENU items, each of which has some SUB- メニューがあります。
MENU items.
ダイアグメニューの選択
DIAG menu selection 本体キーでの操作：PROGRAM （順送り）、（逆送り）キー
Main unit: Select the menu using (Forward) and で選択します。
HTR-5935
(Reverse) keys of PROGRAM.
サブメニューの選択
SUB-MENU selection 本体キーでの操作：PRESET/TUNING （順送り）、（逆送
Main unit: Select the sub-menu using (Forward) and り）キーで選択します。
(Reverse) keys of PRESET/TUNING.
Keys of main unit / 本体キー
DIAG menu selection SUB-MENU selection

ダイアグメニューの選択サブメニューの選択
Reverse Forward Reverse Forward Reverse Forward

逆送り順送り逆送り順送り逆送り順送り
U, C models R, T, K, A, G, E, L, J models
19
HTR-5935
• Functions in DIAG mode ● ダイアグ中の機能

In addition to the DIAG menu items, functions as listed ダイアグメニューの他に、以下の機能が動作します。
below are available. ・インプット切り換え
• Input selection ・センター、リア、リアセンター、サブウーファーレベル調整
• Center/Rear/Rear Center/Sub-woofer level adjustment ・スピーカーリレーA/B
• Speaker relay control of A and B ・ミューティング
• Muting ・パワーオン/オフ
• Power on/off ・マスターボリューム
• Master volume
※ チューナー関連、セットメニュー関連は機能しません。
* Functions related to the tuner and the set menu are not ※ 本体のINPUT MODEキーにより、各ダイアグメニューの信号
available. 処理
（動作状態）を維持したままメニューNo.16“IF STATUS”
* It is possible to confirm Menu No.16 IF STATUS while の確認ができます。
keeping the signal process (operation status) of each
DIAG menu by using the INPUT MODE key of the main
unit.
• Initial settings used to start DIAG ● ダイアグ開始時の初期設定

The following settings are used when starting DIAG. ダイアグ開始時に以下のような設定になります。ダイアグ解除時
When DIAG is canceled, these settings are restored to にはダイアグ開始前の状態に戻ります。
those before starting DIAG.
・マスターボリューム：-20 dB
• Master volume: -20 dB ・インプット：DVD（MULTI CH INPUT オフ）
• Input: DVD (MULTI CH INPUT OFF) ・エフェクトレベル：0 dB
• Effect level: 0 dB ・オーディオミュート：オフ
• Audio mute: OFF ・スピーカーリレーA/B：ON
• Speaker relay of A and B: ON ・スピーカー設定：LARGE / BASS OUT = SWFR
• Speaker setting: LARGE / BASS OUT = SWFR ・ダイアグメニュー：BYPASS (1. ANALOG BYPASS)
• DIAG menu: BYPASS (1. ANALOG BYPASS)
HTR-5935
20
HTR-5935
• Details of DIAG menu ● ダイアグメニュー詳細
1. BYPASS 1. BYPASS
Using the sub-menu, it is possible to select analog bypass サブメニューによりANALOG BYPASS/DSP BYPASSが選択
output or DSP bypass output. 可能です。
ANALOG BYPASS ANALOG BYPASS
1.ANALOG BYPAS
Reference data
INPUT: DVD ANALOG
SUBWOOFER OUTPUT: 50 Hz, Others: 1 kHz
SPEAKERS OUT SUBWOOFER
Input level Volume
FRONT L/R CENTER SURROUND L/R SURROUND BACK L/R OUTPUT
Both ch, -20 dBm +6.0 dB +13.0 dBm -∞ -∞ -∞ -∞
DSP BYPASS DSP BYPASS
1.DSP BYPASS
Reference data
INPUT: DVD ANALOG
Input level Volume
Both ch, -20 dBm +6.0 dB +13.5 dBm -∞ -∞ -∞ -∞
ANALOG BYPASS
XMDT
(J)
FL / FR
(J)
DIR
LC89057 DSP
(DECODE)
C / SW
(POST PROCESSING)
(U, C, R, T, K, A, G, E, L) TI D70Y
SL / SR
A/D SBL / SBR
PCM1803
HTR-5935
DRAM ROM
(Shaded items not used in this example)
DSP BYPASS
XMDT
(J)
FL / FR
(J)
DIR
LC89057 DSP
(DECODE)
C / SW
(POST PROCESSING)
(U, C, R, T, K, A, G, E, L) TI D70Y
SL / SR
A/D SBL / SBR

PCM1803
DRAM ROM

21
HTR-5935
2. RAM THROUGH 2. RAM THROUGH

Using the sub-menu, it is possible to select margin output サブメニューによりMARGIN/Full Bitが選択可能です。
or full-bit output.
RAM MARGIN RAM MARGIN

Following head margin is reserved. 以下のヘッドマージンを取ります。
FRONT CENTER SURROUND SURROUND BACK SUBWOOFER

+15.0 dB +13.5 dB +9.0 dB +7.5 dB +21.0 dB
2.RAM MARGIN
Reference data
INPUT: DVD ANALOG
Input level Volume
Both ch, -20 dBm +6.0 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +2.0 dBm
RAM FULL BIT RAM FULL BIT

No head margin is reserved except SW. SW以外のヘッドマージンを取りません。
FRONT CENTER SURROUND SURROUND BACK SUBWOOFER

0 dB 0 dB 0 dB 0 dB +21 dB
2.RAM FULL BIT

Reference data
INPUT: DVD ANALOG
Input level Volume
Both ch, -20 dBm +6.0 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +2.0 dBm
XMDT
(J)
FL / FR
(J)
DIR
LC89057 DSP
HTR-5935
(DECODE)
C / SW
(POST PROCESSING)
(U, C, R, T, K, A, G, E, L) TI D70Y
SL / SR
A/D SBL / SBR

PCM1803
DRAM ROM
When input source is stereo, signal is assigned as below.

2ch信号入力時、以下のように信号を振り分けて出力します。
Front L → Center / Surround L / Surround Back L, R

Front R → Surround R
Front L +10 dB → SWFR
22
HTR-5935
3. PRO LOGIC 3. PRO LOGIC

Dolby PRO LOGIC is applied to input stereo source. 入力2ch信号にDolby PRO LOGIC処理を行います。
3.PRO LOGIC
Reference data
INPUT: DVD ANALOG
Input level Volume
Each ch, -20 dBm +6.0 dB +13.5 dBm -∞ -∞ -∞ -∞
Both ch, -20 dBm +6.0 dB -20.0 dBm +16.5 dBm -∞ -∞ -∞
XMDT
(J)
FL / FR
(J)
DIR
LC89057 DSP
(DECODE)
C / SW
(POST PROCESSING)
(U, C, R, T, K, A, G, E, L) TI D70Y
SL / SR
A/D SBL / SBR

PCM1803
DRAM ROM
4. SPEAKERS SET 4. SPEAKERS SET

The analog switch settings for each sub-menu are as 各サブメニューにおけるアナログスイッチの設定は以下の通りで
shown in the table below. す。
Sub-menu FRONT L/R CENTER SUR. L/R SUR.B L/R LFE/BASS

1 FRNT: SML 0 dB SMALL LARGE LARGE LARGE SWFR
2 CENTER: NONE LARGE NONE LARGE LARGE SWFR
3 LFE/B: FRNT LARGE SMALL SMALL SMALL FRONT
4 Pre Mix: 5ch – – – – –
5 Front GAIN 1 – – – – –
HTR-5935
6 Front GAIN 2 – – – – –
7 SURR B Check – – – – –
LARGE: This mode is used with a speaker with high LARGE：低音再生能力の高い（ユニットの大きい）スピー
bass reproduction performance (a large カーを使用するモードです。全帯域が出力されま
unit). Full bandwidth signals are output. す。
SMALL: This mode is used with a speaker with low SMALL：低音再生能力の低い（ユニットの小さい）スピー
bass reproduction performance (a small カーを使用するモードです。80 Hz以下がLFE/
unit). The signals of 80 Hz or less are mixed B A S S で指定したチャンネルにミックスされま
into the channel specified by LFE/BASS. す。
NONE: This mode is used with no center speaker. NONE：スピーカーを使用しないモードです。センター成
The center content is reduced by 3 dB and 分は-3 dBされて、FRONT L/R に振り分けられ
distributed to FRONT L/R. ます。
SWFR: LFE of 5.1ch signal or LFE/BASS lower than SWFR： 5.1ch信号のLFEまたは90Hz以下のLFE/BASS
90Hz is output through SUBWOOFER OUT. がSUBWOOFER OUTに出力されます。
FRONT: LFE of 5.1ch signal or LFE/BASS lower than FRONT： 5.1ch信号のLFEまたは90Hz以下のLFE/BASS
90Hz is distributed to FRONT L/R. をFRONT L/Rに振り分けます。
23
HTR-5935
4.FRNT:SML 0dB
4.CENTER:NONE
4.LFE/B:FRNT
4.Pres Mix:5ch
4.Front GAIN 1
4.Front GAIN 2
4.SURR B check
Reference data
INPUT: DVD ANALOG (Both ch)
SPEAKER OUT SUBWOOFER
Sub-menu Input level Volume
1 FRONT: SML 0dB Both ch, -20 dBm +6.0 dB +13.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +5.5 dBm
2 CENTER: NONE Both ch, -20 dBm +6.0 dB +10.5 dBm -∞ +13.5 dBm +13.5 dBm +2.0 dBm
LFE/B: FRNT (1 kHz) Both ch, -20 dBm +6.0 dB -∞ +13.5 dBm +13.5 dBm +13.5 dBm -∞
3
LFE/B: FRNT (50 Hz) Both ch, -20 dBm +6.0 dB +20.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm -∞
4 Pres Mix: 5ch Both ch, -20 dBm +6.0 dB -∞ +13.5 dBm +18.5 dBm -∞ -0.5 dBm
5 Front Gain 1 Both ch, -20 dBm +6.0 dB +20.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +2.0 dBm
6 Front Gain 2 Both ch, -20 dBm +6.0 dB +20.5 dBm +13.5 dBm +13.5 dBm +13.5 dBm +2.0 dBm
7 SURR B check Both ch, -20 dBm +6.0 dB -∞ -∞ -∞ +13.5 dBm -∞
HTR-5935
24
HTR-5935
5. XCH INPUT 5. XCH INPUT

The signal input through the multi ch input is output. マルチCH入力された信号が出力されます。
The speaker impedance can be selected. 6オーム、8オームが選択されます。
XCH INPUT_6 (ohms) XCH INPUT_6（ohms）
5.XCH INPUT_6
Reference data
INPUT: MULTI CH INPUT
Input level Volume
Both ch, -20 dBm +6.0 dB +13.5 dBm +13.5 dBm +13.5 dBm -∞ -10.0 dBm
XCH INPUT_8 (ohms) XCH INPUT_8（ohms）
5.XCH INPUT_8
Reference data
INPUT: MULTI CH INPUT
Input level Volume
Both ch, -20 dBm +6.0 dB +13.5 dBm +13.5 dBm +13.5 dBm -∞ -10.0 dBm
LIMIT SET LIMIT SET

Not applied to these models. このモデルには適用されません。
XXXXXXXXXXXX__
6. MIC CHECK 6. MIC CHECK
6.MIC CHK --dB
HTR-5935
25
HTR-5935
7. DISPLAY CHECK 7. DISPLAY CHECK

This program is used to check the FL display section. The FL表示部のチェックプログラムです。サブメニュー操作により、
display condition varies as shown below according to the 表示状態が以下のように変わります。
sub-menu operation. 信号処理はSTRAIGHTです。
The signal route is STRAIGHT.
Checking FL display section /

FL表示部のチェック
Blinking / 点滅
Initial display / 初期表示
All segments OFF / 全セグメント消灯
All segments ON (dimmer 100%) /

全セグメント点灯（ディマー100%）
All segments ON (dimmer 50%) /

全セグメント点灯（ディマー50%）
HTR-5935
Lighting of segments in lattice /

セグメント格子状点灯
Lighting in lattice / 格子状点灯
Short / ショート Normal / 正常
Segment conditions of the FL driver and the FL tube are 全セグメント消灯・全セグメント点灯によりFLドライバー、FL管

checked by turning ON and OFF all segments. Next, the のセグメントの不良を確認します。
operation of the FL driver is checked by using the dimmer 次に、ディマーコントロールによってFLドライバーの動作チェッ
control. Then a short between segments next to each クを行います。
other is checked by turning ON and OFF all segments al- さらに全セグメントを交互（格子状）
に点灯/消灯することで、隣り
ternately (in lattice). (In the above example, the segments 合うセグメントのショートをチェックします。
in the second row from the top are shorted.) （上図の例では、上から2行目のセグメントがショートしていま
す。）
26
HTR-5935
8. MANUAL TEST 8. MANUAL TEST

The test noise based THX is output to the channel speci- DSPからサブメニューで指定したチャンネルへTHX準拠のテス
fied by the sub-menu from the DSP. トノイズを出力します。
The noise frequency for LFE is 35 to 250 Hz. Other than LFE用のノイズ周波数は35∼250 Hz、それ以外は中心周波数
that, the center frequency is 800 Hz. 800 Hzとなります。
8.TEST ALL 8.TEST FRNT L 8.TEST CENTER

Not applied to these models.
このモデルには適用されません。
8.TEST FRNT R 8.TEST SURR R 8.TEST SB R

8.TEST SB L 8.TEST SURR L 8.TEST PRES L

8.TEST PRES R 8.TEST LFE
9. FACTORY PRESET 9. FACTORY PRESET

This menu is used to reserve/inhibit initialization of the バックアップ用RAM（音場プログラムのパラメーターやセットメ
backup RAM (Parameters and set menu contents, etc. of ニュー内容など）の初期化を予約/禁止します。
the sound field program).
PRESET INHIBIT (Initialization inhibited) / PRESET INHIBIT（初期化禁止）

9.PRESET INHI
RAM initialization is not executed. Select this sub-menu to protect the values set by the user.
Note: The protection history will not be erased using PRESET INHIBIT.
RAMの初期化は行われません。ユーザーの設定値を保護するときは、こちらを選択してください。
9.PRESET RSRV
PRESET RESERVED (Initialization reserved) / PRESET RESERVED（初期化予約）
Initialization of the back-up RAM is reserved. (Actually, initialization is executed the next time that
the power is turned on.) Select this sub-menu to reset to the original factory settings or to reset
the RAM. Use PRESET RESERVED to erase the protection history.
バックアップRAMの初期化が予約されます。（実際に初期化されるのは、次回の電源投入時です。
）工場出
荷時や RAM をリセットしたいときは、こちらを選択してください。
HTR-5935
CAUTION: Before setting to the PRESET RESERVED, 注意： PRESET RESERVEDを選んで初期化をする前に、
write down the existing preset memory. チューナーのユーザーメモリー内容を下表に書き写してく
Content of the Tuner in a table as shown be- ださい。（初期化をすると、ユーザーメモリーの内容は消
low. (This is because setting to the PRESET えてしまいます。）
RESERVED will cause ALL user memory con-
tents to be erased.)
Preset group P1 P2 P3 P4 P5 P6 P7 P8
27
HTR-5935
• PRESET STATIONS / プリセット局
STATION FM FACTORY PRESET DATA (MHz) STATION AM FACTORY PRESET DATA (kHz)
PAGE NO. U, C R, T, K, A, G, E, L J PAGE NO. U, C, R, T, K A, G, E, L J
1 87.5 87.50 76.0 1 630 630 630
2 90.1 90.10 83.0 2 1080 1080 1080
3 95.1 95.10 84.0 3 1440 1440 1440
4 98.1 98.10 86.0 4 530 531 531
A/C/E B/D
5 107.9 108.00 90.0 5 1710 1611 1611
6 88.1 88.10 78.0 6 900 900 900
7 106.1 106.10 88.0 7 1350 1350 1350
8 107.9 108.00 82.1 8 1400 1404 1404
10. AD DATA CHECK 10. AD DATA CHECK

This menu is used to display the A/D conversion value of 本機パネルキー、プロテクションなどを検出しているMicropro-
the Microprocessor which detects panel keys of the main cessorのA/D変換の値を、サブメニューで表示します。オー
unit and protection functions in using the sub-menu. Dur- ディオ信号処理は実行前の状態を維持します。
ing audio signal processing, the condition before execu- K0/K1のメニューにすると、全キーの値を検出するためキー操作
tion is maintained. はできなくなりますが、本機のVOLUMEを回すことにより、次
When K0/K1 menu is selected, keys become non-oper- のサブメニューに進めることができます。このとき1クリック以
able due to detection of the values of all keys. However, it 上回すと、ボリューム値が変化するので注意してください。
is possible to advance to the next sub-menu by turning the
VOLUME of the main unit. When using this function, note ※ 図中の数値は参考例です。
that turning the VOLUME more than 1 click would cause
the volume value to change.
* The figures in the diagram are given as reference only.
PS1/PS2 (Power supply voltage protection detection) PS1/PS2（電源電圧プロテクションの検出）

Power supply voltage protection value (Normal value: PS1: プロテクションの値（正常値 PS1: 17∼66、PS2: 25∼46）
17 to 66, PS2: 25 to 46) PS1：+5Sを検出しています。
PS1: Detects +5S and +5.3X (U, C models). PS2：±12V、±5V、+5D、+3.3D、+5iを検出しています。
PS2: Detects ±12V, ±5V, +5D, +3.3D and +5i. ※ PSは正常値を外れるとプロテクションが働き、電源オフされ
* If PS is out of the normal value range, the protection ます。
function works to turn off the power. （基準電圧：5V=100%）
(Reference voltage: 5 V=100 %)
PS1:039 2:044
DC/TH (protection detection/temperature detection) DC/TH（プロテクションの検出/温度検出）

HTR-5935
DC: DC detect protection value (Normal value: 5 to 36) DC： DC検出プロテクションの値（正常値5∼36）

* If DC is out of the normal value range, the protection ※ DCは正常値を外れるとプロテクションが働き、電源オフされ
function works to turn off the power. ます。
(Reference voltage: 5 V=100 %) （基準電圧：5V=100%）
TH: Detects the temperatur of the heat sink. TH：ヒートシンクの温度を検出しています。
Temperature detected value 温度検出値
(Normal value: 9 to 177) U, C, T, K, A, G, E, J models （正常値: 9∼177）
(Normal value: 9 to 167) R, L models （基準電圧：5V=255）
(Reference voltage: 5 V=255)
DC:007 TH098
28
HTR-5935
IMP SW/POWER LIMIT (impedance/power limiter detection) IMP SW/POWER LIMIT（インピーダンス/パワーリミッターの検出）

IMP: Not applied to these models. IMP：このモデルには適用されません。
PL: Power limiter detection value PL：パワーリミッター検出の値
The voltage value of pin No. 92 of IC451 is dis- IC451 92ピンの入力電圧値を5V/256を基準にして表
played, using 5V/256 as standard. 示します。IC451 92ピンの入力電圧値により、ポート
The port (No. 3) output is controlled by using the in- （3ピン）を制御します。
put voltage value of pin No. 92 of IC451.
IMP:8 PL:245
PANEL KEY (K0/K1) PANEL KEY (K0/K1)

(Panel key of main unit) [Remote control code: –] （本機パネルキー）
A/D of the key fails to function properly when the standard キーのA/Dは基準値から±8を外れると、正常な動きをしませ
value is deviated by ±8. In this case, check the constant of ん。下表をご覧になり、各キーの分圧抵抗の定数、ハンダ不良等
partial pressure resistor, solder condition, etc. Refer to の確認をしてください。
table. （基準電圧：5V=100%）
(Reference voltage: 5 V=100 %)
K0:100 K1:100
Display (%) K0 K1
0-6 PROGRAM —
7 - 13 PROGRAM —
14 - 21 BASS/TREBLE - —
22 - 31 BASS/TREBLE + —
32 - 41 INPUT MODE MULTI CH INPUT
42 - 53 STRAIGHT FM/AM
54 - 63 TONE CONTROL A/B/C/D/E
64 - 72 PRESET/TUNING PRESET
73 - 80 SPEAKERS B PRESET
81 - 88 SPEAKERS A MEMORY
89 - 95 — TUNING MODE
96 - 100 KEY OFF KEY OFF
HTR-5935
29
HTR-5935
11. VIDEO 11. VIDEO

12. XM STATUS (U, C models) 12. XM STATUS（U、C models）

Perform the output check of XM Radio Antenna connected XM端子に接続された、XM Radio Antennaの出力チェックを行
to the XM terminal. います。
1k -1dB/44.1k 1k -1dB/44.1k
The test tone (1kHz, -1dB/44.1kHz) is output. テストトーン（1kHz、-1dB/44.1kHz）を出力します。
1k - 1dB/44
1k -61dB/44.1k 1k -61dB/44.1k
The test tone (1kHz, -61dB/44.1kHz) is output. テストトーン（1kHz、-61dB/44.1kHz）を出力します。
1k -61dB/44
Mute /44.1k Mute /44.1k

Nothing is output. 何も出力されません。
Mute /44
XM Tone/44.1k XM Tone/44.1k
The XM tone (44.1kHz) is output. XMトーン（44.1kHz）を出力します。
XM Tone/44
ISO Tone/44.1k ISO Tone/44.1k

The ISO tone (44.1kHz) is output. ISOトーン（44.1kHz）を出力します。
ISO Tone/44
HTR-5935
1k -1dB/32k 1k -1dB/32k
The test tone (1kHz, -1dB/32kHz) is output. テストトーン（1kHz、-1dB/32kHz）を出力します。
1k - 1dB/32
1k -61dB/32k 1k -61dB/32k
The test tone (1kHz, -61dB/32kHz) is output. テストトーン（1kHz、-61dB/32kHz）を出力します。
1k -61dB/32
30
HTR-5935
Mute /32k Mute /32k

Nothing is output. 何も出力されません。
Mute /32
XM Tone/32k XM Tone/32k
The XM tone (32kHz) is output. XMトーン（32kHz）を出力します。
XM Tone/32
ISO Tone/32k ISO Tone/32k

The ISO tone (32kHz) is output. ISOトーン（32kHz）を出力します。
ISO Tone/32
XM/DT Bus Power: OFF XM/DT Bus Power: OFF

The power of XM module is turned off. XMモジュールの電源をOFFします。
Bus Power:OFF
13. iPod 13. iPod

13.DOCK:NG NNN
HTR-5935
31
HTR-5935
16. IF STATUS (Input function status) 16. IF STATUS

Using the sub-menu, the status data is displayed one after サブメニュー操作により、以下のステータス情報を順次16進数で
another in the hexadecimal notation. 表示します。信号処理は、本メニュー実行前の状態を維持しま
During signal processing, the status before execution of す。
this menu is maintained.
※図中の数値は参考例です。
* Numeric values in the figure example are for reference.
DST: DSP status DST：DSPステータス
DST:3300020000
5th byte
4th byte
3rd byte
2nd byte
1st byte
<1st byte> Digital input/output setting value ＜第1バイト＞デジタル入出力設定値

Upper 4 bits: REC OUT selected / 上位4 bit REC OUT選択 /
lower 4 bits: INPUT selected 下位4 bit INPUT選択
Value Choice Preset name

0 NONE –
1 OPT FRONT –
2 OPT 1 MD/CD-R DSP-AX459 model
3 OPT 2 DVD
4 OPT 3 DTV/CBL
8 COAX 1 CD RX-V459/HTR-5940/HTR-5935 models
9 COAX 2 –
<2nd byte> / ＜第2バイト＞ <3rd byte> / ＜第3バイト＞ <4th byte> / ＜第4バイト＞

Fs information of reproduction signal / Audio code mode information of Format information of reproduction signal /
再生信号のFs情報 reproduction signal / 再生信号のフォーマット情報
再生信号のオーディオコードモード情報
Display Fs (kHz) Display Audio code Display Signal format

00 Analog 00 1+1 00 Analog
01 32 kHz 01 1/0 01 Err
02 44.1 kHz 02 2/0 10 PCM Audio

03 48 kHz 03 3/0 20 Digital Data
04 64 kHz 04 2/1 21 IEC1937
05 88.2 kHz 05 3/1 22 None PCM
HTR-5935
06 96 kHz 06 2/2 23 Unknown

07 128 kHz 07 3/2 50 dts
08 176.4 kHz 08 2/3 51 dts-CD
09 192 kHz 09 3/3 52 dts 96/24
0A Unknown NRM 0A 3/4 54 dts-ES (Matrix)
0B Unknown DBL 0B over 6.1 58 dts-ES (Discrete)
0C Unknown QUAD 0C Milti-Mono 5C dts-ES (Both)
0D Unknown 0D Milti-PCE 60 AAC
0E Undefined 0E Unknown C0 Dolby Digital
0F Undefined C1 Dolby Digital Karaoke
C4 Dolby Digital EX
FF Undefined
32
HTR-5935
<5th byte> / ＜第5バイト＞

Signal processing status information /
信号処理ステータス情報
bit Fs (kHz)
bit 7 Digital mute
bit 6 –
bit 5 6.1 (7.1) processing
bit 4 Analog mute
bit 3 –
bit 2 PCM through
bit 1 –
bit 0 dts analog mute
DMD: Decoder mode information DMD：デコーダー情報

DMD:03C00000
DIF: DIR information DIF：DIR情報

DIF:0001000600
PC: Preamble C information PC：Preamble C情報

PC :0000
CS1, 2: Channel status information CS1、2：チャンネルステータス情報

CS1:0000000000 CS2:00
HTR-5935
DEI: Decoder information DEI：デコーダー情報
DEI:0808000600
BS1-8: Bit stream information BS1-8：ビットストリーム情報

BS1:0000000000 BS8:00
MTT: Mute Trigger MTT：Mute Trigger

MTT:0018001820
33
HTR-5935
DGI: Digital information DGI：DIGITAL系情報

DGI:EE6464F95E
17. DSP BUS CHECK 17. DSP BUS CHECK

This menu is used to self-diagnose whether or not the bus TI
（DA70Y）
と外付けROM/RAMとのバス接続の正否を自己診断
connection for the TI (DA70Y) and the external ROM/RAM します。
is made properly. エラーが検出されなかった場合は、“NoEr”と表示されます。
When no error is detected, "NoEr" appears on display.
No error detected.
TI BUS:NoEr
不良検出なし
or
When this indication is displayed with in seconds or displayed alternately “NoEr” and
TI BUS:Boot
“Boot”, it is highly possible that there are errors.
数秒間この状態、またはNoErと交互に表示される場合、異常が発生している可能性がありま
す。
RDS IC:OK
No applied to these models.
or
このモデルは適用されません。
RDS IC:NG
18. SWFR CUT OFF (HTR-5935 model) 18. SWFR CUT OFF
（HTR-5935 model）
The cut off frequency setting of LFE. LFE出力のカットオフ周波数を設定できます。
Low-pass filter setting. ローパスフィルタの設定です。

18.LFE LPF 200
It can be selected 40 Hz to 200 Hz every 10 STRAIGHTキーにより、40 Hz∼200 Hzまで

Hz by the STRAIGHT key. 10 Hz単位で変更できます。
High-pass filter setting. ハイパスフィルタの設定です。

18.LFE HPF THR
HTR-5935
It can be selected 40 Hz to 200 Hz every 10 STRAIGHTキーにより、40 Hz∼200 Hzまで

Hz and through by the STRAIGHT key. 10 Hz単位とスルーに変更できます。
19. PROTECTION SETTING 19. PROTECTION SETTING

PS_Lo: 0043 PL_6_N_H:0154
20. PROTECTION HISTORY 20. PROTECTION HISTORY

Four protection histories are display. 過去のプロテクション履歴を4つまで表示します。
20-1:NoPRT 20-4:NoPRT
34
HTR-5935
21. SOFT SW 21. SOFT SW

Note) Changing the function setting may hinder the 注）機能設定を変更した場合、正常に動作しないことがありま
proper operation. す。
This menu is used to switch the function settings on P.C.B. P.C.B.上の機能設定をソフト的に切り替えて、製品を動作させる

through the software so as to activate the product. 機能です。
The protection function follows the P.C.B. settings. When プロテクション機能は、P.C.B.の設定にしたがいます。AC接続
connected to AC or in the maker preset state, the unit is またはメーカープリセットで、P.C.B.の設定に初期化されます。
initialized to the P.C. B. setting. Display of each function 初期化後の各機能の表示は、P.C.B.上の設定によります。操作
after initialization varies depending on settings on P.C.B. は、サブメニューを選んだ後、STRAIGHTキーで切り替えま
The operation mode can be changed by selecting the sub- す。
menu and then using the STRAIGHT key.
SW MODE: PCB, MODEL or FNC can be selected. SW MODE：PCB、MODELまたはFNCを選択できます。
21.SW :PCB
MODEL SETTING: 759SE, V659, H5960, V559, H5950, MODEL SETTING：759SE、V659、H5960、V559、

V459 or H5935 can be selected. (SW MODE: Selectable H5950、V459、H5935のいずれかを選択できます。（SW
when MODEL has been selected.) MODE：MODEL時選択できます。）
21.MODEL:V459
DESTINATION: J, U, C, R, T, K, A, B, G (E) or L can be DESTINATION：J、U、C、R、T、K、A、B、G（E）、Lのい

selected. (SW MODE: Selectable when MODEL has been ずれかを選択できます。（SW MODE：MODEL時選択できま
selected.) す。）
21.DEST :G
TUNER DESTINATION: J, UC, ABG or RL can be selected. TUNER DESTINATION：J、UC、ABG、RLのいずれかを選
(SW MODE: Selectable when FNC has been selected.) 択できます。（SW MODE：FNC時選択できます。）
HTR-5935
21.TuDst:ABG
TUNER TYPE: NRM, RDS or XM can be selected. (SW TUNER TYPE：NRM、RDS、XMのいずれかを選択できま

MODE: Selectable when FNC has been selected.) す。（SW MODE：FNC時選択できます。）
21.TuDyp:RDS
VIDEO FORMAT: NTSC or PAL can be selected. (SW VIDEO FORMAT：NTSCまたはPALを選択できます。（SW

MODE: Selectable when FNC has been selected.) MODE：FNC時選択できます。）
21.VIDEO:PAL
35
HTR-5935
ZONE2: NOT or EXIST can be selected. (SW MODE: ZONE2：NOTまたはEXISTを選択できます。（SW MODE：

Selectable when FNC has been selected.) FNC時選択できます。）
21.ZONE2:EXIST
AAC: NOT or EXIST can be selected. (SW MODE: AAC：NOTまたはEXISTを選択できます。

（SW MODE：FNC
Selectable when FNC has been selected.) 時選択できます。）
21.AAC :NOT
TUNER: NOT or EXIST can be selected. (SW MODE: TUNER：NOTまたはEXISTを選択できます。（SW MODE：

21.TUNER:EXIST
ZONE2 AMP: NOT or EXIST can be selected. (SW ZONE2 AMP：NOTまたはEXIST を選択できます。（SW
MODE: Selectable when FNC has been selected.) MODE：FNC時選択できます。）
21.Z2Amp:NOT
OSD: NOT or EXIST can be selected. (SW MODE: OSD：NOTまたはEXISTを選択できます。（SW MODE：FNC

Selectable when FNC has been selected.) 時選択できます。）
21.OSD :EXIST
YPAO: NOT or EXIST can be selected. (SW MODE: YPAO：NOTまたはEXISTを選択できます。（SW MODE：

21.YPAO :NOT
HTR-5935
36
HTR-5935
22. SOFTWARE VERSION 22. SOFTWARE VERSION

The version, checksum and the port specified by the ソフトウェアのバージョン、チェックサム、マイコンの指定ポー
microprocessor are displayed. The signal is processed トを表示します。
using EFFECT OFF. The checksum is obtained by adding 信号はエフェクトOFFです。チェックサムは、プログラムエリア
the data at every 16 bits for each program area and 別にデータを16ビットごとに加算していき、4桁の16進データ
expressing the result as a 4-figure hexadecimal data. で現したものです。
* Numeric values in the figure example are for reference. ※図中の数値は参考例です。
Software version of microprocessor / マイコンのソフトウェアバージョン

VER. AOO8
Checksum value of microprocessor / マイコンのチェックサム

CHECK SUM:1F4A
Software modules version of microprocessor /

0:18 D:23 X:A9
マイコンのモジュール別ソフトウェアバージョン
O: Operation D: DSP X: XM
The condition of ports for model detection / モデル判別ポートの状態

PORT:00000100
Software version of TI (DSP) / TI（DSP）のソフトウェアバージョン

TI VER.10
Checksum value of TI (DSP) / TI（DSP）のチェックサム

TiSUM:41A234F5
Checksum value of EEPROM / EEPROMのチェックサム

EE SUM:0000 (Not applied to these models. / このモデルには適用されません。)
PORT:00000100
Model type 0 Type3 Type2 Type1 Type0 Model
Model type 1 RX-V459
Model type 2 – 1 1 1 DSP-AX459
Model type 3 HTR-5940
– 1 1 0 HTR-5935
HTR-5935
23. TI (DSP) BOOT 23. TI（DSP）BOOT
The rewriting mode of TI (DSP) software. TI（DSP）のソフトウェア書き換えモードです。
(Not applied to these models.) （このモデルには適用されません。）
23.TI BOOT ?
37
HTR-5935
■ AMP ADJUSTMENT / アンプ部調整

Confirmation of Idling Current of MAIN (1) P. C. B. メイン（1）
基板のアイドリング電流の確認
• Right after power is turned on, confirm that each mea- ● 電源投入直後、R1149（FRONT Lch）、R1150（FRONT
sured voltage across the terminals of R1149 (FRONT Rch）
、R1153
（CENTER）
、R1154（SURROUND Lch）
、
Lch), R1150 (FRONT Rch), R1153 (CENTER), R1154 R1152（SURROUND Rch）、R1151（SURROUND
(SURROUND Lch), R1152 (SURROUND Rch), R1151 BACK）の端子間電圧を測定し、0.1 mVから10.0 mV.の間で
(SURROUND BACK) is between 0.1 mV and 10.0 mV. あることを確認してください。
• If it exceeds 10.0 mV, open (cutoff) R1104 (FRONT ● 電圧が10 mVを超えている場合は、R1104 （FRONT Lch）
、
Lch), R1106 (FRONT Rch), R1112 (CENTER), R1114 R1106（FRONT Rch）、R1112（CENTER）、R1114
(SURROUND Lch), R1110 (SURROUND Rch), R1108 （SURROUND Lch）、R1110（SURROUND Rch）、
(SURROUND BACK) and reconfirm the voltage. R1108（SURROUND BACK）
をカットし、電圧を再確認し
てください。
Attention
If the measured voltage exceeds 10.0 mV. after an am- 注意
plifier repair, first check for a defective component be- パワーアンプ修理後に10.0 mV.を超えている場合は、抵抗を
fore cutting the bias resistor. カットする前に故障箇所を調べてください。
• Confirm that the voltage is 0.2 mV-15.0 mV. after 60 ● 60分後、電圧が0.2 mV∼15.0 mV.であることを確認して
minutes. ください。
0.1mV ~ 10.0mV 0.1mV ~ 10.0mV

(DC) (DC)
R1149 (FRONT Lch) R1154 (SURROUND Lch)

R1150 (FRONT Rch) R1152 (SURROUND Rch)
R1153 (CENTER) R1151 (SURROUND BACK Rch)
Cut off
カット
R1104 (FRONT Lch)

R1106 (FRONT Rch)
R1112 (CENTER)
R1114 (SURROUND Lch)

R1110 (SURROUND Rch)
R1108 (SURROUND BACK Rch)
HTR-5935
38
HTR-5935
■ DISPLAY DATA
● V3000 : HNA-17MM03T (WG474000) ● ANODE CONNECTION
} 1 17G 16G 15G 14G 13G~1G
P1 S1 S1 1-1 1-1
P2 W1 2-1 2-1
PATTERN AREA P3 W2 3-1 3-1
P4 4g 4-1 4-1
P5 1a 5-1 5-1
P6 1b 1-2 1-2
● PIN CONNECTION P7 1c 2-2 2-2

P8 1d 3-2 3-2
Pin No. 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
P9 1e 4-2 4-2
Connection F2 F2 NP NP P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31
P10 1f 5-2 5-2
Pin No. 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P11 1g 1-3 1-3
Connection P32 P33 P34 P35 P36 P37 NX NX NX NX NX NX NX 17G 16G 15G 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP F1 F1 P12 2a 2-3 2-3
Note : 1) Fn ..... Filament pin 2) nG ..... Grid pin 3) Pn ..... Anode pin 4) NP ..... No pin 5) NX ..... No extended pin
P13 2b 3-3 3-3
P14 2c 4-3 4-3
P15 2d 5-3 5-3
P16 2e 1-4 1-4
● GRID ASSIGNMENT P17 2f 2-4 2-4
17G 16G 15G P18 2g 3-4 3-4
P19 3g 4-4 4-4
P20 3b 5-4 5-4
P21 3a 1-5 1-5
P22 2-5 2-5
P23 R1 3-5 3-5
1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G 13G 14G
P24 R2 4-5 4-5
P25 R3 5-5 5-5
P26 R4 1-6 1-6
1-1 2-1 3-1 4-1 5-1 W1
P27 R5 2-6 2-6
1-2 2-2 3-2 4-2 5-2 P28 3-6 3-6
1-3 2-3 3-3 4-3 5-3
S1 P29 4-6 4-6
1-4 2-4 3-4 4-4 5-4 P30 – 5-6 5-6
(16G)
1-5 2-5 3-5 4-5 5-5 P31 – 1-7 1-7
1-6 2-6 3-6 4-6 5-6

P32 – 2-7 2-7
R1
W2 R2 P33 – 3-7 3-7
1-7 2-7 3-7 4-7 5-7
1a 2a R4 R5 P34 – 4-7 4-7
S1 R3
(1G~14G) P35 – 5-7 5-7
1f 1b 3a
4g 1g 3b (17G) P36 – –
3g
3b P37 – –
1e 1c 3a
1d
(15G)
39
HTR-5935
HTR-5935
■ DISPLAY DATA
● V3000 : 17-BT-26GNK (WG473900) ● ANODE CONNECTION
} 1 1G~13G 14G 15G 16G 17G
1P 1-1 1-1 S2 S1
2P 2-1 2-1 S26 S6
PATTERN AREA 3P 3-1 3-1 S27 S7
4P 4-1 4-1 S22 S8
5P 5-1 5-1 1a S9
6P 1-2 1-2 1b S10
● PIN CONNECTION 7P 2-2 2-2 1c S11

8P 3-2 3-2 1d S12
Pin No. 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
9P 4-2 4-2 1e
Connection F2 NX NP NP P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31
10P 5-2 5-2 1f S20
Pin No. 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 11P 1-3 1-3 1g
Connection P32 P33 P34 P35 P36 P37 NX NX NX NX NX NX NX 17G 16G 15G 14G 13G 12G 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP NX F1 12P 2-3 2-3 2a
Note : 1) F1, F2 ..... Filament pin 2) NP ..... No pin 3) NX ..... No extend pin 4) 1G~17G ..... Grid pin
13P 3-3 3-3 2b
14P 4-3 4-3 2c
15P 5-3 5-3 2d
16P 1-4 1-4 2e
● GRID ASSIGNMENT 17P 2-4 2-4 2f
17G 16G 15G 18P 3-4 3-4 2g S21
19P 4-4 4-4 S23
20P 5-4 5-4 S24 S3
21P 1-5 1-5 S25 S5
22P 2-5 2-5 S4
23P 3-5 3-5 S15
1G 2G 3G 4G 5G 6G 7G 8G 9G 10G 11G 12G 13G 14G
24P 4-5 4-5 S13 S16
1-1 2-1 3-1 4-1 5-1
S1
25P 5-5 5-5 S14 S17
1-2 2-2 3-2 4-2 5-2 26P 1-6 1-6 S18
1-3 2-3 3-3 4-3 5-3 27P 2-6 2-6 S19
S6 S7 S8 S9 S10 S11 S12 S13 S14
1-4 2-4 3-4 4-4 5-4
28P 3-6 3-6
1-5 2-5 3-5 4-5 5-5

29P 4-6 4-6
(16G) (15G)
30P 5-6 5-6 –
1-6 2-6 3-6 4-6 5-6
31P 1-7 1-7 –
1-7 2-7 3-7 4-7 5-7
32P 2-7 2-7 –
2f S2
(1G~14G) S15 1b 2b 33P 3-7 3-7 –
S16 1g s25
1a 2a s24
S18 S19
34P 4-7 4-7 –
S22 1f 2g s23
S17 S20 S21 35P 5-7 5-7 –
1e s24 s25
(17G) 1d 2d 36P – –
1c 2c
2e
37P – –
S26
S27
40
HTR-5935
■ IC DATA
IC2 : M30625MHP-A98GP (DSP P.C.B.)
Microprocessor
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
P2_0/AN2_0/A0(/D0/-)
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P3_0/A8(/-/D7)
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P1_2/D10
P1_3/D11
P1_4/D12
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P1_1/D9
P3_1/A9
P12_0
P12_1
P12_2
P12_3
P12_4
VCC2
VSS
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P1_0/D8 103 64 P12_5
P0_7/AN0_7/D7 104 63 P12_6
P0_6/AN0_6/D6 105 62 P12_7
P0_5/AN0_5/D5 106 61 P5_0/WRL/WR
P0_4/AN0_4/D4 107 60 P5_1/WRH/BHE
P0_3/AN0_3/D3 108 59 P5_2/RD
P0_2/AN0_2/D2 109 58 P5_3/BCLK
P0_1/AN0_1/D1 110 57 P13_0
P0_0/AN0_0/D0 111 56 P13_1
P11_7 112 55 P13_2
P11_6 113 54 P13_3
P11_5 114 53 P5_4/HLDA
P11_4
P11_3
115
116
M16C/62P Group (M16C/62P) 52
51
P5_5/HOLD
P5_6/ALE
P11_2 117 50 P5_7/RDY/CLKOUT
P11_1 118 49 P13_4
P11_0 119 48 P13_5
P10_7/AN7_KI3 120 47 P13_6
P10_6/AN6_KI2 121 46 P13_7
P10_5/AN5_KI1 122 45 P6_0/CTS0/RTS0
P10_4/AN4_KI0 123 44 P6_1/CLK0
P10_3/AN3 124 43 P6_2/RXD0/SCL0
P10_2/AN2 125 42 P6_3/TXD0/SDA0
P10_1/AN1 126 41 P6_4/CTS1/RTS1/CTS0/CLKS1
AVSS 127 40 P6_5/CLK1
P10_0/AN0 128 39 VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/OUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
P14_1
P14_0
BYTE
CNVSS
P8_7_XCIN
P8_6_XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P6_7/TXD1/SDA1
VCC1
P6_6/RXD1/SCL1
P7_1/RXD2/SCL2/TA0IN/TB5IN(1)
P7_0/TXD2/SDA2/TA0OUT(1)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
8 8 8 8 8 8 8
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6

Port P7
<VCC2 ports> (4) <VCC1 ports> (4) 8
Internal peripheral functions
D/A converter Watchdog timer
Timer (16 bit) (10 bit x 8 channels (15 bits)
Expandable up to 26 channels)
Port P8
XIN-XOUT
Output (timer A): 5 UART or XCIN-XCOUT
7
Input (timer B): 6 clock synchronous serial I/O PLL frequency synthesizer
<VCC1 ports> (4)
HTR-5935
Three-phase motor (8 bit x 8 channels) On-chip oscillator
Port P8_5
control circuit Watchdog timer Clock synchronous serial I/O

(Polynomial: X16+X12+X5+1) (8 bit x 2 channels)
M16C/60 series 16-bit CPU core Memory

R0H R0L SB
Port P9
Watchdog timer ROM (1)

R1H R1L USP
(15 bits) R2
ISP
8
R3 RAM (2)
DMAC INTB
(2 channels) A0 PC
A1
Port P10
FB FLG
D/A converter
(8 bit x 2 channels) Multiplier
8
<VCC1 ports> (4) <VCC2 ports> (4)

Port P11 Port P14 Port P12 Port P13
(3) (3) (3) (3)
8 2 8 8
NOTES:
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1=VCC2.
41
HTR-5935

Microprocessor
I/O
No. Port Name Terminal Name Function
PowerOn Pure Direct Standby Sleep
1 Vref Vref MCU MCU MCU AD reference
2 Avcc Avcc MCU MCU MCU AD power supply
3 P97/Adtrg/Sin4 CEFD O O O FL Driver CE
MOD0 I MODEL distinction 0
4 P96/ANEX1/SOUT4 DTFD SO O O FL Driver TxD
5 P95/ANEX0/CLK4 CKFD SO O O FL Driver CLOCK
6 P94/DA1/TB4in LC DA O O Limiter control output
7 P93/DA0/TB3in XMPWR O O O XM/DT BUS POWER CONTROL (U model)
8 P92/TB2in/SOUT3 SDM SO O O Serial data output to DIR, TI (DA70Y), DAC / DIR: 4M, LSBF/TI: 1M, MSBF
9 P91/TB1in/SIN3 SDD SI O O Serial data input from DIR, TI (DA70Y)
10 P90/TB0in/CLK3 SCK SO O O Serial clock output to DIR, TI (DA70Y) DAC
11 P141 /ICCNV O O O O Reset I2C device of CONV
12 P140 NW_RST O O O Reset signal to Net-module
13 BYTE BYTE MCU MCU MCU Vss : When single chip mode is used
14 CNVss CNVss MCU MCU MCU Vss : When single chip mode is used, Vcc : When flash writing is used
15 P87/Xcin MUTETI O O O MUTE of TI decoder DSP DA70Y (HI=MUTE)
16 P86/Xcout /TIBUSY I O O TI BUSY detection / CDDA writing DATA input
17 /RESET /RES MCU MCU MCU Reset
18 Xout Xout MCU MCU MCU Oscillation output
19 Vss Vss MCU MCU MCU Ground for microprocessor
20 Xin Xin MCU MCU MCU Oscillation input
21 Vcc1 Vcc MCU MCU MCU Power supply +5V for microprocessor
22 P85/NMI NMI MCU MCU MCU No used, connect Vss
23 P84/INT2 /INTTI IRQ O O Interrupt of TI decoder DSP DA70Y
24 P83/INT1 /INTDIR IRQ O O Interrupt of DIR
25 P82/INT0 /VSY IRQ O O O
26 P81/TA4in/U /CSDIR O O O Chip enable of DIR
27 P80/TA4out/U /CSTI O O O Chip enable of TI decoder DSP DA70Y
28 P77/TA3in /CSDAC O O O Chip enable of DAC (2ch/8ch common)
29 P76/TA3out /ICDIR O O O DIR reset
30 P75/TA2in/W /ICTI O O O Reset of TI decoder DSP DA70Y
31 P74/TA2out/W /SPIRDY I O O TI DA601 Serial Ready / WCK input for CDDA writing
32 P73/CTS2/RTS2/TA1in/V /CEEEP O O O EEPROM CE
33 P72/CLK2/TA1out/V FET O O O Control of flash writing
34 P71/RXD2/SCL2/TA0in/TB5in DRXM SI O O XMDT IC RxDU (U model)
35 P70/TXD2/SDA2/TA0out DTXM SO O O XMDT IC TxDU
36 P67/TXD1/SDA1 SDA SO I I I
TXDF SO Data transmission terminal of AF220
38 P66/RXD1/SCL1 SCL SO I I I
HTR-5935
RXDF SO Flash ROM RxD

39 Vss Vss MCU MCU MCU Ground for microprocessor
40 P65/CLK1 N.C. O O O
CLKF SO Clock transmission terminal signal output for AF220
41 P64/CTS1/RTS1/CTS0/CLKS1 BSY O BUSY signal output for AF220
42 P63/TXD0/SDA0 TXDi SO O O serial data output for iPod
TXDNW SO O O
43 P62/RXD0/SCL0 RXDi SI O O Serial data input for iPod
RXDNW SI O O
44 P61/CLK0 iPDET I O O iPod detection
45 P60/CTS0/RTS0 iPAP I O O IPod accessories power detection
46 P137 Z2RY O O O
YST O O O YST amp control (HTR-5935 model)
47 P136 /4ohm O O O IMPEDANCE control / ±B voltage control
48 P135 SBRY O O O SURROUND BACK SP relay output
49 P134 SPC O O O CENTER and SURROUND SP relay output
50 P57/RDY/CLKout SPB O O O FRONT B SP relay output
42
HTR-5935

Microprocessor
I/O
51 P56/ALE SPA O O O FRONT A SP relay output
52 P55/HOLD /EMP I For FLASH writing (LO)
53 P54/HLDA PRI I O O Protection overcurrent detection
54 P133 PSV O O O Power Save
55 P132 PRY O O O Power relay output
56 P131 MASTER I O O MASTER ON/OFF
57 P130 /BLK O O O FL Driver turning off
58 P53/BCLK ISA I O O INPUT Selector Rotary A
59 P52/RD ISB I O O INPUT Selector Rotary B
60 P51/WRH/BHE TONEA I O O Tone Control Rotary A
61 P50/WRL/WR /CE I For FLASH writing (HI)
62 P127 TONEB I O O Tone Control Rotary B
63 P126 VRA I O O Volume Rotary A
64 P125 VRB I O O Volume Rotary B
65 P47/CS3 VIA O O O O VIDEO Selector A
66 P46/CS2 VIB O O O O VIDEO Selector B
67 P45/CS1 VIC O O O O VIDEO Selector C
68 P44/CS0 S/V O O O O
69 P43/A19 /CES O O O O OSD Enable
70 P42/A18 SVIDD I O O O S-Video Signal Detector
71 P41/A17 BYPASS O O O O VIDEO Bypass/ conversion change
72 P40/A16 /INTCNV I O O O
73 P37/A15 /VR1 O O O O VIDEO Rec Out 1 MUTE
74 P36/A14 /VR2 O O O O
75 P35/A13 /PURD O O I
76 P34/A12 /MON O O O O VIDEO Mon Out MUTE
77 P33/A11 CPNTD I O O O Component Signal Detector (DVD)
78 P32/A10 CMP0 O O O O Component Selector 0
79 P31/A9 CMP1 O O O O Component Selector 1
80 P124 CBYPASS O O O O
81 P123 /CNONE O O O O Component Mon Out MUTE
82 P122 TRIG O O O DC TRIGGER input
83 P121 TMT O O O TUNER MUTE
84 P120 SDRN I O O RDS RxDBG
86 P30/A8 SCKN O O O RDS IC Clock (G model)
O O O O
87 Vss Vss MCU MCU MCU Ground for micro-processor
88 P27/A7 SDTN O O O RDS IC TxD (G model)
HTR-5935
O O O O
89 P26/A6 RDSE O O O RDS Enable (G model)
/ICXM O O O DABIC IC reset (U model)
90 P25/A5 SCKP O O O PLL IC Clock
91 P24/A4 SDTP O O O PLL IC TxD
92 P23/A3 CEP O O O PLL IC Enable
93 P22/A2 SDRP I+ O O PLL IC RxD
94 P21/A1 /ST I+ O O TUNER /ST
95 P20/A0 TUNED I+ O O TUNED
96 P17/D15/INT5 PDET IRQ IRQ O Power Down DETECT INT
97 P16/D14/INT4 /PSW IRQ IRQ O Interrupt MASTER / MAIN / Zone2 Power SW
98 P15/D13/INT3 REM IRQ IRQ O Remote Control input
99 P14/D12 /HP I O O HEAD PHONE detection
100 P13/D11 /MTHP O O O HEAD PHONE MUTE input
101 P12/D10 /MTFS O O O MUTE Front/Surround, PreOUT
102 P11/D9 /MTCT O O O MUTE Center
103 P10/D8 /MTSW O O O MUTE SW
104 P07/D7 /MTZ2 O O O Zone 2 MUTER
105 P06/D6 CKEV O O O Electron volume IC Clock
43
HTR-5935

Microprocessor
I/O
106 P05/D5 DTEV O O O Electron volume IC DATA
107 P04/D4 CKZ2 O O O Zone2 Selector (BD3841) Clock (R model)
108 P03/D3 DTZ2 O O O Zone2 Selector (BD3841) DATA (R model)
109 P02/D2 N.C. O O O
110 P01/D1 N.C. O O O
111 P00/D0 CKEX O O O EX. INPUT Selector Clock
112 P117 DTEX O O O EX. INPUT Selector DATA
113 P116 CKBD O O O
114 P115 DTBD O O O
115 P114 DTSEL O O O
116 P113 CKSEL O O O
117 P112 CESEL O O O
MOD4 I MODEL distinction
118 P111 ICEV O O O
119 P110 CEEV O O O
MOD3 I
120 P107/AN7/KI3 PRV2 AD O O
121 P106/AN6/KI2 PRV1 AD O O AD protection power-supply voltage detection
122 P105/AN5/KI1 PRD AD O O AD protection DC detection
123 P104/AN4/KI0 PLDET AD O O AD POWER LIMITTER detection
124 P103/AN3 THM AD O O AD temperature detection
125 P102/AN2 ADKEY0 AD O O AD Key 0
126 P101/AN1 ADKEY1 AD O O AD Key 1
127 Avss Avss MCU MCU MCU Ground for AD
128 P100/AN0 DEST AD O O AD model detection
RX-V459/HTR-5940/DSP-AX459/HTR-5935
Key Input(A-D) Pull-Up Resistance 10 k-Ohms
Ohm +0.0k +1.0k +1.0k +1.5k +2.2k +3.3k +4.7k +4.7k +6.8k +10.0k +22.0k
V ~0.3 ~0.7 ~1.0 ~1.5 ~2.0 ~2.6 ~3.1 ~3.4 ~3.7 ~4.0 ~4.4
ADKEY0 PROGRAM PROGRAM BASS/TREBLE BASS/TREBLE PURE
INPUT MODE STRAIGHT TONE CONTROL PRESET/TUNING SPEAKER B SPEAKER A
94pin/AN2 < > + + DIRECT
ADKEY1 MULTI CH PRESET/TUNING PRESET/TUNING
– – – – FM/AM A/B/C/D/E MEMORY TUNING MODE
95pin/AN1 INPUT < >
MODEL Distinction Port / モデル判別ポート

Pin Function Name RX-V459/HTR-5940/DSP-AX459 HTR-5935
3 P97/Adtrg/Sin4 CEFD/MOD0 1 0
HTR-5935
69 P43/A19 CES/MOD1 1 1
114 P115 DTBD/MOD2 1 1
119 P110 CEEV/MOD3 0 0
117 P112 CESEL/MOD4 0 0
Distinction for AD Port / 仕向け先判別ポート

Pull-Up Resistance 10 k-Ohms
Ohm 0.0k 1.2k 2.7k 4.7k 6.8k 10.0k 15.0k 27.0k 47.0k 100.0k ∞
V 0-0.2 0.3-0.8 0.9-1.3 1.4-1.8 1.8-2.2 2.3-2.7 2.8-3.3 3.4-3.8 3.9-4.3 4.4-4.7 4.8-5.0
A-D (5V=255) 0-13 14-40 41-68 69-92 93-115 116-140 141-170 171-198 199-221 222-244 245-255
DEST 129pin J U, C – R T K A – G, E L –
44
HTR-5935
IC56 : LC89057W-VF4-E (DSP P.C.B)

Digital Audio Interface Transceiver
EMPHA/UO
AUDIO/VO
DGND
DGND
XMCK
RERR
XOUT
DVDD
DVDD
CKST
XIN
INT
36
35
34
33
32
31
30
29
28
27
26
25
DO 37 24 SDIN
DI 38 23 SLRCK
CE 39 22 SBCK
CL 40 21 RDATA
XMODE 41 20 RLRCK
DGND 42 19 DVDD
DVDD 43 LC89057W-VF4-E 18 DGND
TMCK/PIO0 44 17 RBCK
TBCK/PIO1 45 16 RMCK
TLRCK/PIO2 46 15 AGND
TDATA/PIO3 47 14 AVDD
TXO/PIOE 48 13 LPF
10
11
12
1
2
3
4
5
6
7
8
9
*: Pull-down resistor internal
RXOUT
*RX0
RX1
RX2
RX3
DGND
DVDD
*RX4
RX5/VI
*RX6/UI
DVDD
DGND
EMPHA/UO
AUDIO/VO
XMODE
INT
CE
CL
CI
32 33 35 40 39 38 41
RXOUT 1
RX0 2 Microcontroller
Cbit, Ubit 37 DO
RX1 3 I/F
RX2 4 36 RERR
Input
RX3 5 Selector
RX4 8
Demodulation Data
& 21 RDATA
RX5/VI Selector
9 Lock Detect
RX6/UI 10
24 SDIN
16 RMCK
LPF 13 PLL
17 RBCK
Clock 20 RLRCK
TMCK/PIO0 44 Selector 22 SBCK
TBCK/PIO1 45 Modulation 1/N
& 23 SLRCK
TLRCK/PIO2 46
HTR-5935
Parallel Port
TDATA/PIO3 47
TXO/PIOEN 48
29 28 27 34
XIN
XOUT
XMCK
CKST
45
HTR-5935
IC56 : LC89057W-VF4-E (DSP P.C.B)

Digital Audio Interface Transceiver
No. Name I/O Function

1 RXOUT O Input bi-phase selection data output pin
2 RX0 Is TTL-compatible digital data input pin
3 RX1 I Coaxial-compatible digital data input pin with built-in amplifier
6 DGND Digital GND
7 DVDD Digital power supply
9 RX5/VI Is TTL-compatible digital data / Validity flag input pin for modulation
10 RX6/UI Is TTL-compatible digital data / User data input pin for modulation
11 DVDD PLL digital power supply
12 DGND PLL digital GND
13 LPF O PLL loop filter connection pin
14 ACDD PLL analog power supply
15 AGND PLL analog GND
16 RMCK O R system clock output pin (256fs, 512fs, XIN, VCO)
17 RBCK O/I R bit clock input/output pin
18 DGND Digital GND
20 RLRCK O/I R LR clock input/output pin (fs)
21 RDATA O Serial audio data input pin
22 SBCK O S bit clock output pin (32fs, 64fs, 128fs)
23 SLRCK O S LR clock output pin (fs/s, fs, 2fs)
24 SDIN Is Serial audio data input pin
25 DGND Digital GND
27 XMCK O Oscillation amplifier output pin
28 XOUT O Crystal resonator connection output pin
29 XIN I Crystal resonator connection, external supply clock input pin (24.576 MHz or 12.288 MHz)
31 DGND Digital GND
32 EMPHA/UO I/O Emphasis information / U data output / Chip address setting pin
33 AUDIO/VO I/O Non-PCM output / V flag output / Chip address setting pin
34 CKST I/O Clock switch transition period signal / Demodulation master or slave function switch pin
35 INT I/O Microcontroller interrupt output / Modulation or general-purpose I/O switch pin
36 RERR O PLL clock error, data error flag output
37 DO O Microcontroller I/F read data output pin (3-state)
HTR-5935
38 DI Is Microcontroller I/F write data input pin

39 CE Is Microcontroller I/F chip enable input pin
40 CL Is Microcontroller I/F clock input pin
41 XMODE Is System reset input pin
42 DGND Digital GND
44 TMCK/PIO0 I/O Modulation 256fs system clock input / General-purpose I/O input/output pin
45 TMCK/PIO1 I/O Modulation 64fs bit clock input / General-purpose I/O input/output pin
46 TLRCK/PIO2 I/O Modulation fs clock input / General-purpose I/O input/output pin
47 TLRCK/PIO3 I/O Modulation serial audio data input / General-purpose I/O input/output pin
48 TXO/PIOEN O/I Modulation data output / General-purpose I/O enable input pin
1) Input/output I or O = -0.3 to 3.6V, Is = -0.3 to 5.5V

2) Pins 32 and 33 are latch address setting input pins when pin 41 = "L".
3) Pin 34 is a demodulation function master or slave setting input pin when pin 41 = "L".
4) Pin 35 is a modulation function or general-purpose I/O function switch setting input pin when pin 41 = "L".
5) Perform ON/OFF for all power supplies with the same timing as a latch-up countermeasure.
46
HTR-5935
IC60 : D70YE101RFP250 (DSP P.C.B)

Decoder/Post Processor
* No replacement part available. / サービス部品供給なし
SPI0_ENA/I2C1_SDA
SPI0_SCS/I2C1_SCL
SPI0_CLK/I2C0_SCL
EM_CS[2]
EM_CS[0]
EM_BA[0]
EM_BA[1]
EM_A[10]
EM_A[11]
EM_RAS
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_RW
EM_OE
CVDD
CVDD
CVDD
CVDD
DVDD
DVDD
DVDD
DVDD
Vss
Vss
Vss
Vss
Vss
Vss
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Vss 109 72 Vss
SPI0_SIMO 110 71 EM_CKE
SPI0_SOMI/I2C0_SDA 111 70 EM_CLK
DVDD 112 69 Vss
AXR0[0] 113 68 DVDD
Vss 114 67 EM_WE_DQM[1]
AXR0[1] 115 66 EM_D[8]
AXR0[2] 116 65 CVDD
AXR0[3] 117 64 EM_D[9]
Vss 118 63 EM_D[10]
AXR0[4] 119 62 Vss
AXR0[5]/SPI1_SCS 120 61 EM_D[11]
AXR0[6]/SPI1_ENA 121 60 DVDD
AXR0[7]/SPI1_CLK 122 59 EM_D[12]
CVDD 123 58 EM_D[13]
Vss 124 57 CVDD
DVDD 125 56 EM_D[14]
AXR0[8]/AXR1[5]/SPI1_SOMI 126 55 EM_D[15]
AXR0[9]/AXR1[4]/SPI1_SIMO 127 54 Vss
CVDD 128 53 CVDD
Vss 129 52 EM_D[0]
AXR0[10]/AXR1[3] 130 51 EM_D[1]
AXR0[11]/AXR1[2] 131 50 DVDD
CVDD 132 49 EM_D[2]
Vss 133 48 EM_D[3]
AXR0[12]/AXR1[1] 134 47 Vss
AXR0[13]/AXR1[0] 135 46 EM_D[4]
DVDD 136 45 EM_D[5]
AXR0[14]/AXR2[1] 137 44 CVDD
AXR0[15]/AXR2[0] 138 43 EM_D[6]
ACLKR0 139 42 DVDD
Vss 140 41 EM_D[7]
AFSR0 141 40 Vss
ACLKX0 142 39 EM_WE_DQM[0]
AHCLKR0/AHCLKR1 143 38 EM_WE
AFSX0 144 37 EM_CAS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
Vss
AHCLKX0/AHCLKX2
AMUTE0
AMUTE1
AHCLKX1
Vss
ACLKX1
CVDD
ACLKR1
DVDD
AFSX1
AFSR1
Vss
RESET
Vss
CVDD
CLKIN
Vss
TMS
CVDD
TRST
OSCVss
OSCIN
OSCOUT
OSCVDD
Vss
PLLHV
TDI
TDO
Vss
DVDD
EMU[0]
CVDD
EMU[1]
TCK
Vss
Program/Data JTAG EMU

256 RAM
D1
256K Bytes McASP0
Data 64 32
R/W 16 Serializes
Program/Data
C67x+CPU 256 ROM Page1 32
D2 Memory 256K Bytes
Data 64 Controller 32
McASP DMA Bus
R/W Program/Data McASP1

256 ROM Page2 32 6 Serializes
Program 256K Bytes
I/O INT Fetch
Program/Data 32
HTR-5935
McASP2
256 ROM Page3 2 Serializes
256
256K Bytes 32 DIT Only
Program 32 SPI1
CSP 32 32
Peripheral Configuration Bus
Cache 256
32K Bytes PMP DMP
32 SPI0
32 32
32 I2C0
High-Performance
32
Crossbar Switch 32 I2C1
32 32 32 32
32 RT1
I/O Interrupts MAX0 CONTROL MAX1 Events 32 PLL

Out in
EMIF
dMAX
Peripheral Interrupt and DMA Events
47
HTR-5935

PIN NO. SIGNAL NAME TYPE(1) PULL(2) GPIO(3) DESCRIPTION

1 Ground(Vss)
2 AHCLKX0/AHCLKX2 IO - Y McASP0 and McASP2 Transmit Master Clock
3 AMUTE0 IO - Y McASP0 MUTE Output
4 AMUTE1 IO - Y McASP1 MUTE Output
5 AHCLKX1 IO - Y McASP1 Transmit Master Clock
6 Ground(Vss)
7 ACLKX1 IO - Y McASP1 Transmit Bit Clock
8 Core Supply (CVpp)
9 ACLKR1 IO - Y McASP1Receive Bit Clock
10 IO Supply (DVpp)
11 AFSX1 IO - Y McASP1 Transmit Frame Sync (L/R Clock)
12 AFSR1 IO - Y McASP1Receive Frame Sync (L/R Clock)
13 Ground(Vss)
14 RESET IO - N Device reset pin
15 Ground(Vss)
17 CLKIN IO - N Alternate clock input (3.3-V LVCMOS Input)
18 Ground(Vss)
19 TMS IO IPU N Test mode Select
21 TRST IO IPU N Test Reset
22 OSCVss PWR - N Oscillator Vss tap point (for filter only)
23 OSCIN IO - N 1.2-V Oscillator Input
24 OSCOUT O - N 1.2-V Oscillator Output
25 OSCVpp PWR - N Oscillator 1.2-V Vpp tap point (for filter only)
26 Ground(Vss)
27 PLLHV PWR - N PLL 3.3-V Supply Input (requires external filter)
28 TDI IO IPU N Test Data In
29 TDO OZ IPU N Test Data Out
30 Ground(Vss)
31 IO Supply (DVpp)
32 EMU[0] IO IPU N Emulation Pin 0
34 EMU[1] IO IPU N Emulation Pin 1
35 TCK IO IPU N Test Clock

36 Ground(Vss)
37 EM_CAS O - N SDRAM Column Address Strobe
HTR-5935
38 EM_WE O - N SDRAM Write Enable

39 EM_WE_DQM[0] O - N Write Enable or Byte Enable for EM_D[7:0]
40 Ground(Vss)
41 EM_D[7] IO - N EMIF Data Bus [lower 16 Bits]
42 IO Supply (DVpp)
47 Ground(Vss)
50 IO Supply (DVpp)
54 Ground(Vss)
48
HTR-5935


60 IO Supply (DVpp)
62 Ground(Vss)
67 EM_WE_DQM[1] O - N Write Enable or Byte Enable for EM_D[15:8]
68 IO Supply (DVpp)
69 Ground(Vss)
70 EM_CLK O - N SDRAM Clock
71 EM_CKE O - N SDRAM Clock Enable
72 Ground(Vss)
73 IO Supply (DVpp)
74 EM_A[11] O - N EMIF Address Bus
78 Ground(Vss)
81 IO Supply (DVpp)
82 Ground(Vss)
87 Ground(Vss)
92 IO Supply (DVpp)
HTR-5935
94 EM_BA[1] O - N SDRAM Bank Address and Asynchronous Memory LOW-Order Address
95 Ground(Vss)
96 EM_BA[0] O - N SDRAM Bank Address and Asynchronous Memory LOW-Order Address
97 EM_CS[0] O - N SDRAM Chip Select
98 EM_RAS O - N SDRAM Row Address Strobe
99 Ground(Vss)
100 EM_CS[2] O - N Asynchronous Memory Chip Select
102 EM_RW O - N Asynchronous Memory Read/not Write
103 IO Supply (DVpp)
104 EM_OE O - N SDRAM Output Enable
105 SPI0_ENA/I2C1_SDA IO - Y SPI0 Enable (Ready) or I2c1 Serial Data
106 Ground(Vss)
107 SPI0_SCS/I2C1_SCL IO - Y SPI0 Slave Chip Select or I2c1 Serial Clock
108 SPI0_CLK/I2C0_SCL IO - Y SPI0 Serial Clock or I2c0 Serial Clock
109 Ground(Vss)
110 SPI0_SIMO IO - Y SPI0 Data Pin Slave In Master Out
49
HTR-5935


111 SPI0_SOMI/I2C0_SDA IO - Y SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
113 AXR0[0] IO - Y McASP0 Serial Data 0
114 Ground(Vss)
118 Ground(Vss)
120 AXR0[5]/SOI1_SCS IO - Y McASP0 Serial Data 5 or SPI1 Slave Chip Select
121 AXR0[6]/SPI1_ENA IO - Y McASP0 Serial Data 6 or SPI1 Enable (Ready)
122 AXR0[7]/SPI1_CLK IO - Y McASP0 Serial Data 7 or SPI1 Serial Clock
124 Ground(Vss)
126 AXR0[8]/AXR1[5]/SPI1_SOMI IO - Y McASP0 Serial Data 8 or McASP1 Serial Data 5 or SPI1 Data Pin Slave
Out Master In
127 AXR0[9]/AXR1[4]/SPI1_SIMO IO - Y McASP0 Serial Data 9 or McASP1 Serial Data 4 or SPI1 Data Pin Slave In
Master Out
129 Ground(Vss) IO - Y
130 AXR0[10]/AXR1[3] IO - Y McASP0 Serial Data 10 or McASP1 Serial Data 3
131 AXR0[11]/AXR1[2] McASP0 Serial Data 11 or McASP1 Serial Data 2
135 AXR0[13]/AXR1[0] McASP0 Serial Data 13 or McASP1 Serial Data 0
136 IO Supply (DVpp) IO - Y
139 ACLKR0 McASP0 Receive bit Clock
141 AFSR0 IO - Y McASP0 Receive Frame Sync (L/R Clock)
142 ACLKX0 IO - Y McASP0 Transmit Bit Clock
143 AHCLKR0/AHCLKR1 IO - Y McASP0 and McASP1 Receive Master Clock

144 AFSX0 McASP0 Transmit Frame Sync (L/R Clock)
HTR-5935
50
HTR-5935
■ PIN CONNECTION DIAGRAM

• ICs
BD3816K1 BD3841FS TC74HC4051AF F2602E-01 LA7106M-TLM-E
TC74HC4052AF YAC523-EVR2 PCM1780DBQR
64 41
TC74HC4053AF PCM1781DBQR
NJM2581M PCM1803DBR
65 40
17 36 25
37 24
32 16
7 8
14 48 13 16
80 25 1 1 1 12 1
1 24
BD3816K1 LA73050-TLM-E LC72722PM LC89057W-VF4A-E LM61CIZ THERMAL
24 13
25 12
18
12
36 24 36 1
IN +VS
OUT VOUT
COM 1 1 37 48 GND
M30625MHP-A98GP M66003-0131FP NE5532DR OP AMP NJM2068LD NJM2388F05 5.0V

NJM2068MD-TE2 NJM2388F33
NJM4556AL
102 65 48 33
103 64
49 32
8 4
1 8
128 39 64 17
1 38
1
1 16 1
4
NJM2581M VIDEO AMP NJM2885DL1-18 NJM4565M (TE1) NJM7812FA NJM78M05DL1A (TE1) NJM7805FA 5V
NJM2885DL1-33 NJM79M05FA
NJM79M12FA
HTR-5935
2:GND
7
14 8 4
1 1:IN 1
3: IN 1 3: COM
3:OUT 1: OUT 1: OUT
2: COM 3 2: IN
NJU7311AM PCM1680DBQR R1172S121D-E2-F RH5RE58AA-T1-FA SN74AHC1G08DCKR

NJU7312AM
NJU7313AM 4
1: Vin
2: GND 5
6 3 3: Vout 3
1
2
1 3 1
15
14 SN74AHCT08PWR SN74AHCT1G32DCKR
30 28
4
1 1 7 5
14 3
1 1
51
HTR-5935
SN74LV157APWR SN74LV245APWR TRAN TC4013BP FF W9816G6CH-7 SDRAM YAC520-EE2

SN74LVU04APWR TC74VHCU04FT INVER
50 26
10
10
14 7
7 20
20 14
1 1 1 1
1 25
S29AL004D70TF1020
1 48
24 25
• Diodes
1N4002S RB441Q-40 T-77 D2SBA20 1.5A 200V MA8030-L 2.9V RB500V-40 MA8082-H 8.5V
1SS133,176 RB441Q-40 T-77 D5SB20 5A 200V MA8051-M 5.1V RB501V-40
1SS270A MA8056-M 5.6V UDZ 3.6BTE-17 3.6V Anode
1SS355 MA8068-L 6.6V UDZ5.1B 5.1V
1SS380 MA8068-M 6.8V
1T2 MA8075-H 7.7V
Cathode
MTZJ13A 13V MA8091-M 9.1V
MTZJ15A 15V MA8100-M 10V
MTZJ15B 15V Anode S1NB20 1A 200V
MTZJ2.4B 2.4V S1NB60 1.0A 600V
MTZJ27B 27V Anode
+
– –
MTZJ30A 30V
MTZJ5.1C 5.1V ~
~ ~
Cathode + Cathode ~
• Transistors
2SA1015 Y 2SC3326 A,B 2SB1257 2SA1695 O,P,Y 2SA1708 S,T

2SA933S Q,R 2SC3837K T146 N,P 2SB1274 Q,R,S 2SC4468 O,P,Y 2SA1770 S,T
2SA949 O,Y 2SC3906K T146 R,S 2SD1915F S,T 2SC4488 S,T
HTR-5935
2SC1740S QRS 2SD2014 2SC4614 S,T

2SC1815 Y 2SK2158-T2B-A 2SD1938F S,T
2SC1890A D,E 2SK246 Y
2SC2229 O,Y 2SK3288
2SC2240 GR,BL 2SK3850
BC B
E
CB BC C
E E E
2SA1037K Q,R,S
2SC2412K Q,R,S
DTA114ES
DTC114EKA
DTC114ES
DTC124EKA
DTC144ES
C
E
B
52
A B C D E F G H I J
RX-V459/DSP-AX459/HTR-5935
1
■ BLOCK DIAGRAMS
AUDIO BLOCK DIAGRAM
• See page 69-71 → LC89057W D70YE001RFP250
DSP SCHEMATIC DIAGRAM DIR Decoder / Post Prosessor
IC56 IC60
DSP-AX459 model 4
MD/CD-R RX2 AXR0[4]
AXR0[11]
5 131
DVD RX3
Post Prosessor
Input Selector
AXR0[3] 6 IC71
117 FL/FR D/A 27, 26 DAFL/DAFR
Decoder
8
RX4
2 DTV/CBL
R, T, K, A, G, E, L models
FL/FR
DIGITAL
AXR0[2] 11 22, 21 IC72

116 C/SW D/A DAC/DASW
Buffer 21 J206
6 C/SW
SN74LVU04APWR 8 9 RX5 RDA IC73
DVD AXR1[3] AXR0[1] 115 SL/SR 12 D/C 20, 19 DASL/DASR
*VDD=5V 130
SL/SR
IC52 IC74
RX-V459, AXR0[0] 113 SB 13 D/A 16 DASB
HTR-5940, HTR-5935 models U, C models
SB
DSP-AX459 model 1 8ch DAC RX-V459, DSP-AX459, HTR-5940 models
MD/CD-R RXOUT
PCM1680
IC68
Selector
11 9 SN74LV157APWR
3A 3Y 16M SDRAM 4M ROM
3 IC67
IC64 IC66 1B
18, 19 XMDT 37 10
3B 4
XM I2S 1Y
Selector 2
IC55 1A
3 SN74LV157APWR
2ch ADC 1, 2 IC76
U, C models IC58 9 Att. ADL/ADR
PCM1803
-9dB
IC70
• See page 72 → • See page 74 →

OPERATION FUNCTION MAIN SCHEMATIC DIAGRAM
• See page 73 → SCHEMATIC DIAGRAM
Extension Selector
SCHEMATIC DIAGRAM 19, 20

BD3841FS
IC202
PORTABLE
V-AUX
5, 6
AUDIO L/R
IC211
4
Muting
23, 24 26- 32 Q2012, 201 C3039, 3041
HEAD PHONE
NJM4556AL
(-95dB to 0dB)
(0dB to 17dB)
(0dB to 7dB)
IC207
FM/AM 53, 54
TUNER 74, 75 Tone Center Mix RY100
FRONT A L/R
FM/AM (11) Control LFE Mix C1115, 1116
Input Selector
7.2MHz
7ch Selector
Center 51
2- 13 Muting FRONT RY101
Q2014, 201 C1117, 1118 FRONT B L/R
Surround L/R 49, 50
Master Volume
CD
Output Gain
Input Gain
Surround Back 48
MD/CDR
ANALOG
SW 46
5 DVD
Selector / Volume
BD3816K1 IC200 Muting RY103
DTV/CBL CENTER CENTER
Q2019 C1108
76- 79 15- 19, 21
DVR
SPEAKER OUT
Muting SURR. RY104
Q2016, 201 C1119, 1114 SURROUND L/R
REC OUT
MD/CDR
DVR
RX-V459, DSP-AX459, HTR-5940 models
6 RY102
Muting SURROUND
SURR.BACK
Q2018 C1111 BACK
FL/FR HTR-5935 model

MULTI CH INPUT
IC205 Muting RY102

SW SUB WOOFER
Q2009, 201 C1111
C/SW
MUTE CONTROL
• See page 75 →
SL/SR
YST SCHEMATIC DIAGRAM
SPEAKER RELAY
7
SUBWOOFER OUT
POWER AMP
53
A B C D E F G H I J
VIDEO BLOCK DIAGRAM
OUTPUT AMP
LA73050
BYPASS
IC401
CVBS 3 33
2 DVD
INPUT SELECTOR 6dB
74HC4051
DTV/CBL
15 CVBS
• See page 73 → Y 8 29
DVR OUT
14 OPERATION SCHEMATIC DIAGRAM
6dB
C Y
12
3 CVBS
DVR 1
5 IC402 C 31
6 6dB
V-AUX RX-V459,
DSP-AX459,
HTR-5940
models
C Y
/VR1
DVD Y
15
14
12 CVBS 12 24
3 DTV/CBL 1
3 Y 6dB
5 IC403
DVR
Y 17 20
C 6dB
15
C Y
14
12
3 C C 15 22
1 6dB
IC404 RX-V459,
5 DSP-AX459,
RX-V459,
DSP-AX459, HTR-5940
HTR-5940 models models
/MON
MONITOR OUT
4
VIA
VIB
VIC
U, C, R, T, K, A, G, E, L models U, C, R, T, K, A, G, E, L models
Y Y
Pb/Cb Pb/Cb
• See page 72 →
Pr/Cr FUNCTION SCHEMATIC DIAGRAM Pr/Cr
DVD
Y Cb Cr
Y Cb Cr
L1/L2/L3 L1/L2/L3
J model J model
U, C, R, T, K, A, G, E, L models
5
Y
Pb/Cb
Pr/Cr
DTV/
CBL
Y Cb Cr COMP0
COMP1 Y
L1/L2/L3 /CBYPASS 6dB
J model
Input Selector
U, C, R, T, K, A, G, E, L models
74HC4052
Y Y/ Cb/ Cr Cb
BYPASS IN 2, 4, 5, 15, 14, 11 IC287(Cb, Y) 6dB
IC288(Cr, L1) 3, 13
Pb/Cb
6 IC289(L3, L2)
Pr/Cr Cr
6dB
DVR 2, 4, 5, 15, 14, 11 3, 13
Y Cb Cr IC290
L1/L2/L3 L1/L2/L3 OUTPUT AMP
L1/L2/L3
IN OUT
NJM2581
/CNON
J model
/MON
7
54
A B C D E F G H I J
CONTROL/POWER BLOCK DIAGRAM
POWER DETECT
MODEL DETECT
POWER
DEST. DETECT
• See page 69-71 → TRANSFORMER /4ohms
DSP SCHEMATIC DIAGRAM RY105
/RESET
PLDET
PRV2
PRV1
+B
THM
PRD
OPERATION
PRI
/HP
C1105
C1104
• See page 73 →
3/ 69/ 114
/117/ 119
D133
G
SCHEMATIC DIAGRAM
C1107
C1106
120
121
122
123
124
128
2
17
53
96
99
-B
6
LIMITER CONTROL
IR REMOTE 98 RY105
U3000 55
POWER RELAY
D1041, 1402, 1044, 1045

51/ 50/ 49/ 48/ 46
SPEAKER RELAY +BL
C1100
VOLUME 63/ 64 100- 104
MUTE CONTROL
SW300 G
54
C1101
POWER SAVE
47 -BL
/4ohms
INPUT SELECTOR 58/ 59
SW301
-30V
-VP
3 TONE CONTROL/ DSP PROGRAM 60/ 62 7
XMPWR
Q1068
SW302
Microprocessor
8-10/ 15/ 16/ 23/ 24/ 26- 31 FL1
M30627 DSP
IC2 FL2
12/ 42- 45
Net-module
MAIN POWER SW 97
SW323 34/ 35 +12V
XM +12
IC104
C1082
69/ 84/ 86/ 88/ 89/ 117
RDS
D1035
83/ 90- 95 G
C1083
TUNER
-12V
-12
IC105
25/ 65- 68, 70- 74, 76- 81
4 Tack SW 125/ 126 VIDEO SELECTOR
+5V +5A
SW302, 304, 306, 309- 319, 321, 322, 324 115/ 116/ 111- 117
SELECTOR/VOLUME • See page 74 → IC51
MAIN SCHEMATIC DIAGRAM
FL DISPLAY FL DRIVER 3/ 4/ 5/ 57 DSP E
V3000 IC301 • See page 69-71→
18 XL1 20
SCHEMATIC DIAGRAM
+5V
16MHz +5D
IC102
+3.3V
+3.3V
IC54
+1.2V
+1.2V
IC53
RY301 F3001
DG
F3000/J3002
5
+3.3V
+3.3D
IC306
C1087
D1036
G
TE300
C1088
-5V
-5V
IC103
+5V
+5V
IC106
Power Detector
IC300, 302, 303 /Reset
Q3006, 3002
6
D3016
Q3007
D3 VE
+5BU
D2
T3000 s10 +5.5V
+5M
IC1
RY301
D1 Q1
U, C models
+5S
D3018
+5.3V
+5.3X
Q3003
IC100
C1109
D1046
XMPWR
XGND
G
7
POWER RELAY POWER SAVE
55
A B C D E F G H I J K L M N
RX-V459/HTR-5940/HTR-5935/DSP-AX459
SCHEMATIC DIAGRAMS
DSP 1/3
1
DSP
POINT A-1 Pin 18 of IC2 POINT B-2 1 / Pin7, 2 / Pin8 of CB3
POWER ON
(connect the power cable)
to FUNCTION (1)_CB200
C2
3
Page 72
5.0
-11.9 4.9
IC1 : RH5RE58AA-T1-FA
5.0 Voltage regulator
5.0 VIN VOUT
4.3
2 3
4.9
4.9
4.9
0
0
0
0
0
4 +
0
5.0
5.0
5.2
–
0
-11.9 4.9
5.0
5.0
0.1
5.0
0.1
0.1
0.1
4.9
5.0
5.0
0.1
4.9
Vref
0
0
0
0
0
0
5.0
4.9
4.9
4.9
4.9
0.1
1
0
GND
0
5.0
5.0 0.1 0 -11.9 4.9

0.1 4.8
0 5.0
0 5.0
0 5.0 5.0
to OPERATION (1)_CB309
0 4.9
5.0 4.3
IC4, 5 : SN74AHCT1G32DCKR
MICRO PROCESSOR 0.1
Single 2-input positive-OR gate
C9
0 5.0
5 5.0
0 4.9
Page 73
0 4.9 A 1 5 Vcc
0 0 B 2
0 0
GND 3 4 Y
0 5.9 0 0.2
0 0
M30625MHP-A98GP
5.0
0 4.9
0
0 4.9
2.7 0
2.0 0
0.4 0
5.0 5.0
1.0 0.1
5.2
A-1 0 IC6 : SN74AHC1G08DCKR
6 5.2 0 5.0 0.1 3.3 0.1 2-input positive-AND gate
0 0
0
0 0
4.3
0.4
2.7
A 1 5 Vcc
1.2 0.2
B 2
2.0
0
GND 3 4 Y
5.0
4.9
2.5
0
2.4
5.0
4.9
0
0
5.0
5.2
4.9
5.0
5.0
5.0
5.0
5.0
0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
I3
0.6
0.1
4.9
4.9
4.9
4.8
0.5
5.0
to FLASH WRITER
IC2 : M30625MHP-A98GP
0
0
5.0
Page 72
2-input positive-AND gate

7
5.0
0.1 5.0
0.1
8 8 8 8 8 8 8
5.0
5.0
0.1
5.0 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
5.0
Port P7
<VCC2 ports> (4) <VCC1 ports> (4)
8
Internal peripheral functions
D/A converter Watchdog timer
Timer (16 bit) (10 bit x 8 channels (15 bits)
Expandable up to 26 channels)
Port P8
XIN-XOUT
Output (timer A): 5 UART or XCIN-XCOUT
7
Input (timer B): 6 clock synchronous serial I/O PLL frequency synthesizer
to OPERATION (4)_W3009
<VCC1 ports> (4)

Three-phase motor (8 bit x 8 channels) On-chip oscillator
Port P8_5
control circuit Watchdog timer Clock synchronous serial I/O
8 (Polynomial: X16+X12+X5+1) (8 bit x 2 channels)
XX
M16C/60 series 16-bit CPU core Memory

Page 73
R0H R0L SB
Port P9
Watchdog timer ROM (1)
R1H R1L USP
(15 bits) R2
ISP
8
B-2
R3 RAM (2)
DMAC INTB
(2 channels) A0 PC
A1
Port P10
5.0 5.0 FB FLG
D/A converter
2
to MAIN (1)_W1026
10.1 5.8 5.2 5.2 5.0 (8 bit x 2 channels) Multiplier
8
0
H2
5.8 4.3
5.2 <VCC1 ports> (4) <VCC2 ports> (4)
5.8 4.9
Port P11 Port P14 Port P12 Port P13
Page 74
0.1
0.1 5.1 (3) (3) (3) (3)
9 4.9 8 2 8 8
NOTES:
1. ROM size depends on microcomputer type.
to MAIN (1)_W1007
0 2. RAM size depends on microcomputer type.

3. Ports P11 to P14 exist only in 128-pin version.
H1
4. Use M16C/62PT on VCC1=VCC2.

Page 74
★ All voltages are measured with a 10MΩ/V DC electronic volt meter.

★ Components having special characteristics are marked s and must be replaced
10 with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
69
1
DSP 2/3
IC61, 62 : SN74AHCT1G32DCKR IC63 : SN74AHCT08PWR

Single 2-input positive-OR gate Quadruple 2-input positive-AND gates
DSP
A 1 5 Vcc 1A 1 14 Vcc
B 2 1B 2 13 4B
GND 3 4 Y 1Y 3 12 4A
3.3
3.3
1.3 3.1 3.3 5.0
0
2A 4 11 4Y
0
100/16
100/16
1.3 3.1 POINT A-1 Pin 28 of IC55 POINT A-2 Pin 29 of IC56
3.3
5.0
2B 5 10 3B
3.2
0.1
3.1
0.9
0 0 3.3 5.0
100/16
0 2Y 6 9 3A
3.1
2 0.1 3.3 GND 7 8 3Y
0 3.3
0 3.3
4.0 0
0.3 0
0 0 IC64 : W9816G6CH -7
DIR
&6
3.3 3.3 512K x 2 banks x 16 bits SDRAM
0.3 1.6
0.1
0.6 1.5
5.0 CLK 35 CLOCK
0 A-2 1.7
3.3 BUFFER
0 3.3
CKE 34
3.3
0 0
CONTROL COLUMN DECODER

CS 18
SIGNAL R
RAS 17 GENERATOR O
0
4.0 COMMAND W
3.3
3.3
1.7
1.7
1.7
0
CAS 16 DECODER
D CELL ARRAY 2 DQ0
3.3
0.5
0.1
5.0
5.0
5.0
5.0
0 WE 15 E BANK #0
0
C
5.0
0.6
0.5
5.0
5.0
5.0
5.0
5.0
O 3 DQ1
4.9 D
3 A10 20
E
R
5 DQ2
6 DQ3
DIGITAL IN SENSE AMPLIFIER
8 DQ4
FL/FR
0.1
3.1
3.2
0
0.1
0.1
0.1
0.1
9 DQ5
0
0.3 C/SW MODE
3.3
3.3
3.3
3.3
11 DQ6
0.9
A0 21
3.5
∼ REGISTER
0 A3 24 ADDRESS 12 DQ7
REFRESH DQ
4.9
PL/PR SL/SR A4 27
BUFFER
COUNTER BUFFER 39 DQ8
∼
40 DQ9
A9 32
ANALOG IN SBL/SBR BA 19
42 DQ10
43 DQ11
45 DQ12
0.3 46 DQ13
REFRESH COLUMN COLUMN DECODER
0 COUNTER COUNTER 48 DQ14
R
O 49 DQ15
4.9 W
D CELL ARRAY
E BANK #1
C
O
D
E
R 14 LDQM
4 SENSE AMPLIFIER 36 UDQM
5.0
2.4 2.4 0.6

0
IC66 : S29AL004D70TF1020
4M-bit COMS 3.0 volt-only boot sector flash memory
0 4.9 0
BUFFER
3.1
0.9
RY/ BY# DQ0–DQ15 (A- 1)
0 4.9 0 VCC
Sect or Sw itc hes
SELECTOR VSS
3.3
Erase V olt ag e In put/ Out put
RESET# Generat or Buff ers
0.1
1.3
3.3
3.3
0
0
0
0
0
WE# State
3.3
Contr ol
5 BYTE#
0.4
1.7
1.7
1.7
0.5
1.7
1.7
1.7
1.7
Comm and
Regi st er
3.3
1.2
1.2
3.3
1.2
3.3
0
0
PGM Vo ltage
Generator
Chip Enab le Data

Out put Enable STB Lat ch
CE#
0 0 OE#
Logic
1.7 0
0.1 0
0 0
Y-Decoder Y- Gating
0 0 0 3.3 STB
0 3.3
Addr ess La t ch
VCC De te ct or Tim er
5.4 0.1 0
1.2 1.2 X- Decoder Cell M atrix
XM 1.7 3.3
A0– A17
0.1 3.3 0
0 3.3
1.7 0
1.5
1.5
1.5
1.5
0 0 3.3
3.3 0
3.3
3.5
0.2
6
0
0 3.3
A15 1 48 A16
1.2 0.4 A14 2 47 BYTE#
0 0 3.3 1.7 A13 3 46 VSS
16M SDRAM 4M ROM

3.3
A12 4 45 DQ15/A-1
1.9 3.3
0 0.1 A11 5 44 DQ7
A-1 3.5
0 0 A10 6 43 DQ14
3.5 0 3.3 1.2 A9 7 42 DQ6
0
1.8 1.2 0.1 A8 8 41 DQ13
NC 9 40 DQ5
0 3.5 0 0.1 NC 10 39 DQ12
WE# 11 38 DQ4
0 0 0 12 VCC
0.2 RESET# 37
0 0 0 3.0 NC 13 36 DQ11
NC 14 35 DQ3
3.5 1.2 1.2 RY/BY# 15 34 DQ10
3.5
XMDT 3.5
3.5 0
1.6
1.8 3.3 0
NC
A17
A7
A6
16
17
18
19
33
32
31
30
DQ2
DQ9
DQ1
DQ8
0 0 3.3
No replacement part available. 0 0.2 0.1 0.1 0 A5
A4
20
21
29
28
DQ0
1.8
OE#
3.3 3.3 0.1 0.1 0 3.3 A3 22 27 VSS
3.3 サービス部品供給なし 2.8 0 0 0 0 A2
A1
23
24
26
25
CE#
A0
0 2.9 0.2 0.2 0.1 0.1
0
3.3 0 0.2 0.2 0.4 0.1

0
3.5
3.5
3.3 1.2 3.3 3.3 0.1 0.1

7
1.8
0.2
1.8
1.2 0.1 0.2 0.1 0.1 0.1

0.2
0.2
3.3 0.1 0.1 0.2 2.9 0.2

3.3 0.1 0 0 0.1
0 3.3 0.1 0.2 0.2
IC65 : SN74LV245APWR
0.1 0.2 3.3 0.2 Octal bus transceiver with 3-state outputs
3.3 3.3 3.3
2.9 3.3 0.1
0
3.3
1.2
3.3
1.2
0
1.2
3.3
1.2
3.3
0
0
DIR 1 20 Vcc
3.3
3.3
1.7
3.3
3.3 2.9 0.2
0.1
0.1
0.1
0.2
0.2
0.1
0.2
0.1
0.2
0.2
0.1
0.2
0.2
0.2
3.3 1.7 0.2
A1 2 19 OE
S29AL004D70TF1020
3.3 3.3 0 0.2
2.9
2.9
0 0 0.2
A2 3 18 B1
3.3 0.1 2.8 0.1
0.1
0.4 0.1 1.8 0.2

A3 4 17 B2
0.1 2.9 1.6 0.2
0.1 2.8 3.0 3.3 A4 5 16 B3
0.1 1.8 0.1 0
3.0 1.6 0.1 3.3 A5 6 15 B4
8 3.3 0 0.1 3.3

A6 7 14 B5
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
IC56 : LC89057W-VF4A-E IC58 : SN74LV157APWR IC59 : SN74AHC1G08DCKR

Digital audio interface transceiver Quadruple 2-line to 1-line data selectors/multiplexers 2-input positive-AND gate
9 EMPHA/UO AUDIO/VO INT CL CE CI XMODE

1A 2
IC53 : R1172S121D-E2-F 32 33 35 48 39 38 41
4 1Y
A 1 5 Vcc
IC52 : SN74LVU04APWR IC54 : NJM2885DL1-33 1B 3
Power supply B 2
Hex inverters Low dropout voltage regulator A/B 1 16 VCC
RXOUT 1 Microcontroller 2A 5 GND 3 4 Y
Cbit, Ubit 37 DO 1A 2 15 G
I/F 7 2Y
2B 6 1B 3 14 4A
1A 1 14 VCC VIN 1 3 VOUT RX0 2
1Y 4 13 4B
36 RERR
RX1 3 3A 11 2A 5 12 4Y
1Y 2 13 6A
VDD VOUT Thermal
Protection
RX2 4
RX3 5
Input Demodulation Data
21 RDATA
3B 10
9 3Y
2B
2Y
6
7
11
10
3A
3B
2A 3 12 6Y Selector & Selector GND 8 9 3Y
Bandgap RX4 8 Lock detect
4A 14
2Y 4 11 5A Reference
RX5/VI 9
24 SDIN 12 4Y
3A 5 10 5Y RX6/UI 10 4B 13
★ All voltages are measured with a 10MΩ/V DC electronic volt meter. 3Y 6 9 4A LPF 13 PLL
16 RMCK G 15
★ Components having special characteristics are marked s and must be replaced 17 RBCK A/B 1
GND 7 8 4Y GND 2 Clock 20 RLRCK
with parts having specifications equal to those originally installed. TMCK/PIO0 44 Selector
22 SBCK
★ Schematic diagram is subject to change without notice. TBCK/PIO1 45 Modulation
1/N
10 Vref TLRCK/PIO2 46
&
Parallel Port
23 SLRCK
TDATA/PIO3 47
Current Limit
TXO/PIOEN 48
CE GND 29 28 27 34
XIN XOUT XMCK CKST
70
DSP 3/3
1
Page 72 D2 Page 74 J7
to FUNCTION (1)_CB202 to MAIN (2)_W1004
DSP
IC71-74, 75, 76 : NJM4565M

Dual operational amplifier
V+
8
2, 6
–INPUT OUTPUT
+INPUT 1, 7
3, 5
8.8 5.1
3
8.8 5.1
V–
0 4
LC89057W-VF4A-E
LC89057W-VF4AD-E
ANALOG IN IC70 : PCM1803DBR
5.0
5.0
1.7 1.7
1.3 0 Stereo A/D converter
0 0 11.8
2.5
2.5
3.3 3.3 0
0
2.5
1.7 0 0
4 3.3 5.0
VINL
Delta-Sigma BCK
0
3.3 2.5 Modulator LRCK
0
0 2.5
DOUT
0 2.5 Serial
0 2.5
x1/64, x1/128 Interface
0 0
0 VREF1 Decimation
2.5
Reference Filter
-11.9 VREF2 With Mode/
FRONT L High-Pass Filter Format FMT0
2ch DAC VINR

Delta-Sigma
Control FMT1
MODE0
Modulator MODE1
11.8
0 BYPAS
0 0
TEST
FRONT L OSR
5.0 2.5
Power Supply Clock and Timing Control PDWN
3.3 2.5
SCKI
3.1 2.6
5 1.7 0 0
0
0
1.7 5.1 -11.9 VCC AGND DGND VDD
C/SW 1.7 2.5
1.7 2.5
SL/SR 5.0 2.5 CENTER
0 2.5
1.7 0
1.7 5.1
0.5 2.5 IC69 : PCM1781DBQR
0
11.8
Audio digital-to-analog converter
0
0 0
SUB
WOOFER
BCK
DIGITAL IN
0 0
8ch DAC LRCK Audio
Serial Output Amp VOUTL
0 0 0 0 DATA Port DAC and
0 Low-Pass Filter
-11.9
6 4 /8
3.3 3.3 Oversampling
Enhanced
0.1 0 Digital
Multilevel
0.1 1.7 (FMT) Filter VCOM
1.7 1.7
SURROUND L With
Delta-Sigma
Modulator
MS (DEMP0) Function
0 1.7 Serial Control
0 1.7 SBL/SBR MC (DEMP1)
Control
1.7 Port Output Amp
0 1.7 0
11.8 DAC and
MD (MUTE) Low-Pass Filter
0 0 VOUTR
(TEST)
System Clock
FL/FR
SCK System
0 0
Clock Zero Detect Power Supply
SELECTOR 0
-11.9 Manager
7 SURROUND
BACK L
VCC
ZEROL/NA (1)
ZEROR/ZEROA (1)
AGND
(ZEROA)
11.8
0
0 0
(1) Open-drainoutputforthePCM1782
NOTE: Signal names in parentheses ( ) areforthe PCM1781.
0 0
0
-11.9
IC68 : PCM1680DBQR
Audio digital-to-analog converter
8
Outp ut A mp and VOUT1

DAC
BCK Low-P ass Filter
LRCK
DAC
Serial Low-P ass Filter
IC51 : NJM78M05DL1A IC67 : SN74LV157APWR DATA1 (1, 2) Input
Voltage regulator Quadruple 2-line to 1-line data selectors/multiplexers DATA2 (3, 4)
I/F
DAC
Low-P ass Filter
DATA3 (5, 6)
DATA4 (7, 8) 8 VCOM
1A Outp ut A mp and
2 Oversampling DAC
Enhanced Low-P ass Filter VOUT4
4 1Y Digital Filter Multilevel
1B 3 With DeltaœSigma
INPUT Function Modulator DAC
Outp ut A mp and
A/B 1 16 VCC Controller Low-P ass Filter VOUT5
2A 5
1A 2 15 G MS/ADR
7 2Y Outp ut A mp and
9 2B 6 1B
1Y
3
4
14
13
4A
4B
MC/SCL DAC
Low-P ass Filter VOUT6
MD/SDA Function
OUTPUT 3A 11 2A 5 12 4Y
Control Outp ut A mp and
2B 6 11 3A I/F DAC
9 3Y Low-P ass Filter
3B 10 2Y 7 10 3B VOUT7
GND 8 9 3Y
MSEL Outp ut A mp and
4A 14 DAC
Low-P ass Filter VOUT8
12 4Y
4B 13
System Clock
COMMON G 15
Syst em Clock
A/B 1 SCK Zero Detect Power Supply
Manager
VCC1
VCC2
VDD
ZERO1
ZERO2
DGND
AGND1
AGND2
10
with parts having specifications equal to those originally installed.
71
1
FUNCTION
Page 71 C1 Page 73 G6
Page 69 B3
to DSP_CB56 to OPERATION (5)_W3007
to DSP_CB1
0.1
0.1 0.1
0.1 0.1
0.1 -6.9
0.1 0
0.1 7.1
EXTENSION 0
0
0.1
0
3 SELECTOR 0
0
0 0.1
0 0.1
Page 73 J3 Page 69 B7
0 0
0 0 to DSP_CB2 IC200 : BD3816K1
to OPERATION (2)_CB252 7-channel volume IC for 7-channel
65 GOUTFR
79 ROUTC2
78 ROUTC1
77 ROUTB2
76 ROUTB1
80 AGND13
73 AGND12
70 AGND11
75 ROUTA2
74 ROUTA1
66 THGND
67 MUTE
72 VCC
71 VEE
69 DA
68 CL
LOGIC
REC C
REC B
REC A
AGND1 1 64 VINFR
0.1
0.1
0.1
0.1
0
INA1 2 63 GOUTFL
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
SURROUND
0
SUB
BD3816K1
INA2 3 62 VINFL
WOOFER BACK L/R

INB1 4 61 AGND10
0.1 0.1
0.2
0.3
0.2
5.5
5.8
2.5
4 INB2 5 60 TNF1
0
0.1 0 C-2 Input
TREBLE
0 0 select ING SW
INC1 6 59 TNF2
0.1 0.1
1.0
0.1 0 58 BNFA1
4.9 INC2 7
0.1 0.1 2.5 2.5 2.5
1.0
0.1 0 IND1 8 Output BASS 57 BNFB1
2.5 2.5
3.2
3.2
5.3
0
0
0
2.7
mode
0.1 0.1
1.0
0.7 5.0 select

0.1 0.1 0.1 0 IND2 9 56 BNFA2
0.1 0.1 0.7 0
3.1
3.1
0 0.1 0 INE1 10 55 BNFB2
0.1 0.1 0 0
FUNCTION (4)
0.1
0.1 0 0.1 0 0.1
4.9 4.9 4.9 INE2 11 Master + 54 OUTFR
0.1 0.1 0 0 Volume
0.1 0.1 -4.9 0.1 0
INF1 12 + 53 OUTFL
0.1 0.1 0
0
0.1
0.1
SURROUND L 0
0
CENTER
0.1
INF2 13 52 AGND9
0.1 0 AGND2 14 FRL select 51 OUTC

0.1 0
0.1 0 11.9 5.8 INDVDFR 15 50 OUTSR
ANALOG IN 0.1 0
INDVDFL 16 49 OUTSL
6.5
0.1 0
0.1 0
INDVDC 17 48 OUTCB
FRONT L
0.6
0.6
0.1
0.1
0 0.1
5
to TUNER
6.5
INDVDSR 18 47 AGND8
0
INDVDSL 19 46 OUTSW
0.1
0.1
OUTPUT
0
0
0
0
0
7.1
-6.9
0
INDVDCB 20 45 AGND7
0
0
0.1
0.1
0.1
0.1
0.1
0.1
INDVDSW 21 44 VINC
AMP
10.6
7.1
AGND3 22 43 GOUTC
7.8
0.6
0.6
6.1ch select
5.0
0.7 5.0 0 OUT1 23 42 VINSR
0
0.1 0.1 -4.9 0.1

7.8
0.7 0.1 0 5.0 OUT2 24 41 GOUTSR

0.1 0.5 -4.9 0.1
0
0.1 0.5
00
0 5.0
0 0.1 -4.9 0.1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
-7.7
INDSPFR
INDSPFL
INDSPC
INDSPSR
INDSPSL
INDSPCB
INDSPSW
GOUTSW
VINSW
GOUTCB
VINCB
GOUTSL
VINSL
AGND4
AGND5
AGND6
-4.9 0.6 0
0 0.6 2.9
-7.6
-10.7 2.9 4.9

-6.9
6 2.9 5.0
IC202 : BD3841FS
INPUT SELECTOR Function switch
RECC1
RECC2
RECA1
RECA2
RECB1
RECB2
DGND
OUT1
OUT2
BIAS
10.1
VCC
VEE
INI1
INI2
9.4
DA
CL
9.4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
0.1
to OPERATION (1)_W3002
0.1 0.1
0.1
5.0 5.0 5.0 LOGIC
0.8
0
0.7 5.0
E9
0.1 0.1 0.1

0.1 0.1 0.4
+
–
–
0.1 0.3
Page 73
0.1 0.1
0
0.8 0 0.1
0.1 -5.0 0.6
0.1 0.1 0.6
F-SW1
F-SW2
7 0.1
-10.1
0
-10.1
-10.8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
INPUT
INA1
INA2
INB1
INB2
INC1
INC2
IND1
IND2
INE1
INE2
INF1
INF2
ING1
ING2
INH1
INH2
SELECTOR *
F-SW1: INPUT FUNCTION 1
F-SW2: INPUT FUNCTION 2
11.9
0
0 0 0.1
-11.9
0
to MAIN (1)_W1028
B3
0
INPUT IC209 : LC72722PM
0.1 -11.9
Page 74
SELECTOR
0 0
0
-12.0
FUNCTION (3) RDS signal processor
FL OUT
VREF
8
C IN
0 0 R, L models
0
1 5 6
VDDA 3 PLL CLOCK 14 VDDD
to MAIN (1)_W1027
(57 kHz) RECOVERY

REFERENCE (1187.5 Hz)
VOLTAGE
B2
VSSA 4 15 VSSD
VREF
57 kHz DATA
MPX IN 2 ANTIALIASING SMOOTHING
bpf 19 RDS-ID
Page 74
FILTER FILTER DECODER

(SCF)
0.1
-11.9
DO 20
0.1 CL 21 RAM ERROR CORRECTION SYNC / EC 18 SYNC
-11.9
DI 22 CCB (24 BLOCK DATA) (SOFT DECISION) CONTROLLER 24 SYR
11.9 0 0.1
-11.9 CE 23
0.1
T1 CLK (4.332 MHz)
0 7 MEMORY
0 0
0 0 T2 8 CONTROL
0.1 0.1 0.8 TEST SYNC SYNC
-11.9 T3 9 DETECT-1 DETECT-2
0 OSC/DIVIDER
T4 10
-11.9 0
to POWER TRANSFORMER
9 11 16 17 13 12
X IN
X OUT
T5
T6
T7
FUNCTION (1) FUNCTION (2) Page 73 D2
Page 73 L3 IC286-288, 289 : TC74HC4052AF

Analog multiplexers/demultiplexers
to OPERATION (2)_W2501 IC211 : NJM4556AL IC290 : NJM2581M IC291 : TC74VHCU04FT IC205, 207 : NJM4565M
INH VCC Video amplifier Hex inverters
Dual operational amplifier Dual operational amplifier
6 16
★ All voltages are measured with a 10MΩ/V DC electronic volt meter. V+ A 10 LEVEL BINARY TO 1-OF-4 VIN1 1
6dB
AMP
75
Driver 14 V+1
1A 1 14 VCC
V+
8
★ Components having special characteristics are marked s and must be replaced B 9 CONVERTER DECODER WITH INHIBIT
1Y 2 13 6A
8
GND 8 BIAS
with parts having specifications equal to those originally installed. VEE 7
NEE1 2 13 VOUT1
2A 3 12 6Y
★ Schematic diagram is subject to change without notice. 0X 12 SW
10 –INPUT
2, 6
1, 7
OUTPUT
1X 14 SW
VIN2 3 6dB
AMP
75
Driver 12 V+2
2Y 4 11 5A –INPUT
2, 6
OUTPUT
+INPUT +INPUT 1, 7
3, 5
13 X-COM VEE2 4
BIAS
11 VOUT2
2X 15 SW 3A 5 10 5Y 3, 5
3X 11 SW VIN3 5 6dB 75

10 V+3 3Y 6 9 4A
AMP Driver
0Y 1 SW INHIBIT B A
BIAS GND 7 8 4Y
0 0 0 0x, 0y VEE3 6 9 VOUT3
V– 1Y 5 SW V–
4 3 Y-COM 0 0 1 1x, 1y 4
2Y 2 SW 0 1 0 2x, 2y PowerSave 7 REF 8 GND
3Y 4 SW 0 1 1 3x, 3y
1 X X NONE
72
OPERATION
1
IC251 : LA73050-TLM-E
Analog amplifier
U, C, T, K, A, G, J models
to POWER TRANSFORMER
2 Page 72 J9
N.C. 1 36 N.C.
R, L models N.C. 2 35 N.C.
to POWER CABLE to FUNCTION (3)_W3005A,W3005B

VIN1 3 34 +VCC1
+Vcc
DCCNT1 4 6dB DR 33 VOUT1

Page 74 J8 Page 72 H3 Page 72 C9
to MAIN (2)_W1006 to FUNCTION (2)_CB290 to FUNCTION (1)_CB201 GND 5 32 GND
VIN2 6 31 VOUT2
6dB DR
MUTE1 7 30 N.C.
RX-V459/DSP-AX459 models
VIN3 8 29 VOUT3
RX-V459/DSP-AX459 models 6dB DR
N.C. 9 28 -VCC1
220K
3 N.C. 10 27 -VCC2
N.C. 11 26 N.C.
VIN4 12 25 +VCC2
+Vcc
to DSP_CB3
B8
DCCNT2 13 6dB DR 24 VOUT4
GND 14 23 GND
Page 69
VIN5 15 22 VOUT5
6dB DR
D3015 VU99500 VU99500 VU99470 VU99500 VU99500 VU99500 VU99500 VU99500
s13 MA8091-M9.1V MA8091-M9.1V MA8082-H8.5V MA8091-M9.1V MA8091-M9.1V MA8091-M9.1V MA8091-M9.1V MA8091-M9.1V 16
MUTE2 21 N.C.
VIN6 17 20 VOUT6
6dB DR
4 -VCC4 18 19 -VCC3
OPERATION (4) IC253~255 : TC74HC4051AF

Analog multiplexers/demultiplexers
TC74HC4051AF
4 1 16 VCC
Page 74 H7
6 2 15 2
to MAIN (1)_W1029 OPERATION (1)
COM 3 14 1
5
7 4 13 0
to TRANSFORMER
5 5 12 3
INH 6 11 A
VEE 7 10 B
TC74HC4051AF
GND 8 9 C
no_use (HTR-5935 model)

IC301 : M66003-0131FP
6 FL display driver
TC74HC4051AF
Display code
RAM CGROM
(35 bit x 166) 44 SEG00
(8-bit x 60)
FL DRIVER no_use (HTR-5935 model) Code

write
Segment
output
circuit
19
17
SEG25
SEG26
E1
dot data
CGROM 9 SEG34
CS 2 Serial data (35 bit x 16)
write
SCK 3 receive
Code/
6800P
SDATA 4 circuit
command
Page 72
control 45 SEG35
circuit DIG11/
52
6800P
SEG42
51 DIG12/
SEG41
code Segment DIG13/
select 50
digit SEG40
select/ 49 DIG14/
XIN 7
Clock output SEG39
timing Display
generator clock controller scan pulse circuit 48 DIG15/
XOUT 6 SEG38
7 47 DIG16/
SEG37
46 DIG17/
SEG36
63 DIG00
Digit
RESET 1 output
Vcc1 8 circuit
53 DIG10
Vcc2 18
OPERATION (5) Vss 5
Vp 64
OPERATION (3)
8 RX-V459/HTR-5940/
DSP-AX459 models
RX-V459/HTR-5940/DSP-AX459 models
IC302 : TC4013BP
HTR-5935 model Dual D-type flip flop
OPERATION (2)
RESET1 4
SET1 6 1 Q1
100K
DATA1 5
HTR-5935 models 2 Q1
CL CL
CL CL
CLOCK1 3 CL
Page 69 B5 Page 72 E7
CL
to DSP_CB5 to FUNCTION (1)_CB205
9 OPERATION (6) RESET2 10
SET2 8 13 Q2
DATA2 9
12 Q2
CL CL
CL CL
CLOCK2 11 CL
CL
VSS 7
VDD 14
10
73
1
MAIN
Page 69 B9
MAIN (1)
to DSP_CB9
59.9
FRONT L 59.9
59.8
1.1 59.9
0
0.6
1.1
0.6
0.1
58.8
Page 69 B9
1.1
58.2 -0.4 59.6
to DSP_CB4
0.1
-1.0
1.0
HTR-5935 models: 100
-1.0 0.6
0
2 58.2 59.3 -0.5

4.7/50 0
0
-0.6
-0.6 0
-0.5
0 MAIN (5)
SUBWOOFER -0.5 0.1
0.1
-1.0 0.1
-1.0
-57.2
-60.1
-60.1
5.0 IC100, 102, 106 : NJM2388F
0
Page 72 E8 -57.7
-57.2 0 0
Low dropout voltage regulator with ON/OFF control
0 0
to FUNCTION (1)_CB207 -58.3
Vin 1 2 Vout
0 0
58.8 0
0
59.9
0.1
0.1
58.2 1.1 1.1 59.9 no use(RX-V459/DSP-AX459 models)
0.1
0.1
1.1
1.1
0.6 59.6
Page 72 E8 58.2 59.3
0.6 0.1
Bandgrap
4.7/50 0
-0.4
0.1
0 Reference +
to FUNCTION (1)_CB206 -
-1.0
0.6
0
-1.0
3 -0.6
-0.6 0 Cont 4
ON/OFF
control
-0.5
Over Voltage Thermal Over Current

0 Protection Protection Protection
-0.5 -0.5
-1.0 0.1
GND 3
-60.1 -60.1
-1.0
-57.2 RX-V459/DSP-AX459
-57.2
0 models
SURROUND BACK L/R -57.7
-58.3
36.8
36.8
36.8
36.8
36.8
59.9
1.1 59.9
IC101: LM61CIZ
58.8
Temperature sensor
1.1
1.1
36.8
0.6
10.0
8.2
10.2
10.5
0.6
10.0
58.2 59.6
1.1 0
-0.4
-1.0 0
8.2
4.8
-1.0 0
58.2 4.3
59.3
4
10.2
4.7/50 4.8
0 0
4.3
38.6
-0.6 -0.6
4.8
4.2
0
RX-V459/DSP-AX459
10.5
-0.5 -0.5
0
models 0.1
-1.0 0
4.8
-1.0
-60.1 -60.1
-57.2
4.2
0
-57.7
-57.2
RX-V459/DSP-AX459 models -58.3
CENTER
59.9
58.8 1.1 59.9

1.1
1.1
58.2 0.6 0.6

1.1
0 59.6
-0.4
0
-1.0
58.2 59.5
5 4.7/50
0 0
-1.0 0
36.9 0
-0.6 -0.6
0
0
-0.5 -0.5 0
0
-1.0 -36.5
-28.6
-1.0
-57.2
-60.1 -60.1
-29.2
-37.5 0
IC103 : NJM79M05FA
36.9
-57.7
0
Voltage regulator
-57.2 36.9
-58.3 36.9
SURROUND L/R -29.2 0.1 COMMON
0
AC56.7
59.9
1.1
to TRANSFORMER
59.9
OUTPUT
1.1
1.1
58.7
0.6
0.6
58.2 0.1
1.1 -0.4 0 59.6
-1.0
-1.0
6 58.2 59.3 0 60.0 -60.1
4.7/50 0
0 0
AC88.7
C5
-0.5 -0.5
INPUT
0
-0.5 -0.5
Page 73
0
-1.0
-1.0
-60.1 -60.1
-57.2
0
-57.7
-58.3
-57.2
IC104 : NJM7812FA
MAIN (4) -59.1
-58.2 20.4 RX-V459/DSP-AX459
Voltage regulator
59.9
AC32.0
1.1 -0.1 -0.1
models
1.1
59.9
INPUT
-58.2 -59.4
1.1
1.1
4.7/50 0.6 -21.1

0 0 0.6
AC19.8
-0.4 0 59.6
-13.6 -13.6
-1.0
0
-1.0
7 0
30.4
OUTPUT
AC23.1
20.4 13.8
-0.1 13.3
-0.1
0 0
-0.5
-21.1
-0.5
-1.0
0
-1.0
-60.1
-60.1
-57.7 20.4 11.9
COMMON
0
0 Page 71 D1
-57.2
-58.3
-57.2
0 to DSP_CB57
-13.6 -21.0 -12.0
-54.2 -59.4 59.4

30.3 23.2
-14.1
-48.7 0 IC105 : NJM79M12FA
-59.4 -16.9 Page 74 H9 Voltage regulator
-14.1 4.5
4.2
4.8 0.1 RX-V459/DSP-AX459 to MAIN (1)_W1002A
8 0 0
4.2
0.1
models COMMON
to TRANSFORMER
0
0
0 0
11.2
5.0
0
11.2
5.0
0
11.2
3.3
-58.9
0
0.9 5.0 OUTPUT
HTR-5935 model Page 73 I3
-58.3 -60.1 0
0
11.8 11.8
-12.9 -5.0
INPUT
11.2
11.8 11.5 0
5.0
0
9 MAIN (2)
IC107 : NJM2388F
Low dropout voltage regulator with ON/OFF control
Page 75 B4 Page 74 J8
Vin 1 2 Vout
YST_CB500 to MAIN (2)_W1002B
Bandgrap
Reference +
-
ON/OFF
Cont 4 control
Over Voltage Thermal Over Current

Protection Protection Protection
10 GND 3

74
YST HTR-5935
1
SUBWOOFER
3
to MAIN (1)_CB101
C9
Page 74
YST
IC500 : NJM2068LD
Dual operational-amplifier
V+
8
2, 6 OUTPUT
–INPUT
9 +INPUT
3, 5
1, 7
V–
4

10 with parts having specifications equal to those originally installed.
75
Service News Audio
YAMAHA CORPORATION P.O. BOX1, HAMAMATSU, JAPAN BULLETIN
NO. E-1075
RX-V459/HTR-5940 DATE October 2006
HTR-5935 RELATED
BULLETIN NO.
Service Manual Correction
Please make the correction on your Service Manual as follows.
ERROR Page69
Contents: SCHEMATIC DAIGRAMS DSP 1/3
Location: IC2 (MICRO PROCESSOR) Port.120
Error Description: 2.7V
CORRECT
Correct Description: 1.8V

Yamaha Htr-5940-Au

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AV RECEIVER/AV AMPLIFIER

100998 2006 All rights reserved.

■ SELF DIAGNOSIS FUNCTION (DIAG)／自己診断機能（ダイアグ） No. MAIN MENU

10. ISO Tone / 32k

• Starting DIAG ● ダイアグの起動

Keys of main unit / 本体キー

Turn on the power while pressing these keys.

• Starting DIAG in the protection cancel ● プロテクション解除モードでの起動

In this mode, the “SLEEP” segment of the FL display of the

• Display provided when DIAG started ● ダイアグ起動時の表示

When there is no history of protection function: プロテクション履歴が無い場合：

Opening message / オープニング表示 DIAG menu display / ダイアグメニュー表示

When there is no protection history After a few seconds

NO PROTECT A 1.ANALOG BYPAS

When there is a history of protection function: プロテクション履歴がある場合：

The protection function worked due to ex- スピーカーをショートさせた時などが原因で、プ

The protection function worked due to a 電源電圧による原因で、プロテクションが働いた

The protection function worked due to a DC アンプの故障でスピーカーに直流電圧が掛かるな

The protection function worked due to the 温度制限を越えた原因で、プロテクションが働い

For detection of each protection function (except I-PRO- 各プロクテクションの検出に関しては、後述のダイアグメニュー

History of protection function プロテクションの履歴

• Display during menu operation ● メニュー動作中の表示

• Operation procedure of DIAG menu and ● ダイアグメニューとサブメニューの操作

Keys of main unit / 本体キー

DIAG menu selection SUB-MENU selection

Reverse Forward Reverse Forward Reverse Forward

• Functions in DIAG mode ● ダイアグ中の機能

• Initial settings used to start DIAG ● ダイアグ開始時の初期設定

• Details of DIAG menu ● ダイアグメニュー詳細

ANALOG BYPASS ANALOG BYPASS

DSP BYPASS DSP BYPASS

(Shaded items not used in this example)

A/D SBL / SBR

(Shaded items not used in this example)

2. RAM THROUGH 2. RAM THROUGH

RAM MARGIN RAM MARGIN

FRONT CENTER SURROUND SURROUND BACK SUBWOOFER

RAM FULL BIT RAM FULL BIT

FRONT CENTER SURROUND SURROUND BACK SUBWOOFER

2.RAM FULL BIT

A/D SBL / SBR

(Shaded items not used in this example)

When input source is stereo, signal is assigned as below.

Front L → Center / Surround L / Surround Back L, R

3. PRO LOGIC 3. PRO LOGIC

A/D SBL / SBR

(Shaded items not used in this example)

4. SPEAKERS SET 4. SPEAKERS SET

Sub-menu FRONT L/R CENTER SUR. L/R SUR.B L/R LFE/BASS

5. XCH INPUT 5. XCH INPUT

XCH INPUT_6 (ohms) XCH INPUT_6（ohms）

XCH INPUT_8 (ohms) XCH INPUT_8（ohms）

LIMIT SET LIMIT SET

6.MIC CHK --dB

7. DISPLAY CHECK 7. DISPLAY CHECK

Checking FL display section /

Initial display / 初期表示

All segments OFF / 全セグメント消灯

All segments ON (dimmer 100%) /

All segments ON (dimmer 50%) /

Lighting of segments in lattice /

Lighting in lattice / 格子状点灯

Short / ショート Normal / 正常