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Low Drift, Low Power Instrumentation Amplifier AD621
Low Drift, Low Power Instrumentation Amplifier AD621
Instrumentation Amplifier
AD621
FEATURES CONNECTION DIAGRAM
EASY TO USE 8-Lead Plastic Mini-DIP (N), Cerdip (Q)
Pin-Strappable Gains of 10 and 100 and SOIC (R) Packages
All Errors Specified for Total System Performance
Higher Performance than Discrete In Amp Designs
G = 10/100 1 8 G = 10/100
Available in 8-Lead DIP and SOIC
–IN 2 AD621 7 +VS
Low Power, 1.3 mA Max Supply Current TOP VIEW
Wide Power Supply Range (ⴞ2.3 V to ⴞ18 V) +IN 3
(Not to Scale)
6 OUTPUT
–VS 4 5 REF
EXCELLENT DC PERFORMANCE
0.15% Max, Total Gain Error
ⴞ5 ppm/ⴗC, Total Gain Drift gain drift errors are achieved by the use of internal gain setting
125 V Max, Total Offset Voltage resistors. Fixed gains of 10 and 100 can easily be set via external
1.0 V/ⴗC Max, Offset Voltage Drift pin strapping. The AD621 is fully specified as a total system,
LOW NOISE therefore, simplifying the design process.
9 nV/√Hz, @ 1 kHz, Input Voltage Noise For portable or remote applications, where power dissipation,
0.28 V p-p Noise (0.1 Hz to 10 Hz) size, and weight are critical, the AD621 features a very low
EXCELLENT AC SPECIFICATIONS supply current of 1.3 mA max and is packaged in a compact
800 kHz Bandwidth (G = 10), 200 kHz (G = 100) 8-lead SOIC, 8-lead plastic DIP or 8-lead cerdip. The AD621
12 s Settling Time to 0.01% also excels in applications requiring high total accuracy, such
as precision data acquisition systems used in weigh scales and
APPLICATIONS
transducer interface circuits. Low maximum error specifications
Weigh Scales
including nonlinearity of 10 ppm, gain drift of 5 ppm/°C, 50 µV
Transducer Interface and Data Acquisition Systems
offset voltage, and 0.6 µV/°C offset drift (“B” grade), make
Industrial Process Controls
possible total system performance at a lower cost than has been
Battery-Powered and Portable Equipment
previously achieved with discrete designs or with other mono-
PRODUCT DESCRIPTION lithic instrumentation amplifiers.
The AD621 is an easy to use, low cost, low power, high accu-
When operating from high source impedances, as in ECG and
racy instrumentation amplifier that is ideally suited for a wide
blood pressure monitors, the AD621 features the ideal combina-
range of applications. Its unique combination of high perfor-
tion of low noise and low input bias currents. Voltage noise is
mance, small size and low power, outperforms discrete in amp
specified as 9 nV/√Hz at 1 kHz and 0.28 µV p-p from 0.1 Hz to
implementations. High functionality, low gain errors, and low
10 Hz. Input current noise is also extremely low at 0.1 pA/√Hz.
30,000 The AD621 outperforms FET input devices with an input bias
current specification of 1.5 nA max over the full industrial tem-
perature range.
TOTAL ERROR, ppm OF FULL SCALE
25,000
3 OP AMP
IN AMP 10,000
TOTAL INPUT VOLTAGE NOISE, G = 100 – Vp-p
20,000 (3 OP 07S)
1,000
15,000
TYPICAL STANDARD
BIPOLAR INPUT
10,000 AD621A 100
(0.1 – 10Hz)
IN AMP
5,000
10
AD621 SUPERETA
0 BIPOLAR INPUT
0 5 10 15 20 IN AMP
1
SUPPLY CURRENT – mA
GAIN
Gain Error VOUT = ± 10 V 0.15 0.05 0.15 %
Nonlinearity,
VOUT = –10 V to +10 V RL = 2 kΩ 2 10 2 10 2 10 ppm of FS
Gain vs. Temperature –1.5 ±5 –1.5 ±5 –1 ±5 ppm/°C
TOTAL VOLTAGE OFFSET
Offset (RTI) VS = ± 15 V 75 250 50 125 75 250 µV
Over Temperature VS = ± 5 V to ± 15 V 400 215 500 µV
Average TC VS = ± 5 V to ± 15 V 1.0 2.5 0.6 1.5 1.0 2.5 µV/°C
Offset Referred to the
Input vs. Supply (PSR)2 VS = ± 2.3 V to ± 18 V 95 120 100 120 95 120 dB
Total NOISE
Voltage Noise (RTI) 1 kHz 13 17 13 17 13 17 nV/√Hz
RTI 0.1 Hz to 10 Hz 0.55 0.55 0.8 0.55 0.8 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz–10 Hz 10 10 10 pA p-p
INPUT CURRENT VS = ± 15 V
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10储2 10储2 10储2 GΩ储pF
Common-Mode 10储2 10储2 10储2 GΩ储pF
Input Voltage Range3 VS = ± 2.3 V to ± 5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
Over Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
Over Temperature –VS + 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ± 10 V 93 110 100 110 93 110 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ± 2.3 V to ± 5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
Over Temperature –VS + 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
Over Temperature –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V
Short Current Circuit ± 18 ± 18 ± 18 mA
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth 800 800 800 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step 12 12 12 µs
REFERENCE INPUT
RIN 20 20 20 kΩ
IIN VIN +, VREF = 0 50 60 50 60 +50 +60 µA
Voltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
POWER SUPPLY
Operating Range ± 2.3 ± 18 ± 2.3 ± 18 ± 2.3 ± 18 V
Quiescent Current VS = ± 2.3 V to ± 18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices’ military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSRR is defined.
3
Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.
–2– REV. B
AD621
Gain = 100 (Typical @ 25ⴗC, VS = ⴞ15 V, and RL = 2 k⍀, unless otherwise noted.)
GAIN
Gain Error VOUT = ± 10 V 0.15 0.05 0.15 %
Nonlinearity,
VOUT = –10 V to +10 V RL = 2 kΩ 2 10 2 10 2 10 ppm of FS
Gain vs. Temperature –1 ±5 –1 ±5 –1 ±5 ppm/°C
TOTAL VOLTAGE OFFSET
Offset (RTI) VS = ± 15 V 35 125 25 50 35 125 µV
Over Temperature VS = ± 5 V to ± 15 V 185 215 225 µV
Average TC VS = ± 5 V to ± 15 V 0.3 1.0 0.1 0.6 0.3 1.0 µV/°C
Offset Referred to the
Input vs. Supply (PSR)2 VS = ± 2.3 V to ± 18 V 110 140 120 140 110 140 dB
Total NOISE
Voltage Noise (RTI) 1 kHz 9 13 9 13 9 13 nV/√Hz
RTI 0.1 Hz to 10 Hz 0.28 0.28 0.4 0.28 0.4 µV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz–10 Hz 10 10 10 pA p-p
INPUT CURRENT VS = ± 15 V
Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA
Over Temperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C
Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA
Over Temperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C
INPUT
Input Impedance
Differential 10储2 10储2 10储2 GΩ储pF
Common-Mode 10储2 10储2 10储2 GΩ储pF
Input Voltage Range3 VS = ± 2.3 V to ± 5 V –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 –VS + 1.9 +VS – 1.2 V
Over Temperature –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 –VS + 2.1 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 –VS + 1.9 +VS – 1.4 V
Over Temperature –VS + 2.1 +VS – 1.4 –VS + 2.1 +VS – 1.4 –VS + 2.3 +VS – 1.4 V
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ± 10 V 110 130 120 130 110 130 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ± 2.3 V to ± 5 V –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 –VS + 1.1 +VS – 1.2 V
Over Temperature –VS + 1.4 +VS – 1.3 –VS + 1.4 +VS – 1.3 –VS + 1.6 +VS – 1.3 V
VS = ± 5 V to ± 18 V –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 –VS + 1.2 +VS – 1.4 V
Over Temperature –VS + 1.6 +VS – 1.5 –VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V
Short Current Circuit ± 18 ± 18 ± 18 mA
DYNAMIC RESPONSE
Small Signal,
–3 dB Bandwidth 200 200 200 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step 12 12 12 µs
REFERENCE INPUT
RIN 20 20 20 kΩ
IIN VIN +, VREF = 0 50 60 50 60 50 60 µA
Voltage Range –VS + 1.6 +VS – 1.6 –VS + 1.6 +VS – 1.6 VS + 1.6 +VS – 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001
POWER SUPPLY
Operating Range ± 2.3 ± 18 ± 2.3 ± 18 ± 2.3 ± 18 V
Quiescent Current VS = ± 2.3 V to ± 18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA
Over Temperature 1.1 1.6 1.1 1.6 1.1 1.6 mA
TEMPERATURE RANGE
For Specified Performance –40 to +85 –40 to +85 –55 to +125 °C
NOTES
1
See Analog Devices’ military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSEE is defined.
3
Input Voltage Range = CMV + (Gain × VDIFF).
Specifications subject to change without notice.
REV. B –3–
AD621
ABSOLUTE MAXIMUM RATINGS 1 ESD SUSCEPTIBILITY
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V ESD (electrostatic discharge) sensitive device. Electrostatic
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 650 mW charges as high as 4000 volts, which readily accumulate on the
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS human body and on test equipment, can discharge without
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 25 V detection. Although the AD621 features proprietary ESD pro-
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite tection circuitry, permanent damage may still occur on these
Storage Temperature Range (Q) . . . . . . . . . –65°C to +150°C devices if they are subjected to high energy electrostatic dis-
Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C charges. Therefore, proper ESD precautions are recommended
Operating Temperature Range to avoid any performance degradation or loss of functionality.
AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . . – 40°C to +85°C
AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to +125°C ORDERING GUIDE
Lead Temperature Range
Temperature Package Package
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Model Range Description Option1
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma- AD621AN –40°C to +85°C 8-Lead Plastic DIP N-8
nent damage to the device. This is a stress rating only; functional operation of the AD621BN –40°C to +85°C 8-Lead Plastic DIP N-8
device at these or any other conditions above those indicated in the operational AD621AR –40°C to +85°C 8-Lead Plastic SOIC R-8
section of this specification is not implied. Exposure to absolute maximum rating
AD621BR –40°C to +85°C 8-Lead Plastic SOIC R-8
conditions for extended periods may affect device reliability.
2
Specification is for device in free air: AD621SQ/883B2 –55°C to +125°C 8-Lead Cerdip Q-8
8-Lead Plastic Package: θJA = 95°C/W AD621ACHIPS –40°C to +85°C Die
8-Lead Cerdip Package: θJA = 110°C/W
NOTES
8-Lead SOIC Package: θJA = 155°C/W 1
N = Plastic DIP; Q = Cerdip; R = SOIC.
2
See Analog Devices’ military data sheet for 883B specifications.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
1.125 (3.57)
+VS OUTPUT
7 6
RG 8
5
REFERENCE
0.0708
(2.545)
RG 1
4 –VS
2 3
–IN +IN
–4– REV. B
Typical Performance Characteristics–AD621
50 50
40 40
PERCENTAGE OF UNITS
PERCENTAGE OF UNITS
30 30
20 20
10 10
0 0
–200 –100 0 +100 +200 –800 –400 0 +400 +800
INPUT OFFSET VOLTAGE – V INPUT BIAS CURRENT – pA
TPC 1. Typical Distribution of VOS, Gain = 10 TPC 4. Typical Distribution of Input Bias Current
50 2.0
SAMPLE SIZE = 90
30
1.0
20
0.5
10
0 0
–80 –40 0 +40 +80 0 1 2 3 4 5
INPUT OFFSET VOLTAGE – V WARM-UP TIME – Minutes
TPC 2. Typical Distribution of VOS, Gain = 100 TPC 5. Change in Input Offset Voltage vs. Warm-Up Time
50 1000
SAMPLE SIZE = 90
40
VOLTAGE NOISE – nV/ Hz
PERCENTAGE OF UNITS
100
30
GAIN = 10
20
10
10 GAIN = 100
0 1
–400 –200 0 +200 +400 1 10 100 1k 10k 100k
INPUT OFFSET CURRENT – pA FREQUENCY – Hz
TPC 3. Typical Distribution of Input Offset Current TPC 6. Voltage Noise Spectral Density
REV. B –5–
AD621
1000
100mV 1s
100
CURRENT NOISE – nV/ Hz
90
100
10
0%
10
1 10 100 1000
FREQUENCY – Hz
TPC 7. Current Noise Spectral Density vs. Frequency TPC 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical
Div, 1 Second per Horizontal Div
100,000
FET INPUT
IN AMP
1000
100
AD621A
10
TIME – 1 sec/div
1k 10k 100k 1M 10M
SOURCE RESISTANCE – ⍀
TPC 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10 TPC 10. Total Drift vs. Source Resistance
160
120
RTI NOISE – 0.1V/div
100 GAIN = 10
CMR – dB
80
60
40
20
0
TIME – 1 sec/div 0.1 1 10 100 1k 10k 100k 1M
FREQUENCY – Hz
TPC 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100 TPC 11. CMR vs. Frequency, RTI, for a Zero to 1 kΩ
Source Imbalance
–6– REV. B
AD621
180 35
G = 10 & 100
160
30
G = 100
20
100
15
80
10
60
40 5
20 0
0.1 1 10 100 1k 10k 100k 1M 1k 10k 100k 1M
FREQUENCY – Hz FREQUENCY – Hz
TPC 12. Positive PSR vs. Frequency TPC 15. Large Signal Frequency Response
160 –0.5
120 –1.5
G = 10
PSR – dB
100
80 +1.5
60 +1.0
40 +0.5
20 –VS +0.0
0.1 1 10 100 1k 10k 100k 1M 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE ⴞ Volts
TPC 13. Negative PSR vs. Frequency TPC 16. Input Voltage Range vs. Supply Voltage
–0.5 RL = 10k⍀
(REFERRED TO SUPPLY VOLTAGES)
INPUT VOLTAGE LIMIT – Volts
CLOSED-LOOP GAIN – V/V
100 –1.0
–1.5
RL = 2k⍀
10
+1.5 RL = 2k⍀
1 +1.0
+0.5
RL = 10k⍀
0.1 –VS +0.0
100 1k 10k 100k 1M 10M 0 5 10 15 20
FREQUENCY – Hz SUPPLY VOLTAGE ⴞ Volts
TPC 14. Closed-Loop Gain vs. Frequency TPC 17. Output Voltage Swing vs. Supply Voltage,
G = 10
REV. B –7–
AD621
30
OUTPUT VOLTAGE SWING – Volts p-p
VS = ⴞ 15V
5V 1mV 10s
G = 10
100
20 90
10
10
0%
0
0 100 1k 10k
LOAD RESISTANCE – ⍀
TPC 18. Output Voltage Swing vs. Resistive Load TPC 21. Large Signal Pulse Response and Settling
Time, G = 100 (0.5 mV = 0.1%), RL = 2 kΩ, CL = 100 pF
100 100
90 90
10 10
0% 0%
TPC 19. Large Signal Pulse Response and Settling TPC 22. Small Signal Pulse Response, G = 100,
Time Gain, G = 10 (0.5 mV = 0.01%), RL = 1 kΩ, RL = 2 kΩ, CL = 100 pF
CL = 100 pF
20
20mV 10s
TO 0.01%
100
15
90
SETTLING TIME – s
TO 0.1%
10
10
5
0%
0
0 5 10 15 20
OUTPUT STEP SIZE – Volts
TPC 20. Small Signal Pulse Response, G = 10, TPC 23. Settling Time vs. Step Size, G = 10
RL = 1 kΩ, CL = 100 pF
–8– REV. B
AD621
20
100V 2V
TO 0.01%
100
15
90
SETTLING TIME – s
TO 0.1%
10
10
5
0%
0
0 5 10 15 20
OUTPUT STEP SIZE – Volts
TPC 24. Settling Time vs. Step Size, Gain = 100 TPC 27. Gain Nonlinearity, G = 10, RL = 10 kΩ, Vertical
Scale: 100 µ V/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div
2.0
10k⍀ 1k⍀ 10k⍀
1.5 1% 10T 1%
+IB
1.0 +VS VOUT
INPUT CURRENT – nA
100k⍀
0.5 1%
INPUT –
–IB 20V p-p
0 G = 10 G = 100
G = 10
11k⍀ 1k⍀ AD621
G = 100
–0.5 0.1% 0.1%
–1.0 +
–1.5 –VS
–2.0
–125 –75 –25 25 75 125 175
TEMPERATURE – ⴗC
TPC 25. Input Bias Current vs. Temperature TPC 28. Settling Time Test Circuit
100
90
10
0%
REV. B –9–
AD621
+VS
R5 at a gain of 10 or the parallel combination of R5 and R6 at a
7
gain of 100.
I1 20A VB 20A I2 This creates a differential gain from the inputs to the A1/A2
outputs given by G = (R1 + R2) / RG + 1. The unity-gain
–
– +
subtracter A3 removes any common-mode signal, yielding a
+
A1 A2 10k⍀
single-ended output referred to the REF pin potential.
C1 C2
10k⍀
– OUTPUT
The value of RG also determines the transconductance of the
A3 preamp stage. As RG is reduced for larger gains, the transcon-
+ 6
R1 25k⍀ R2 25k⍀
10k⍀ ductance increases asymptotically to that of the input transistors.
R3 10k⍀
400⍀ R5 REF This has three important advantages: (a) Open-loop gain is
–IN Q1 Q2 +IN 5
5555.6⍀ boosted for increasing programmed gain, thus reducing gain-
2 R4 3
R6 400⍀ related errors. (b) The gain-bandwidth product (determined by
555.6⍀
1 8 C1, C2 and the preamp transconductance) increases with pro-
G = 100 G = 100
grammed gain, thus optimizing frequency response. (c) The
input voltage noise is reduced to a value of 9 nV/√Hz, deter-
4
–VS
mined mainly by the collector current and base resistance of the
input devices.
Figure 3. Simplified Schematic of AD621 Make vs. Buy: A Typical Bridge Application Error Budget
The AD621 offers improved performance over discrete three op
THEORY OF OPERATION amp IA designs, along with smaller size, fewer components and
The AD621 is a monolithic instrumentation amplifier based on 10 times lower supply current. In the typical application, shown
a modification of the classic three op amp circuit. Careful layout in Figure 4, a gain of 100 is required to amplify a bridge output of
of the chip, with particular attention to thermal symmetry builds 20 mV full scale over the industrial temperature range of –40°C to
in tight matching and tracking of critical components, thus +85°C. The error budget table below shows how to calculate
preserving the high level of performance inherent in this circuit, the effect various error sources have on circuit accuracy.
at a low price. Regardless of the system it is being used in, the AD621 provides
On chip gain resistors are pretrimmed for gains of 10 and 100. greater accuracy, and at low power and price. In simple systems,
The AD621 is preset to a gain of 10. A single external jumper absolute accuracy and drift errors are by far the most significant
(between Pins 1 and 8) is all that is needed to select a gain of contributors to error. In more complex systems with an intelligent
100. Special design techniques assure a low gain TC of 5 ppm/°C processor, an autogain/autozero cycle will remove all absolute
max, even at a gain of 100. accuracy and drift errors leaving only the resolution errors of
Figure 3 is a simplified schematic of the AD621. The input gain nonlinearity and noise, thus allowing full 14-bit accuracy.
transistors Q1 and Q2 provide a single differential-pair bipolar Note that for the discrete circuit, the OP07 specifications for
input for high precision, yet offer 10× lower Input Bias Current, input voltage offset and noise have been multiplied by 2. This is
thanks to Superβeta processing. Feedback through the Q1-A1-R1 because a three op amp type in amp has two op amps at its inputs,
loop and the Q2-A2-R2 loop maintains constant collector cur- both contributing to the overall input error.
rent of the input devices Q1 and Q2, thereby impressing the
input voltage across the gain-setting resistor, RG, which equals
–10– REV. B
AD621
5V
20k⍀
+
3k⍀ 3k⍀
REF
AD621B IN
3k⍀ 3k⍀
DIGITAL
10k⍀ ADC DATA
– OUTPUT
+
20k⍀ AD705 AGND
–
1.7mA 1.3mA 0.10mA 0.6mA
MAX MAX
REV. B –11–
AD621
INPUT A: +
ⴞ10V CM
VDIFF
ⴞ0.5V
–
+
VCOM
OPTIONAL
ⴞ10V– –
ⴛ10 VOUT2
+
DAC AD621 TOTAL GAIN = 100
INPUT B: 0 TO ⴞ10V
ⴞ1V + 10k⍀
+
OFFSET VDIFF + VOFFSET
ⴞ(1.25V + 1V)
–
TO TO
REF C VOUT1
R
–
AD548
Figure 6. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal
(VS = ± 15 V)
The AD621, as well as many other monolithic instrumentation The AD621’s input amplifiers can provide output voltage within
amplifiers, is based on the “three op amp” in amp circuit (Fig- 2.5 V of the supplies. To avoid saturation of the input amplifier
ure 7) amplifier. Since the input amplifiers (A1 and A2) have a the input voltage must therefore obey the equations:
common-mode gain of unity and a differential gain equal to the VCM + G × VDIFF/2 ≤ (Upper Supply – 2.5 V)
set gain of the overall in amp, the voltages V1 and V2 are defined
by the equations VCM – G × VDIFF/2 ≥ (Lower Supply + 2.5 V)
V1 = VCM + G × VDIFF/2 Figure 8 shows the trade-off between common-mode and
differential-mode input for ± 15 V supplies and G = 10.
V2 = VCM – G × VDIFF/2
By cascading with use of the optional AD621, the circuit of
The common-mode voltage will drive the outputs of amplifiers Figure 6 will provide ± 1 V of zero suppression at gains of 10
A1 and A2 to the differential-signal voltage, multiplied by the and 100 (at VOUT1 and VOUT2 respectively) with maximum TCs
gain, spreads them apart. For a 10 V common-mode 0.1 V of ± 4 ppm/°C and ± 8 ppm/°C, respectively. Therefore, depend-
differential input, V1 would be at 10.5 V and V2 at 9.5 V. ing on the magnitude of the differential input signal, either
INPUT AMPLIFIER OUTPUT AMPLIFIER VOUT1 or VOUT2 may be used as the output.
DIFFERENTIAL GAIN = 10 DIFFERENTIAL GAIN = 1
COMMON MODE GAIN = 1 COMMON MODE GAIN = 1/1000
1.2
+ V1 10k⍀
A1 1.0
– 10k⍀
20k⍀
VDIFF – ⴞVolts
– 0.8
4.44k⍀ A3
+
20k⍀ 0.6
– 10k⍀
A2
+ V2 10k⍀ 0.4
0.2
Figure 7. Typical Three Op Amp Instrumentation
Amplifier, Differential Gain = 10
0
0 2 4 6 8 10 12
VCM – ⴞVolts
–12– REV. B
AD621
Precision V-I Converter INPUT OVERLOAD CONSIDERATIONS
The AD621 along with another op amp and two resistors make Failure of a transducer, faults on input lines, or power supply
a precision current source (Figure 9). The op amp buffers the sequencing can subject the inputs of an instrumentation ampli-
reference terminal to maintain good CMR. The output voltage fier to voltages well beyond their linear range, or even the supply
VX of the AD621 appears across R1 which converts it to a cur- voltage, so it is essential that the amplifier handle these over-
rent. This current less only the input bias current of the op amp loads without being damaged.
then flows out to the load. The AD621 will safely withstand continuous input overloads of
+VS ± 3.0 volts (± 6.0 mA). This is true for gains of 10 and 100, with
power on or off.
VIN+ R1 The inputs of the AD621 are protected by high current capacity
AD621
+VX–
dielectrically isolated 400 Ω thin-film resistors R3 and R4 (Fig-
ure 3) and by diodes which protect the input transistors Q1 and
VIN–
Q2 from reverse breakdown. If reverse breakdown occurred, there
IL
would be a permanent increase in the amplifier’s input current.
–VS
AD705 The input overload capability of the AD621 can be easily increased
while only slightly degrading the noise, common-mode rejection
VX (VIN+ ) – (VIN–) G
IL =
R1
=
R1 LOAD and offset drift of the device by adding external resistors in series
with the amplifier’s inputs as shown in Figure 10.
Table II summarizes the overload voltages and total input
Figure 9. Precision Voltage to Current Converter noise for a range of range of r values. Note that a 2 kΩ resis-
(Operates on 1.8 mA, ± 3 V) tor in series with each input will protect the AD621 from a
± 15 volt continuous overload, while only increasing input noise
INPUT AND OUTPUT OFFSET VOLTAGE to 13 nV√Hz—about the same level as would be expected from
The AD621 is fully specified for total input errors at gains of 10 a typical unprotected 3 op amp in amp.
and 100. That is, effects of all error sources within the AD621
are properly included in the guaranteed input error specs, elimi- Table II. Input Overload Protection vs. Value of Resistor RP
nating the need for separate error calculation.
Total Input Noise Maximum Continuous
Total Error RTI = Input Error + (Output Error/G) Value of in nV√Hz @ 1 kHz Overload Voltage, VOL
Total Error RTO = (Input Error × G) + Output Error Resistor RP G = 10 G = 100 In Volts
0 14 9 3
REFERENCE TERMINAL
499 Ω 14 10 6
Although usually grounded, the reference terminal may be used
1.00 kΩ 14 11 9
to offset the output of the AD621. This is useful when the load
2.00 kΩ 15 13 15
is “floating” or does not share a ground with the rest of the system.
3.01 kΩ* 16 14 21
It also provides a direct means of injecting a precise offset.
4.99 kΩ* 17 16 33
Another benefit of having a reference terminal is that it can be
*1/4 watt, 1% metal-film resistor. All others are 1/8 watt, 1% RN55
quite effective in eliminating ground loops and noise in a circuit or equivalent.
or system.
+VS
RP
VOL VOUT
AD621
VOL RP
GAIN = 10 OR 100
–VS
REV. B –13–
AD621
Gain Selection +VS
+VS
The AD621 has accurate, low temperature coefficient (TC),
gains of 10 and 100 available. The gain of the AD621 is nomi- 0.1F 0.1F
–
nally set at 10; this is easily changed to a gain of 100 by simply –
connecting a jumper between Pins 1 and 8. INPUTS AD621 –
+ OUTPUT
+ AD526
+ 2
G = 10
555.5⍀ 20k⍀
0.1F
REXT 5,555.5⍀ AD621 –VS
0.1F
–VS
–14– REV. B
AD621
GROUNDING +VS
AD621 VOUT
0.1F 0.1F
1F 1F 1F
LOAD
+INPUT
7
2 4 11 4 + –VS
7 9 11 15 1 REFERENCE
AD621 6 AD585 DIGITAL
6 S/H AD574A
3 5 DATA
ADC OUTPUT
TO POWER SUPPLY GROUND
Figure 15. Basic Grounding Practice Figure 16b. Ground Returns for Bias Currents when Using
a Thermocouple Input
GROUND RETURNS FOR INPUT BIAS CURRENTS +VS
Input bias currents are those currents necessary to bias the input
–INPUT
transistors of an amplifier. There must be a direct return path
for these currents; therefore when amplifying “floating” input AD621 VOUT
sources such as transformers, or ac-coupled sources, there must LOAD
+INPUT
be a dc path from each input to ground as shown in Figures 16a REFERENCE
through 16c. Refer to the Instrumentation Amplifier Application 100k⍀ 100k⍀
–VS
Guide (free from Analog Devices) for more information regard-
ing in amp applications. TO POWER SUPPLY GROUND
REV. B –15–
AD621
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8 5
0.25 0.31
C00776–0–1/01 (rev. B)
(6.35) (7.87)
1 4
0.035 0.01
0.165 0.01 (0.89 0.25)
(4.19 0.25)
SEATING PLANE
0.125 (3.18) 0.011 0.003
MIN (4.57 0.76)
0.18 0.03
0.10 (4.57 0.76) 0 - 15
0.018 0.003
(0.46 0.08) (2.54)
TYP
0.033
(0.84)
NOM
8 5
0.310 (7.87)
0.220 (5.59)
1 4
0.070 (1.78)
0.030 (0.76)
0.320 (8.13)
0.405 (10.29) MAX 0.290 (7.37)
0.150
0.200 (5.08) (3.81) 0.015 (0.38)
0.125 (3.18) MIN 0.008 (0.20)
8 5
0.244 (6.200)
1 4 0.228 (5.80)
0.018 (0.46)
0.050 (1.27) 0.014 (0.36) 0.205 (5.20)
TYP 0.181 (4.60)
0.094(2.39)
0.010 (0.25) 0.100 (2.59) 0.015 (0.38) 0.045 (1.15)
0.004 (0.10) 0.007 (0.18) 0.020 (0.50)
–16– REV. B