Professional Documents
Culture Documents
SN54/74LS90 SN54/74LS92 SN54/74LS93: Low Power Schottky
SN54/74LS90 SN54/74LS92 SN54/74LS93: Low Power Schottky
SN54/74LS92
DECADE COUNTER; SN54/74LS93
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
DECADE COUNTER;
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
DIVIDE-BY-TWELVE COUNTER;
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY COUNTER
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi- LOW POWER SCHOTTKY
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
• Low Power Consumption . . . Typically 45 mW J SUFFIX
• High Count Rates . . . Typically 42 MHz CERAMIC
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08
Binary 14
1
• Input Clamp Diodes Limit High Speed Termination Effects
LOGIC SYMBOL
1 2
MS
14 CP0 14 CP0 14 CP0
1 CP1 1 CP1 1 CP1
MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3 MR Q0 Q1 Q2 Q3
1 2 1 2 1 2
2 3 12 9 8 11 6 7 12 11 9 8 2 3 12 9 8 11
VCC = PIN 5 VCC = PIN 5 VCC = PIN 5
GND = PIN 10 GND = PIN 10 GND = PIN 10
NC = PINS 4, 13 NC = PINS 2, 3, 4, 13 NC = PIN 4, 6, 7, 13
NC 2 13 NC
J Q J Q J Q J Q
14
CP0 NC 3 12 Q0
CP CP CP CP
KC Q KC Q KC Q KC Q NC 4 11 Q1
D D D D
VCC 5 10 GND
1
CP1 MR1 6 9 Q2
6
MR1 12 11 9 8 MR2 7 8 Q3
MR2
7 Q0 Q1 Q2 Q3
NC = NO INTERNAL CONNECTION
= PIN NUMBERS NOTE:
VCC = PIN 5 The Flatpak version has the same
GND = PIN 10 pinouts (Connection Diagram) as
the Dual In-Line Package.
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade, C. Divide-By-Two and Divide-By-Five Counter — No external
Divide-By-Twelve, and Binary Counters respectively. Each interconnections are required. The first flip-flop is used as a
device consists of four master/slave flip-flops which are binary element for the divide-by-two function (CP0 as the
internally connected to provide a divide-by-two section and a input and Q0 as the output). The CP1 input is used to obtain
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight binary divide-by-five operation at the Q3 output.
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
LS92
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore, A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
decoded output signals are subject to decoding spikes and must be externally connected to the Q0 output. The CP0 in-
should not be used for clocks or strobes. The Q0 output of put receives the incoming count and Q3 produces a sym-
each device is designed and specified to drive the rated metrical divide-by-twelve square wave output.
fan-out plus the CP1 input of the device. B. Divide-By-Two and Divide-By-Six Counter —No external
A gated AND asynchronous Master Reset (MR1 • MR2) is interconnections are required. The first flip-flop is used as a
provided on all counters which overrides and clocks and binary element for the divide-by-two function. The CP1 in-
resets (clears) all the flip-flops. A gated AND asynchronous put is used to obtain divide-by-three operation at the Q1
Master Set (MS1 • MS2) is provided on the LS90 which and Q2 outputs and divide-by-six operation at the Q3 out-
overrides the clocks and the MR inputs and sets the outputs to put.
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices LS93
may be operated in various counting modes. A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
LS90 to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
A. BCD Decade (8421) Counter — The CP1 input must be ex- performed at the Q0, Q1, Q2, and Q3 outputs as shown in
ternally connected to the Q0 output. The CP0 input receives the truth table.
the incoming count and a BCD count sequence is pro-
B. 3-Bit Ripple Counter— The input count pulses are applied
duced.
to input CP1. Simultaneous frequency divisions of 2, 4, and
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 8 are available at the Q1, Q2, and Q3 outputs. Independent
output must be externally connected to the CP0 input. The use of the first flip-flop is available if the reset function coin-
input count is then applied to the CP1 input and a divide-by- cides with reset of the 3-bit ripple-through counter.
ten square wave is obtained at output Q0.
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
Q 1.3 V 1.3 V
Figure 1
*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the appropriate Truth Tables.
CP 1.3 V CP 1.3 V
tPHL tPLH
Q0 • Q3
Q 1.3 V (LS90) 1.3 V
Figure 2 Figure 3