Quanta ZU1

5 4 3 2 1
ZU1 SYSTEM BLOCK DIAGRAM

P C I DEVICE IDSEL# R EQ# / GNT# Interrupts CLOCK
DVI / 7307 CLOCK GENERATOR

Chrontel Merom 479 CPU
CB1410 AD17 R EQ0# / GNT0# INT A# C K 505/PCI1
CK505
(only for ezDock) uFCPGA Thermal Sensor
MR510 AD18 R EQ1# / GNT1# INTB# C K 505/PCI0
D D
Page 21 T IAB23 AD25 R EQ2# / GNT2# INTE# C K 505/PCI2
Page 2 Page 3
Page 3,4
S-VIDEO CONN FSB

Page 20
667/800 Mhz
DDRII
SDVO Dual Channel DDR2 SO-DIMM 0
LCD CONN TV 533/667 MHz
SO-DIMM 1 RJ45
(12.1"WXGA) LVDS NB Page 18
Page 20 VGA Page 12,13
Crestline
(GM965) Transformer
CRT Port Page 5~11 Page 18
Page 19
X4 DMI interface
Mini Card / Giga Lan
HDD (SATA) SATA
C
WLAN (BCM 5787)
C
Page 26
SB Page 27 Page 18
PATA PCIE-0 PCIE-1
ODD (PATA) PCI-Express
Page 26
USB 2.0 ICH8M
Azalia
Page 14~17
PCI Bus
USB Port x 3
USB0~2 Page 27
LPC
Bluetooth PCMCIA Card Reader
USB4 Page 27 1394
Controller Controller Controller
Super I/O
Finger Printer uR PC8763L (CB 1410) (MR510)
(TI 43AB23)
USB6 Page 29 NS PC87383
Page 28 Page 30 Page 22 Page 23 Page 25
B B
CCD
USB8 Page 20
SPI ROM Touch Pad K/B CONN FIR PCMCIA Card Reader 1394 CONN
Page 28 Page 29 Page 29 Page 30 Page 24 Page 24 Page 25
HP HP AMP
Page 32 Page 31
Audio Codec 5V/3V (ISL6236) 1.25V 1.5V 1.25V
PCI-Express PCIE-2
(ALC268) ezDockII/II+ Page 34 Page 38
INT SPK SPK AMP DVI
Page 32 Page 32 Connector USB3
USB VCORE(ISL6262A) Discharge
PCIE , Lan ,1394
Ser & Par Port 1394*2 Page 35 Page 38
Line in & MIC
Page 32 Page 31 PS2 , VGA, DVI TV out / CRT Switch
SPDIF,SM BUS Page 20 A1A
A
VTT 1.05V (SC411) Charger (ISL6251) (11/2):(1) Re-name. A
MediaBay
(2) Gerber out
Express Card Audio Page 36 Page 39
MDC 1.5 10/100/1G Switch 1.8V (TPS51116)

Page 31 Page 33 Page 18 PROJECT : ZU1
Page 37 Quanta Computer Inc.
Size D oc um ent Num ber R ev
Bloc k Diagram 1A
D ate: T h u r s day, Novem ber 02, 2006 Sheet 1 of 39

5 4 3 2 1
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5 4 3 2 1
Clock Generator
Clock Gen I2C
L55
+3V C 288 . 1 U_4
BKP1608HS181-T_6
A1A:(9/24) C 542 0_6 C 294 . 1 U_4 +3V

ICS FAE suggest to change R 436
C2,C4 from 4.7uF to 10uF 1 0U_8 C 287 1 0U_8
ICS9LPRS365BGLFT Q21
R HU0 0 2N06 R 197
SLG8SP512T: AL8SP512K05
2
C 540 . 1 U_4 U1 9 IC(64P)SLG8SP512TTR(TSSOP) 10K_4
VD D _ C K_VDD_PCI 2 48 A1A:(9/20) remove IO_VOUT 3 1 C GDAT_SMB
VDD_PCI IO_VOUT 1 3,16,18,27,33 PDAT_SMB
C 292 . 1 U_4 VD D _CK_VDD_48 9
A1A:(9/28) VD D _ CK_VDD_SRC 16 VDD_48 64 C GCLK_SMB
D Reverse RC0603 footprint for EMI VD D _ CK_VDD_REF VDD_PLL3 SCLK C GDAT_SMB D
61 63
VDD_REF SDA +3V
0_6 C 319 . 1 U_4 VD D _ CK_VDD_SRC 39
CK505 38
VDD_SRC SRC5/PCI_STOP# PM_STPPCI# 16
R 199 VD D _ C K_VDD_CPU 55 37 P M_STPCPU# 16 Q20
VDD_CPU SRC5#/CPU_STOP# R HU0 0 2N06 R 195
2
12 54 C L K_CPU_BCLK_R RP36 1 2 0X2
+ 1.05V_VDD VDD_96_IO CPU0 C LK_CPU_BCLK 3
0_6 C 318 . 1 U_4 20 53 C L K_CPU_BCLK#_R 3 4 10K_4
VDD_PLL3_IO CPU0# C LK_CPU_BCLK# 3
R 444 26 3 1 C GCLK_SMB
VDD_SRC_IO_1 1 3,16,18,27,33 PCLK_SMB
45 51 C L K_MCH_BCLK_R RP35 1 2 0X2
VDD_SRC_IO_3 CPU1 C L K_MCH_BCLK 5
36 50 C L K_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# C L K_MCH_BCLK# 5
49
VDD_CPU_IO
47
A1A:(9/20) remove SATACLKREQ function, change R value from 475ohm to 22 ohm SRC8/ITP 46
SRC8#/ITP#
R 188 22_4 P C I_CLK_510_R 1 35 C LK_PCIE_3GPLL#_R RP34 3 4 0X2
23 P C I_CLK_510 PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
34 C LK_PCIE_3GPLL_R 1 2 Pin Active Control signal
SRC10 C LK_PCIE_3GPLL 6
R 434 33_4 P C I_CLK_CB714_R 3
22 P CI_CLK_CB714 PCI1/CR#_B
+3V R 429 10K_4 33 P CIE_CLK_RBS_R R 194 475_4 C L K_MCH_OE# 6
R 433 33_4 PCLK_1394_R SRC11/CR#_H P CIE_CLK_RBS#_R R 185 475_4 32 Low SRC9/9#
25 PCLK_1394 4 32 P CIE_CLKREQ# 33
PCI2/TME SRC11#/CR#_G
R 187 33_4 PCLK_591_R 5 30 C L K _PCIE_EZ1_R RP29 3 4 0X2
28 PCLK_591 PCI3 SRC9 PCIE_CLK1+ 33
+3V R 428 *10K_4 31 C L K _PCIE_EZ1#_R 1 2 33 Low SRC10/10#
SRC9# P CIE_CLK1- 33
R 431 22_4 P C I_CLK_SIO_R 6
2 7,30 P C I_CLK_SIO PCI4/SRC5_EN
R 427 10K_4 44
R 186 22_4 P C L K _ICH_R SRC7/CR#_F
7 43 A1A:(9/24) Base on above table, SWAP SRC3 and SRC9
R 181 *10K_4 PCIF5/ITP_EN SRC7#/CR#_E
+ 3V
C G_ XIN 60 41 C L K _ P CIE_ICH_R RP37 1 2 0X2
15 P C L K _ICH XTAL_IN SRC6 C L K _ PCIE_ICH 15
R 182 10K_4 40 C L K _ P CIE_ICH#_R 3 4
SRC6# C L K _ PCIE_ICH# 15
CG_XOUT 59
XTAL_OUT C L K _ P C IE_MINI1_R RP30 +3V
27 3 4 0X2 C L K _ P CIE_MINI1 27
R 430 33_4 F S A SRC4 C L K _ P C IE_MINI1#_R
10 28 1 2 C L K _ P CIE_MINI1# 27
16 C LKUSB_48 CLK_BSEL0 R 426 2.2K_4 USB_48/FSA SRC4#
C CLK_BSEL1 57 24 C L K _ PCIE_LAN_R RP31 3 4 0X2 C
FSB/TEST/MODE SRC3/CR#_C C L K _PCIE_LAN 18
25 C L K _PCIE_LAN#_R 1 2 R 184 10K_4 P CIE_CLKREQ#
SRC3#/CR#_D C L K _PCIE_LAN# 18
CLK_BSEL2 R 441 10K_4 FSC 62
REF0/FSC/TESTSEL C LK_PCIE_SATA_R RP32
21 3 4 0X2 C LK_PCIE_SATA 14
R 442 22_4 SRC2/SATA C LK_PCIE_SATA#_R
16 1 4 M_ ICH 8 22 1 2 C LK_PCIE_SATA# 14
VSS_PCI SRC2#/SATA#
11 A1A:(9/24) Add PCIE_CLKREQ# PU to +3V
R 443 22_4 VSS_48 D REFSSCLK_R RP41
30 S IO_14M 15 17 1 2 0X2 D REFSSCLK 6
19 VSS_IO SRC1/SE1 18 D REFSSCLK#_R 3 4 D REFSSCLK# 6
A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length VSS_PLL3 SRC1#/SE2
52
VSS_CPU D R EFCLK_R RP33
23 13 3 4 0X2 D R EFCLK 6
29 VSS_SRC1 SRC0/DOT96 14 D R EFCLK#_R 1 2
VSS_SRC2 SRC0#/DOT96# D REFCLK# 6
A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm 42
A1A:(9/20) change R value from 33ohm to 22 ohm(Intel check list 1.301) VSS_SRC3
58 56 C K _PW RGD 16
VSS_REF CKPWRGD/PWRDWN#
ICS9LPRS365AGLFT/ SLG8SP512T During initial power-up be used to
sample FSB speed with FSA/B/C
C310 33P_4 C G_ XIN <c hec k list>
Clock Gen Differential IO power

( 1 ) P C I2 / T ME: PU be us ed, the CK505 c annot over c loc k any of the c loc k for Trus t Mode s ec urity purpos es .
2
Y2
( 2 )PCI4/SRC5_EN: PU be us ed, the CK505 will be c onfigured to us e Pin37/38 to SRC5 c loc k. + 1 .05V_VDD +1.05V
1 4 . 3 18MHZ If PD be detec t at powe-on,the CK505 will s etting Pin 37/38 to PCI_STOP/CUP_SOTP
(Default is s etting to PCI_STOP/CUP_SOTP)
1
C299 33P_4 CG_XOUT L 26

BKP1608HS181-T_6
<check list> ( 3 ) P CIF5/ITP_EN: PU be us ed, the CK505 will be c onfigured to us e Pin46/47 to CPU ITP c loc k.
EMI FIL TER BKP1608HS181-T(180,1.5A)
If PD be detec t at powe-on,the CK505 will s etting Pin 46/47 to SRC8 C 320 C 309 C 300 C 301 C 316 C 314 C 317 C 290 C315 C 291 C 293
B XTAL length < 500mils (Default is s etting to SRC8) B
* 10U_8 * 1 0U_8 * 1 0U_8 1 0 U_8 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4
R 432 * 33_4 PCLK_1394_R ( 4 )SLG8SP512 Pin 6 s elec t Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,
28 P CLK_DEBUG
Pin 37, 38 will fixed be us e CPU_Stop and PCI_Stop.
BIOS/ ERIC 0 .1U c los e to eac h VDD_IO Power pin
(5)SLG505YC64 CK505 Standar parts follow s tandar s etting
IF M/B NEED LPC DEBUG PORT, \THEN STUFF THIS RESITER.
CPU Clock select

BSEL Frequency Select Table
R 180 0_4 CLK_BSEL0
3 C PU_BSEL0 MC H_BSEL0 6
FSC FSB FSA Frequency
+ 1 .05V_CPU R 425 *56_4
0 0 0 266Mhz
R 179 1K_4
A1A: (10/23) stuff

0 0 1 133Mhz
R 440 0_4 CLK_BSEL1 0 1 1 166Mhz

R 439 *0_4 0 1 0 200Mhz

A1A: (9/20) Remove 0ohm
A A
+ 1 .05V_CPU R 198 1K_4 1 1 0 400Mhz

A1A: (10/23) stuff
1 1 1 Reserved
R 448 0_4 CLK_BSEL2
1 0 1 100Mhz PROJECT : ZU1
R 449 *0_4
1 0 0 333Mhz Quanta Computer Inc.
R 447 1K_4 Size D oc um ent Num ber R ev
+ 1 .05V_CPU
CLK. GEN./ CK505 1A
A1A: (10/23) stuff
5 4 3 2 1

5 4 3 2 1
CPU Thermal monitor

U3 0 A
5 H_ A# [16:3]
H_ A #3 J4 H1
A[3]# ADS# H_ ADS# 5
CPU(HOST)
ADDR GROUP 0
H_ A #4 L5 E2
A[4]# BNR# H_ B NR# 5 + 3V
H_ A #5 L4 G5
A[5]# BPRI# H_ B PRI# 5
H_ A #6 K5
H_ A #7 A[6]#
M3 H5 H_ D EFER# 5
H_ A #8 A[7]# DEFER#
N2 F21 H_ D R D Y# 5
H_ A #9 A[8]# DRDY#
J1 E1 H_ D B SY# 5
H_ A#10 A[9]# DBSY#
N3
H_ A#11 A[10]#
P5 F1 H_BREQ#0 5
H_ A#12 P2 A[11]# BR0# A1A:(9/29) change from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
A[12]#
CONTROL
H_ A#13 L2 D20 H_ IE RR# R 109 56.2_4 + 1.05V_CPU
H_ A#14 A[13]# IERR# +3V R 388 R 387 R 385
P4 B3 H_ INIT# 14
H_ A#15 A[14]# INIT#
P1
H_ A#16 R1 A[15]# H4 Q31 10K_4 10K_4 200_6
A[16]# LOCK# H_LOCK# 5
2
D M1 R HU0 0 2N06 L M 86VCC D
5 H_ADSTB0# ADSTB[0]#
5 H_ REQ#[4:0] C1 H_ CPURST# 5
H _REQ#0 K3 RESET# F3 C 466
H_ RS#0 5 28 2 ND_MBCLK 3 1
H _REQ#1 REQ[0]# RS[0]#
H2 F4 H_ RS#1 5
H _REQ#2 REQ[1]# RS[1]# . 1 U_4
K2 G3 H_ RS#2 5
H _REQ#3 J3 REQ[2]# RS[2]# G2 +3V
REQ[3]# TRDY# H_ T R DY# 5
H _REQ#4 L1 U2 7
REQ[4]# Q30 H_ T H ERMDA
5 H_ A#[35:17] G6 H_ HIT# 5
HIT#
2
H_ A#17 Y2 E4 R HU0 0 2N06 8 1
A[17]# HITM# H_ HITM# 5 SCLK VCC
H_ A#18 U5
H_ A#19 A[18]# C 461
R3 AD4 28 2 ND _MBDATA 3 1 7 2
A[19]# BPM[0]# SDA DXP
ADDR GROUP 1
H_ A#20 W6 AD3
H_ A#21 U4 A[20]# BPM[1]# AD1 A1A: (9/4) +3V 6 3 2200P_4
XDP/ITP SIGNALS
H_ A#22 A[21]# BPM[2]# Remove XDP/ITP signals ALERT# DXN
Y5 AC4
H_ A#23 A[22]# BPM[3]# H_ T H ERMDC
U1 AC2 4 5
H_ A#24 R4 A[23]# PRDY# AC1 A1A: (9/26) Add (U3/Pin6) PU to 3V R 389 OVERT# GND
H_ A#25 A[24]# PREQ# XDP_TCK A1A: (10/30) remove, already PU in ICH8
T5 AC5
H_ A#26 A[25]# TCK XDP_TDI *10K_4 MAX6657
T3 AA6
A[26]# TDI
H_ A#27 W2
A[27]# TDO
AB3 16 THERM_ALERT# R 390 *0_4 T HERM_ALERT#_R ADDRESS: 98H
H_ A#28 W5 AB5 XDP_TMS
H_ A#29 A[28]# TMS XDP_TRST# + 3V R 381 10K_4 C P UF AN #_ON
Y4
A[29]# TRST#
AB6 <check list>
H_ A#30 U2 C20 XDP_DBRESET# R 112 0_4
H_ A#31 A[30]# DBR# S YS_RST# 16 Layout Note:Routing 10:10 mils and away
V4
H_ A#32 A[31]# from noise source with ground gard
W3
H_ A#33 A[32]# R 107 5 6.2_4
AA4
A[33]#
THERM AL + 1 .05V_CPU
H_ A#34 AB2
H_ A#35 A[34]#
AA3 D21 H_ PROCHOT_R# R 111 * 2.2K_4
H_PROCHOT# 35
A[35]# PROCHOT#
5 H_ADSTB1# V1 A24 H_ T H ERMDA
ADSTB[1]# THERMDA
CPU FAN
B25 H_ T H ERMDC
THERMDC + 3V
14 H_ A20M# A6
A20M# <check list>
ICH
A5 C7 T HERMTRIP#_PW R
14 H_ F ERR# FERR# THERMTRIP# Default PU 56ohm if no use.
14 H_ IGNNE# C4
C IGNNE# Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K A1A: (9/26) Add CPUFAN#_ON to (U4/PIN1) C
R 173 0 _4 H_STPCLK_R# D5 A1A: (10/23) Add Diode D36 and PU +5V for (U4/Pin1) R 70
14 H_STPCLK# STPCLK#
14 H_ INTR C6
LINT0
H CLK
14 H _ NMI B4 A22 10K_4
LINT1 BCLK[0] C L K_CPU_BCLK 2
14 H_ S MI# A3 A21 C L K_CPU_BCLK# 2
SMI# BCLK[1] + 5V
T P_CPU_RSVD01 M4
T55 RSVD[01]
T P_CPU_RSVD02 N5 28 F ANS IG
T50 RSVD[02]
T P_CPU_RSVD03 T2 R 383
T56 RSVD[03] C N23
T P_CPU_RSVD04 V3 U2 8
T53 RSVD[04]
T P_CPU_RSVD05 B2 10K_4 2 3 T H_ FAN_POW ER
T108 +5V
RESERVED
T P_CPU_RSVD06 C3 RSVD[05] VIN VO 1 4

T48 5
T P_CPU_RSVD07 D2 RSVD[06] C P UF AN #_ON D 39 C P UF AN #_ON_R GND 2
T52 1 6
T P_CPU_RSVD08 D22 RSVD[07] B AS316 /FON GND 7 C 99 C 96 C 106 3 5
T5 RSVD[08] GND
T P_CPU_RSVD09 D3 4 8 P T I_CW Y030-B0G1Z
T54 RSVD[09] 28 C P UF AN# VSET GND
T P_CPU_RSVD10 F6 1 0U_8 . 0 1U_4 * . 01U_4
T49 RSVD[10] G995
Me rom Ball-out Rev 1a

FANPWR = 1.6*VSET
5 H_ D #[15:0] H_ D#[47:32] 5
U3 0B A1A: (9/24) change FAN CONN (follow ZC3)
H_ D#0 E22 Y22 H_ D#32
H_ D#1 D[0]# D[32]# H_ D#33
F24 AB24
H_ D#2 E26 D[1]# D[33]# V24 H_ D#34
H_ D#3 D[2]# D[34]# H_ D#35
G22 V26
D[3]# D[35]#
DATA GRP 0
H_ D#4 F23 V23 H_ D#36

H_ D#5 D[4]# D[36]# H_ D#37
G25 T22
H_ D#6 D[5]# D[37]# H_ D#38
E25 U25
D[6]# D[38]#
PU/PD (ITP700) Thermal Trip
H_ D#7 E23 U23 H_ D#39
H_ D#8 D[7]# D[39]# H_ D#40
K24 Y25
DATA GRP 2
H_ D#9 G24 D[8]# D[40]# W22 H_ D#41 + 1 .05V_CPU

H_ D#10 D[9]# D[41]# H_ D#42
J24 Y23
B H_ D#11 D[10]# D[42]# H_ D#43 B
J23 W24
H_ D#12 D[11]# D[43]# H_ D#44 + 1 .05V_CPU
H22 W25
D[12]# D[44]#
3
H_ D#13 F26 AA23 H_ D#45
H_ D#14 D[13]# D[45]# H_ D#46
K22 AA24
H_ D#15 D[14]# D[46]# H_ D#47
H23 AB25
J26 D[15]# D[47]# Y26 2 Q18 R 183 D 19
5 H_ DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5 6 ,16,35 D E L AY_VR_PW RGOOD
5 H_DSTBP#0 H26 AA26 H_DSTBP#2 5
DSTBP[0]# DSTBP[2]# F D V301N *10K_4 *BAS316
5 H_ D INV#0 H25 U22 H_ D INV#2 5
DINV[0]# DINV[2]#
5 H_ D #[31:16] H_ D#[63:48] 5
1
H_ D#16 N22 AE24 H_ D#48 XDP_TMS R 157 3 9_4 + 1 .05V_CPU C271 * 1 U_6
H_ D#17 D[16]# D[48]# H_ D#49
K25 AD24
H_ D#18 D[17]# D[49]# H_ D#50
P26 AA21
H_ D#19 D[18]# D[50]# H_ D#51
R23 AB22
H_ D#20 D[19]# D[51]# H_ D#52 XDP_TDI R 150 1 50_4
L23 AB21
D[20]# D[52]#
DATA GRP 1
H_ D#21 M24 AC26 H_ D#53 R 174 A1A: (9/26)

H_ D#22 D[21]# D[53]# H_ D#54 change name from THERM_SYS_PWR to SYS_SHDN#
L22 AD20
H_ D#23 D[22]# D[54]# H_ D#55 5 6.2_4 Q19
M23 AE22
2
H_ D#24 D[23]# D[55]# H_ D#56 MMBT3904
P25 AF23
+ 1.05V_CPU H_ D#25 D[24]# D[56]# H_ D#57
P23 AC25
H_ D#26 D[25]# D[57]# H_ D#58 T HERMTRIP#_PW R
P22 AE21 1 3
DATA GRP 3
D[26]# D[58]# S YS _ S HDN# 34

<Check list & CRB> H_ D#27 T24 AD21 H_ D#59 <Check list & CRB>
H_ D#28 D[27]# D[59]# H_ D#60 XDP_TCK R 152 2 7_4
Layout note: Z=55 ohm R24 AC22 Layout note: L<0.5"
H_ D#29 D[28]# D[60]# H_ D#61
L25 AD23
H_GTLREF<0.5" H_ D#30 D[29]# D[61]# H_ D#62 COMP0/2 Z=27.4ohm
T25 AF22
H_ D#31 D[30]# D[62]# H_ D#63
N25
D[31]# D[63]#
AC23 COMP1/3 Z=54.9 R 175 *0_4
P M_THRMTRIP# 6 ,14
R 92 L26 AE25 XDP_TRST# R 151 6 80_4
5 H_ DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 5
1K_4 M26 AF24
5 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 5
5 H_ D INV#1 N24
DINV[1]# DINV[3]#
AC20 H_ D INV#3 5 <CRB & Design guide>
H_ GTLREF AD26 C OMP0 R 89 2 7.4_6
Layout Note:Connect from
GTLREF COMP[0]
R26 <CRB & Design guide>
R 94 * 1K_4CPU_TEST1 C23 MISC U26 C OMP1 R 91 5 4.9_4 SB and daisy chain to CPU A1A: (9/4) <checklist>
A R 93 * 1K_4CPU_TEST2 D25 TEST1 COMP[1] C OMP2 R 172 2 7.4_6
Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing A
TEST2 COMP[2]
AA1 CORE VR.Not use T Retain the termination resistors
CPU_TEST3 C24 Y1 C OMP3 R 169 5 4.9_4 on these signals even when ITP700Flex (ZS1 default NC)
T4 TEST3 COMP[3] connect.(SB/VR/CPU/NB) is not implemented.
C 132 * . 1 U_4
CPU_TEST4 AF26
CPU_TEST5 AF1 TEST4 E5
T57 TEST5 DPRSTP# IC H_DPRSTP# 6 ,14,35
CPU_TEST6 A26 B5
T6 TEST6 DPSLP# H_DPSLP# 14
R 90 D24
DPWR# H_ DPW R# 5
2K_6 B22 D6
2 CPU_BSEL0 BSEL[0] PWRGOOD H_ P W RGD 14
B23 D7
2
2
CPU_BSEL1
CPU_BSEL2 C21
BSEL[1]
BSEL[2]
SLP#
PSI#
AE6
H_ CPUSLP# 5
P SI# 35
PROJECT : ZU1
A1A: (9/22) Remove H_PWRGD_XDP
Quanta Computer Inc.
CPU(1 of 2)/FAN/Thermal 1A

5 4 3 2 1

5 4 3 2 1
CPU(Power)
VC C_CORE
U3 0 D
A4 P6
VSS[001] VSS[082]
A8 P21
VSS[002] VSS[083]
A11 P24
A14 VSS[003] VSS[084] R2
U3 0C VSS[004] VSS[085]
A16 R5
VSS[005] VSS[086]
A7
VCC[001] VCC[068]
AB20 <REV.NO. 0.5/REF.NO.19343> A19
VSS[006] VSS[087]
R22
C 517 C 222 C 481 C 483 C 499 C 479 C 513 C 515 C 221 C 498 A9 AB7 A23 R25
A10 VCC[002] VCC[069] AC7 AF2 VSS[007] VSS[088] T1
D 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 VCC[003] VCC[070] Ivcc Max 52A VSS[008] VSS[089] D
A12 AC9 B6 T4
VCC[004] VCC[071] VSS[009] VSS[090]
A13 AC12 B8 T23
A15 VCC[005] VCC[072] AC13 B11 VSS[010] VSS[091] T26
VCC[006] VCC[073] Ivccp Max 6A(VCCP supply before Vcc stable) VSS[011] VSS[092]
A17 AC15 B13 U3
A18
VCC[007] VCC[074]
AC17 Max 2A(VCCP supply after Vcc stable) B16
VSS[012] VSS[093]
U6
A20 VCC[008] VCC[075] AC18 B19 VSS[013] VSS[094] U21
VCC[009] VCC[076] VSS[014] VSS[095]
B7 AD7 Ivcca Max 130mA B21 U24
VCC[010] VCC[077] VSS[015] VSS[096]
B9 AD9 B24 V2
VCC[011] VCC[078] VSS[016] VSS[097]
B10 AD10 C5 V5
VCC[012] VCC[079] VSS[017] VSS[098]
B12 AD12 C8 V22
C 478 C 480 C 482 C 514 C 502 C 171 C 191 C 172 C 512 C 521 VCC[013] VCC[080] VSS[018] VSS[099]
B14 AD14 C11 V25
VCC[014] VCC[081] + 1.05V_CPU VSS[019] VSS[100]
B15 AD15 C14 W1
1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 B17 VCC[015] VCC[082] AD17 C16 VSS[020] VSS[101] W4
VCC[016] VCC[083] VSS[021] VSS[102]
B18 AD18 C19 W23
VCC[017] VCC[084] VSS[022] VSS[103]
B20 AE9 C2 W26
C9 VCC[018] VCC[085] AE10 C22 VSS[023] VSS[104] Y3
VCC[019] VCC[086] VSS[024] VSS[105]
C10 AE12 C25 Y6
VCC[020] VCC[087] C 250 C154 C 153 C 251 C 249 C 152 VSS[025] VSS[106]
C12 AE13 D1 Y21
VCC[021] VCC[088] VSS[026] VSS[107]
C13 AE15 D4 Y24
VCC[022] VCC[089] . 1 U_6 . 1 U_6 . 1 U_6 . 1 U_6 . 1 U_6 . 1 U_6 VSS[027] VSS[108]
C15 AE17 D8 AA2
VCC[023] VCC[090] VSS[028] VSS[109]
C17 AE18 D11 AA5
VCC[024] VCC[091] VSS[029] VSS[110]
DESIGN GUIDE C18 AE20 D13 AA8
C 230 C 223 C 500 C 503 C 231 C 501 D9 VCC[025] VCC[092] AF9 D16 VSS[030] VSS[111] AA11
CHANGE FROM 22UF *20 TO 10UF *32 VCC[026] VCC[093] VSS[031] VSS[112]
D10 AF10 D19 AA14
1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 VCC[027] VCC[094] VSS[032] VSS[113]
D12 AF12 D23 AA16
D14 VCC[028] VCC[095] AF14 D26 VSS[033] VSS[114] AA19
VCC[029] VCC[096] VSS[034] VSS[115]
D15 AF15 E3 AA22
VCC[030] VCC[097] VSS[035] VSS[116]
D17 AF17 E6 AA25
VCC[031] VCC[098] + 1.05V_CPU +1.05V VSS[036] VSS[117]
D18
VCC[032] VCC[099]
AF18 <CRB> E8
VSS[037] VSS[118]
AB1
E7 AF20 R for test only E11 AB4
VCC[033] VCC[100] VSS[038] VSS[119]
E9 E14 AB8
VCC[034] C P U_G21 R 108 0 _4 R 176 0_1210 VSS[039] VSS[120]
E10 G21 E16 AB11
C E12 VCC[035] VCCP[01] V6 C P U _V6 R 159 0 _4 E19 VSS[040] VSS[121] AB13 C
VCC[036] VCCP[02] VSS[041] VSS[122]
E13 J6 E21 AB16
C 516 C 193 C 504 C 192 C 173 C 484 VCC[037] VCCP[03] + C 280 VSS[042] VSS[123]
E15 K6 E24 AB19
1 0U_8 VCC[038] VCCP[04] VSS[043] VSS[124]
E17
VCC[039] VCCP[05]
M6 <Check list> F5
VSS[044] VSS[125]
AB23
1 0 U_8 1 0U_8 1 0 U_8 1 0U_8 1 0 U_8 C H61001ME96 E18 J21 3 30U_7343 F8 AB26
C AP CHIP 10UF 6.3V(+-20%,X5R,0805) VCC[040] VCCP[06] ESR=12m ohm VSS[045] VSS[126]
E20 K21 F11 AC3
VCC[041] VCCP[07] VSS[046] VSS[127]
F7 M21 F13 AC6
F9 VCC[042] VCCP[08] N21 F16 VSS[047] VSS[128] AC8
VCC[043] VCCP[09] VSS[048] VSS[129]
F10 N6 F19 AC11
VCC[044] VCCP[10] VSS[049] VSS[130]
F12 R21 F2 AC14
F14 VCC[045] VCCP[11] R6 F22 VSS[050] VSS[131] AC16
VCC[046] VCCP[12] VSS[051] VSS[132]
F15 T21 F25 AC19
+ C 198 + C 217 + C 197 VCC[047] VCCP[13] VSS[052] VSS[133]
F17 T6 G4 AC21
VCC[048] VCCP[14] +1.5V VSS[053] VSS[134]
F18
VCC[049] VCCP[15]
V21 <CRB> G1
VSS[054] VSS[135]
AC24
F20 W21 .01U near to B26 ball G23 AD2
3 30U_7343 * 330U_73433 30U_7343 VCC[050] VCCP[16] VSS[055] VSS[136]
AA7 G26 AD5
VCC[051] + V CCA_PROC R 386 0_6 VSS[056] VSS[137]
AA9 B26 H3 AD8
A1A:(10/13) stuff C69, unstuff C68 AA10 VCC[052] VCCA[01] C26 H6 VSS[057] VSS[138] AD11
(base on layout location) VCC[053] VCCA[02] VSS[058] VSS[139]
AA12 H21 AD13
VCC[054] VC C_CORE C472 C 471 VSS[059] VSS[140]
AA13 AD6 H_ VID0 35 H24 AD16
VCC[055] VID[0] VSS[060] VSS[141]
AA15 AF5 H_ VID1 35 J2 AD19
VCC[056] VID[1] . 0 1U_4 1 0 U_8 VSS[061] VSS[142]
<Check list> AA17
VCC[057] VID[2]
AE5 H_ VID2 35 J5
VSS[062] VSS[143]
AD22
AA18 AF4 J22 AD25
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20) AA20 VCC[058] VID[3] AE3
H_ VID3 35
R 156 J25 VSS[063] VSS[144] AE1
VCC[059] VID[4] H_ VID4 35 VSS[064] VSS[145]
Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32) AB9
VCC[060] VID[5]
AF3 H_ VID5 35 K1
VSS[065] VSS[146]
AE4
AC10 AE2 100_6 K4 AE8
VCC[061] VID[6] H_ VID6 35 VSS[066] VSS[147]
AB10 K23 AE11
VCC[062] VSS[067] VSS[148]
AB12 K26 AE14
VCC[063] VSS[068] VSS[149]
AB14 AF7 VC CSENSE 35 L3 AE16
VCC[064] VCCSENSE VSS[069] VSS[150]
AB15 L6 AE19
AB17 VCC[065] L21 VSS[070] VSS[151] AE23
VCC[066] VSS[071] VSS[152]
AB18 AE7 VSSSENSE 35 L24 AE26
B VCC[067] VSSSENSE VSS[072] VSS[153] B
M2 A2
Me rom Ball-out Rev 1a VSS[073] VSS[154]
M5 AF6
VSS[074] VSS[155]
. <Demo board> M22
VSS[075] VSS[156]
AF8
R 160 M25 AF11
Routing 27.4ohm with 50mils spacing VSS[076] VSS[157]
N1 AF13
100_6 PU/PD near to CPU 1" N4 VSS[077] VSS[158] AF16
VSS[078] VSS[159]
N23 AF19
VSS[079] VSS[160]
N26 AF21
P3 VSS[080] VSS[161] A25
VSS[081] VSS[162]
AF25
VSS[163]
.
A A
PROJECT : ZU1
CPU(2 of 2) 1A

5 4 3 2 1

5 4 3 2 1
NB(HOST)
H_A#[35:3] 3
U29A
3 H_D#[63:0]
J13 H_A#3
H_D#0 H_A#_3 H_A#4
E2 B11
+1.05V_GMCH H_D#1 H_D#_0 H_A#_4 H_A#5
G2 C11
H_D#2 H_D#_1 H_A#_5 H_A#6
G7 M11
H_D#3 H_D#_2 H_A#_6 H_A#7
M6 C15
H_D#4 H_D#_3 H_A#_7 H_A#8
H7 F16
H_D#5 H_D#_4 H_A#_8 H_A#9
H3 L13
R86 H_D#6 H_D#_5 H_A#_9 H_A#10
D G4 G17 D
H_D#7 H_D#_6 H_A#_10 H_A#11
F3 C14
221_4 H_D#8 H_D#_7 H_A#_11 H_A#12
N8 K16
H_D#9 H_D#_8 H_A#_12 H_A#13
H2 B13
H_ SW ING H_D#10 H_D#_9 H_A#_13 H_A#14
M10 L16
H_D#11 H_D#_10 H_A#_14 H_A#15
N12 J17
H_D#12 H_D#_11 H_A#_15 H_A#16
N9 B14
H_D#_12 H_A#_16
R85 C137 <check list> H_D#13 H5
H_D#_13 H_A#_17
K19 H_A#17
0.1U close to B3 H_D#14 P13 P15 H_A#18
100_4 .1U_4 H_D#15 H_D#_14 H_A#_18 H_A#19
K9 R17
H_D#16 H_D#_15 H_A#_19 H_A#20
M2 B16
H_D#17 H_D#_16 H_A#_20 H_A#21
W10 H20
H_D#18 H_D#_17 H_A#_21 H_A#22
Y8 L19
H_D#19 H_D#_18 H_A#_22 H_A#23
V4 D17
H_D#20 H_D#_19 H_A#_23 H_A#24
M3 M17
H_D#21 H_D#_20 H_A#_24 H_A#25
J1 N16
H_D#22 H_D#_21 H_A#_25 H_A#26
N5 J19
H_D#23 H_D#_22 H_A#_26 H_A#27
N3 B18
H_D#24 H_D#_23 H_A#_27 H_A#28
W6 E19
H_D#25 H_D#_24 H_A#_28 H_A#29
W9 B17
H_D#26 H_D#_25 H_A#_29 H_A#30
N2 B15
H _RCOMP H_D#27 H_D#_26 H_A#_30 H_A#31
Y7 E17
H_D#_27 H_A#_31
H_D#28 Y9
H_D#_28 H_A#_32
C18 H_A#32 H_A#[35:32] are not supported in
<check list> H_D#29 P4
H_D#_29 H_A#_33
A19 H_A#33 Calero Interposer
R95 10:20 mils(Width:Spacing) H_D#30 W3 B19 H_A#34
C
H_D#31 N1
H_D#_30 H_A#_34
N19 H_A#35 Crestline support 36 bit address C
24.9_4 H_D#32 H_D#_31 H_A#_35
AD12
H_D#33 H_D#_32
AE3 G12 H_ADS# 3
H_D#34 H_D#_33 H_ADS#
AD9 H17
HOST
H_D#_34 H_ADSTB#_0 H_ADSTB0# 3
H_D#35 AC9 G20
H_D#_35 H_ADSTB#_1 H_ADSTB1# 3
H_D#36 AC7 C8
H_D#_36 H_BNR# H_ BNR# 3
H_D#37 AC14 E8
H_D#_37 H_BPRI# H_BPRI# 3
H_D#38 AD11 F12
H_D#_38 H_BREQ# H_BREQ#0 3
H_D#39 AC11 D6
H_D#_39 H_DEFER# H_DEFER# 3
H_D#40 AB2 C10
+1.05V_GMCH H_D#_40 H_DBSY# H_ DBSY# 3
H_D#41 AD7 AM5
H_D#_41 HPLL_CLK CLK_MCH_BCLK 2
H_D#42 AB1 AM7
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 2
H_D#43 Y3 H8
H_D#_43 H_DPWR# H_DPW R# 3
H_D#44 AC6 K7
H_D#_44 H_DRDY# H_ D R D Y# 3
H_D#45 AE2 E4
H_D#_45 H_HIT# H_HIT# 3
R87 H_D#46 AC5 C6
H_D#_46 H_HITM# H_HITM# 3
H_D#47 AG3 G10
H_D#_47 H_LOCK# H_LOCK# 3
54.9_4 <check list> H_D#48 AJ9
H_D#_48 H_TRDY#
B7 H_ TRDY# 3
Impedance 55ohm H_D#49 AH8
H_SCOMP H_D#50 H_D#_49
AJ14
H_D#51 H_D#_50
AE9
H_D#52 H_D#_51
AE11 H_ DINV#[3:0] 3
H_D#53 H_D#_52 H _DINV#0
AH12 K5
H_D#54 H_D#_53 H_DINV#_0 H _DINV#1
AJ5 L2
H_D#55 H_D#_54 H_DINV#_1 H _DINV#2
B AH5 AD13 B
+1.05V_GMCH H_D#56 H_D#_55 H_DINV#_2 H _DINV#3
AJ6 AE13
H_D#57 H_D#_56 H_DINV#_3
AE7 H_DSTBN#[3:0] 3
H_D#58 H_D#_57 H_DSTBN#0
AJ7 M7
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AJ2 K3
H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2
AE5 AD2
R88 H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AJ3 AH11
H_D#_61 H_DSTBN#_3
<check list> H_D#62 AH2
H_D#_62 H_DSTBP#[3:0] 3
54.9_4 Impedance 55ohm H_D#63 AH13 L7 H_DSTBP#0
H_D#_63 H_DSTBP#_0 H_DSTBP#1
K2
H_SCOMP# H_DSTBP#_1 H_DSTBP#2
AC2
H_ SW ING H_DSTBP#_2 H_DSTBP#3
B3 AJ10
H _RCOMP H_SWING H_DSTBP#_3
C2 H_REQ#[4:0] 3
+1.05V_GMCH H_RCOMP H_REQ#0
M14
H_SCOMP H_REQ#_0 H_REQ#1
W1 E13
H_SCOMP# H_SCOMP H_REQ#_1 H_REQ#2
W2 A11
H_SCOMP# H_REQ#_2 H_REQ#3
H13
H_REQ#_3 H_REQ#4
3 H_CPURST# B6 B12
R392 H_CPURST# H_REQ#_4
3 H_CPUSLP# E5 H_RS#[2:0] 3
H_CPUSLP# H_RS#0
E12
1K_4 H_RS#_0 H_RS#1
D7
H_RS#_1 H_RS#2
D8
H_AVREF H_RS#_2
B9
H_ DVREF H_AVREF
A9
H_DVREF
A A
R391 C473 <check list> CRESTLINE_1p0
0.1U close to B9
2K_4 .1U_4
PROJECT : ZU1
A1A:(9/20) remove R74 (0 ohm) Size D o cument Number R ev
GMCH HOST(1 of 7) 1A
D ate: T hursday, November 02, 2006 Sheet 5 of 39

5 4 3 2 1

5 4 3 2 1
U29B
MC H_ RSVD1 P36 U2 9C +VCC_PEG

T39 RSVD1
MC H_ RSVD2 P37 AV29
T46 RSVD2 SM_CK_0 M_ CLK_DDR0 13
MC H_ RSVD3 R35 BB23 J40
T36 RSVD3 SM_CK_1 M_ CLK_DDR1 13 20 INT _LVDS_PW M L_BKLT_CTRL
MC H_ RSVD4 N35 BA25 H39 N43 EXP_A_COMPX R 164 24.9_4
T43 RSVD4 SM_CK_3 M_ CLK_DDR3 13 20 INT _LVDS_BLON L_BKLT_EN PEG_COMPI
MC H_ RSVD5 AR12 AV23 + 3V R 146 10K_4 E39 M43
T9 RSVD5 SM_CK_4 M_ CLK_DDR4 13 L_CTRL_CLK PEG_COMPO
MC H_ RSVD6 AR13 R 154 10K_4 E40
T12 RSVD6 L_CTRL_DATA
MC H_ RSVD7 AM12 AW30 C37
T8 RSVD7 SM_CK#_0 M_ CLK_DDR#0 13 20 INT _ LVDS_EDIDCLK L_DDC_CLK
MC H_ RSVD8 AN13 BA23 D35 J51
T11 RSVD8 SM_CK#_1 M_ CLK_DDR#1 13 20 INT _ L VDS_EDIDDATA L_DDC_DATA PEG_RX#_0
MC H_ RSVD9 J12 AW25 K40 L51 P EG_RXN1
T10 RSVD9 SM_CK#_3 M_ CLK_DDR#3 13 20 INT _ L VDS_DIGON L_VDD_EN PEG_RX#_1 P EG_RXN1 21
RSVD
MC H_ RSVD10 AR37 AW23 N47
T45 RSVD10 SM_CK#_4 M_ CLK_DDR#4 13 PEG_RX#_2
MC H_ RSVD11 AM36 R 148 2.4K_4 L VD S_IBGL41 T45
T42 RSVD11 LVDS_IBG PEG_RX#_3
MC H_ RSVD12 AL36 BE29 L43 T50
T38 RSVD12 SM_CKE_0 M_CKE0 12,13 T47 LVDS_VBG PEG_RX#_4
MC H_ RSVD13 AM37 AY32 N41 U40
D T40 RSVD13 SM_CKE_1 M_CKE1 12,13 LVDS_VREFH PEG_RX#_5 D
MC H_ RSVD14 D20 BD39 N40 Y44
T21 RSVD14 SM_CKE_3 M_CKE3 12,13 LVDS_VREFL PEG_RX#_6
BG37 M_CKE4 12,13 20 INT_TXLCLKOUT- D46 Y40
SM_CKE_4 C45 LVDSA_CLK# PEG_RX#_7 AB51
20 INT_TXLCLKOUT+ LVDSA_CLK PEG_RX#_8
C 157 . 1 U_4 BG20 D44 W49
SM_CS#_0 M_CS#0 1 2,13 LVDSB_CLK# PEG_RX#_9
BK16 M_CS#1 1 2,13 E42 AD44
SM_CS#_1 LVDSB_CLK PEG_RX#_10
LVDS
BG16 M_CS#2 1 2,13 AD40
MC H_ RSVD20 SM_CS#_2 PEG_RX#_11
T7 H10 BE13 M_CS#3 1 2,13 20 INT_TXLOUT0- G51 AG46
RSVD20 SM_CS#_3 LVDSA_DATA#_0 PEG_RX#_12
MUXING
MC H_ RSVD21 B51 E51 AH49
T103 RSVD21 20 INT_TXLOUT1- LVDSA_DATA#_1 PEG_RX#_13
MC H_ RSVD22 BJ20 BH18 F49 AG45
T84 RSVD22 SM_ODT_0 M_ODT0 12,13 20 INT_TXLOUT2- LVDSA_DATA#_2 PEG_RX#_14
MC H_ RSVD23 BK22 BJ15 AG41
T86 RSVD23 SM_ODT_1 M_ODT1 12,13 PEG_RX#_15
MC H_ RSVD24 BF19 BJ14
GRAPHICS
T13 RSVD24 SM_ODT_2 M_ODT2 12,13
MC H_ RSVD25 BH20 BE16 G50 J50
T25 RSVD25 SM_ODT_3 M_ODT3 12,13 20 INT_TXLOUT0+ LVDSA_DATA_0 PEG_RX_0
MC H_ RSVD26 BK18 E50 L50 PEG_RXP1
T83 RSVD26 20 INT_TXLOUT1+ LVDSA_DATA_1 PEG_RX_1 PEG_RXP1 21
MC H_ RSVD27 BJ18 BL15 M _RCOMP F48 M47
T82 RSVD27 SM_RCOMP 20 INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_2
MC H_ RSVD28 BF23 BK14 M _RCOMP# U44
T30 RSVD28 SM_RCOMP# S MD DR_VREF PEG_RX_3
MC H_ RSVD29 BG23 T49
T15 RSVD29 PEG_RX_4
MC H_ RSVD30 BC23 BK31 S M _RCOMP_VOH G44 T41
T33 RSVD30 SM_RCOMP_VOH LVDSB_DATA#_0 PEG_RX_5
MC H_ RSVD31 BD24 BL31 S M_RCOMP_VOL B47 W45
DDR
T17 RSVD31 SM_RCOMP_VOL LVDSB_DATA#_1 PEG_RX_6
1 2,13 M_ A_A14 BJ29 B45 W41
RSVD32 LVDSB_DATA#_2 PEG_RX_7
1 2,13 M_B_A14 BE24 AR49 S MD D R _VREF_MCH R 83 0_6 AB50
MC H_ RSVD34 RSVD33 SM_VREF_0 PEG_RX_8
T44 BH39 AW4 Y48
MC H_ RSVD35 RSVD34 SM_VREF_1 R 84 *10K_6 PEG_RX_9
T18 AW20 + 1 . 8VSUS_GMCH E44 AC45
MC H_ RSVD36 BK20 RSVD35 R 82 *10K_6 A47 LVDSB_DATA_0 PEG_RX_10 AC41
T85 RSVD36 LVDSB_DATA_1 PEG_RX_11
MC H_ RSVD37 C48 A45 AH47
T98 RSVD37 LVDSB_DATA_2 PEG_RX_12
MC H_ RSVD38 D47 B42 D R EFCLK AG49
PCI-EXPRESS
T51 RSVD38 DPLL_REF_CLK D R EFCLK 2 PEG_RX_13
MC H_ RSVD39 B44 C42 D R EFCLK# AH45
T95 RSVD39 DPLL_REF_CLK# D R EFCLK# 2 PEG_RX_14
MC H_ RSVD40 C44 H48 D REFSSCLK AG42
T96 RSVD40 DPLL_REF_SSCLK D R EFSSCLK 2 PEG_RX_15
MC H_ RSVD41 A35 H47 D REFSSCLK#
T90 RSVD41 DPLL_REF_SSCLK# D REFSSCLK# 2
MC H_ RSVD42 B37 IN T_TV_COMP E27 N45 C_PEG_TXN0
T91 RSVD42 20 INT_TV_COMP TVA_DAC PEG_TX#_0
MC H_ RSVD43 B36 K44 INT _ T V_Y/G G27 U39 C_PEG_TXN1
T89 C LK_PCIE_3GPLL 2 20 INT _ T V_Y/G
CLK
MC H_ RSVD44 RSVD43 PEG_CLK INT _TV_C/R TVB_DAC PEG_TX#_1 C_PEG_TXN2
T88 B34 K45 C LK_PCIE_3GPLL# 2 20 INT _TV_C/R K27 U47
RSVD44 PEG_CLK# TVC_DAC PEG_TX#_2
TV
MC H_ RSVD45 C34 N51 C_PEG_TXN3
C T87 RSVD45 PEG_TX#_3 C
D MI_TXN[3:0] 15 F27 R50
TVA_RTN PEG_TX#_4
J27 T42
D M I_TXN0 TVB_RTN PEG_TX#_5
AN47 L27 Y43
DMI_RXN_0 AJ38 D M I_TXN1 TVC_RTN PEG_TX#_6 W46
DMI_RXN_1 D M I_TXN2 R 417 2.2K_4 T V_DCONSEL_0 PEG_TX#_7
AN42 + 3V M35 W38
DMI_RXN_2 D M I_TXN3 R 415 2.2K_4 T V_DCONSEL_1 TV_DCONSEL_0 PEG_TX#_8
AN46 D MI_TXP[3:0] 15 P33 AD39
DMI_RXN_3 TV_DCONSEL_1 PEG_TX#_9
AC46
AM47 DMI_TXP0 R 153 * 0_4 PEG_TX#_10 AC49
DMI_RXP_0 DMI_TXP1 R 145 * 0_4 PEG_TX#_11
2 MC H_BSEL0 P27 AJ39 AC42
CFG_0 DMI_RXP_1 DMI_TXP2 PEG_TX#_12
2 MC H_BSEL1 N27 AN41 AH39
N24 CFG_1 DMI_RXP_2 AN45 DMI_TXP3 PEG_TX#_13 AE49
2 MC H_BSEL2 CFG_2 DMI_RXP_3 D MI_ RXN[3:0] 15 PEG_TX#_14
MC H_ CFG_3 C21 AH44
T24 CFG_3 PEG_TX#_15
MC H_ CFG_4 C23 AJ46 D MI _RXN0
T26 CFG_4 DMI_TXN_0
11 MC H_ CFG_5 F23 AJ41 D MI _RXN1 19 INT _CRT_BLU
INT _CRT_BLU H32 M45 C_PEG_TXP0
MC H_ CFG_6 CFG_5 DMI_TXN_1 CRT_BLUE PEG_TX_0
T19 N23 AM40 D MI _RXN2 G32 T38 C_PEG_TXP1
MC H_ CFG_7 CFG_6 DMI_TXN_2 CRT_BLUE# PEG_TX_1
T27 G23 AM44 D MI _RXN3 D MI_RXP[3:0] 15 19 INT _ CRT_GRN
INT _ CRT_GRN K29 T46 C_PEG_TXP2
MC H_ CFG_8 CFG_7 DMI_TXN_3 CRT_GREEN PEG_TX_2
J20 J29 N50 C_PEG_TXP3
DMI
T22 CFG_8 CRT_GREEN# PEG_TX_3

CFG
11 MC H_ CFG_9 C20 AJ47 D M I_RXP0 IN T_CRT_RED F29 R51

CFG_9 DMI_TXP_0 19 INT_CRT_RED CRT_RED PEG_TX_4
VGA
MC H_ CFG_10 R24 AJ42 D M I_RXP1 E29 U43
T32 CFG_10 DMI_TXP_1 CRT_RED# PEG_TX_5
MC H_ CFG_11 L23 AM39 D M I_RXP2 W42
T23 CFG_11 DMI_TXP_2 PEG_TX_6
11 MC H_ CFG_12 J23 AM43 D M I_RXP3 Y47
CFG_12 DMI_TXP_3 PEG_TX_7
11 MC H_ CFG_13 E23 19 INT_CRT_DDCCLK K33 Y39
MC H_ CFG_14 CFG_13 CRT_DDC_CLK PEG_TX_8
T20 E20 19 INT_CRT_DDCDAT G35 AC38
MC H_ CFG_15 K23 CFG_14 R 416 30_4 H S YNC 1 F33 CRT_DDC_DATA PEG_TX_9 AD47
T28 CFG_15 19 INT _ HS YNC CRT_HSYNC PEG_TX_10
11 MC H_ CFG_16 M20 R411 1.3K_6 C R T IREF C32 AC50
MC H_ CFG_17 CFG_16 R 418 30_4 VS YNC 1 E33 CRT_TVO_IREF PEG_TX_11
GRAPHICS VID
T29 M24 19 INT _ VS YNC AD43

MC H_ CFG_18 CFG_17 CRT_VSYNC PEG_TX_12
T34 L32 AG39
CFG_18 PEG_TX_13
11 MC H_ CFG_19 N33 AE50
CFG_19 PEG_TX_14
11 MC H_ CFG_20 L35 AH43
CFG_20 PEG_TX_15
E35 T37 C RESTLINE_1p0

B R 158 0_4 P M_ B MBUSY#_R GFX_VID_0 T93 B
16 P M_ B MBUSY# G41 A39
R 424 0_4 IC H _DPRSTP#_R PM_BM_BUSY# GFX_VID_1 T92
3 ,14,35 IC H_DPRSTP# L39 C38
PM_DPRSTP# GFX_VID_2 T94
13 PM_EXTTS#0 L36 B39
PM_EXT_TS#_0 GFX_VID_3
PM
13 PM_EXTTS#1 R 147 0_4 PM_EXTTS#1_R J36 E36 T41

PM_EXT_TS#_1 GFX_VR_EN
3,16,35 D E L AY_VR_PW RGOOD AW49
R 115 100_4R S T _ IN#_MCH AV20 PWROK
15 PLTRST#_NB RSTIN# +1.25V_AXD
3 ,14 P M_THRMTRIP# R 116 *0_4
P M_ T HRMTRIP#_GMCH N20
R 149 0_4P M_ D PRSLPVR_GMCH G36 THERMTRIP# C_PEG_TXP0 C 270 . 1 U_4
16,35 P M_DPRSLPVR DPRSLPVR SDVOB_R+ 21
C_PEG_TXN0 C 272 . 1 U_4 SDVOB_R- 21
AM49 R155 C_PEG_TXP1 C 278 . 1 U_4 SDVOB_G+ 21
CL_CLK C L_CLK0 16
AK50 C_PEG_TXN1 C 277 . 1 U_4 SDVOB_G- 21
CL_DATA C L _DATA0 16
T105 T P _ MCH_NC1 BJ51 AT43 1K_4 C_PEG_TXP2 C 276 . 1 U_4
NC_1 CL_PWROK MPW ROK 16 SDVOB_B+ 21
T P _ MCH_NC2 C_PEG_TXN2 C 275 . 1 U_4
ME
T106 BK51 AN49 CL_RST#0 16 SDVOB_B- 21

T P _ MCH_NC3 NC_2 CL_RST#
T107 BK50 AM50 + 1 .25V_CL_VREF C_PEG_TXP3 C 273 . 1 U_4 SDVOB_CLK+ 21
T P _ MCH_NC4 NC_3 CL_VREF C_PEG_TXN3 C 274 . 1 U_4
T102 BL50 SDVOB_CLK- 21
T99 T P _ MCH_NC5 BL49 NC_4
T P _ MCH_NC6 NC_5 C 246 R161
T80 BL3
T78 T P _ MCH_NC7 NC_6
BL2
NC_7
NC
T76 T P _ MCH_NC8 BK1 . 1 U_4 392_6

T P _ MCH_NC9 NC_8
T75 BJ1 H35 SDVO_CTRLCLK 21
T P _ MCH_NC10 NC_9 SDVO_CTRL_CLK
MISC
T77 E1 K36 S DVO_CTRLDATA 21

T81 T P _ MCH_NC11 NC_10 SDVO_CTRL_DATA C L K_MCH_OE#
A5 G39 C L K_MCH_OE# 2
T104 T P _ MCH_NC12 NC_11 CLK_REQ#
C51 G40 MC H_ IC H_ S YNC# 16
T P _ MCH_NC13 NC_12 ICH_SYNC#
T100 B50
T P _ MCH_NC14 NC_13
T101 A50
T97 T P _ MCH_NC15 NC_14 GMCH_TEST1 R 143 0_4
A49 A37
T P _ MCH_NC16 NC_15 TEST_1 GMCH_TEST2 R 129 20K_4
T79 BK2 R32
NC_16 TEST_2
C RESTLINE_1p0
R 133 1K_4 S M _RCOMP_VOH

A
+ 1 . 8 VSUS_GMCH A
R 117 150_4 IN T_TV_COMP
R 114 C 207 C 177
M _RCOMP# + 1 . 8VSUS_GMCH +3V R 118 150_4 INT _ T V_Y/G
3 .01K_4 . 0 1U_4 2 . 2U_6
R 113 150_4 INT _TV_C/R
R 105 S M_RCOMP_VOL
R 106 R 423 10K_4 C L K_MCH_OE#
2 0_4 PROJECT : ZU1
20_4 R 421 10K_4 PM_EXTTS#0 R 119 150_4 INT _CRT_BLU
R 123 C 194 C 180
M _RCOMP R 419 10K_4 PM_EXTTS#1 R 122 150_4 INT _ CRT_GRN Quanta Computer Inc.
1 K_4 . 0 1U_4 2 . 2U_6 Size D oc um ent Num ber R ev
R 126 150_4 IN T_CRT_RED
GMCH DMI/VIDEO(2 of 7) 1A

5 4 3 2 1

5 4 3 2 1
NB(Memory controller)
13 M_A_DQ[63:0] 13 M_B_DQ[63:0]
U29D U29E
D M_A_DQ0 AR43 BB19 M_B_DQ0 AP49 AY17 D
SA_DQ_0 SA_BS_0 M_A_BS#0 12,13 SB_DQ_0 SB_BS_0 M_B_BS#0 12,13
M_A_DQ1 AW44 BK19 M_B_DQ1 AR51 BG18
M_A_DQ2 BA45 BF29 M_B_DQ2 AW50 BG36
M_A_DQ3 AY46 M_B_DQ3 AW51
SA_DQ_3 M_A_CAS# 12,13 SB_DQ_3 M_B_CAS# 12,13
M_A_DQ4 AR41 BL17 M_B_DQ4 AN51 BE17
M_A_DQ5 SA_DQ_4 SA_CAS# M_B_DQ5 SB_DQ_4 SB_CAS#
AR45 M_A_DM[7:0] 13 AN50 M_B_DM[7:0] 13
M_A_DQ6 SA_DQ_5 M_A_DM0 M_B_DQ6 SB_DQ_5 M_B_DM0
AT42 AT45 AV50 AR50
M_A_DQ7 SA_DQ_6 SA_DM_0 M_A_DM1 M_B_DQ7 SB_DQ_6 SB_DM_0 M_B_DM1
AW47 BD44 AV49 BD49
BB45 BD42 BA50 BK45
BF48 AW38 BB50 BL39
BG47 AW13 BA49 BH12
BJ45 BG8 BE50 BJ7
BB47 AY5 BA51 BF3
BG50 AN6 AY49 AW2
M_A_DQ14 SA_DQ_13 SA_DM_7 M_B_DQ14 SB_DQ_13 SB_DM_7
BH49 M_A_DQS[7:0] 13 BF50 M_B_DQS[7:0] 13
M_A_DQ15 SA_DQ_14 M_A_DQS0 M_B_DQ15 SB_DQ_14 M_B_DQS0
BE45 AT46 BF49 AT50
A
M_A_DQ16 SA_DQ_15 SA_DQS_0 M_A_DQS1 M_B_DQ16 SB_DQ_15 SB_DQS_0 M_B_DQS1
AW43 BE48 BJ50 BD50
B
BE44 BB43 BJ44 BK46
BG42 BC37 BJ43 BK39
BE40 BB16 BL43 BJ12
MEMORY
BF44 BH6 BK47 BL7
MEMORY
BH45 BB2 BK49 BE2
BG40 AP3 M_A_DQS#[7:0] 13 BK43 AV2 M_B_DQS#[7:0] 13
M_A_DQ23 SA_DQ_22 SA_DQS_7 M_A_DQS#0 M_B_DQ23 SB_DQ_22 SB_DQS_7 M_B_DQS#0
BF40 AT47 BK42 AU50
M_A_DQ24 SA_DQ_23 SA_DQS#_0 M_A_DQS#1 M_B_DQ24 SB_DQ_23 SB_DQS#_0 M_B_DQS#1
AR40 BD47 BJ41 BC50
C
M_A_DQ25 SA_DQ_24 SA_DQS#_1 M_A_DQS#2 M_B_DQ25 SB_DQ_24 SB_DQS#_1 M_B_DQS#2 C
AW40 BC41 BL41 BL45
AT39 BA37 BJ37 BK38
AW36 BA16 BJ36 BK12
AW41 BH7 BK41 BK7
AY41 BC1 BJ40 BF2
AV38 AP2 BL35 AV3
M_A_DQ31 SA_DQ_30 SA_DQS#_7 M_B_DQ31 SB_DQ_30 SB_DQS#_7
AT38 M_A_A[13:0] 12,13 BK37 M_B_A[13:0] 12,13
M_A_DQ32 SA_DQ_31 M_A_A0 M_B_DQ32 SB_DQ_31 M_B_A0
AV13 BJ19 BK13 BC18
SA_DQ_32 SA_MA_0 SB_DQ_32 SB_MA_0
SYSTEM
M_A_DQ33 AT13 BD20 M_A_A1 M_B_DQ33 BE11 BG28 M_B_A1

SA_DQ_33 SA_MA_1 SB_DQ_33 SB_MA_1
SYSTEM
M_A_DQ34 AW11 BK27 M_A_A2 M_B_DQ34 BK11 BG25 M_B_A2
M_A_DQ35 SA_DQ_34 SA_MA_2 M_A_A3 M_B_DQ35 SB_DQ_34 SB_MA_2 M_B_A3
AV11 BH28 BC11 AW17
AU15 BL24 BC13 BF25
AT11 BK28 BE12 BE25
BA13 BJ27 BC12 BA29
BA11 BJ25 BG12 BC28
BE10 BL28 BJ10 AY28
BD10 BA28 BL9 BD37
BD8 BC19 BK5 BG17
AY9 BE28 BL5 BE37
BG10 BG30 BK9 BA39
AW9 BJ16 BK10 BG13
DDR
M_A_DQ46 SA_DQ_45 SA_MA_13 M_B_DQ46 SB_DQ_45 SB_MA_13

BD7 BJ8
DDR
M_A_DQ47 SA_DQ_46 M_B_DQ47 SB_DQ_46
BB9 BJ6 AV16 M_B_RAS# 12,13
M_A_DQ48 SA_DQ_47 M_B_DQ48 SB_DQ_47 SB_RAS# T P_SB_RCVEN#
BB5 BE18 M_A_RAS# 12,13 BF4 AY18 T14
M_A_DQ49 SA_DQ_48 SA_RAS# T P_SA_RCVEN# M_B_DQ49 SB_DQ_48 SB_RCVEN#
B AY7 AY20 T31 BH5 B
M_A_DQ50 SA_DQ_49 SA_RCVEN# M_B_DQ50 SB_DQ_49
AT5 BG1 BC17 M_B_WE# 12,13
M_A_DQ51 SA_DQ_50 M_B_DQ51 SB_DQ_50 SB_WE#
AT7 BA19 M_A_WE# 12,13 BC2
M_A_DQ52 SA_DQ_51 SA_WE# M_B_DQ52 SB_DQ_51
AY6 BK3
BB7 BE4
AR5 BD3
AR8 BJ2
AR9 BA3
AN3 BB3
AM8 AR1
AN10 AT3
AT9 AY2
AN9 AY3
AM9 AU2
AN11 AT2
SA_DQ_63 SB_DQ_63
CREST LINE_1p0 CREST LINE_1p0
A A
PROJECT : ZU1
Size Document Number R ev
MCH DDR(3 of 7) 1A
Date: T hursday, November 02, 2006 Sheet 7 of 39

5 4 3 2 1

5 4 3 2 1
+ 3 V _ V CCS Y NC + 1 . 0 5 V _ V CC_ GMCH

NB(Power-1) R 136 10_4 V C C G F P L L OW D 13 1 2 P D Z 5 .6 B
+ 1 . 0 5 V _ V CC_ GMCH
+ V GF X _ CORE _ INT ADD 10ohm
U 2 9G THEY ONLY USE IN UMA (GM OR GML)
+ 1 . 0 5 V _ V CC_ GMCH
AT35 U 2 9F
VCC_1
AT34 T17
VCC_2 VCC_AXG_NCTF_1
AH28 T18 +1 .0 5 V AB33
VCC_3 VCC_AXG_NCTF_2 VCC_NCTF_1
AC32 T19 AB36
VCC_5 VCC_AXG_NCTF_3 VCC_NCTF_2
AC31 T21 AB37
D VCC_4 VCC_AXG_NCTF_4 + C95 C 225 C 199 C 216 C 2 08 VCC_NCTF_3 D
AK32 T22 AC33 T27
VCC_6 VCC_AXG_NCTF_5 A1A(10/23): Short R116 VCC_NCTF_4 VSS_NCTF_1
AJ31 T23 AC35 T37
VCC_7 VCC_AXG_NCTF_6 3 3 0 U_ 7 3 43 2 2 U_ 8 . 2 2 U_ 4 . 2 2 U_ 4 . 1 U_ 4 VCC_NCTF_5 VSS_NCTF_2
AJ28 T25 AC36 U24
VCC_8 VCC_AXG_NCTF_7 VCC_NCTF_6 VSS_NCTF_3
AH32 U15 AD35 U28
VCC CORE
AH31 U16 AD36 V31
AH29 U17 AF33 V35
AF32 U19 AF36 AA19
U20 AH33 AB17
VCC_AXG_NCTF_12 VCC_NCTF_11 VSS_NCTF_8
VSS NCTF
U21 AH35 AB35
U23 AH36 AD19
R 127 0_4+ 1 . 0 5 V _ V CC_ GMCH_ V CC1 3 VCC_AXG_NCTF_14 A1A:(9/26) Change +VCC_CFXCORE_INT to +1.05V VCC_NCTF_13 VSS_NCTF_10
R30 U26 AH37 AD37
VCC_13 VCC_AXG_NCTF_15 +1 .0 5V VCC_NCTF_14 VSS_NCTF_11
V16 AJ33 AF17
VCC_AXG_NCTF_16 A1A(10/23): Short R115,R117 VCC_NCTF_15 VSS_NCTF_12
V17 AJ35 AF35
V19 AK33 AK17
V20 AK35 AM17
VCC_AXG_NCTF_19 + V GF X _ CORE _ INT VCC_NCTF_18 VSS_NCTF_15
V21 AK36 AM24
V23 AK37 AP26
V24 AD33 AP28
+ 1 . 8 V S US _ GMCH VCC_AXG_NCTF_22 VCC_NCTF_21 VSS_NCTF_18
Y15 AJ36 AR15
+ 1 .8 V S US
POWER VCC_AXG_NCTF_23 VCC_NCTF_22 VSS_NCTF_19
VCC NCTF
Y16 AM35 AR19
Y17 AL33 AR28
VCC_AXG_NCTF_25 + C 4 64 + C 463 C 156 C 150 C 164 C 1 82 C 151 C 155 VCC_NCTF_24 VSS_NCTF_21
AU32 Y19 AL35
VCC_SM_1 VCC_AXG_NCTF_26 VCC_NCTF_25
AU33 Y20 AA33
VCC_SM_2 VCC_AXG_NCTF_27 3 3 0 U_ 7 3 43 . 4 7 U_ 6 1 U_ 6 1 0 U_ 8 2 2 U_ 8 . 1 U_ 4 . 1 U_ 4 VCC_NCTF_26
AU35 Y21 AA35
VCC_SM_3 VCC_AXG_NCTF_28 3 3 0 U_ 7 3 43 VCC_NCTF_27
AV33 Y23 AA36
C 2 10 + C 144 C 215 C 2 32 VCC_SM_4 VCC_AXG_NCTF_29 VCC_NCTF_28
AW33 Y24 AP35
AW35 Y26 AP36
. 1 U_ 4 3 3 0 U_ 7 3 43 2 2 U_ 8 2 2 U_ 8 VCC_SM_6 VCC_AXG_NCTF_31 VCC_NCTF_30
AY35 Y28 AR35
BA32 Y29 AR36
C BA33 AA16 Y32 C
BA35 AA17 Y33
BB33
BC32
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
AB16
AB19
Y35
Y36
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
POWER
BC33 AC16 Y37 A3
VCC_SM_13 VCC_AXG_NCTF_38 VCC_NCTF_37 VSS_SCB1
BC35 AC17 T30 B2
VCC_SM_14 VCC SM VCC_AXG_NCTF_39 VCC_NCTF_38 VSS_SCB2
VSS SCB
BD32 AC19 T34 C1
BD35 AD15 T35 BL1
BE32 AD16 U29 BL51
BE33 AD17 U31 A51
BE35
BF33
VCC_SM_19 VCC GFX NCTF VCC_AXG_NCTF_44
AF16
AF19
U32
U33
VCC_NCTF_43
BF34 AH15 U35
BG32 AH16 U36
BG33 AH17 V32
BG35 AH19 V33
VCC_SM_24 VCC_AXG_NCTF_49 VCC_NCTF_48 +1 .0 5V
BH32 AJ16 V36
BH34 AJ17 V37
BH35 AJ19
VCC_SM_27 VCC_AXG_NCTF_52
BJ32 AK16 AT33
VCC_SM_28 VCC_AXG_NCTF_53 VCC_AXM_1
BJ33 AK19 AT31
VCC_SM_29 VCC_AXG_NCTF_54 +1 .0 5 V VCC_AXM_2
VCC AXM
BJ34 AL16 AK29
BK32 AL17 AK24
BK33 AL19 AK23
BK34 AL20 AL24 AJ26
VCC_SM_33 VCC_AXG_NCTF_58 VCC_AXM_NCTF_1 VCC_AXM_6
BK35 AL21 AL26 AJ23
VCC_SM_34 VCC_AXG_NCTF_59 VCC_AXM_NCTF_2 VCC_AXM_7
BL33 AL23 AL28
VCC_SM_35 VCC_AXG_NCTF_60 C 188 C 179 C 206 C 186 C 178 C 1 89 VCC_AXM_NCTF_3
AU30 AM15 AM26
VCC_SM_36 VCC_AXG_NCTF_61 VCC_AXM_NCTF_4
VCC AXM NCTF

AM16 AM28
+ V GF X _ CORE _ INT VCC_AXG_NCTF_62 2 2 U_ 8 . 2 2 U_ 4 . 2 2 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 VCC_AXM_NCTF_5
AM19 AM29
B VCC_AXG_NCTF_63 VCC_AXM_NCTF_6 B
AM20 AM31
VCC_AXG_NCTF_64 VCC_AXM_NCTF_7
AM21 AM32
VCC_AXG_NCTF_65 VCC_AXM_NCTF_8
R20 AM23 AM33
VCC_AXG_1 VCC_AXG_NCTF_66 VCC_AXM_NCTF_9
T14 AP15 AP29
W13 AP16 AP31
W14 AP17 AP32
Y12 AP19 AP33
AA20 AP20 AL29
AA23 AP21 AL31
AA26 AP23 AL32
AA28 AP24 AR31
AB21 AR20 AR32
AB24 AR21 AR33
AB29 AR23
VCC_AXG_12 VCC_AXG_NCTF_77
AC20 AR24
VCC GFX
AC21 AR26
AC23 V26
VCC_AXG_15 VCC_AXG_NCTF_80 C RE S T L INE _ 1 p 0
AC24 V28
AC26 V29
AC28 Y31
AC29
VCC_AXG_19
AD20
VCC_AXG_20
AD23
VCC_AXG_21 V C CS M_ L F 1
AD24 AW45
VCC_AXG_22 VCC_SM_LF1 V C CS M_ L F 2
AD28 BC39
VCC_AXG_23 VCC_SM_LF2
VCC SM LF
AF21 BE39 V C CS M_ L F 3
AF26 BD17
AA31 BD4
AH20 AW8
A AH21 AT6 A
VCC_AXG_28 VCC_SM_LF7
AH23
VCC_AXG_29 C 145 C 147 C 136 C 158 C 238 C 224 C 252
AH24
VCC_AXG_30
AH26
VCC_AXG_31 . 1 U_ 4 . 1 U_ 4 . 2 2 U_ 4 . 2 2 U_ 4 . 4 7 U_ 6 1 U_ 6 1 U_ 6
AD31
VCC_AXG_32
AJ20
AN14
VCC_AXG_33
VCC_AXG_34
PROJECT : ZU1
Size D o c u m e n t Nu mb e r Rev
C RE S T L INE _ 1 p 0
GMCH Power-1(4 of 7) 1A
D a te: T h u r s d a y, No ve mb e r 0 2 , 2 0 0 6 Sheet 8 of 39
5 4 3 2 1

5 4 3 2 1
NB(Power-2) + 3 V_ VCCSYNC
CRT/TV Disable/Enable guideline
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
+ 3V R 130 0 _6
If SDVO Dis able If SDVO enable If SDVO enable
IND C HIP 10UH(20%,100MA,LB2012T100MR) C 205 Ball Enable Dis able Ball Enable Dis able Signal LVDS Dis able LVDS Dis able LVDS enable
<FAE>
. 1 U_4 VC CA_CRT 3 .3V G ND VCCA_C_TVO 3 .3V G ND VC C D_LVDS G ND 1 .8V 1 .8V
L 53 1 0 UH_8
INT VGA disable
+1.25V
VCCSYNC connect to GND VC CD_CRT 1 .5V G ND VCCD_TVO 1 .5V 1 .5V VC C A_LVDS G ND G ND 1 .8V
+ C 527 C262 VCCDQ_CRT 1 .5V G ND VC C ABG_DAC 3 .3V G ND VCCTX_LVDS G ND G ND 1 .8V

+ 3V L 18 BKP1608HS181-T_6
4 70U_7343 . 1 U_4 VC CA_A_TVO3 .3V G ND VS SABG_DAC G ND G ND
C 226 C 522 C 220 R 412 EXTERNAL INTERNAL
D VCCA_B_TVO3 .3V G ND VC C _ S YNC 3 .3V G ND D
* 2 2U_8 . 1 U_4 2 2 N_4 * 0_4
+ 1 .05V_GMCH
U2 9 H
+1.05V
J32 U13
L 25 1 0 UH_8 R 128 0_6 VCCSYNC VTT_1
+1.25V + 3V_TV_DAC U12
+ 3 V _VCCA_CRT_DAC VTT_2 A1A(10/23): Short R122
A33 U11
C 505 C 508 R 132 VCCA_CRT_DAC_1 VTT_3 C 142 C 126 C 148 C 134 + C 462
B33 U9
+ C 528 C264 VCCA_CRT_DAC_2 VTT_4
U8
VTT_5
CRT
. 1 U_4 2 2 N_4 * 0_4 U7 4 . 7U_8 4 . 7U_8 2 . 2U_8 . 4 7U_6 3 30U_7343
4 70U_7343 . 1 U_4 + 3 V _VCCA_DAC_BG VTT_6
A30 U5
VCCA_DAC_BG VTT_7 U3
VTT_8 +1.25V_AXD
B32 U2
VSSA_DAC_BG VTT_9
U1
VTT_10 T13
VTT_11
VTT
+ 1 .25V_VCCA_DPLLA B49 T11 R 121 0_6 +1.25V
VCCA_DPLLA VTT_12
T10
+ 1.25V_VCCA_DPLLB VTT_13
H49 T9
EMI FILTER BKP1608HS181-T(180,1.5A) VCCA_DPLLB VTT_14 C 187 C 195
T7
VTT_15
PLL
+1.25V L 49 BKP1608HS181-T_6 + 1 . 25VM_VCCA_HPLL AL2 T6
VCCA_HPLL VTT_16 1 U_6 * 2 2U_8
T5
C 469 C 138 + 1 .25VM_VCCA_MPLL AM2 VTT_17 T3
VCCA_MPLL VTT_18
T2
2 2 U_8 . 1 U_4 VTT_19
R3
VTT_20
A LVDS
+1.8VSUS_VCC_TX_LVDS A41 R2 R 405 0_6
VCCA_LVDS VTT_21 +1.25V
R1
C 244 VTT_22
B41
L 50 BKP1608HS181-T_6 VSSA_LVDS C 477 C 475
1000P_4 AT23
VCC_AXD_1 1 U_6 1 0 U_8
AU28
C 133 VCC_AXD_2
K50 AU24
VCCA_PEG_BG VCC_AXD_3
AXD
C R 384 R 166 0_8 + 3 V_VCCA_PEG_BG AT29 C
+ 3V VCC_AXD_4
0 .5_6 . 1 U_4 K49 AT25
VSSA_PEG_BG VCC_AXD_5
A PEG
C 266 AT30
C465 V1 .25M_MPLL_RC
2 2 U_8 VCC_AXD_6 R 165 0 _6 +1.25V
. 1 U_4 + 1.25V_VCCD_PEG_PLL U51 AR29
VCCA_PEG_PLL VCC_AXD_NCTF C 265
R 120 0_6 + 1 .25VM_VCCA_SM AW18 B23 + 1 .25V_VCC_AXF . 1 U_4

+1.25V VCCA_SM_1 VCC_AXF_1
AV19 B21
VCCA_SM_2
POWER VCC_AXF_2
AXF
C 143 C 165 C 159 C176 C 168 AU19 A21
+ AU18 VCCA_SM_3 VCC_AXF_3 L19 1 UH_ 8
VCCA_SM_4 + 1 . 8VSUS_GMCH
1 00U_7343 * 2 2U_8 4 . 7U_6 2 2U_8 1 U_6 AU17 AJ50 + 1 . 2 5V_VCC_DMI
VCCA_SM_5 VCC_DMI C170 C 211
A SM
AT22 R134 1_6 + V1.8_SMCK_RC C 233 2 2 U_8
VCCA_SM_7
AT21 BK24 + 1 .8VSUS_VCC_SM_CK . 1 U_4 2 2 U_8
VCCA_SM_8 VCC_SM_CK_1
SM CK
AT19 BK23
VCCA_SM_9 VCC_SM_CK_2
AT18 BJ24
R 124 0_6 AT17 VCCA_SM_10 VCC_SM_CK_3 BJ23
+1.25V VCCA_SM_11 VCC_SM_CK_4
AR17
C 200 C 203 C213 C 201 VCCA_SM_NCTF_1
AR16
VCCA_SM_NCTF_2
+ 3V_TV_DAC + 1.8VSUS
L51 * 1 U_6 * 1 U_6 2 2U_8 . 1 U_4 A43 +1.8VSUS_VCC_TX_LVDS L 21 1 UH_8
VCC_TX_LVDS
A CK
BKP1608HS181-T_6 + 1 .25VM_VCCA_SM_CK BC29
BB29 VCCA_SM_CK_1
+3V VCCA_SM_CK_2
C40 + 3 V_VCC_HV C 239 + C 526
C 489 C 487 R 404 VCC_HV_1
C25 B40
VCCA_TVA_DAC_1 VCC_HV_2
HV
B25 1000P_4 2 20U_7343
. 1 U_4 2 2 N_4 *0_4 VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27 AD51
VCCA_TVB_DAC_2 VCC_PEG_1
TV
B28 W50
VCCA_TVC_DAC_1 VCC_PEG_2 + VCC_PEG
PEG
A28 W51
R 131 *0_4 VCCA_TVC_DAC_2 VCC_PEG_3
V49
B VCC_PEG_4 B
V50
VCC_PEG_5
D TV/CRT
R 138 0_6 + 1 .5V_VCCD_CRT M32
+ 1 . 5V_VCCD_TVDAC VCCD_CRT
L29
C 488 C 493 R 402 VCCD_TVDAC
AH50
VCC_RXR_DMI_1
DMI
+ 1 . 5V_VCCD_QDAC N28 AH51
. 1 U_4 2 2 N_4 *0_4 VCCD_QDAC VCC_RXR_DMI_2
C 485 + 1.25V R 81 0_6 + 1 . 2 5 VM_MCH_VCCD_HPLL AN2
VCCD_HPLL L54 9 1 nH
A7 +1.05V
VTTLF1
VTTLF
2 2U_8 C 128 + 1.25V_VCCD_PEG_PLL U48 F2
VCCD_PEG_PLL VTTLF2 A1A: (9/20) Remove R138 0 ohm
AH1
. 1 U_4 C 259 VTTLF3 C 284 + C 529
J41
VCCD_LVDS_1 LVDS C 129 C 470 C 146
H42
C 492 C 494 C 495 R 401 . 1 U_4 VCCD_LVDS_2 1 0 U_8 2 20U_7343
. 4 7 U_4 . 4 7U_4 . 4 7U_4
1 0 U_8 . 1 U_4 2 2 N_4 *0_4 +1.25V L 24 BKP1608HS181-T_6
C RESTLINE_1p0 <FAE>
VCC_RXR_DMI and VCC_PEG
R 168 C 268 connect to+1.05V
1_8 . 1 U_4
+V1.25S_PEGPLL_FB
C 263
A1A: (9/20) Remove +VCC_RXR_DMI
1 0 U_8
+ 1.5V R 137 0 _6
C 196 C 214
. 1 U_4 2 2 N_4 D8 2 1 +1.05V_SD

P D Z5.6B
A
+1.05V A
+ 3 V_VCC_HV
+ 1 .8VSUS R 163 0_6 + 1 .8V_VCCD_LVDS R 64
10_4
R 125 100_6 C 257 C 243
R 67 0 _4
1 U_6 * 10U_8
+3V
PROJECT : ZU1
C 519 C 511 C 507
A1A:(10/18) C 112
INTEL CRB VCCD_QDAC Filter Modification:
change L13 to R258(100ohm),
. 1 U_4 2 2 N_4 1 U_6 <CRB> Quanta Computer Inc.
. 1 U_4
change R145(*0 ohm) to C247(1uF) +1.25V AND +1.25M shall be Size D oc um ent Num ber R ev
+1.5V for Calero Interposer

5 4 3 2 1

5 4 3 2 1
NB(Power-3)
U29I
U29J
A13 AW24 C46 W11
VSS_1 VSS_100 VSS_199 VSS_287
A15 AW29 C50 W39
A17 AW32 C7 W43
A24 AW5 D13 W47
AA21 AW7 D24 W5
AA24 AY10 D3 W7
AA29 AY24 D32 Y13
AB20 AY37 D39 Y2
D VSS_8 VSS_107 VSS_206 VSS_294 D
AB23 AY42 D45 Y41
AB26 AY43 D49 Y45
AB28 AY45 E10 Y49
AB31 AY47 E16 Y5
AC10 AY50 E24 Y50
AC13 B10 E28 Y11
AC3 B20 E32 P29
VSS_15 VSS_114 VSS_213 VSS_301 VSS_GMCH_T29 R409 0_4
AC39 B24 E47 T29
AC43 B29 F19 T31
AC47 B30 F36 T33
VSS_18 VSS_117 VSS_216 VSS_304 VSS_GMCH_R28 R410 0_4
AD1 B35 F4 R28
AD21 B38 F40
VSS_20 VSS_119 VSS_218
AD26 B43 F50
AD29 B46 G1
AD3 B5 G13 AA32
AD41 B8 G16 AB32
AD45 BA1 G19 AD32
AD49 BA17 G24 AF28
AD5 BA18 G28 AF29
AD50 BA2 G29 AT27
AD8 BA24 G33 AV25
AE10 BB12 G42 H50
AE14 BB25 G45
AE6 BB40 G48
AF20 BB44 G8
AF23
AF24
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
BB49
BB8
H24
H28
VSS_231
VSS_232
VSS_233
AF31 BC16 H4
C AG2 BC24 H45 C
AG38 BC25 J11
AG43 BC36 J16
AG47 BC40 J2
AG50 BC51 J24
AH3 BD13 J28
AH40 BD2 J33
AH41
AH7
VSS_43
VSS_44
VSS_45
VSS_142
VSS_143
VSS_144
BD28
BD45
J35
J39
VSS_241
VSS_242
VSS_243
VSS
AH9 BD48
VSS_46 VSS_145
AJ11 BD5 K12
AJ13 BE1 K47
AJ21 BE19 K8
AJ24 BE23 L1
AJ29 BE30 L17
AJ32 BE42 L20
AJ43 BE51 L24
AJ45 BE8 L28
AJ49 BF12 L3
AK20 BF16 L33
AK21 BF36 L49
AK26 BG19 M28
AK28 BG2 M42
AK31 BG24 M46
AK51 BG29 M49
AL1 BG39 M5
AM11 BG48 M50
AM13 BG5 M9
B AM3 BG51 N11 B
AM4 BH17 N14
AM41 BH30 N17
AM45 BH44 N29
AN1 BH46 N32
AN38 BH8 N36
AN39 BJ11 N39
AN43 BJ13 N44
AN5 BJ38 N49
AN7 BJ4 N7
AP4 BJ42 P19
AP48 BJ46 P2
AP50 BK15 P23
AR11 BK17 P3
AR2 BK25 P50
AR39 BK29 R49
AR44 BK36 T39
AR47 BK40 T43
AR7 BK44 T47
AT10 BK6 U41
AT14 BK8 U45
AT41 BL11 U50
AT49 BL13 V2
AU1 BL19 V3
AU23 BL22
VSS_89 VSS_188
AU29 BL37
VSS_90 VSS_189 CRESTLINE_1p0
AU3 BL47
VSS_91 VSS_190
AU36 C12
VSS_92 VSS_191
AU49 C16
A VSS_93 VSS_192 A
AU51 C19
VSS_94 VSS_193
AV39 C28
VSS_95 VSS_194
AV48 C29
VSS_96 VSS_195
AW1 C33
VSS_97 VSS_196
AW12 C36
AW16
VSS_98
VSS_99
VSS_197
VSS_198
C41 PROJECT : ZU1
CRESTLINE_1p0 Quanta Computer Inc.
Size Document Number Rev
5 4 3 2 1

5 4 3 2 1
Strap table
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description Configuration
CFG[2:0] FSB Frequency Select 010 = FSB 800MHz

D 011 = FSB 667MHz D
CFG[4:3] Reserved
CFG5 DMI X2 Select 0 = DMI X2

1 = DMI X4(Default)
CFG6 Reserved
CFG7 CPU Strap 0 = Reserved

1 = Mobile CPU(Default)
CFG8 Low power PCI Express 0 = Normal mode

1 = Low Power mode
CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes

1 = Normal operation(Default)
CFG[11:10] Reserved
C C
CFG[13:12] XOR/ALLZ 00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
CFG[15:14] Reserved
CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable

1 = Dynamic ODT Enable(Default)
CFG[18:17] Reserved
SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default)

1 = SDVO Card Present
CFG19 DMI Lane Reversal 0 = Normal operation(Default)

1 = Reverse Lanes
CFG20 SDVO/PCIe concurrent 0 = Only SDVO or PCIE x1 is operation(Default)

1 = SDVO and PCIE x1 are operating simultaneously via the PEG port
B B
DMI X2 Select DMI Lane Reversal XOR /ALLz /Clock Un-gating PCI Express Graphics SDVO Present
MC H_ CFG_5 Low = DMIX2 MC H_CFG_19 Low = Norm al operation(Default) MC H_CFG_12MC H_CFG_13 C onfiguration MC H_ CFG_9 Low = Revers e Lane Strap define at External
Hi g h = IDMIX4(Default) Hi gh = Reverse Lane High = Norm al operation(Default)
DVI control page
0 0 Cloc k gating dis able
+3V
6 MC H_ CFG_5 6 MC H_ CFG_9
0 1 XOR Mode Enable
1 0 ALL-z Mode Enable

R 394 R 396
R 420
*4.02K_4 1 1 Norm al operation(Default) *4.02K_4
*4.02K_4
6 MC H_ CFG_19
FSB Dynamic ODT SDVO/PCIE Concurrent operation

Low = Only SDVO or PCIE X1 is
MC H_CFG_16 Low = ODT Disable MC H_CFG_20 operational(Default)
High = ODT Enable(Default) High = SDVO andPCIE X1 are operating
sim ultaneous ly via the PEG port
6 MC H_ CFG_12
A 6 MC H_ CFG_13 A
6 MC H_ CFG_16 +3V
R 397 R 395
R 393
* 4.02K_4 *4.02K_4
*4.02K_4 R 422 PROJECT : ZU1
*4.02K_4
6 MC H_ CFG_20 GMCH Strap(7 of 7) 1A

5 4 3 2 1

1 2 3 4 5 6 7 8
DDR2 Dual channel A/B PU
A A
M _ A _ A [1 3 ..0 ]
M_ A _ A [1 3 ..0 ] 7 ,1 3
M _ B _ A [1 3 ..0 ]
M_ B _ A [1 3 ..0 ] 7 ,1 3
DDRII A CHANNEL DDRII B CHANNEL
S M D DR_ V T E RM S M D DR_ V T E RM
C 160 C 2 19 C 163 C 254 C 212 C 247 C 1 62 C 184 C 241 C 229 C 260 C 2 45 C 161 C 255 C 1 90 C 166 C 183 C 167 C 237 C 2 48 C 256 C 209 C 169 C 253 C 2 58 C 204
. 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
B B
M_ A _A3 R P 16 1 2 56X2 S M DDR_ V T E RM

M_ A _A1 3 4
M_ A _A7 R P 21 1 2 56X2 M_ A _A8 R P20 1 2 56X2 S M DDR_ V T E RM

M_ A _A5 3 4 M_ A _A6 3 4
M_ A _A2 R P 17 1 2 56X2 R P28 1 2 56X2

6 ,1 3 M_ CK E 3
M_ A _A4 3 4 7 ,1 3 M_ B _ B S#2 3 4
M_ A _ A11 R P 26 1 2 56X2 RP4 1 2 56X2

7 ,1 3 M_ A _ BS#0
6 ,1 3 M_ CK E 1 3 4 6 ,1 3 M_ ODT 1 3 4
M_ A _ A12 R P 24 1 2 56X2
M_ A _A9 3 4 6 ,1 3 M_ ODT 3 RP1 1 2 56X2
6 ,1 3 M_ CS # 2 3 4
R P 27 1 2 56X2
7 ,1 3 M_ A _ B S#2
3 4 M_ A _ A10 R P12 1 2 56X2
6 ,1 3 M_ CK E 0
7 ,1 3 M_ A _ CA S# 3 4
M_ A _A0 R P 11 1 2 56X2
3 4 RP7 1 2 56X2
7 ,1 3 M_ A _ BS#1 7 ,1 3 M_ A _ W E #
6 ,1 3 M_ CS # 1 3 4
C C
7 ,1 3 M_ A _ RA S # RP8 1 2 56X2
6 ,1 3 M_ CS # 0 3 4
M_ B _ A10 R P 10 1 2 56X2 S M DDR_ V T E RM

3 4 7 ,1 3 M_ B _ W E # RP5 1 2 56X2
7 ,1 3 M_ B _ BS#0
7 ,1 3 M_ B _ CA S # 3 4
M_ B _A3 R P 13 1 2 56X2
M_ B _A1 3 4 M_ B _A7 R P25 1 2 56X2
6 ,1 3 M_ CK E 4 3 4
M_ B _A0 RP 9 1 2 56X2
3 4 RP6 1 2 56X2
7 ,1 3 M_ B _ BS#1 6 ,1 3 M_ CS # 3
7 ,1 3 M_ B _ RA S # 3 4
M_ B _A6 R P 18 1 2 56X2
M_ B _ A11 3 4 6 ,1 3 M_ ODT 0 RP2 1 2 56X2
M_ A _ A13 3 4
M_ B _ A12 R P 19 1 2 56X2
M_ B _A5 3 4 6 ,1 3 M_ ODT 2 RP3 1 2 56X2
M_ B _ A13 3 4
M_ B _A2 R P 15 1 2 56X2
M_ B _A4 3 4
M_ B _A8 R P 22 1 2 56X2
D M_ B _A9 3 4 D
INTEL FAE (08/17)

ADD MA14 FOR DUAL LAYERS RAM PROJECT : ZU1
R 144 56_4 S M DDR_ V T E RM
6 ,1 3
6 ,1 3
M_ A _ A14
M_ B _ A14
R 135 56_4 Quanta Computer Inc.
DDR RES. ARRAY 1A
1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8
DDR2 Dual channelSA/B CONN

MD D R _VREF_DIMM
M_ A_DM[0..7] 7
S MD D R _ VREF_DIMM
M_ B_DM[0..7] 7
M_ A_DQ[0..63] 7 M_B_DQ[0..63] 7
+ 1.8VSUS
M_ A_DQS[0..7] 7 M_B_DQS[0..7] 7
+ 1.8VSUS + 1.8VSUS + 1.8VSUS + 1.8VSUS
M_ A_DQS#[0..7] 7 M_B_DQS#[0..7] 7
C N24
M_ A_A[0..13] 7 ,12 M_ B_A[0..13] 7 ,12
C N25 1 2
VREF VSS46 M_B_DQ4
1 2 3 4
VREF VSS46 M _A_DQ4 M_B_DQ0 VSS47 DQ4 M_B_DQ1
3 4 5 6
M _A_DQ6 VSS47 DQ4 M _A_DQ0 M_B_DQ5 DQ0 DQ5 + C 135 C 496 C 523 C 218 C 510 C 525
5 6 7 8
M _A_DQ5 DQ0 DQ5 DQ1 VSS15 M _B_DM0
7 8 9 10
9 DQ1 VSS15 10 M_ A_DM0 M_B_DQS#0 11 VSS37 DM0 12 3 30U_7343 2 . 2U_6 2 . 2U_6 2 . 2U_6 2 . 2U_6 2 . 2U_6
M _A_DQS#0 VSS37 DM0 M_B_DQS0 DQS#0 VSS5 M_B_DQ2
11 12 13 14
M _A_DQS0 DQS#0 VSS5 M _A_DQ7 DQS0 DQ6 M_B_DQ6
13 14 15 16
DQS0 DQ6 M _A_DQ1 M_B_DQ7 VSS48 DQ7
15 16 17 18
M _A_DQ2 17 VSS48 DQ7 18 M_B_DQ3 19 DQ2 VSS16 20 M_B_DQ12
A M _A_DQ3 DQ2 VSS16 M _A_DQ13 DQ3 DQ12 M_B_DQ13 A
19 20 21 22
DQ3 DQ12 M _A_DQ9 M_B_DQ9 VSS38 DQ13
21 22 23 24
M _A_DQ12 23 VSS38 DQ13 24 M_B_DQ8 25 DQ8 VSS17 26 M _B_DM1
M _A_DQ8 DQ8 VSS17 M_ A_DM1 DQ9 DM1
25 26 27 28
DQ9 DM1 M_B_DQS#1 VSS49 VSS53 + 1.8VSUS S MD D R _VREF_DIMM +3V
27 28 29 30 M_ CLK_DDR3 6
M _A_DQS#1 29 VSS49 VSS53 30 M_B_DQS1 31 DQS#1 CK0 32
DQS#1 CK0 M_ CLK_DDR0 6 DQS1 CK0# M_ CLK_DDR#3 6
M _A_DQS1 31 32 33 34
DQS1 CK0# M_CLK_DDR#0 6 VSS39 VSS41
33 34 M_B_DQ11 35 36 M_B_DQ14
M _A_DQ11 VSS39 VSS41 M _A_DQ14 M_B_DQ10 DQ10 DQ14 M_B_DQ15 C 174 C 202 C 520 C 497 C 307 C 308 C 113 C 118
35 36 37 38
M _A_DQ15 DQ10 DQ14 M _A_DQ10 DQ11 DQ15
37 38 39 40
DQ11 DQ15 VSS50 VSS54 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 2 . 2U_6 2 . 2U_6 . 1 U_4
39 40
VSS50 VSS54
41 42
41 42 M_B_DQ20 43 VSS18 VSS20 44 M_B_DQ16
PC4800 DDR2 SDRAM

M _A_DQ17 VSS18 VSS20 M _A_DQ21 M_B_DQ17 DQ16 DQ20 M_B_DQ21
43 44 45 46
45 46 47 48
47 DQ17 DQ21 48 M_B_DQS#2 49 VSS1 VSS6 50
PC4800 DDR2 SDRAM

VSS1 VSS6 DQS#2 NC3 PM_EXTTS#1 6
M _A_DQS#2 49 50 PM_EXTTS#0 6 M_B_DQS2 51 52 M _B_DM2 Close to DIMM0
M _A_DQS2 DQS#2 NC3 M_ A_DM2 DQS2 DM2
51 52 53 54
DQS2 DM2 VSS19 VSS21
SO-DIMM (200P)
53 54 M_B_DQ22 55 56 M_B_DQ18
55 56 57 58
57 58 59 60
SO-DIMM (200P)
DQ19 DQ23 M_B_DQ29 VSS22 VSS24 M_B_DQ24
59 60 61 62
M _A_DQ24 61 VSS22 VSS24 62 M _A_DQ29 M_B_DQ28 63 DQ24 DQ28 64 M_B_DQ25
M _A_DQ25 DQ24 DQ28 M _A_DQ28 DQ25 DQ29 + 1.8VSUS
63 64 65 66
DQ25 DQ29 M _B_DM3 VSS23 VSS25 M_B_DQS#3
65 66 67 68
M_ A_DM3 67 VSS23 VSS25 68 M _A_DQS#3 69 DM3 DQS#3 70 M_B_DQS3
DM3 DQS#3 M _A_DQS3 NC4 DQS3
69 70 71 72
NC4 DQS3 M_B_DQ26 VSS9 VSS10 M_B_DQ31
71 72 73 74
M _A_DQ26 VSS9 VSS10 M _A_DQ30 M_B_DQ27 DQ26 DQ30 M_B_DQ30 + C 127 C 490 C 234 C 509 C 491 C 518
73 74 75 76
M _A_DQ27 75 DQ26 DQ30 76 M _A_DQ31 77 DQ27 DQ31 78
DQ27 DQ31 VSS4 VSS8 3 30U_7343 2 . 2U_6 2 . 2U_6 2 . 2U_6 2 . 2U_6 2 . 2U_6
77 78 6 ,12 M_CKE3 79 80 M_CKE4 6 ,12
VSS4 VSS8 CKE0 CKE1
6 ,12 M_CKE0 79 80 M_CKE1 6,12 81 82
B 81 CKE0 CKE1 82 83 VDD7 VDD8 84 B
VDD7 VDD8 NC1 A15
83 84 7 ,12 M_B_BS#2 85 86 M_B_A14 6 ,12 INTEL FAE (08/17)
NC1 A15 A16_BA2 A14
7 ,12 M_A_BS#2 85 86 M_ A_A14 6 ,12 87 88
87 A16_BA2 A14 88 M _B_A12 89 VDD9 VDD11 90 M _B_A11 ADD MA14 FOR DUAL LAYERS RAM
M_ A_A12 VDD9 VDD11 M_ A_A11 M _B_A9 A12 A11 M _B_A7
89 90 91 92
M_ A_A9 A12 A11 M_ A_A7 M _B_A8 A9 A7 M _B_A6 + 1.8VSUS S MD D R _VREF_DIMM + 3V
91 92 INTEL FAE (08/17) 93 94
M_ A_A8 A9 A7 M_ A_A6 A8 A6
93 94 95 96
95 A8 A6 96 ADD MA14 FOR DUAL LAYERS RAM M _B_A5 97 VDD5 VDD4 98 M _B_A4
M_ A_A5 VDD5 VDD4 M_ A_A4 M _B_A3 A5 A4 M _B_A2
97 98 99 100
M_ A_A3 A5 A4 M_ A_A2 M _B_A1 A3 A2 M _B_A0 C 242 C 524 C 506 C 185 C 304 C 306 C 100 C110
99 100 101 102
M_ A_A1 101 A3 A2 102 M_ A_A0 103 A1 A0 104
A1 A0 M _B_A10 VDD10 VDD12 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 2 . 2U_6 2 . 2U_6 . 1 U_4
103 104 105 106 M_B_BS#1 7,12
M_ A_A10 VDD10 VDD12 A10/AP BA1
105 106 M_A_BS#1 7 ,12 7 ,12 M_B_BS#0 107 108 M_B_RAS# 7 ,12
107 A10/AP BA1 108 109 BA0 RAS# 110
7 ,12 M_A_BS#0 BA0 RAS# M_ A_RAS# 7 ,12 7 ,12 M_B_W E# WE# S0# M_CS#2 6 ,12
7 ,12 M_A_W E# 109 110 M_CS#0 6 ,12 111 112
WE# S0# VDD2 VDD1
111 112 7 ,12 M_B_CAS# 113 114 M_ODT2 6 ,12
VDD2 VDD1 CAS# ODT0 M _B_A13
7 ,12 M_ A_CAS# 113 114 M_ODT0 6 ,12 6 ,12 M_CS#3 115 116
CAS# ODT0 M_ A_A13 S1# A13
6 ,12 M_CS#1 115
S1# A13
116 117
VDD3 VDD6
118 Close to DIMM1
117 118 6 ,12 M_ODT3 119 120
VDD3 VDD6 ODT1 NC2
6 ,12 M_ODT1 119 120 121 122
ODT1 NC2 M_B_DQ37 VSS11 VSS12 M_B_DQ36
121 122 123 124
123 124 125 126
125 126 127 128
127 DQ33 DQ37 128 M_B_DQS#4 129 VSS26 VSS28 130 M _B_DM4
M _A_DQS#4 VSS26 VSS28 M_ A_DM4 M_B_DQS4 DQS#4 DM4
129 130 131 132
M _A_DQS4 DQS#4 DM4 DQS4 VSS42 M_B_DQ39
131 132 133 134
DQS4 VSS42 M _A_DQ35 M_B_DQ34 VSS2 DQ38 M_B_DQ33 +3V
133 134 135 136
M _A_DQ39 VSS2 DQ38 M _A_DQ38 M_B_DQ35 DQ34 DQ39
135 136 137 138
M _A_DQ34 DQ34 DQ39 DQ35 VSS55 M_B_DQ44
137 138 139 140
DQ35 VSS55 M _A_DQ44 M_B_DQ40 VSS27 DQ44 M_B_DQ45
139 140 141 142
M _A_DQ40 141 VSS27 DQ44 142 M _A_DQ45 M_B_DQ41 143 DQ40 DQ45 144
M _A_DQ41 DQ40 DQ45 DQ41 VSS43 M_B_DQS#5 Q13 R 53 R 54
143 144 145 146
C DQ41 VSS43 M _A_DQS#5 M _B_DM5 VSS29 DQS#5 M_B_DQS5 C
145 146 147 148
2
M_ A_DM5 VSS29 DQS#5 M _A_DQS5 DM5 DQS5 R HU0 0 2N06 10K_4 10K_4
147 148 149 150
DM5 DQS5 M_B_DQ46 VSS51 VSS56 M_B_DQ42
149 150 151 152
M _A_DQ42 VSS51 VSS56 M _A_DQ43 M_B_DQ43 DQ42 DQ46 M_B_DQ47 D D RDAT_SMB
151 152 153 154 2 ,16,18,27,33 PDAT_SMB 3 1
153 154 155 156
155 DQ43 DQ47 156 M_B_DQ53 157 VSS40 VSS44 158 M_B_DQ52
157 158 159 160
M _A_DQ49 DQ48 DQ52 M _A_DQ52 DQ49 DQ53 +3V
159 160 161 162
161 DQ49 DQ53 162 163 VSS52 VSS57 164
VSS52 VSS57 NCTEST CK1 M_ CLK_DDR4 6
163 164 165 166 Q12
NCTEST CK1 M_ CLK_DDR1 6 VSS30 CK1# M_ CLK_DDR#4 6
165 166 M_B_DQS#6 167 168
M_ CLK_DDR#1 6
2
M _A_DQS#6 VSS30 CK1# M_B_DQS6 DQS#6 VSS45 M _B_DM6 R HU0 0 2N06
167 168 169 170
M _A_DQS6 DQS#6 VSS45 M_ A_DM6 DQS6 DM6
169 170 171 172
DQS6 DM6 M_B_DQ51 VSS31 VSS32 M_B_DQ55 D D RCLK_SMB
171 172 173 174 2 ,16,18,27,33 PCLK_SMB 3 1
173 174 175 176
M _A_DQ51 175 DQ50 DQ54 176 M _A_DQ55 177 DQ51 DQ55 178
DQ51 DQ55 M_B_DQ56 VSS33 VSS35 M_B_DQ60
177 178 179 180
179 180 181 182
181 182 183 184
DQ57 DQ61 M _B_DM7 VSS3 VSS7 M_B_DQS#7
183 184 185 186
M_ A_DM7 VSS3 VSS7 M _A_DQS#7 DM7 DQS#7 M_B_DQS7
185 186 187 188
DM7 DQS#7 M _A_DQS7 M_B_DQ59 VSS34 DQS7
187 188 189 190
M _A_DQ62 VSS34 DQS7 M_B_DQ62 DQ58 VSS36 M_B_DQ63
189 190 191 192
M _A_DQ59 DQ58 VSS36 M _A_DQ58 DQ59 DQ62 M_B_DQ58 S MD D R _VREF_DIMM
191 192 193 194
DQ59 DQ62 M _A_DQ63 D D RDAT_SMB VSS14 DQ63
193 194 195 196
D D RDAT_SMB VSS14 DQ63 D D RCLK_SMB SDA VSS13 R 69 10K_4
195 196 197 198
D D RCLK_SMB SDA VSS13 R 74 10K_4 +3V SCL SA0 R 65 10K_4
197 198 199 200
+3V SCL SA0 R 71 10K_4 VDD(SPD) SA1
+ 3V 199 200
VDD(SPD) SA1 F O X_AS0A426-NARN-7F R 192 * 0_6
+3V S MD DR_VREF
F O X_AS0A426-N2RN-7F
SO-DIMM0 SPD Address is 0xA0 SO-DIMM1 SPD Address is 0xA4
R 191 10K_4 R 193 10K_4
D SO-DIMM0 TS Address is 0x30 SO-DIMM1 TS Address is 0x34 + 1.8VSUS D
H: 5.2mm H: 9.2mm A1A:(10/30) no stuff R166, stuff R167,R168
CLOCK 0,1 CLOCK 3,4

CKE 0,1 CKE 2,3 PROJECT : ZU1
DDR SO-DIMM(200P) 1A

1 2 3 4 5 6 7 8

5 4 3 2 1
RTC VC CRTC
D 23 C H5 00H-40 VC CRTC C 328 1 U_6

CHANGE FROM 18PF
+ 3VPCU TO 10PF
<check list>
C 548 10P_4
VC CRTC_4 D 22 C H5 00H-40 R 210 20K_6
Delay 18~25ms
1
R 205 R 246 G1 C 363 Y4 R 231
1K_4 1 U_6 3 2 . 768KHZ 10M_6
2
D 1 M_6 * SHORT_PAD U3 2 A D
CLK_32KX1 AG25 E5
RTCX1 FWH0/LAD0 L AD0 27,28,30
C 547 10P_4 CLK_32KX2 AF24 F5
RTCX2 FWH1/LAD1 L AD1 27,28,30 + 1 .05V_V_CPU_IO
C N1 2 G8
FWH2/LAD2 L AD2 27,28,30
1 RTCRST# AF23 F6
1 RTCRST# FWH3/LAD3 L AD3 27,28,30
2
2 S M_ I NTRUDER# AD22 + 1 . 05V_V_CPU_IO
C4 L F RAME# 27,28,30
ACS_85204-0200L INTRUDER# FWH4/LFRAME#
A1A: (9/24) change RTC CONN (follow ZC3)
RTC
LPC
IC H_ INT V RMEN AF25 G9
INTVRMEN LDRQ0# LDRQ#0 30
CMOS Setting G1 L AN100_SLP AD21 E6 L DRQ#1 R 209 R 222
LAN100_SLP LDRQ1#/GPIO23 T66
Clear CMOS Short B24 AF13 G ATEA20 * 56.2_4 *56.2_4 R 237
GLAN_CLK A20GATE GATEA20 28
Keep CMOS Open A20M#
AG26 H_ A20M# 3
D22 5 6.2_4
LAN_RSTSYNC H _DPRSTP#_R R 221 0 _4
AF26 IC H_DPRSTP# 3 ,6,35
DPRSTP# H _DPSLP#_R R 224 0 _4
A1A: 9/1 Remove GLAN C21
LAN_RXD0 DPSLP#
AE26 H_DPSLP# 3
B21
LAN_RXD1
C22 AD24 H_ F ERR# 3
LAN_RXD2 FERR#
LAN / GLAN
VC CRTC_3
D21 AG29 H_ P W RGD_R R 220 0 _4
LAN_TXD0 CPUPWRGD/GPIO49 H_ P W RGD 3
E20
LAN_TXD1
C20 AF27 H_ IGNNE# 3
LAN_TXD2 IGNNE#
+ 5 VPCU AH21 AE24
GLAN_DOCK#/GPIO13 INIT# H_ INIT# 3
AC20 H_ INTR 3
INTR
CPU
R 232 * 24.9_4 GL AN_COMP_SB D25 AH14 R C IN#
+ 1.5V_PCIE GLAN_COMPI RCIN# R C IN# 28 + 1 .05V_V_CPU_IO
R 201 1.2K_6
VC CRTC_1 R 200 1K_4 VC CRTC_2 3 1 C25
GLAN_COMPO
AD23 H _ NMI 3
+3V +3V AC Z _BCLK NMI H_ S M I#_R R 219 0 _4
AJ16 AG28 H_ S MI# 3
R 202 Q22 AC Z_ S YNC AJ15 HDA_BIT_CLK SMI#
2
HDA_SYNC R 212
AA24 H_STPCLK# 3
4.7K_4 MMBT3904 AC Z_RST# STPCLK#
AE14
C HDA_RST# AE27 H_ T HERMTRIP_R 56.2_4 C
R 467 R 289 THRMTRIP#
31 AC Z_ S D IN0 AJ17
HDA_SDIN0 IC H_TP8 R214 2 4_6 R 211 *0_4
31 AC Z_ S D IN1 AH17 AA23 T59 P M_THRMTRIP# 3 ,6
*10K_4 *10K_4 AC Z_ S D IN2 AH15 HDA_SDIN1 TP8
HDA_SDIN2 P DD[15:0] 26
IHDA
R 206 T111 AC Z_ S D IN3 AD13 V1 P DD0
T63 HDA_SDIN3 DD0 P DD1
DD1
U2 Placement close SB L<2"
15K_4 AC Z _SDOUT AE13 V3 P DD2
R S T _RBAY# HDA_SDOUT DD2 T1 P DD3
R S T _RBAY# DD3 P DD4
AE10 V4
R B AYO N# R B AYO N# HDA_DOCK_EN#/GPIO33 DD4 P DD5
AG14 T5
HDA_DOCK_RST#/GPIO34 DD5 AB2 P DD6
SATA_LED# DD6 P DD7
29 SATA_LED# AF10 T6
SATALED# DD7 P DD8 +3V + 3V
T3
C 407 3900P_4 S ATA_RXN0_C AF6 DD8 R2 P DD9
26 S ATA_RXN0 SATA0RXN DD9
C 408 3900P_4 SATA_RXP0_C AF5 T4 P DD10
26 SATA_RXP0 SATA0RXP DD10
C 406 3900P_4 SATA_TXN0_C AH5 V6 P DD11
26 SATA_TXN0 SATA0TXN DD11
C 405 3900P_4 SATA_TXP0_C AH6 V5 P DD12 0810 UR FAE: R 273 R262
26 SATA_TXP0 SATA0TXP DD12 U1 P DD13
AG3
DD13
V2 P DD14 RCIN# DOESN'T NEED PU 10K_4 8.2K_4
SATA1RXN DD14 P DD15
AG4 U6
SATA1RXP DD15
IDE
AJ4 R C IN#
SATA1TXN P D A[2:0] 26
AJ3 AA4 P DA0 G ATEA20
SATA1TXP DA0 P DA1
A1A: (9/20) Remove SATA1/SATA2 AA1
DA1
SATA
AF2 AB3 P DA2 A1A: (9/20) RCIN# PU 10K
SATA2RXN DA2
AF1
SATA2RXP
AE4 Y6 PDCS1# 26
SATA2TXN DCS1#
AE3 Y5
SATA Disable SATA2TXP DCS3# PDCS3# 26
2 C LK_PCIE_SATA# AB7 W4 P DIOR# 26

SATA_CLKN DIOR#
1.Connect to GND: SATA[2:0]RXp/n , SATARBIAS , SATARBIAS# , SATA_CLKP , SATACLKN 2 C LK_PCIE_SATA AC6
SATA_CLKP DIOW#
W3 P DIOW # 26
2.NC: SATA[2:0]TXp/n , SATALED# Y2 P D DACK# 26
DDACK#
AG1 Y3 IR Q14 26
B 3.VccSATAPLL should be connected directly to Vcc1_5,Filter cap are not required R 495 2 4.9_4 S A TA_BIAS SATARBIAS# IDEIRQ B
AG2 Y1 P IO R DY 26
SATARBIAS IORDY
4.BIOS disable DDREQ
W5 P DDREQ 26
<check list>
IC H8 M REV 1.0
L<500mils
SB Strap HDA A1A: 9/6 base on Intel design guide, add it.
XOR Chain Entrance Strap
ICH8-M Internal VR Enable strap ICH8-M LAN100_SLP Strap AC Z _SDOUT R 282 3 3_4
AC Z_ S D OUT_AUDIO 31
(Internal VR for Vccsus1_05,VccSus1_5 and VccCL1_5) (Internal VR for VccLAN1_05 and VccCL1.05) IC H_ RSV0 HD A_SDOUT Des c ription
R 283 3 3_4
AC Z_ SDOUT_MDC 31
INT VRMEN Low = Internal VR disable L AN100_SLP Low = Internal VR dis able 0 0 R S VD
High = Internal VR enable(Default) High = Internal VR enable(Default)
0 1 Enter XOR Chain AC Z_ S YNC R 464 3 3_4

AC Z_ S YNC _ AUDIO 31
1 0 Norm al opration(Default) R 465 3 3_4

AC Z_ S YNC _MDC 31
1 1 S e t PCIE port c onfig bit 1

AC Z _BCLK R 462 3 3_4
B IT _ CLK_AUDIO 31
R 463 3 3_4
VC CRTC +3V B IT_CLK_MDC 31
VC CRTC
A1A: (9/20) Change INTVRMEN from PU to PD A1A: 9/1 Disable the internal VR powering AC Z_RST# R 268 3 3_4
A AC Z_ R ST#_AUDIO 3 1,32 A
VccLAN1_05, and VccCL1_05
R 227 R 272 R 267 3 3_4
AC Z_RST#_MDC 31
*332K_6 R 226 *1K_6
*332K_6
IC H_ INT V RMEN AC Z _SDOUT
L AN100_SLP
IC H_TP3 16
PROJECT : ZU1
R 228
0 _4 R 241
0_4 R 457 Quanta Computer Inc.
*1K_4
ICH8M HOST(1 of 4) 1A

5 4 3 2 1

5 4 3 2 1
SB-PCIE/USB/DMI
U32D A16 SWAP Override strap
33 PCIE_RXN1 P27 V27 DMI_RXN0 6
PERN1 DMI0RXN
33 PCIE_RXP1 P26 V26 DMI_RXP0 6
C343 .1U_4 PCIE_TXN1_C PERP1 DMI0RXP PCI_GNT#3 Low = A16 swap override enabled
33 PCIE_TXN1 N29 U29 DMI_TXN0 6
C342 .1U_4 PCIE_TXP1_C PETN1 DMI0TXN High = Default
N28 U28
Direct Media Interface

33 PCIE_TXP1 PETP1 DMI0TXP DMI_TXP0 6
to Docking
M27 Y27 DMI_RXN1 6
PERN2 DMI1RXN GNT3# R301 *1K_4
M26 Y26 DMI_RXP1 6
PERP2 DMI1RXP
L29 W29 DMI_TXN1 6
PETN2 DMI1TXN
L28 W28 DMI_TXP1 6
PETP2 DMI1TXP
D D
PCI-Express
18 PCIE_RXN3 K27 AB26 DMI_RXN2 6
PERN3 DMI2RXN
18 PCIE_RXP3 K26 AB25 DMI_RXP2 6
C335 .1U_4 PCIE_TXN3_C PERP3 DMI2RXP
to LAN 18 PCIE_TXN3 J29
PETN3 DMI2TXN
AA29 DMI_TXN2 6
C334 .1U_4 PCIE_TXP3_C J28 AA28
18 PCIE_TXP3 PETP3 DMI2TXP DMI_TXP2 6
27 PCIE_RXN4 H27 AD27 DMI_RXN3 6

PERN4 DMI3RXN +1.5V_PCIE
27 PCIE_RXP4 H26 AD26 DMI_RXP3 6
C337 .1U_4 PCIE_TXN4_C PERP4 DMI3RXP
27 PCIE_TXN4 G29 AC29 DMI_TXN3 6
C336 .1U_4 PCIE_TXP4_C PETN4 DMI3TXN
27 PCIE_TXP4 G28 AC28 DMI_TXP3 6
PETP4 DMI3TXP
to WLAN F27 T26 R244
PERN5 DMI_CLKN CLK_PCIE_ICH# 2
F26 T25 CLK_PCIE_ICH 2
PERP5 DMI_CLKP 24.9_4
E29
PETN5
E28 Y23
PETP5 DMI_ZCOMP DMI_IRCOMP_R
Y24
DMI_IRCOMP
D27
PERN6/GLAN_RXN
D26 G3 USBP0- 27
PERP6/GLAN_RXP USBP0N
C29
PETN6/GLAN_TXN USBP0P
G2 USBP0+ 27 <CRB>
C28 H5 USBP1- 27 DMI_IRCOMP_R<500mils
PETP6/GLAN_TXP USBP1N
H4 USBP1+ 27
USBP1P
C23 H2 USBP2- 27
SPI_CLK USBP2N
B23 H1 USBP2+ 27
SPI_CS0# USBP2P
E22 J3 USBP3- 33
SPI_CS1# USBP3N
SPI
A1A: 9/1 remove SPI interface J2 t o Docking
USBP3P USBP3+ 33
D23 K5 USBP4- 27
SPI_MOSI USBP4N t o Bluetooth
F21 K4 USBP4+ 27
SPI_MISO USBP4P USBP5-
K2 T114
USBOC#0 USBP5N USBP5+ A 1A:(10/2) Remove USB5
AJ19 K1 T113
USBOC#1 OC0# USBP5P
AG16 L3 USBP6- 29
USBOC#2 OC1#/GPIO40 USBP6N t o finger printer
C
USBOC#3
AG15
AE15
OC2#/GPIO41 USB USBP6P
L2
M5 USBP7-
USBP6+ 29
C
USBOC#4 OC3#/GPIO42 USBP7N USBP7+ T67 A 1A:(10/2) Remove USB7

AF15 M4 T69
USBOC#5 OC4#/GPIO43 USBP7P
AG17 M2 USBP8- 20
USBOC#6 OC5#/GPIO29 USBP8N t o CCD
AD12 M1 USBP8+ 20
USBOC#7 OC6#/GPIO30 USBP8P USBP9-
AJ18 N3 T70
USBOC#8 OC7#/GPIO31 USBP9N USBP9+
AD14 N2 T112
USBOC#9 OC8# USBP9P
AH18
OC9#
F2
USBRBIAS# USB_RBIAS_PN
F3
USBRBIAS
ICH8M REV 1.0
R328
<CRB>
22.6_6
USB_RBIAS_PN<500mils
SB-PCI +3V
RP40
6 5
U32B SERR# 7 4
22,23,25 AD[0..31]
AD0 D20 A4 REQ0# REQ0# 8 3
AD0 REQ0# REQ0# 22
AD1 GNT0# IN TH# INTC#
AD2
E19
D19
AD1 PCI GNT0#
D7
E18 REQ1#
GNT0# 22 9
10
2
1 INTB#
AD2 REQ1#/GPIO50 REQ1# 23 +3V
AD3 A20 C18 GNT1#
AD4 AD3 GNT1#/GPIO51 REQ2# GNT1# 23
D17 B19 8.2KX8
AD4 REQ2#/GPIO52 REQ2# 25
AD5 A21 F18 GNT2# +3V_S5
AD5 GNT2#/GPIO53 GNT2# 25
AD6 A19 A11 REQ3#
B
AD7 AD6 REQ3#/GPIO54 GNT3# RP42 B
C19 C10
AD8 AD7 GNT3#/GPIO55 USBOC#0
A18 6 5
AD9 AD8 USBOC#7 USBOC#2
B16 C17 CBE0# 22,23,25 7 4
AD10 AD9 C/BE0# USBOC#5 USBOC#3
A12 E15 CBE1# 22,23,25 8 3
AD11 AD10 C/BE1# USBOC#1 USBOC#4
E16 F16 CBE2# 22,23,25 9 2
AD12 AD11 C/BE2# USBOC#6
A14 E17 CBE3# 22,23,25 +3V_S5 10 1
AD13 AD12 C/BE3#
G16
AD14 AD13 IRD Y# 8.2KX8
A15 C8 IRD Y# 22,23,25
AD15 AD14 IRDY#
B6 D9 PAR 22,23,25
AD16 AD15 PAR USBOC#8 R264 8.2K_4
C11 G6 PCIRST# 22,23,27 +3V_S5
AD17 AD16 PCIRST# DEVSEL#
A9 D16 DEVSEL# 22,23,25
AD18 AD17 DEVSEL# PERR# USBOC#9 R251 8.2K_4
D11 A7 PERR# 22,23,25 +3V_S5
AD19 AD18 PERR# LOCK#
B12 B7
AD20 AD19 PLOCK# SERR# +3V
C12 F10 SERR# 22,23,25
AD21 AD20 SERR# STOP#
D10 C16 STOP# 22,23,25 RP38
AD22 AD21 STOP# TR DY#
C7 C9 TRDY# 22,23,25
AD23 AD22 TRDY# FRAME# REQ1#
F13 A17 FRAME# 22,23,25 6 5
AD24 AD23 FRAME# DEVSEL# REQ2#
E11 7 4
AD25 AD24 PLT_RST-R# R230 0_6 FRAME# TR DY#
E13 AG24 PLTRST#_NB 6 8 3
AD26 AD25 PLTRST# PCLK_ICH STOP# INTG#
E12 B10 PCLK_ICH 2 9 2
AD27 AD26 PCICLK
D8 G7 PCI_PME# 22,23,25 +3V 10 1
AD28 AD27 PME#
A6
AD29 AD28 8.2KX8 +3V
E8
AD30 AD29 +3V
D6 RP39
AD31 AD30
A3
AD31 LOCK# 6 5
IRD Y# INTE#
INTA# F9
Interrupt I/F F8 INTE# C546 PERR#
7
8
4
3 INTD#
22 INTA# PIRQA# PIRQE#/GPIO2 INTE# 25
INTB# B5 G11 INTF# INTF# 9 2 REQ3#
23 INTB# PIRQB# PIRQF#/GPIO3
A INTC# C5 F12 INTG# .1U_4 10 1 INTA# A
T68 PIRQC# PIRQG#/GPIO4 +3V
INTD# A10 B3 IN TH# R490 *0_4 U20
T64 CRT_SENSE# 19,28,33
5
PIRQD# PIRQH#/GPIO5 8.2KX8

ICH8M REV 1.0 PLT_RST-R# 2
4 PLTRST# 16,18,21,25,26,27,28,30,33
1
PROJECT : ZU1
TC7SH08FU R248
3
100K_6 Quanta Computer Inc.

ICH8 M PCIE(2 of 4)/ BIOS 1A
Date: Thursday, November 02, 2006 Sheet 15 of 39

5 4 3 2 1

5 4 3 2 1
SB-GPIO
U3 2C EM AIL LED OUT THAT IS ACTIVE LOW.
PCLK_SMB AJ26 AJ12
2 ,13,18,27,33 PCLK_SMB SMBCLK SATA0GP/GPIO21 E MAIL_LED# 29
PDAT_SMB AD19 AJ10 B O A RD_ID2
NEW ADD SMB OF CL 2 ,13,18,27,33 PDAT_SMB
CL_RST#1 SMBDATA SATA1GP/GPIO19 R B AYID 0
AG21 AF11
SATA
GPIO
NEW ADD CL_RST#1 FOR WLAN 27 CL_RST#1 LINKALERT# SATA2GP/GPIO36
SMB
<FAE> AC17 AG11 R B AYID 1
C R B S T P_PCI# PU is no stuff. A1A:(9/29) no support iAMT, remove SMB_CLK_ME,SMB_DATA_ME SMLINK0 SATA3GP/GPIO37
AE19
C RB STP_CPU# always keeps high to +3V SMLINK1 1 4 M_ ICH
AG9 1 4 M_ ICH 2
e n sure ME alive in M1 state. R I# CLK14 C LKUSB_48 C LKUSB_48 1 4 M_ ICH
AF17 G5
Clocks
( C L K _ MCH_BCLK/# m ust keep alive to RI# CLK48 C LKUSB_48 2
A1A: (9/11) Remove RI#
m ake ME work) F4 D3 IC H 8_SIO_32K SIO/ PC87383 DOES NOT NEED 32KHz
I think there will be update for this design, 30 LPC_PD# SUS_STAT#/LPCPD# SUSCLK T71
S YS_RST# AD15 R 335 R 481
I s u g g est you to keep PU and 0 3 S YS_RST# SYS_RESET#
AG23 SLP_S3# R 234 100_4
isolation resis tors for this signal. SLP_S3# S USB# 28
AG12 AF21 SLP_S4# R 243 100_4 * 10_4 *33_4
6 P M_ B MBUSY# BMBUSY#/GPIO0 SLP_S4# S USC# 28
R256 R 254 AD18 SLP_S5#
*10K_4 *10K_4 SMB_ALERT# AG22 SLP_S5# T60 <FAE>
D SMBALERT#/GPIO11 A1A: (9/26) Remove S4_STAT#, need be confirm? S i n c e your CPU VRM has no C 412 C 559 D
AH27
S4_STATE#/GPIO26
GPIO
R 459 0_4 P M_ STPPCI_ICH# AE20 DPRSTP# pin, c onnect
2 PM_STPPCI# STP_PCI#/GPIO15
SYS
R 460 0_4 P M_ STPCPU_ICH# AG18 AE23 IC H _PW ROK P M_DPRSLPVR to IMVP6 is c orrec t *10P_4 *10P_4
2 PM_STPCPU# STP_CPU#/GPIO25 PWROK
+3V C L K R UN# AH11 AJ14 P M _DPRSLPVR_R R 466 100_4 P M_DPRSLPVR
28,30 C L K R UN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 P M_DPRSLPVR 6 ,35
Power MGT
A1A: (9/26) change name from VR_PWRGD_CLKEN#
to VR_PWRGD_CK410# C338 . 1 U_4 P CIE_W AKE# AE17 AE21 PM_BATLOW #_R
1 8,27 P C IE_W AKE# WAKE# BATLOW#
U3 1 S E RIRQ AF12 If n o us e internal LAN MAC c onnec t LAN_RST# to PLTRST#
2 2,23,28,30 S ERIRQ SERIRQ
1 5 T HERM_ALERT# AC13 C2 D NB SW ON# Us e internal LAN MAC c onnec t LAN_RST# to RSMRST#
3 THERM_ALERT# THRM# PWRBTN# D NBSW ON# 28 s h ould go high no s ooner than 10 m s after both Vc c LAN3_3 and
2 A1A: 9/1 change to PLTRST#
35 VR _PW RGD_CK410# Vc c L AN1_5 have reac hed their nom inal voltages .
3 4 VR _ PW RGD_CLKEN AJ20 AH20 P M_ L AN_ENABLE_R R 247 0_4 PLTRST#
VRMPWRGD LAN_RST# PLTRST# 1 5,18,21,25,26,27,28,30,33
NC 7 S Z04 R 250 100K_4 T110 IC H_TP7 AJ22 AG27 RSMRST#_R
TP7 RSMRST# A1A:(9/16) need be confirm?
K BSMI# AJ8 E1 Remove SUSM#
28 K B SMI# TACH1/GPIO1 CK_PWRGD C K_PW RGD 2 used to control power planes to the Intel AMT sub-system
L I D591# AJ9 +3V_S5 +3V
2 0,28,29 L ID591# TACH2/GPIO6
D 24 BAS316 D O C K IN#_R AH9 E3
18 D O C KIN# TACH3/GPIO7 CLPWROK MPW ROK 6
S C I# AE16
28 S C I# GPIO8
A1A: (9/20)change neme to DOCKIN# G PIO12 AC19 AJ25
B O A RD_ID0 A1A: (9/11) Remove LAN_PHYPC GPIO12 SLP_M# FOR CONTROLLER LINK
AG8
B O A RD_ID1 TACH0/GPIO17 ADD CL1 BUS
AH12 F23 C L_CLK0 6
B O A RD_ID3 GPIO18 CL_CLK0 R 233 R 453
AE11 AE18 C L_CLK1 27
GPIO20 CL_CLK1
GPIO
Controller Link
IC H_ GPIO22 AG10 3.24K_6 3.24K_6
T109 IC H_ GPIO27 SCLOCK/GPIO22
AH25 F22 C L _DATA0 6
T61 IC H_ GPIO28 QRT_STATE0/GPIO27 CL_DATA0
AD16 AF19 C L _DATA1 27
+3V A1A: (9/26) Remove SATACLKREQ# G PIO35 AG13 QRT_STATE1/GPIO28 CL_DATA1
R S T_HDD# SATACLKREQ#/GPIO35 C L_VREF0_SB
26 R S T_HDD# AF9 D24
R 468 IC H_ GPIO39 SLOAD/GPIO38 CL_VREF0 C L_VREF1_SB
AJ11 AH23
IC H_ GPIO48 SDATAOUT0/GPIO39 CL_VREF1 C 357
AD10
*10K_4 SDATAOUT1/GPIO48 AJ23 C 355
CL_RST# CL_RST#0 6
<check list> AC Z _SPKR AD9 . 1 U_4
31 AC Z_SPKR SPKR
internal PD AJ27 IC H_ GPIO24 . 1 U_4 R 452
MEM_LED/GPIO24
MISC
C R469 0 _4 MC H_ IC H_ S Y NC#_R AJ13 AJ24 R 229 453_4 C
6 MC H_ IC H_ S YNC# MCH_SYNC# ME_EC_ALERT/GPIO10
AF22 A1A: (9/26) Remove (1)ME_EC_ALERT# 453_4
EC_ME_ALERT/GPIO14 (2)EC_ME_ALERT
14 IC H_TP3 AJ21 AG19
TP3 WOL_EN/GPIO9
IC H8 M REV 1.0 A1A: (9/11) Remove LAN_WOL_EN circuit
A1A:(10/12) change from +3V to +3VSUS

+ 3VSUS (Refer to ZC1)
C o n t r oller Link 1 VREF for IAMT s upport only
C 393 . 1 U_4
5
D E L A Y_VR_PW RGOOD 1 U2 1
3 ,6,35 D E L AY_VR_PW RGOOD
4 IC H _PW ROK
A1A:(9/29) no support iAMT, remove 2ND_MBCLK,2ND_MBDATA,Q11,Q12 PW ROK_EC 2
28 PW ROK_EC
3
R 298 100K_4 + 3V
T C 7 SH08FU
INTEL CRB NEED THOSE PU & PD. INTEL FAE (08/17)
A1A:(9/20) Refer to ZD1, Add ICH_PWROK circuit
+3V_S5 "Add RSMRST# isolation (important!!! See ww22 Santa Rosa MoW)"
+3VSUS
S YS_RST# R 263 10K_4
R 207
D NB SW ON# R 329 *10K_4 P M_ L AN_ENABLE_R R456 10K_4 Q23 4 .7K_4

No Reboot strap MMBT3906
Internal Pull up INTEL CRB SHOW IT
RSMRST#_R 3 1 R SMRST# 28
HD A_SPKR Low = Default IC H_ GPIO24 R 454 *10K_4
B Hi gh = No Reboot D O C K IN#_R R 319 8.2K_4 B
TO ICH8 FROM uR(EC)
2
A1A:(10/30) change DOCKIN#_R PU from +3V to +3V_S5 +3V R 215
+3V 10K_4
2
AC Z _SPKR R 288 * 10K_4 L I D591# R 473 10K_4 D 21
INTEL CRB: PU +3V K BSMI# R 480 10K_4 3 B AV99
BIOS/ ERIC: UNSTUFF S C I# R 261 10K_4
1
IC H_ GPIO39 R 470 10K_4
2
+3V D 20
INTEL CRB SHOW IT
IC H_ GPIO22 R 312 10K_4 3 B AV99
G PIO35 R 265 10K_4 IC H_ GPIO48 R 315 10K_4
R S T_HDD# R 314 10K_4
T HERM_ALERT# R 270 8 .2K_4 R B AYID 0 R 311 8.2K_4 P M_ L AN_ENABLE_R R204 * 0_4 R 196
1
R B AYID 1 R 300 8.2K_4 2.2K_4
S E RIRQ R 299 10K_4
DISABLE LAN: STUFF
C L K R UN# R 305 8 .2K_4 P M_DPRSLPVR R 269 100K_4
IC H _PW ROK R 238 10K_4

+3V_S5
ECN 2A R I# R 258 10K_4

+3V +3V + 3V +3V
INTEL CRB V1.301 CL_RST#1 R 242 *10K_4 Board ID ID3 ID2 ID1 ID0
CL_RST# NO NEED PU.
A
A1A:(9/29) no support iAMT, remove PU +3V_S5 circuit (R259/R258)
With EZ Dock 0 0 0 0 R474 R 472 R 310 R 324 A
*10K_4 *10K_4 *10K_4 *10K_4

PCLK_SMB R 455 2.2K_4 W/O EZ Dock 0 0 0 1
B O A RD_ID3 B O A RD_ID2 B O A RD_ID1 B O A RD_ID0
PDAT_SMB R 255 2.2K_4
RSV 0 0 1 0
SMB_ALERT# R 235 10K_4 PROJECT : ZU1
R475 R 471 R 304 R 320
P CIE_W AKE# R 260 1K_4 RSV 0 0 1 1
10K_4 10K_4 10K_4 10K_4 Quanta Computer Inc.
PM_BATLOW #_R R 245 8.2K_4
RSV 0 1 0 0 Size D oc um ent Num ber R ev
G PIO12 R 259 10K_4 ICH8M GPIO(3 of 4) 1A

5 4 3 2 1

5 4 3 2 1
+3V_S5 +3V
VC CRTC
C 332 C 352 C 330 +1.05V
2
D 25 D 40
1 U_4 . 1 U_4 . 1 U_4 U3 2 F
AD25 A13 +1.05V_SB R 505 0_1206
P D Z5.6B P D Z5.6B VCCRTC VCC1_05[01] U32E
B13
VCC1_05[02]
A16 C13 A23 K7
1
R 331 1 0_6 R 266 100_6 +5VREF_SB V5REF[1] VCC1_05[03] C 382 VSS[001] VSS[099]
+5V_S5 +5V T7 C14 A5 L1
V5REF[2] VCC1_05[04] C 373 A1A:(9/28) EMI suggest c278 from 0.1u to 10uF VSS[002] VSS[100]
D14 AA2 L13
C 401 C385 + 5VREF_SUS_SB G4 VCC1_05[05] E14 . 1 U_4 AA7 VSS[003] VSS[101] L15
V5REF_SUS VCC1_05[06] 1 0 U_8 VSS[004] VSS[102]
F14 A25 L26
. 1 U_4 . 1 U_4 VCC1_05[07] VSS[005] VSS[103]
AA25 G14 AB1 L27
VCC1_5_B[01] VCC1_05[08] +1.5V VSS[006] VSS[104]
AA26 L11 AB24 L4
AA27 VCC1_5_B[02] VCC1_05[09] L12 AC11 VSS[007] VSS[105] L5
D VCC1_5_B[03] VCC1_05[10] VSS[008] VSS[106] D
AB27 L14 AC14 M12
VCC1_5_B[04] VCC1_05[11] VC C D MIP LL_ICH R 239 1 _8 VSS[009] VSS[107]
AB28 L16 AC25 M13
+ 1.5V_PCIE AB29 VCC1_5_B[05] VCC1_05[12] L17 L 27 AC26 VSS[010] VSS[108] M14
VCC1_5_B[06] VCC1_05[13] 1 UH_1210 VSS[011] VSS[109]
D28 L18 AC27 M15
VCC1_5_B[07] VCC1_05[14] C 348 C 340 VSS[012] VSS[110]
D29 M11 AD17 M16
VCC1_5_B[08] VCC1_05[15] VSS[013] VSS[111]
CORE
+1.5V L56 E25 M18 IND C HIP 1UH +-20% 1440MA CBC3225T1R0MR AD20 M17
FBMJ2125HS420-T_8 VCC1_5_B[09] VCC1_05[16] . 0 1U_4 1 0 U_6 VSS[014] VSS[112]
E26 P11 AD28 M23
VCC1_5_B[10] VCC1_05[17] VSS[015] VSS[113]
E27 P18 AD29 M28
+ C543 C 360 C346 C 353 VCC1_5_B[11] VCC1_05[18] VSS[016] VSS[114]
Intel use 0.5UH inductor F24
VCC1_5_B[12] VCC1_05[19]
T11
+1.25V
AD3
VSS[017] VSS[115]
M29
F25 T18 AD4 M3
2 20U_7343 2 2 U_8 2 2U_8 2 . 2U_6 VCC1_5_B[13] VCC1_05[20] VSS[018] VSS[116]
G24 U11 AD6 N1
VCC1_5_B[14] VCC1_05[21] VSS[019] VSS[117]
H23 U18 AE1 N11
H24 VCC1_5_B[15] VCC1_05[22] V11 + 1 .25V_DMI R 451 0 _8 +1.05V AE12 VSS[020] VSS[118] N12
VCC1_5_B[16] VCC1_05[23] VSS[021] VSS[119]
J23 V12 AE2 N13
VCC1_5_B[17] VCC1_05[24] VSS[022] VSS[120]
J24 V14 AE22 N14
+ 1.5V K24 VCC1_5_B[18] VCC1_05[25] V16 C 544 R 216 0 _6 AD1 VSS[023] VSS[121] N15
VCC1_5_B[19] VCC1_05[26] VSS[024] VSS[122]
K25 V17 AE25 N16
A1A: (9/20) Change back R281 to 0 ohm VCC1_5_B[20] VCC1_05[27] 2 2 U_8 VSS[025] VSS[123]
L23 V18 AE5 N17
VCC1_5_B[21] VCC1_05[28] C 356 C 341 C 541 VSS[026] VSS[124]
L24 AE6 N18
VCC1_5_B[22] VSS[027] VSS[125]
VCCA3GP
R 450 0_8+1.5V_SATA R 489 0_8+ 1.5V_APLL_RR +1.5V_APLL L25 R29 AE9 N26
VCC1_5_B[23] VCCDMIPLL . 1 U_4 . 1 U_4 4 . 7U_6 VSS[028] VSS[126]
M24 AF14 N27
L60 C 390 C 396 VCC1_5_B[24] VSS[029] VSS[127]
M25 AE28 AF16 N4
1 0 UH_8 N23 VCC1_5_B[25] VCC_DMI[1] AE29 + 1 .05V_V_CPU_IO AF18 VSS[030] VSS[128] N5
C V01001MN08 1 0 U_6 1 U_6 VCC1_5_B[26] VCC_DMI[2] +3V VSS[031] VSS[129]
N24 AF3 N6
VCC1_5_B[27] VSS[032] VSS[130]
N25 AC23 AF4 P12
P24 VCC1_5_B[28] V_CPU_IO[1] AC24 AG5 VSS[033] VSS[131] P13
VCC1_5_B[29] V_CPU_IO[2] VSS[034] VSS[132]
P25 AG6 P14
VCC1_5_B[30] + V3 . 3 _DMI_ICH R 213 0_6 VSS[035] VSS[133]
R24 AF29 AH10 P15
VCC1_5_B[31] VCC3_3[01] VSS[036] VSS[134]
R25 AH13 P16
R26 VCC1_5_B[32] AD2 + V3 .3_SATA_ICH R 326 0_6 AH16 VSS[037] VSS[135] P17
VCC1_5_B[33] VCC3_3[02] VSS[038] VSS[136]
R27 AH19 P23
VCC1_5_B[34] + V3 . 3S_VCCPCORE_ICH VSS[039] VSS[137]
T23 AC8 AH2 P28
C T24 VCC1_5_B[35] VCC3_3[03] AD8 AF28 VSS[040] VSS[138] P29 C
VCCP_CORE
VCC1_5_B[36] VCC3_3[04] C 397 C 545 VSS[041] VSS[139]
T27 AE8 AH22 R11
VCC1_5_B[37] VCC3_3[05] VSS[042] VSS[140]
T28 AF8 AH24 R12
T29 VCC1_5_B[38] VCC3_3[06] . 1 U_4 . 1 U_4 AH26 VSS[043] VSS[141] R13
C 375 VCC1_5_B[39] + V3 . 3S_IDE_ICH VSS[044] VSS[142]
U24 AA3 AH3 R14
VCC1_5_B[40] VCC3_3[07] VSS[045] VSS[143]
U25 U7 AH4 R15
1 U_6 VCC1_5_B[41] VCC3_3[08] C 395 VSS[046] VSS[144]
V23 V7 AH8 R16
V24 VCC1_5_B[42] VCC3_3[09] W1 AJ5 VSS[047] VSS[145] R17
VCC1_5_B[43] VCC3_3[10] . 1 U_4 R 302 0_6 VSS[048] VSS[146]
V25 W6 B11 R18
IDE
VCC1_5_B[44] VCC3_3[11] VSS[049] VSS[147]
W25 W7 B14 R28
Y25 VCC1_5_B[45] VCC3_3[12] Y7 R 303 0_6 B17 VSS[050] VSS[148] R4
VCC1_5_B[46] VCC3_3[13] VSS[051] VSS[149]
B2 T12
+ V3 . 3S_PCI_ICH R 309 0_6 VSS[052] VSS[150]
AJ6 A8 B20 T13
VCCSATAPLL VCC3_3[14] B15 B22 VSS[053] VSS[151] T14
VCC3_3[15] VSS[054] VSS[152]
AE7 B18 B8 T15
C 384 VCC1_5_A[01] VCC3_3[16] VSS[055] VSS[153]
AF7 B4 C24 T16
VCC1_5_A[02] VCC3_3[17] VSS[056] VSS[154]
ARX
AG7 B9 C26 T17
1 U_6 AH7 VCC1_5_A[03] VCC3_3[18] C15 C 372 C 379 C 388 C27 VSS[057] VSS[155] T2
VCC1_5_A[04] VCC3_3[19] VSS[058] VSS[156]
AJ7 D13 C6 U12
PCI
VCC1_5_A[05] VCC3_3[20] . 1 U_4 . 1 U_4 . 1 U_4 VSS[059] VSS[157]
D5 D12 U13
VCC3_3[21] VSS[060] VSS[158]
AC1 E10 D15 U14
VCC1_5_A[06] VCC3_3[22] VSS[061] VSS[159]
AC2 E7 D18 U15
VCC1_5_A[07] VCC3_3[23] VSS[062] VSS[160]
ATX
AC3 F11 A1A:(10/30) change to +1.5V D2 U16

AC4 VCC1_5_A[08] VCC3_3[24] D4 VSS[063] VSS[161] U17
VCC1_5_A[09] + 3 V_ 1 . 5 V_HDA_IO_ICH R 287 0_6 VSS[064] VSS[162]
AC5 AC12 +3V E21 U23
VCC1_5_A[10] VCCHDA R 308 *0_6 VSS[065] VSS[163]
+1.5V E24 U26
+ VC C SUSHDA R 286 0_6 VSS[066] VSS[164]
AC10 AD11 +3V_S5 E4 U27
VCC1_5_A[11] VCCSUSHDA R 313 *0_6 C 377 VSS[067] VSS[165]
AC9 +1.5V_S5 E9 U3
VCC1_5_A[12] T P _ VCCSUS1_05_ICH_1 C 380 VSS[068] VSS[166]
J6 F15 U5
VCCSUS1_05[1] T P _ VCCSUS1_05_ICH_2 . 1 U_4 VSS[069] VSS[167]
AA5 AF20 E23 V13
AA6 VCC1_5_A[13] VCCSUS1_05[2] . 1 U_6 A1A:(10/25) Add +1.5V_S5 F28 VSS[070] VSS[168] V15
R 327 0 _6 + 1.5V_USB VCC1_5_A[14] T P _ V CCSUS1_5_ICH_1 VSS[071] VSS[169]
AC16 F29 V28
B VCCSUS1_5[1] VSS[072] VSS[170] B
G12 F7 V29
C 387 VCC1_5_A[15] T P _ V CCSUS1_5_ICH_2 +3V_S5 VSS[073] VSS[171]
G17 J7 G1 W2
VCC1_5_A[16] VCCSUS1_5[2] VSS[074] VSS[172]
H7 E2 W26
. 1 U_4 VCC1_5_A[17] + V3 . 3A_ICH R 316 0 _6 VSS[075] VSS[173]
C3 G10 W27
VCCSUS3_3[01] VSS[076] VSS[174]
AC7 G13 Y28
AD7 VCC1_5_A[18] AC18 G19 VSS[077] VSS[175] Y29
VCC1_5_A[19] VCCSUS3_3[02] C 345 C 369 VSS[078] VSS[176]
AC21 G23 Y4
VCCSUS3_3[03] VSS[079] VSS[177]
D1 AC22 G25 AB4
VCCPSUS
VCCUSBPLL VCCSUS3_3[04] AG20 . 1 U_4 2 2N_4 G26 VSS[080] VSS[178] AB23

VCCSUS3_3[05] VSS[081] VSS[179]
F1 AH28 G27 AB5
USB CORE
L6 H25 AB6
C 404 VCC1_5_A[21] VSS[083] VSS[181]
L7 P6 H28 AD5
M6 P7 H29 U4
. 1 U_4 VCC1_5_A[23] VCCSUS3_3[08] VSS[085] VSS[183]
M7 C1 H3 W24
VCC1_5_A[24] VCCSUS3_3[09] + V3 . 3 A_USB_ICH R 340 0 _8 VSS[086] VSS[184]
N7 H6
+1.5V_SATA W23 VCCSUS3_3[10] P1 J1 VSS[087] A1
VCC1_5_A[25] VCCSUS3_3[11] VSS[088] VSS_NCTF[01]
P2 J25 A2
T P _ VC CLAN1_05_ICH_1 VCCSUS3_3[12] C 415 VSS[089] VSS_NCTF[02]
F17 P3 J26 A28
VCCPUSB
T P _ VC CLAN1_05_ICH_2 VCCLAN1_05[1] VCCSUS3_3[13] VSS[090] VSS_NCTF[03]

G18 P4 J27 A29
VCCLAN1_05[2] VCCSUS3_3[14] 4 . 7U_6 T P _ VC CLAN1_05_ICH_1 C 365 . 1 U_6 VSS[091] VSS_NCTF[04]
P5 J4 AH1
R 461 0 _6 + 3 V _VCCLAN VCCSUS3_3[15] T P _ VC CLAN1_05_ICH_2 C 371 . 1 U_6 VSS[092] VSS_NCTF[05]
+ 3V F19 R1 J5 AH29
VCCLAN3_3[1] VCCSUS3_3[16] VSS[093] VSS_NCTF[06]
G20 R3 K23 AJ1
C 366 VCCLAN3_3[2] VCCSUS3_3[17] T P _ VCCSUS1_05_ICH_1 C 391 . 1 U_6 VSS[094] VSS_NCTF[07]
R5 K28 AJ2
+ 1 . 5V_VCCGLANPLL VCCSUS3_3[18] T P _ VCCSUS1_05_ICH_2 C 362 . 1 U_6 VSS[095] VSS_NCTF[08]
A24 R6 K29 AJ28
. 1 U_4 VCCGLANPLL VCCSUS3_3[19] VSS[096] VSS_NCTF[09]
K3 AJ29
VSS[097] VSS_NCTF[10]
GLAN POWER
A26 G22 T P _ VCCCL1_05_ICH T P _ V CCSUS1_5_ICH_1 K6 B1

VCCGLAN1_5[1] VCCCL1_05 T62 VSS[098] VSS_NCTF[11]
A27 T P _ V CCSUS1_5_ICH_2 B29
VCCGLAN1_5[2] T65 VSS_NCTF[12]
B26 A22 VC C C L 1 _ 5_INT_ICH T P _ VCCCL1_05_ICH
VCCGLAN1_5[3] VCCCL1_5 T58
+1.5V R 458 1 _8 L57 1 UH_1210 B27 IC H8 M REV 1.0
VCCGLAN1_5[4] + V3 . 3M_ICH C 364 C 367
B28 F20
C 361 C 358 VCCGLAN1_5[5] VCCCL3_3[1]
G21
IND C HIP 1UH +-20% 1440MA CBC3225T1R0MR VCCCL3_3[2] 1 U_6 * . 1U_4
B25
A 1 0U_6 2 . 2U_6 VCCGLAN3_3 A
IC H8 M REV 1.0
+ 1.5V_PCIE
C 359
R 257 0 _6 +3V PROJECT : ZU1
4 . 7U_6
R 240 0_6 + 3 V_GLAN
+3V
ICH8M Power(4 of 4) 1A

5 4 3 2 1

5 4 3 2 1
A1A: (9/20) Change from +3V_S5 to +3V_LAN_S5

+3V_S5
Giga LAN BCN5787M
A1A:(9/27) Change +3V_LAN_S5 to +3V
10
18
27
38
50
56
4
1
6
9
C 59 C 46 to Docking
. 1U_4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
GND11
GND12
GND13
10U_8 TX0P 2 48 TX0P _PR
A1A:(9/28) EMI suggest c311 from 0.1u to 10uF A0 0B1 TX0N_PR TX0P _PR 33
47 TX0N_PR 33
TX0N 3 1B1
A1 TX1P _PR
43
2B1 TX1N_PR TX1P _PR 33
42 TX1N_PR 33
D 11 BAS316 3B1
LINK LE D# 1 2 LA N_MB _LINKLED# TX1P 7 37 TX2P _PR
A2 4B1 TX2N_PR TX2P _PR 33
D 10 BAS316 36
100# TX1N 5B1 TX2N_PR 33
D 1 2 8 D
V A UX_12 D9 BAS316 A3 TX3P _PR
32
1000# 1 6B1 TX3N_PR TX3P _PR 33
+3V_S5 2 31
PI3L500 7B1 TX3N_PR 33
TX2P 11 22
A4 0LED1 LA N_A CTLED# 33
23
TX2N 1LED1 LA N_LILED# 33
C122 C 61 C123 C 82 C 92 12 52
C467 C457 C456 C468 A5 2LED1
. 1U-16V_4 . 1U-16V_4 . 1U-16V_4 . 1U-16V_4 . 1U-16V_4 V A UX_25 46 TX0P _SYS
4. 7U-10V_8 . 1U-16V_4 . 1U-16V_4 . 1U-16V_4 0B2 TX0N_SYS
45
TX3P 14 1B2
A6
VDDP+AVDD)
41 TX1P _SYS
V A UX_12 TX3N 2B2 TX1N_SYS
15 40
C460 C459 +3V_S5 A7 3B2
U10 TX2P _SYS
BCM5787MKMLG . 1U-16V_4 . 1U-16V_4 V A UX_25 35
L11 B LM11A601S_6 4B2 34 TX2N_SYS
V A UX_12 B IA S V DD LA N_MB _ACTLED# 19 5B2
LED0 TX3P _SYS
15
19
56
61
17
68
C 71 C 67 C121 C 79 C 89 R376 30
6
LA N_MB _LINKLED# 20 6B2 29 TX3N_SYS
4. 7U-10V_8 . 1U-16V_4 . 1U-16V_4 . 1U-16V_4 . 1U-16V_4 C 65 LED1 7B2
5
VDDP
VDDP
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
13 VDDC 36 . 1U-16V_4 10K_4 54 25 S Y S _A CTLED#
VDDC BIASVDD LED2 0LED2 S Y S _LINK LED#
20 26
VDDC L48 B LM11A601S_6 D4 BAS316 LA N_DOCK IN# 17 1LED2
34 16 D OCK IN#
51
55 VDDC 23 XTA LV DD SEL 2LED2
VDDC XTALVDD A1A: (9/20) Add Diode for isolation
60 A1A:(9/20) Add SYS_ACTLED#,
GND00
GND01
GND02
GND03
GND04
GND05
GND06
GND07
GND08
GND09
GND10
VDDC
L10 B LM11A601S_6 C458 0: A to B1 5
NC SYS_LINKLED#
A V DDL 39 38 . 1U-16V_4 1: A to B2 U6
AVDDL AVDD L14 B LM11A601S_6 P I3L500 (LAN SW)
44
C 58 C 62 46 AVDDL BCM5787M 45 A V DD_F14
13
16
21
24
28
33
39
44
49
53
55
AVDDL 10mm X 10mm AVDD
51
4. 7U-10V_8 . 1U-16V_4 AVDDL 6 8 -Pin QFN 52 A1A:(9/20) the chip already integrate
L12 B LM11A601S_6 AVDD C455 C 63 internal terminators
GP HY _P LLVDD 35 . 1U-16V_4 . 1U-16V_4 A1A: 9/6 chnage from MAX4892 to PI3L500
V A UX_12 GPHY_PLLVDD
C 57 C 68
49 TX3N
4. 7U-10V_8 . 1U-16V_4 TRD3- 50 TX3P
C C
L13 B LM11A601S_6 TRD3+
+3V_S5 P CIE _P LLVDD 30 48 TX2N
C 77 C 80 PCIE_PLLVDD TRD2- 47 TX2P
TRD2+ V A UX_25
4. 7U-10V_8 . 1U-16V_4 42 TX1N B LM11A601S_6 U3
Q17 L9 B LM11A601S_6 TRD1- TX1P L8 + 3V _2.5V_LAN 1
27 43 24
2
DTC144E UA R 80 P CIE _S DS _VDD 33 PCIE_VDD TRD1+ TX0P _SYS TCT1 MCT1 X-TX0P
2 23
4. 7K_4 C 66 C 75 PCIE_VDD 41 TX0N C449 C 42 TX0N_SYS 3 TD1+ MX1+ 22 X-TX0N
TRD0- TX0P TD1- MX1-
40
4. 7U-10V_8 . 1U-16V_4 24 TRD0+ . 1U-16V_4. 1U-16V_4 + 3V _2.5V_LAN 4 21
P CIE _W A KE_R# PCIE_GND LINK LE D# TX1P _SYS TCT2 MCT2 X-TX1P
3 1 2 5 20
16, 27 P CIE _WAKE# LINKLED# 100# TX1N_SYS TD2+ MX2+ X-TX1N
1 +3V_S5 6 19
SPD100LED# 67 1000# TD2- MX2-
C 85 . 1U-16V_4 TXDP _C SPD1000LED# LA N_MB _ACTLED# + 3V _2.5V_LAN 7
26 66 18
15 P CIE _RXP3 T XDN_C PCIE_TXDP TRAFFICLED# TX2P _SYS TCT3 MCT3 X-TX2P
C 88 . 1U-16V_4 25 8 17
15 P CIE _RXN3 PCIE_TXDN TX2N_SYS TD3+ MX3+ X-TX2N
31 8 T72 R 38 R 29 R 66 R382 9 16
15 P CIE _TXP3 PCIE_RXDP GPIO2 C450 C 38 TD3- MX3-
32
15 P CIE _TXN3 P CIE _W A KE_R# 12 PCIE_RXDN 4. 7K_4 U5 + 3V _2.5V_LAN10 15
R 79 0_4 -LA N_RST WAKE# *4. 7K_4 . 1U-16V_4. 1U-16V_4 TX3P _SYS TCT4 MCT4 X-TX3P
10 9 T73 11 14
15, 16, 21, 25, 26,27,28,30,33 P LTRST# PERST# UART_MODE TD4+ MX4+
A1A: (9/20) Internal PU

29 7 BCM_WP 4. 7K_4 B CM_SDA 1 8 SI TX3N_SYS 12 13 X-TX3N
2 CLK _P CIE _LAN REFCLK+ GPIO1_SERIALDI T3 SI SO TD4- MX4-
28 4 4. 7K_4 B CM_SCL 2 7
2 CLK _P CIE _LAN# REFCLK- GPIO0_SERIALDO T2 SCK GND
B CM_RESET# 3 6 NS 892402P R 28 R 27 R 26 R 25
RESET# VCC +3V_S5
B CM_RESET# CS# 4 5 BCM_WP
A1A:(9/1 BCM recommend) R377 1K_4 A UX_PRES 54 CS# WP# C 52
+3V_S5 VAUXPRSNT
Pull up pin 53 (Vmainprsnt) to the system main power (3.3v), R378 1K_4 VMA_PRES 53 . 1U-16V_4 75_4 75_4 75_4 75_4
+3V VMAINPRSNT
but not the standby power . R 78 4. 7K_4 3 65 B CM_SCL A T45DB 011B -S C(LAN FLASH) A1A:(10/11) C 31
LOW_PWR SCLK MGND
63 SI Change the pin name from GND to MGND
LA N_SMBC 58 SI 64 B CM_SDA 1500P -2KV_1808
A1A:(10/27) PULL up +3V_S5 on SB side 2, 13, 16,27,33 PCLK_SMB LA N_SMBD SMB_CLK SO CS#
57 62
2, 13, 16,27,33 PDAT_SMB SMB_DATA CS#
C 94 27P -50V_4 XTA LO_R R60 200_4 XTALO 22 59
XTALO NC/(ENERGY_DET) T1 C N19
XTA LI 21
XTALI
+3V_S5
Y1 RD AC 37 R369 220_4 11
3
RDAC LA N RE GCTL25 +3V_S5 YELLOW__P
B 25Mhz 18 C 54 C 44 B
R 42 REGCTL25 Q9 S Y S _A CTLED# 12
1 MMJT9435 . 1U-16V_4 4. 7U-10V_8 YELLOW_N
1. 24K_6
C114 27P -50V_4
14 LA N RE GCTL12
REGCTL12 X-TX3N 1
2
4
A1A: (9/1 BCM recommend) change to 1.24k as default RX2-
V A UX_25
11 X-TX3P 2
T74 NC(CLK_REQ#) RX2+
16 C 53 C 51
REG_GND LA N_RE G1_2V X-TX1N 3
A1A: (9/1 BCM recommend) . 1U-16V_4 47U-6. 3V_1210 RX1-
Change pull-up resistor value to 47-k. at pin 58 (SMB)CLK) X-TX2N 4 13
GND
3
TX2- GND1
and pin 57 (SMB_DATA) as the SM-Bus isn't used. Package Body C 90 C 86
10U/10V_8
Q16 X-TX2P 5 14 C445 . 1U-10V_4
MMJT9435 . 1U-16V_4 TX2+ GND2
1
69
A1A: (9/1 BCM recommend) X-TX1P 6 C 11 . 01U-16V_4

RX1+
Change capacitance value from 47-uF to 10-uF. A1A:(9/20) change from
LAN_MB_ACTLED#, LAN_MB_LINKLED# to X-TX0N 7 C 36 1500P -2KV_1808
2
4
TX1-
CS# SI B CM_SCL V A UX_12 SYS_ACTLED#, SYS_LINKLED# X-TX0P
+3V_S5 8
C 93 C104 TX1+
. 1U-16V_4 10U-6. 3V_8

R 61 R379 R380 R 72 R368 220_4 9 MGND
+3V_S5 GREEN_P A1A:(10/11)
4. 7K_4 *4. 7K_4 4. 7K_4 *4. 7K_4
S Y S _LINK LED# 10 Change the pin name from GND to MGND in CN26.13
GREEN_N
CS# LA N_RE G1_2V R 30 1. 5_1206 +3V_S5
A OP _C100D8-108A4-L
R 47 *1_1206 V A UX_25 A1A:Add diode for 10/100M

& 1000M led control A1A:(9/21) Change CONN (refer to ZC1)
A EEPROM Strapping A1A: (9/1 BCM recommend) A

in order to pull up C321/C51 and Q17 pin 3 to
3V_LAN rail.
SO SI CS# SCLK
24c64 1 1 0 1
AT45DB011B 1 0 1 1 PROJECT : ZU1

Size Doc ument Number Rev
GigaLAN (BCM5787M) / RJ45 1A
Dat e: Thurs day , November 02, 2006 S heet 18 of 39

5 4 3 2 1

1 2 3 4 5 6 7 8
CRT Select
A A
U4
16 +5V
I N T _CRT_RE D VCC S Y S _V GA _RED
6 I N T_CRT_RE D 4 2
C_A A0 3
A1 D OCK _R 33
I N T _CRT_GRN 7 5 S Y S _V GA _GRN C 41
6 I N T_ CRT_GRN C_B B0
6 . 1U_4
B1 DOCK _G 33
I N T_CRT_B LU 9 11 S Y S _V GA _BLU
6 I N T_CRT_B LU C_C C0 10
C1 DOCK _B 33
12 14
C_D D0
13
P R_INS E RT_5V 1 D1
20, 33 P R_INS E RT_5V SE
15 8
EN# GND
S N74CB TLV 3257PWR
SEL FUNCTION
LOW IN_0
HIGH IN_1
A1A: (9/20) Remove NEZ@ ciucuit
B B
CRT CONNECTOR AND ESD CRT_S E NS E #_L D 37 MTW 355 CRT_S E NS E# 15, 28,33
C8 . 1U_4
A1A:(10/18) Change CRT_SENSE# from
CRT CONN Pin11 to Pin5
D 38
*MTW 355
C R TV DD3
16
D1 SSM14 C N 18
+5V
RESERVE FOR ESD
S UY _070546FR015S 200ZR
6
S Y S _V GA _RED L5 B LM18B A 220SN1_6 C R T_R1 1 11
7
S Y S _V GA _GRN L4 B LM18B A 220SN1_6 C RT_G1 2 12
8
S Y S _V GA _BLU L6 B LM18B A 220SN1_6 C RT_B 1 3 13
C C
9
4 14
R5 R6 R7 C 15 C 16 C 17 C6 C5 C4 10
150_4 150_4 150_4 10P_4 10P _4 10P _4 10P _4 10P _4 10P_4 5 15
CRT_SENSE#_L
17
A1A: (9/20) change name from CRTVDD3 to +5V A1A:(9/21) Change CONN P/N (Follow ZC1)
D O CK _V S Y NC 33
CORRECT
ADD BYPASS CAP D O C K _HS Y NC 33
A1A: (9/20) change from 39ohm to 0 ohm
+5V
U1
+5V 1 16 C R TV S Y NC1 R 12 0_4 L43 B LM18B A 220SN1_6 C R T V S Y NC
C 25 VCC_SYNC SYNC_OUT2 C R TH S Y NC1R 10 0_4 L44 B LM18B A 220SN1_6 C R TH S Y NC
14
. 1U_4 7 SYNC_OUT1
C 23 . 22U/ 25V_6 8 VCC_DDC C 439 C440
BYP I N T_V S Y NC +5V
15
SYNC_IN2 I N T_ HS Y NC *47P -50V_4 *47P -50V_4
2 13
+3V VCC_VIDEO SYNC_IN1 A1A:change from 2.7k to 2.2k
C 22 C R T_R1 3 10 I N T_ CRT_DDCCLK R 16 2. 2K_4 R 370 R371
VIDEO_1 DDC_IN1 +3V
. 1U_4 C RT_G1 4 11 I N T_ CRT_DDCDA T R 17 2. 2K_4 2. 7K _4 2. 7K_4
C RT_B 1 VIDEO_2 DDC_IN2
5
VIDEO_3 9 D D CCLK _1
DDC_OUT1 D O CK _DDCK 33
6 12 D D CDA T_1
D GND DDC_OUT2 D O CK _DDDA 33 D
A1A:(10/18) Change net name: IP 4772 CM2009: AL002009W01
from SYS_VGA_RED to CRT_R1 C7 C 441 to Docking
from SYS_VGA_GRN to CRT_G1
IP4772: AL004772000
from SYS_VGA_BLU to CRT_B1 *47P -50V_4 *47P -50V_4
6 I N T_HS Y NC
6 I N T_V S Y NC A1A: (9/20) change to 30 ~ 50p, default: don't stuff PROJECT : ZU1
6 I N T_ CRT_DDCCLK
6 I N T_ CRT_DDCDA T
CRT 1A

1 2 3 4 5 6 7 8
5 4 3 2 1
LVDS
CN2
1 INT_TXLOUT2-
6 INT_TXLOUT2- 1
3 INT_TXLOUT2+
6 INT_TXLOUT2+ 3
5
INT_TXLOUT1- 5
6 INT_TXLOUT1- 7
INT_TXLOUT1+ 9 7
6 INT_TXLOUT1+ 9
11
INT_TXLOUT0- 11
6 INT_TXLOUT0- 13
INT_TXLOUT0+ 15 13
6 INT_TXLOUT0+
INT_TXLCLK OUT-
17
19
15
17
CAMERA MODULE
6 INT_TXLCLK OUT- 19
INT_TXLCLK OUT+ 21
6 INT_TXLCLK OUT+ 21
23
I NT_LV DS _E DIDCLK 25 23
6 I NT_LV DS _E DIDCLK 25 +3V
INT_LV DS _E DIDDA TA 27
6 INT_LV DS _E DIDDA TA 27
29 1 3 C CD_P OW E R
29 +3V
A1A:(10/2) change from USB7 to USB8 R 20 0_4 US B P 8-_CN 2 A1A: (9/20) Change LVDS CONN to 30pin
15 US B P8- 2
R 19 0_4 US B P 8+ _CN +3V C 30 10U_8
+
D 15 USBP8+ 4 (9/21)change footprint to 88242-3000-30P-RUV D
A1A: (9/20) Come from 965GM for PWM control 4 Q1 R 21
6
2
8 6 A O3413 C 444 1000P_4 4. 7K _4
R 15 0_4 L7 D IS P ON 8
6 INT_LV DS _PWM 10
R 13 *0_4 V A DJ 10
28 C ONTRA S T 12 BECAUSE UR'S SUGGESTION,
B LM18P G181S N1D_6 14 12 R 11
+3V 14 ACTICE CHANGE FROM LOW TO HIGH.
3
16
C 28 . 1U_4 C CD_P OW E R 16 2. 2K_4
18
D MIC-CLK 20 18
31 D MIC-CLK 2 C CD_P OW E RON 28
D MIC-12 20 I NT_LV DS _E DIDCLK
22
31 DMIC-12 22 6 I NT_LV DS _E DIDCLK
L C D V CC 24
24 Q2
26
1
V IN R8 0_8 I N V CC0 28 26 31 +3V D TC144E U
28 31
30 32
30 32
A CS _88242-3001
R9
2. 2K_4
1
C 12
+ C 13 +3V INT_LV DS _E DIDDA TA
A1A(10/5):Change C377 from CH6102M9900 6 INT_LV DS _E DIDDA TA
to CH61004M3E5 (refer to ZC3) 10U-25V _1210 2 1000P_4
C 14
+3V
1000P_4
C 24 U2
. 1U_4 6 1 L C DV CC_1 R 18 0_8 L C D V CC

IN OUT
4 2 C 26 C 18 C 20
IN GND C 27 C 29
D IS P _ON 3 5 . 1U_4 . 01U_4 10U_8
6 I NT_LV DS _DIGON ON/OFF GND . 1U_4 10U_8
C A A T4280 C
R 14
<demo circuit>
Crestline suggest 100K 100K _4
G73 suggest 10K(ZS1 Default)
8/27 change back to 100K
TV Out (SVHS) MiniDIN 7-pin MR Sensor

+3V
TV -CHROMA R 22
10K _4
3
D IS P ON D2 B A S 316
L ID591# 16, 28,29
B MR# 16, 28,29 B
2
D 35
U8 D3 B A S 316
INT_LV DS _B LON 6
16 +5V * DA 204U A1A:(9/27) change form LID SW to MR#
VCC S Y S _TV _Y/G
6 INT_TV _Y / G 4 2 +3V
C_A A0
3 DOCK _TV _Y / G 33
A1 S Y S _TV _C/R
6 I NT_TV _C/ R
7 5
C_B B0 C 78 R 24 *1K _4
6 D OCK _TV _C/ R 33
9 B1 11 S Y S _TV _COMP
6 INT_TV _COMP C_C C0 . 1U_4
10 A1A:(10/26) change from 100k +-5% to 100k +-1%
C1 DOCK _TV _COMP 33
12 14
C_D D0
13
P R_INS E RT_5V D1
19, 33 P R_INS E RT_5V 1
15 SE 8 TV -LUMA R 23
EN# GND
<demo circuit>
S N74CB TLV 3257PWR 100K_4 Crestline suggest 100K
SEL FUNCTION G73 suggest 10K(ZS1 Default)
3
LOW IN_0
HIGH IN_1 A1A: (9/20) Remove "NEZ@" circuit
3
1
D 36 2 E C_FP B A CK# 28
C N 17 * DA 204U
B LM18P G181SN1D_6 Q3
1
+3V
5
L3 L1 B LM18P G181SN1D_6
S Y S _TV _C/R TV -CHROMA 6 4 TV -LUMA S Y S _TV _Y/G D TC144E U
5
6 4
9 8
R2 C 19 C3 9 8 C1 C9 R3
150_4 6P _4 6P_4 6P _4 6P_4 150_4 TV -COMP
A 3 A
3 1
7
3
7
A1A:(9/21) Change CONN (Follow ZC1) S UY _030107FR007S 112FR

L2 B LM18P G181SN1D_6
TV -COMP S Y S _TV _COMP
1
D 34
* DA 204U PROJECT : ZU1

R4 +3V
C2 C 10
6P _4 6P_4 150_4
LVDS/M R senseor/SVIDEO 1A

5 4 3 2 1
5 4 3 2 1
SDVO-DVI A1A:(9/21) Change R value from 2.2k to 4.7k.

(FAE suggest R value from 4K~9K)
6 SDVOB_R+
6 S DVOB_R-
+ 2.5V R 56 4.7K_4 SDVO_CTRLCLK
6 SDVOB_G+
6 S DVOB_G-
D VI_ A VDD + 2.5V R 51 4.7K_4 S DVO_CTRLDATA
6 SDVOB_B+
6 SDVOB_B-
NB internal PD for SDVO is not implement
6 SDVOB_CLK+ Nedd external PU for SDVO exist
D 6 SDVOB_CLK- D
IN T- C107 . 1 U_4
P EG_RXN1 6
D VI_ A VDD
I NT+ C 97 . 1 U_4
PEG_RXP1 6
AS->Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0).
When AS is low the address is 72h, when high the address is 70h.
48
47
46
45
44
43
42
41
40
39
38
37
U1 2
SDVOB_CLK-
SDVOB_CLK+
SDVOB_B-
SDVOB_B+
SDVOB_G-
SDVOB_G+
SDVOB_R-
SDVOB_R+
AVDD3
AGND3
AVDD2
AGND2
+ 2.5V R 62 10K_4 R 63 *100K_4
1 5,16,18,25,26,27,28,30,33 PLTRST#
+ 3V L46 BLM11A601S_6 D VI_ AVDD_PLL 1 36 D VI_ A VDD L 16 BLM11A601S_6 + 2.5V

AVDD_PLL AVDD1
2 35
C108 C 115 AS RESET* RSV C 125 C 111 C124 C 117
3 34
AS BSCAN IN T-
6 S DVO_CTRLCLK 4 33
. 1 U_4 1 0U_8 SPC SDVOB_INT- I NT+ . 1 U_4 . 1 U_4 . 1 U_4 1 0 U_8
6 S DVO_CTRLDATA 5 32
SPD SDVOB_INT+
6 31
7 AGND_PLL AGND1 30
D V ODATA DGND1 DGND2
8 29 D VI_DET 33
D VOCLK SD_PROM HPDET D VI_ D VDD
9 28
10 SC_PROM DVDD2 27 P ROM2
33 D OCK_DDC_DT SD_DDC PROM2
11 26 P ROM1
33 D O CK_DDC_CK SC_DDC PROM1
+ 2.5V L47 BLM11A601S_6 D VI_ D VDD 12 25 to Docking
DVDD1 VSWING
TGND1
TGND2
TVDD1
TVDD2
TDC0*
TDC1*
TDC2*
TDC0
TDC1
TDC2
C 87 C 91 C 81 R 50
TLC*
TLC
. 1 U_4 . 1 U_4 1 0U_8 1 .2K_4
C C
13
14
15
16
17
18
19
20
21
22
23
24
C H7 307C-DEF
to Docking D VI _TVDD L 45 BLM11A601S_6 +3V

C 73 C 72 C 74
. 1 U_4 . 1 U_4 1 0 U_8

33 D VI_CLK-
33 D VI_CLK+
33 D VI_D0-
33 D VI_D0+
33 D VI_D1-
33 D VI_D1+
33 D VI_D2-
33 D VI_D2+
B B
FOR CH7312 HDCP USE

7312
+2.5V +2.5V
PN
U1 3
4 R 68 * 0_4
A GND A
8 7 1 2
VCC E# +3V + 3V
U1 1
3
2 A2 5 P ROM1 C 98 D VOCLK 6 1
A1 D P ROM2 D V ODATA SCL A0
1 6 * . 1U-10V_4 5 2
A0 C SDA A1 C 109
3
R 57 *1K_4 D VOCLK A2
* C H9901
+ 3V
7
WP VCC
8 * . 1U_4 PROJECT : ZU1
4
R 52 *1K_4 D V ODATA GND
R 75 *10K_4
+ 3V
*AT24C16 Quanta Computer Inc.
+ 2.5V 2 1 P ROM1
R 73 *10K_4
P ROM2
DVI (CH7307) 1A
2 1
5 4 3 2 1

5 4 3 2 1
+3V
P C I_ CL K _ CB 7 1 4 R 1 90 *2 2 _ 4 P C L K _ P CM_ R C 302 *1 0 p _ 4
C 534 C 532 C 531 C 537 R 178 *0 _ 6 P C IRS T #

A1A:(9/22) refer to BL3. Add G_RST# circuit. R 177 1 0 0 K_6
+3V
. 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4
C B _ RS MRS T # delay 10ms at least
V C C D 1#
V C C D 0#
C 281 V P P D1
C 535 C 536 C 295 C 303 . 2 2 U_ 6 V P P D0
D . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 I NT A # A _ C R S V D/D2 D
15 I NT A # A _ C R S V D/D2 24
S E R I RQ A _ C R S V D/D1 4
1 6 ,2 3 ,2 8 ,3 0 S E R I RQ A _ C R S V D/D1 4 24
P CI_ P ME # R 445 0_4 P CM_ P ME# A _ C RS V D/A 1 8
1 5 ,2 3 ,2 5 P CI_ P ME # A _ C RS V D/A 1 8 24
P CMS P K
31 P CMS P K
A1A:(9/22) C B _ RS MRS T # A _ C C D1 # A _ C C D1 #
+3V A _ C C D1 # 24
FAE suggest R383's value under 47 ohm. R E Q0 # A _ C C D2 # A _ C C D2 #
15 R E Q0 # A _ C C D2 # 24
C 283 C 282 G NT 0 #
15 GNT 0 #
A D1 7 R 189 47_4 P C M_ IDS E L A _ CV S 1 # C 539 C 533
A _ CV S 1 # 24
. 1 U_ 4 . 1 U_ 4 P C IRS T # R 437 A _ CV S 2 #
1 5 ,2 3 ,2 7 P CIRS T # A _ CV S 2 # 24
P C I_ CL K _ CB 7 1 4
2 P C I_ CL K _ CB 7 1 4
1 0 P _4 1 0 P _4
F RA ME # 4 3 K _4
1 5 ,2 3 ,2 5 F RA ME #
IR DY #
P CM_ S US #
1 5 ,2 3 ,2 5 I R D Y #
TRDY #
1 5 ,2 3 ,2 5 T R D Y #
DE V S E L #
1 5 ,2 3 ,2 5 DE V S E L#
S T OP#
1 5 ,2 3 ,2 5 STOP#
P E R R#
1 5 ,2 3 ,2 5 P E RR#
S E R R#
1 5 ,2 3 ,2 5 S E RR#
M10
M11
M13
M12
N11
N10
N13
N12
E10
L11
L10
L12
J13
M1
M9
G4
H1
N9
C6
D9
K3
K1
A1
K9
K8
A2
A4
B1
F4
U17
L3
L2
L1
L8
J4
A D [ 3 1 ..0 ] A _ C A D[3 1 ..0 ]
DEVSEL#
PERR#
PCIRST#
IDSEL
RI_OUT#/PME#
RSVD/D2
RSVD/D14
RSVD/A18
CVS1/VS1
STOP#
TRDY#
IRDY#
G_RST#
FRAME#
PCIGNT#
PCIREQ#
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
CCD1#/CD1#
CCD2#/CD2#
SPKROUT
MFUNC0
VPPD1
VPPD0
CVS2/VS2
SERR#
PCICLK
SUSPEND#
VCCD1#
VCCD0#
1 5 ,2 3 ,2 5 A D [ 3 1 ..0 ] A _ C A D [3 1 ..0 ] 24
A D0 N8 B2 A _ CA D3 1
A D1 AD0 CAD31/D10 A _ CA D3 0
K7 C3
L7 B3
N7 A3
M7 C4
C N6 A6 C
A D6 AD5 CAD26/A0 A _ CA D2 5
M6 D7
K6 C7
M5 A8
L5 D8
A D1 0 AD9 CAD22/A4 A _ CA D2 1
K5 A9
A D1 1 AD10 CAD21/A5 A _ CA D2 0
M4 C9
A D1 2 AD11 CAD20/A6 A _ CA D1 9
K4 A10
A D1 3 AD12 CAD19/A25 A _ CA D1 8
N3 B10
A D1 4 AD13 CAD18/A7 A _ CA D1 7
M3 D10
A D1 5 AD14 CAD17/A24 A _ CA D1 6
N2 E12
A D1 6 AD15 CAD16/A17 A _ CA D1 5
J2 F10
A D1 7 AD16 CAD15/IOWR# A _ CA D1 4
J1 E13
ENE1410 AJ014100T41 A D1 8 H4
AD17 CAD14/A9
F13 A _ CA D1 3
A D1 9 AD18 CAD13/IORD# A _ CA D1 2
H3 F11
A D2 0 AD19 CAD12/A11 A _ CA D1 1
G3 G10
A D2 1 AD20 CAD11/OE# A _ CA D1 0
G2 G11
A D2 2 AD21 CAD10/CE2# A _ CA D9
F1 G12
AD22 CAD9/A10
ID Select : AD17 A D2 3 F2
AD23 CAD8/D15
H12 A _ CA D8
A D2 4 E2 H10 A _ CA D7
A D2 5 AD24 CAD7/D7 A _ CA D6
Interrupt Pin : INTA# E3
AD25 CAD6/D13
J11
A D2 6 E4 J12 A _ CA D5
Request Indicate : REQ0# D1
AD27 CAD4/D12
K13
A D2 8 D2 J10 A _ CA D3
Grant Indicate : GNT0# D4
AD29 CAD2/D11
K10
A D3 0 C1 K12 A _ CA D1
C2 L13
AD31 CAD0/D3
CSTSCHG/BVD1/STSCHG#
CCLKRUN#/WP/IOIS16#
CAUDIO/BVD2/SPKR#
C BE0#
CINT#/READY/IREQ#
B 1 5 ,2 3 ,2 5 C BE0# N5 B
C BE1# CBE0#
1 5 ,2 3 ,2 5 C BE1# N1
CBE1#
CREQ#/INPACK#
C BE2# J3 H13 A _ CC/B E 0 #
CSERR#/WAIT#
1 5 ,2 3 ,2 5 C BE2# A _ CC/B E 0 # 24
CDEVSEL#/A21
CBE2# CCBE0#/CE1#
CRST#/RESET
CFRAME#/A23
C BE3# A _ CC/B E 1 # M004 : to fix cardbus issue
CBLOCK#/A19
1 5 ,2 3 ,2 5 C BE3# E1 E11 A _ CC/B E 1 # 24
CPERR#/A14
CBE3# CCBE1#/A8
CTRDY#/A22
CSTOP#/A20
CGNT#/WE#
CIRDY#/A15
P AR M2 A11 A _ CC/B E 2 # 05/03 '06
1 5 ,2 3 ,2 5 PAR PAR CCBE2#/A12 A _ CC/B E 2 # 24
CCLK/A16
B7 A _ CC/B E 3 #
CCBE3#/REG# A _ CC/B E 3 # 24
D13 A _ CP A R
VCCA1
VCCA2
VCC10
CPAR/A13 A _ CP A R 24
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
C B1410
D3
H2
F12
C10
F3
C5
B8
B9
L4
K11
B6
G1
K2
L6
L9
G13
A7
B4
B5
D6
D11
C13
C12
B13
A13
A12
B11
D5
B12
M8
N4
H11
D12
C8
C11
A5
+3V A V CC +3V
+5V +3V U18 +3V
V C C D 0# 1 16
V C C D 1# VCCD0# SHDN# V P P D0
2 15
VCCD1# VPPD0 V P P D1
3 14
3.3V VPPD1 A V CC AVPP
4 13
3.3V AVCC
5 12
5V AVCC
6 11
5V AVCC R _ A _ CCL K R 4 46 10_4 A _ CCL K
7 10 A _ CCL K 24
GND AVPP A _ CRS T #
8 9 A _ CRS T # 24
OC# 12V A _ C C L K RUN#
A
A _ C C L K RUN# 24 A
A _ CF RA ME #
ENE CP-2211 A _ CIRD Y#
A _ CF RA ME # 24
A _ C I R D Y # 24
A _ C T RDY #
+5V +3V A V CC AVPP A _ C T RDY # 24
A V CC A _ CDE V S E L # < O rg Na me >
A _ CDE V S E L # 24
A _ CS T OP#
A _ C P E RR#
A _ CS T OP# 24
<Org A d d r1> PROJECT : ZU1
A _ C P E RR# 24
A _ C S E RR# <Org A d d r2>
C 312 C 3 13 C 311 C 296 C 530 C 298 C 2 85 C 286 C 297 C 538 A _ C RE Q#
A _ C S E RR# 24
A _ C RE Q# 24
<Org A d d r3> Quanta Computer Inc.
A _ CGNT # <Org A d d r4>
A _ CGNT # 24
4 . 7 U_ 6 . 1 U_ 4 4 .7 U_ 6 . 1 U_ 4 4 . 7 U_ 6 . 1 U_ 4 4 . 7 U_ 6 . 1 U_ 4 . 1 U_ 4 . 1 U_ 4 A _ CB L OCK #
A _ CB L OCK # 24
A _ CINT # Size D o c u m e n t Nu mb e r Rev
A _ CINT # 24
A _ C S T S CHG PCMCIA (ENE CB1410) 3A
A _ C S T S CHG 24
A _ C A U DIO
A _ C A U DIO 24
5 4 3 2 1

5 4 3 2 1
SERIRQ
16,22,28,30 SERIRQ
48MHz Clock
ID Select : AD18 INTB# SDPW REN33# +3V
15 INTB# SDPW REN33# 24 Y6
Interrupt Pin : INTB# GND_SD SDCLKI 3 4
OUT VDD
Request Indicate : REQ1# 2 1 C576

24 XDRE#/MSCLK GND OE
xDDATA3/MSDATA3 R534
xDDATA3/MSDATA3 24
Grant Indicate : GNT1# xDDATA5/MSDATA2 *TXC-48MHz-30PPM-15Pf *.01U_4
24 SDWP xDDATA5/MSDATA2 24
xDDATA2/MSDATA0 *0_4
24 SDCD# xDDATA2/MSDATA0 24
XDDATA6/MSDATA1
XDDATA6/MSDATA1 24
D XDWP# +3V D
+3V_CRVCC XDWP# 24
XDBSY#
+3V +3V XDBSY# 24
R548
+3V_CRVCC A1A:(9/26) Add 22ohm for R490 and 10p for C839
A1A:(9/22) remove R634,R636 Change Y7 from 50MHz to 48MHz
R522 *0_4 XDCE#
S DCD#
XDCE# 24
SUSPEND#
GND_SD
PRST#
43K_4 A1A:(9/28) base on EMI suggest: remove R490,C839
SERIRQ
R496 *0_4
S DWP
SUSPEND#
GRST# should +3V
connect to Power
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
On reset if U39 A1A:(9/22) XMDAT4B is for 8 bit MMC,remove it.
99
98
97
support S3
XPMPWR_ENIZ
XSDCDIZ
XSDWPISMWPDIZ
XMSCLKOSMREOZ
XMDAT5BSMWPOZ
XMDAT6BSMBSYIZ
XSUSPENDIZ
XGRSTIZ
XMDAT7BSMCEOZ
XPMPWR_O
NC
XPMPWR_VCC
NC
NC
VCC
VCC_SD
GND_SD
VCC
VSS
XMSDAT3BSMDAT3B
XMSDAT2BSMDAT5B
XMSDAT0BSMDAT2B
XMSDAT1BSMDAT6B
XMFUNC7B
XMFUNC6B
XMFUNC5B
XMFUNC4B
XMFUNC3B
XMFUNC2B
XMFUNC1B
XMDAT4B
VSS
AD[31..0]
15,22,25 AD[31..0]
AD0 96 XDDATA1/MSBS
MSBSOSMDAT1 XDDATA1/MSBS 24
AD1 SDPW REN33# 1 95 XDPW REN#MSPWREN#
XSDPWR33OZ MS_SMPWROZ XDPW REN#MSPWREN# 24
AD2 2 94 INTB#
C AD3 GND_SD NC MFUNC0 510_PME# R564 0_4 PCI_PME# C
3 93 PCI_PME# 15,22,25
AD4 xDCLE/SDDAT2 4 GND_SD RIOUTZ_PMEOZ R563 43K_4
24 XDCLE/SDDAT2 92 +3V
AD5 xDDATA4/SDDAT35 SDDAT2SMCLE VSS AD0
24 xDDATA4/SDDAT3 91
AD6 xDALE/SDCMD 6 SDDAT3SMDAT4 PCIAD0 MSINX#
24 xDALE/SDCMD 90 MSINX# 24
AD7 XDWE#/SDCLK 7 SDCMDSMALE MSINSIZ XDCD#
24 XDWE#/SDCLK 89 XDCD# 24
AD8 xDDATA7/SDDAT08 SDCLKSMWEOZ SMCDIZ AD1
AD9 xDDATA0/SDDAT19 SDDAT0SMDAT7 PCIAD1 AD2
AD10 SDDAT1SMDAT0 PCIAD2 AD3
+3V_CRVCC 10 86
AD11 VCC_SD PCIAD3 AD4
11 85
AD12 NC PCIAD4 AD5
12 84
AD13 NC PCIAD5 AD6
13 83
AD14 NC PCIAD6 AD7
14 82
AD15 NC PCIAD7
15 81 +3V
AD16 REQ# NC VCC
15 REQ1# 16 80
AD17 GNT# PCIREQOZ VSS
15 GNT1# 17 79
AD18 AD31 PCIGNTIZ NC
18 78
AD19 AD30 PCIAD31 NC
19 77
AD20 AD29 PCIAD30 NC
20 76
AD21 PCIAD29 NC
21 75
AD22 AD28 VSS NC C/BE0#
22 74 CBE0# 15,22,25
AD23 AD27 PCIAD28 PCICBE0Z AD8 A1A:(9/22) Add PU/PD resister
23 73
AD24 AD26 PCIAD27 PCIAD8 AD9
24 72
AD25 AD25 PCIAD26 PCIAD9 AD10 XDDATA1/MSBS R562 43K_4
25 71
AD26 AD24 PCIAD25 PCIAD10 AD11 xDDATA3/MSDATA3 R527 43K_4
26 70
AD27 C/BE3# PCIAD24 PCIAD11 xDDATA5/MSDATA2 R533 43K_4
B
15,22,25 CBE3# 27 69 +3V B
AD28 AD18 R503 47_4 510_IDSEL PCICBE3Z VCC AD12 xDDATA2/MSDATA0 R538 43K_4
28 68
AD29 PCIIDSELI PCIAD12 AD13 XDDATA6/MSDATA1 R539 43K_4
+3V 29 67
AD30 VCC PCIAD13 AD14
30 66
NC PCIAD14
PCIDEVSELZ
AD31 AD15 +3V
PCISERROZ
31 65
PCIFRAMEZ
NC PCIAD15
PCIPERRZ
PCITRDYZ
PCISTOPZ
PCICBE2Z
PCICBE1Z
A1A:(9/22) FAE suggest R value under 47 ohm. 32
PCIIRDYZ
PCIRSTIZ
NC
PCIAD23
PCIAD22
PCIAD21
PCIAD20
PCIAD19
PCIAD18
PCIAD17
PCIAD16
PCICLKI
PCIPAR
SDCLKI XDCD# R560 10K_4
VCC SDCD# R565 43K_4
VCC
VSS
VSS
SDWP R561 43K_4
NC
NC
NC
NC
NC
NC
NC
+3V +3V_CRVCC
MR510
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PCI_CLK_510_L
A1A:(9/26) For EMI solution

(close to MR510) XDWP# R540 43K_4
FRAME# XDCE# R556 43K_4
C599 C607 C636 C637 XDWE#/SDCLK R499 43K_4
C/BE2#
C/BE1#
TR DY#
PERR#
SERR#
DEVSEL#
I RD Y#
STOP#
PRST#
PCI_CLK_510_L XDBSY# R547 43K_4

SDCLKI
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
PAR
.1U_4 .1U_4 .1U_4 .1U_4 XDRE#/MSCLK R528 10K_4
R524 XDALE/SDCMD R498 43K_4
XDCLE/SDDAT2 R497 43K_4
*0_4 XDDATA0/SDDAT1 R500 43K_4
XDDATA4/SDDAT3 R552 43K_4
1
+3V +3V C600 XDDATA7/SDDAT0 R555 43K_4
15,22,27 PCIRST#
C577 C643 C645 C646
2 PCI_CLK_510 *10P_4
R529 22_4A1A:(9/26) For EMI solution
2
A .1U_4 .1U_4 .1U_4 .1U_4 A
+3V_CRVCC 15,22,25 CBE2#
15,22,25 FRAME#
15,22,25 I RDY# PROJECT : ZU1
15,22,25 TRDY#
C615 C582 C618
15,22,25 DEVSEL#
15,22,25 STOP#
C644 C566
15,22,25 PERR#
15,22,25 SERR# Size Document Number Re v
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4
15,22,25 PAR 1A
15,22,25 CBE1# Card Reader (MR510)
5 4 3 2 1

5 4 3 2 1
AVCC
R438 43K_4 A_CAD11
CN13 FOX_WZ21131-G2-8F
1
A_CAD0 GND
22 A_CAD0 2
A_CAD1 D3 - CAD0
22 A_CAD1 3 75
A_CAD3 D4 - CAD1 GND
22 A_CAD3 4 76
D 22 A_CAD5 5 77 D
22 A_CAD7 6 78
A_CC/BE0# D7 - CAD7 GND
A1A:(9/21) Change CONN (P/N not ready) 22 A_CC/BE0# 7
CE1- CCBE0 GND
79
A_CAD9 8 80
22 A_CAD9 A_CAD11 A10- CAD9 GND
22 A_CAD11 9 81
A_CAD12 OE - CAD11 GND
22 A_CAD12 10 82
+3V_CRVCC A_CAD14 A11- CAD12 GND
22 A_CAD14 11 83
A_CC/BE1# A9 - CAD14 GND
22 A_CC/BE1# 12 84
A_CPAR A8 - CCBE1 GND
22 A_CPAR 13
CN15 A_CPERR# A13- CPAR
22 A_CPERR# 14
XDBSY# A_CGNT# A14- CPERR
23 XDBSY# 1 22 A_CGNT# 15
XDRE#/MSCLK_R xD-R/B A_CINT# WE/PGM - CGNT
2 22 A_CINT# 16
XDCE# xD-RE RDY/BSY,IRQ*INT
23 XDCE# 3 AVCC 17
XDCLE/SDDAT2 xD-CE VCC
23 XDCLE/SDDAT2 4
XDALE/SDCMD xD-CLE
23 XDALE/SDCMD 5 AVPP 18
XDWE#/SDCLK_R xD-ALE A_CCLK VPP1
6 22 A_CCLK 19
XDWP# xD-WE A _ C IRDY# A16- CCLK
23 XDWP# 7 22 A _ C IRDY# 20
XDDATA0/SDDAT1 xD-WP A_CC/BE2# A15- CIRDY
23 XDDATA0/SDDAT1 8 22 A_CC/BE2# 21
XDDATA1/MSBS xD-D0 A_CAD18 A12- CCBE2
23 XDDATA1/MSBS 9 22 A_CAD18 22
XDCLE/SDDAT2 xD-D1 A_CAD20 A7 - CAD18
10 22 A_CAD20 23
XDDATA4/SDDAT3 SD-DAT2 A_CAD21 A6 - CAD20
11 22 A_CAD21 24
XDALE/SDCMD SD-DAT3 A_CAD22 A5 - CAD21
12 22 A_CAD22 25
SD-CMD A_CAD23 A4 - CAD22
13 22 A_CAD23 26
4in1-GND A_CAD24 A3 - CAD23
14 22 A_CAD24 27
XDRE#/MSCLK_R MS-VCC A_CAD25 A2 - CAD24
15 22 A_CAD25 28
XDDATA3/MSDATA3 MS-SCLK A_CAD26 A1 - CAD25
16 22 A_CAD26 29
MSINX# MS-DATA3 A_CAD27 A0 - CAD26
23 MSINX# 17 22 A_CAD27 30
XDDATA5/MSDATA2 MS-INS A_CAD29 D0 - CAD27
18
MS-DATA2 22 A_CAD29 31
D1 - CAD29
A1A:(9/22) Change PCMCIA CONN (follow BH1)
XDDATA2/MSDATA0 19 A_CRSVD/D2 32
MS-DATA0 22 A_CRSVD/D2 D2 - RFU
XDDATA6/MSDATA1 20 A_CCLKRUN# 33
MS-DATA1 22 A_CCLKRUN# WP,IOIS16-CKRUN
XDDATA1/MSBS 21 34
MS-BS GND
22
C 4in1-GND C
23 35
XDWE#/SDCLK_R SD-VCC A_CCD1# GND
24 22 A_CCD1# 36
XDDATA7/SDDAT0 SD-CLK A_CAD2 CD1- CCD1
25 22 A_CAD2 37
XDDATA2/MSDATA0 SD-DAT0 A_CAD4 D11- CAD2
23 XDDATA2/MSDATA0 26 22 A_CAD4 38
XDDATA3/MSDATA3 xD-D2 A_CAD6 D12- CAD4
XDDATA4/SDDAT3 xD-D3 A_CRSVD/D14 D13- CAD6
23 XDDATA4/SDDAT3 28 22 A_CRSVD/D14 40
XDDATA0/SDDAT1 xD-D4 A_CAD8 D14- RFU
29 22 A_CAD8 41
XDDATA5/MSDATA2 SD-DAT1 A_CAD10 D15- CAD8
XDDATA6/MSDATA1 xD-D5 A_CVS1# CE2- CAD10
23 XDDATA6/MSDATA1 31 22 A_CVS1# 43
XDDATA7/SDDAT0 xD-D6 A_CAD13 RFSH,VS*1-CVS1
23 XDDATA7/SDDAT0 32 22 A_CAD13 44
xD-D7 A_CAD15 IORD-CAD13
33 22 A_CAD15 45
XDCD# xD-VCC A_CAD16 IOWR-CAD15
23 XDCD# 34 22 A_CAD16 46
SDWP xD-CD-SW A_CRSVD/A18 A17- CAD16
23 SDWP 35 22 A_CRSVD/A18 47
SDCD# SD-WP-SW A_CBLOCK# A18- RFU
23 SDCD# 36 22 A_CBLOCK# 48
SD-CD-SW A_CSTOP# A19- CBLOCK
37 22 A_CSTOP# 49
GND A_CDEVSEL# A20- CSTOP
38 22 A_CDEVSEL# 50
GND A21- CDEVSEL
AVCC 51
VCC
TTN_R015-210-LM 52
AVPP A _CTRDY# VPP2
22 A_CTRDY# 53
A_CFRAME# A22- CTRDY
22 A_CFRAME# 54
A_CAD17 A23- CFRAME
22 A_CAD17 55
A_CAD19 A24- CAD17
22 A_CAD19 56
XDWE#/SDCLK XDWE#/SDCLK_R A_CVS2# A25- CAD19
23 XDWE#/SDCLK 22 A_CVS2# 57
R493 22_4 A_CRST# NC - CVS2
22 A_CRST# 58
R488 A_CSERR# RESET-CRST
22 A_CSERR# 59
A1A:(9/26) For EMI solution A_CREQ# WAIT-CSERR
22 A_CREQ# 60
*0_4 (close to socket) A_CC/BE3# INPACK-CREQ
22 A_CC/BE3# 61
A_CAUDIO REG- CCBE3
22 A_CAUDIO 62
1
C562 A_CSTSCHG BVD2,SP-CAUDIO

22 A_CSTSCHG 63
A_CAD28 BVD1,STSCHG-C*
22 A_CAD28 64
B *10P_4 A_CAD30 D8 - CAD28 B
65
2
22 A_CAD30 A_CAD31 D9 - CAD30

22 A_CAD31 66
A_CCD2# D10- CAD31
22 A_CCD2# 67
CD2- CCD2
68
GND
85
HOLE1
86
N-PTH_Hole
N-PTH_Hole
XDCD# +3V HOLE2
87
A1A:(9/26) For EMI solution HOLE3
88
1
C642 (close to socket) HOLE4
GND
GND
GND
GND
MSINX# R523 43K_4
1
*10P_4 C598
2
69
70
71
72
73
74
*10P_4
2
XDRE#/MSCLK XDRE#/MSCLK_R A1A:(9/26) PU MSINX# to +3V

23 XDRE#/MSCLK
R515 22_4
R514
A1A:(9/26) For EMI solution
*0_4 (close to socket)
1
C581
+3V +3V +3V_CRVCC
*10P_4
2
Q32
R535 1 8
GND OUT
2 7
IN OUT C587 C593 A1A:(9/26)Change C437 from 0.1u to 10uF
3 6
43K_4 IN OUT .1U_4 A1A:(9/28)EMI suggest add C484 0.1uF
XDPWREN#MSPWREN# R537 0_4 4 5 10U-10V_8
23 XDPWREN#MSPWREN# SDPWREN33# EN# OUTNC
A R536 0_4 A
23 SDPWREN33#
G545B2P8U
+3V
C617
PROJECT : ZU1
.1U_4

CARD Re a de r & PCMCIA SLOT 1A

5 4 3 2 1

5 4 3 2 1
+3V P LTRS T# R 518 *0_4 GNT2#
C 580 C579
R 516
12P -50V_4 12P -50V_4
Y5
22K _4
G_RS T#
2 1
C 588
. 1U-10V_4 24. 576MHZ
D D
15 I NTE #
2 P CLK _1394
C549
15 G NT2#
R 479 R478
15 RE Q2#
1U-16V _6
15, 22,23 P CI_P ME#
C 572 R487 56. 2_4 56. 2_4
15, 22,23 A D[ 0. . 31]
. 1U-10V _4 R 554 0_6 L1394_TPA2+
R 510 6. 34K_4 R 559 0_6 L1394_TPA2-
R 553 0_6 L1394_TPB2+
R 550 0_6 L1394_TPB2-
4. 7K _4
+3V +3V C 609 P LLV DD A V DD
FILTER1
FILTER0
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
. 1U-10V_4 R 285 R284
R0
R1
56. 2_4 56. 2_4
XO
XI
A1A(10/24):change P/N and footprint to 1394-020115FR004SX01ZL-4P-H
A1A(10/25):change footprint to 1394-020115FR004S518ZL-4P-V

128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
U 33 C376
99
98
97
R 271 C N 32
270P -25V_4 5
VDDP
PCI_PCLK
DVDD
DGND
DGND
DVDD
PLLGND
PLLVDD
AVDD
AGND
XO
XI
PCI_AD24
PCI_AD25
REG18
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_PME#
PCI_REQ#
PCI_GNT#
G_RST#
PCI_INTA#
PCI_CLKRUN#
REG_EN#
FILTER1
FILTER0
R0
R1
56. 2_4 L1394_TPB2- 1
L1394_TPA2- 3 6
L1394_TPA2+ 4
1 96 TP B IAS2 L1394_TPB2+ 2
DGND TPBIAS2 TPA2+
2 95
15, 22,23 CB E 3# PCI_C/BE3# TPA2+
A D25 R 531 150_4 3 94 TPA2-
4 VDDP TPA2- 93
A D23 PCI_IDSEL AVDD TPB2+ C378 S UY _020115FR004S 518ZL
5 92
A D22 PCI_AD23 TPB2+ TPB2- R 477 R476
6 91
PCI_AD22 TPB2- 1U-16V _6
7 90
A D21 8 DVDD AVDD 89 56. 2_4 56. 2_4
A D20 PCI_AD21 AGND TP B IAS1
9 88
A D19 PCI_AD20 TPBIAS1 TPA1+ R 281 0_6 1394TPAP1
10 87 1394TPAP1 33
C A D18 11 PCI_AD19 TPA1+ 86 TPA1- R 280 0_6 1394TP AN1 C
PCI_AD18 TPA1- 1394TP AN1 33
12 85 R 279 0_6 1394TPBP1
DGND AVDD 1394TPBP1 33
A D17 13 84 R 278 0_6 1394TP BN1
PCI_AD17 AGND 1394TP BN1 33
A D16 14 83 TPB1+
PCI_AD16 TPB1+ TPB1-
15 82
15, 22,23 CB E 2# PCI_C/BE2# TPB1-
16 81
VDDP AVDD R 295 R294
15, 22,23 FRA ME# 17 80
PCI_FRAME# AGND TP B IAS0
18 79
15, 22,23 I R D Y # PCI_IRDY# TPBIAS0
19 78 TPA0+ 56. 2_4 56. 2_4
DVDD TPA0+ TPA0-
15, 22,23 TR D Y # 20 77
PCI_TRDY# TPA0-
15, 22,23 DE V S EL# 21 76
22 PCI_DEVSEL# AGND 75 TPB0+
15, 22,23 S TOP# PCI_STOP# TPB0+
23 74 TPB0-
24 DGND TPB0- 73 C389
15, 22,23 P E RR# PCI_PERR# AGND
25 72 A V DD R 306
15, 22,23 S E RR# PCI_SERR# AVDD
26 71 270P -25V_4
15, 22,23 PAR PCI_PAR AGND
27 70 56. 2_4
15, 22,23 CB E 1# DVDD AVDD
28 69 R323 390K_4
A D15 PCI_C/BE1# CPS
29 68
30 PCI_AD15 PHY_TEST_MA 67
A D14 VDDP CNA
31 66
GPIO3/TEST1
GPIO2/TEST0
32 PCI_AD14 DGND 65
PCI_C/BE0#
CYCLEOUT
DGND DVDD
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_RST#
CYCLEIN
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
REG18
DGND
DGND
DGND
DVDD
DVDD
VDDP
SDA
SCL
PC2
PC1
PC0
R 321 R 322 C392

R 293 R292
1U-16V _6
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TS B 43AB23 4. 7K_4 4. 7K_4 56. 2_4 56. 2_4
R 277 0_6 1394TPAP0

1394TPAP0 33
R 276 0_6 1394TP AN0
1394TP AN0 33
R 275 0_6 1394TPBP0
1394TPBP0 33
SDA R 274 0_6 1394TP BN0
1394TP BN0 33
S CL
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
B
R 291 R290 B
56. 2_4 56. 2_4

R517 C 571
15, 22,23 CB E 0#
R 512 R 502 R 494
15, 16, 18, 21, 26, 27,28,30,33 P LTRST#
. 1U-10V_4
4. 7K_4 4. 7K_4 220_4 220_4
C386
R 307
+3V 270P -25V_4
56. 2_4
C 383
. 1U-10V _4
+3V
R297 R 296
P LLV DD
2. 7K_4 2. 7K _4
U 23 L58
1 8 B LM18P G181S N1D_6
A0 VCC C 558
2 7
A1 NC
10U/10V_8
3 6 C 565 C574
A3 SCL 1000p/ 50V_4 1000p/ 50V_4
4 5
GND SDA
24LC02BT A V DD
L59
B LM18P G181S N1D_6
C 557 C 553 C 394 C 561 C 552 C 555 C 550 C551
10U/10V_8
C 595
A 1000p/ 50V_4 1000p/ 50V_4 . 01U_4 . 01U_4 . 1U-10V _4 . 1U-10V_4 . 1U-10V_4 A
1000p/ 50V_4
C 556 C628 C 605 C554 C 578 C626 C623

10U/10V_8
C 603 C 625 C597 C 627 C624

. 01U_4 . 01U_4 . 01U_4 . 01U_4 . 01U_4 . 1U-10V_4 . 1U-10V _4 . 1U-10V_4 . 1U-10V _4 270P -25V_4 270P -25V_4 PROJECT : ZU1
1394(TSB43AB23) 1A

5 4 3 2 1
1 2 3 4
SATA HDD C N27
1
GND1
2 SATA_TXP0 14
A1A:(10/2)change footprint to SATA-C166D9-100B-22P-R RXP
3 SATA_TXN0 14
A1A:(10/9)change footprint to SATA-C16669-100A-22P-R RXN
4
GND2
5 S ATA_RXN0 14
TXN 6 SATA_RXP0 14
1 2
TXP
7 2 1
GND3
RST
GND
R 249 0_8 HD D _ VDD 8 +3.3VSATA R 225 *0_8
A
+ 5V 3.3V +3V A
9
3.3V
10
3.3V 11
C 381 GND
12
C 368 + C 370 C 374 GND
13 20
GND 14 HD D _ VDD
. 1 U_4 1 5 0U_7343 . 1 U_4 . 1 U_4 5V
15
5V
16 SATA HDD DOESN'T USE 3V PWR
5V
17
GND
18
RSVD
19
GND
GND
20
12V +3.3VSATA
X
21
12V
22 44 43
12V 43 44
C 351 C 350 C354
* 4 .7U_8 * 4 .7U_8 * . 1U_4

AOP_C16669-12204-L
PATA ODD
B B
+3V + 5V
Q24
2
D TC144EU R 236
10K_4
R 252 *0_4
16 R S T_HDD#
R 253 33_4 1 3 -IDERST
1 5,16,18,21,25,27,28,30,33 PLTRST#
A1A: change from 0 to 33ohm
+5V
C 325 C329 C 331 C324
. 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4

A1A:(9/29) change footpint: CDR-C124A9-100C-50P
C ODD Connector C
C N2 6
1 2
-IDERST 3 4 P DD8
P DD7 5 6 P DD9 P DD0 P D D[0..15] 14
P DD6 7 8 P DD10 P DD1
P DD5 9 10 P DD11 P DD2
P DD4 11 12 P DD12 P DD3
P DD3 13 14 P DD13 P DD4
P DD2 15 16 P DD14 P DD5
P DD1 17 18 P DD15 P DD6
P DD0 19 20 P DDREQ P DD7
21 22 P D IOR# P DD8
P DIOW # 23 24 P DD9
P IO R DY 25 26 P D DACK# P DD10
IR Q14 27 28 P DD11
P DA1 29 30 - P D IAG P DD12
P DA0 31 32 P DA2 P DD13
P DCS1# 33 34 P DCS3# P DD14
O DDLED# 35 36 P DD15
29 ID ELED# 37 38 P D IOR#
39 40 P D IOR# 14
+ 5V + 5V P DIOW #
41 42 P D IOW # 14
P D DACK#
43 44 P D DACK# 14
A1A:(10/30) remove D23, already add in page29 IR Q14
45 46 IRQ14 14
R CSEL P IO R DY
47 48 P IO R D Y 14
C 344 P DDREQ
51
52
49 50 P DDREQ 14
C 327 + C 326
P D A[2:0] 14
51
52
R 203 . 1 U_4 1 50U_7343 . 1 U_4 P DA0

P DA1
470_4 P DA2
D D
NC FOR SLAVE
P DCS1#
P DCS1# 14
AOP_C124A9-150A1-L P DCS3#
P DCS3# 14
A1A:(10/30) add 150uF ,0.1uF for +5V
- P D IAG R 217 *10K_4 +5V PROJECT : ZU1

R 223 4.7K_4 P IO R DY
+3V
A1A:(10/30) no stuff <check list & FAE>
+3V
R 218 8.2K_4 IR Q14
Must be PU even when IDE device is not use
SATA-HDD & PATA-ODD 1A

1 2 3 4

1 2 3 4 5 6 7 8
MINI-Card
BLUETOOTH MODULE CONNECTOR A1A: (9/25) change CONN (follow ZH3)
C N5
B T _ P O W ER
1
Q 10 2
15 U S B P4 + 3
AO 3 4 1 3
15 U S B P4 - 4
B T _ L ED
29 B T _ L ED 5
+ 3 V SU S 1 3 B T _ P O W ER _ R L15 B K2 1 2 5 H S3 3 0 _ 8 B T _ P O W ER AC S_ 8 8 2 6 6 - 0 5 0 0 1 -06
A C 105 1 0U_8 A
+
2
C 101 1 0 0 0 P_ 4
C 102
A1A:(10/25) SI suggest to remove 22pF*2 . 01U_4
B T _ P O W ER O N # 28
A1A: (9/20) Change from +3V to +3V_WL_VDD

A1A: (10/23)change +3V to +3VSUS USB CONN + 5 V_ S5
U 16
2 8 USBPWR1
IN1 OUT3
3 7
IN2 OUT2
6
+ 3 VSU S + 1 .5 V OUT1
4
L28 28 U S B O N# EN#
1
+ 3 V _ W L _ VD D 9 GND 5 R 435 * 6 .3 4 K_ 4
GND-C OC#
F B J 3 2 1 6 H S8 0 0 _ 1 2 0 6 + 5 V_ S5 TP S 2 061DGNR
C 3 98 C 413 C 414 C 419 + C 402 C 403
1 0 U /1 0 V/X5 R _ 8 . 1U_4 . 1U_4 . 1U_4
1 0U_8 . 1U_4
C 3 05
. 1 U_4 USBPWR1
B B
POWER DECOUPLING C 279
C 2 89
100U_3528 1 0 0 0 P_ 4
C N 11
+ 1 .5 V + 3 V _ W L _ VD D + 3 V _ W L _ VD D 1 5
15 U S B P0 - 2 6
15 U S B P0 + 3 7
A1A:(10/30)change form +3VSUS to +3V_WL_VDD
4 8
A1A: 9/ 4 Reser ved f or debug only 0_4 R 3 3 6 + 1 .5 V_ MIN I- C a r d
S U Y _ 0 2 0 1 3 3 MB0 0 4 S5 5 7 ZL
U 15
+ C 424 C 422 C M1 2 9 3 - 0 4 SO
P C I R ST# R 3 4 9 *0_4 C L _ D A TA1 _ C N 1 6 + 5 V_ S5 A1A: (9/24)change USB CONN (follow ZC3)
1 5 ,2 2 ,2 3 P C I R ST# CH1 CH4
P C L K_ SIO R 3 5 0 *0_4 C L _ C L K1 _ C N 1 0U_8 . 1U_4
2 ,3 0 P C I _ C L K_ SIO
2 5
VN VP
3 4
CH2 CH3
CN28 A1A:(10/25) SI suggest to remove 22pF*2
51 52
R 353 0 _ 4C L _ R ST# 0 _ C N Reserved +3.3V
16 C L _ R ST# 1 49 50
R 348 0 _ 4C L _ D A TA1 _ C N 47 Reserved GND 48
16 C L _ D ATA1 Reserved +1.5V
R 356 0 _ 4C L _ C L K1 _ C N 45 46 A1A: (9/26) Remove (CN20/Pin46)BT_LED
16 C L _ C L K1 Reserved LED_WPAN#
R 354 0 _ 4K E D R O N _ G N D _ 4 3 43 44
R 351 *0_6 K E D R O N _ V CC Reserved LED_WLAN# W I R E L E S S_ L ED # 29
41 42
A1A(10/30): + 3 V _ W L _ VD D 39
Reserved LED_WWAN#
40 CN21 + 5 V_ S5
Add (CN20/Pin39,41) to R 355 0 _ 4K E D R O N _ G N D _ 3 7 Reserved GND U S B O N#
37 38 1 2
+3V_WL_VDD (follow ZO1) Reserved USB_D+ A1A: (9/20) Remove USB ciucuit 1 2 + 5 V_ S5 C 45
35 36 15 U S BP1 - 3 4
GND USB_D- 3 4
15 P C IE_ TXP4 33 34 15 U S B P1 + 5 6
C PETp0 GND M I N I _ D AT_ SMB 5 6 C
15 P C I E_ TXN 4 31 32 7 8
PETn0 SMB_DATA M I N I _ C L K_ SMB 7 8
29 30 15 U S BP2 - 9 10
GND SMB_CLK 9 10 . 1U_4
27 28 15 U S B P2 + 11 12
P C I E_ R XP4 GND +1.5V 11 12
15 P C I E_ R XP4 25 26
P C I E _ R XN 4 PERp0 GND ( B- B) AC S 8 8 0 2 8 - 1 2 1 0M
15 P C I E_ R XN 4 23 24
A1A:(10/20) Remove 0.1uF *2pcs PERn0 +3.3Vaux
21 22 P L TR ST# 1 5 ,1 6 ,1 8 ,2 1 ,2 5 ,2 6 ,2 8 ,3 0,33
GND PERST# R F_ E N _ R R R 343 0_4 A1A: (10/13) change CONN (follow ZH2 Audio DB)
28 u R _ S O U T_ C R 19 20 R F_ EN 28
Reserved Reserved
28 uR_SWD 17 18
Reserved GND
15 16 0_4 R 3 37
GND Reserved L F R A ME# 1 4 ,2 8 ,3 0
13 14 0_4 R 3 45
+ 3 V SU S 2 C L K _ P C IE_ MIN I1 REFCLK+ Reserved L A D3 1 4 ,2 8 ,3 0
11 12 0_4 R 3 44
2 C L K _ P C IE_ MIN I1 # REFCLK- Reserved L A D2 1 4 ,2 8 ,3 0
9 10 0_4 R 3 38
GND Reserved L A D1 1 4 ,2 8 ,3 0
7 8 0_4 R 3 39
CLKREQ# Reserved L A D0 1 4 ,2 8 ,3 0
5 6
Reserved +1.5V
3
Reserved GND
4 A1A: 9/ 4 Reser ved f or debug only
Q 25 1 2
2
R 3 57 WAKE# +3.3V
D T C 1 4 4 EU 4 .7 K_ 4 AC S_ 8 8 9 1 1 - 5 2 0 4
3 1 P C I E _ W AKE# _ MIN I- C a r d
1 6 ,1 8 P C I E _ W AKE#
+ 3V
Q 14
R H U 0 02N06 R48
2
1 0 K_ 4
D 3 1 M I N I _ D AT_ SMB D
2 ,1 3 ,1 6 ,1 8 ,3 3 P D A T _ SMB
+ 3V
Q 15
R H U 0 02N06 R58 PROJECT : ZU1
2
1 0 K_ 4
2 ,1 3 ,1 6 ,1 8 ,3 3 P C L K _ SMB 3 1 M I N I _ C L K_ SMB Quanta Computer Inc.
Size D o c u m e n t N u mb e r Rev
Mini card/USB/Bluetooth 1A
D a te : T h u r s d a y , N o v e mb e r 0 2 , 2 0 0 6 Sh e e t 27 of 39
1 2 3 4 5 6 7 8

5 4 3 2 1
+ 3 VPCU
A1A: (9/25) change VBAT from +3VPCU to +A3VPCU
+ A3 VPCU + 3V
1/13 Comfirm by vendor mail:
VDD must power up after VCC/AVCC SM BUS PU + 3 VPCU
M BCLK R 98 4.7K_4
L52 B L M18AG601SN1_6 + A 3VPCU M BDATA R 99 4.7K_4
A1A:(9/16)Change from WPC8769 to WPC8763 2 N D_MBCLK R 102 4.7K_4
C 474 C 228 C 236 1/13 Comfirm by vendor mail: 2 ND _MBDATA R 100 4.7K_4
C 140 C 476
. 1 U_4 . 1 U_4 1 0 U_8
VBAT for keep PLL power let power up can quick. +3V
. 1 U_4 1 0U_8 If no VBAT will switch to VCCpower.
If PLL no power will cause boot time delay. E C_GPIO42 R 139 4.7K_4
CRT_SENSE# R 398 4.7K_4
8769AGND 08/10 FAE:
115
102
I/O ADDRESS SETTING
C 235 C 139 C175 C 486 C 227 C 141
19
46
76
88
80
0.1UF
4
1 0 U_8 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 U1 4 MTEMP C 149
D . 1 U_4 D
AVCC
VDD
VCC1
VCC2
VCC3
VCC4
VCC5
VBAT
I/O Address
A1A: (9/25) place the above capacitors as close to the pins as possible
A1A: (9/26) Add it. Capacitors as close to EC as possible BADDR1-0 Index Data
L F RAME# 3 97
1 4,27,30 L F RAME# LFRAME AD0/GPI90 MTEMP 39
L A D0 126 98 A1A: (9/26) Remove TEMP_ABAT 00 XOR TREE TEST MODE
1 4,27,30 L AD0 LAD0 AD1/GPI91
L A D1 127 99
1 4,27,30 L AD1 LAD1 AD2/GPI92
L A D2 128 A/D 100 A1A: (9/24) remove ME_EC_ALERT# 01 CORE DEFINED
1 4,27,30 L AD2 LAD2 AD3/GPI93
L A D3 1 108
1 4,27,30 L AD3 LAD3 AD4/GPIO05
PCLK_591 2 96 10 2Eh 2Fh
2 PCLK_591 LCLK AD5/GPIO04
PCLK_591 8 11 164Eh 164Fh
1 6,30 C L K RUN# CLKRUN/GPIO11/HGPIO02 101 CC-SET 39
DA0/GPI94
14 GATEA20 121
GA20 DA1/GPI95
105 C P UF AN# 3 SHBM=0: Enable shared memory with host BIOS
R 142
D/A DA2/GPI96
106
14 R C IN# 122 107
KBRST DA3/GPI97 C C D_POW ERON# R 408 10K_4
* 22_4 BADDR0
D 14 BAS316 S C I#_uR 29 LPC A1A:(9/29)SWAP GPIO3 & GPIO6 (follow EC team)
16 S C I# ECSCI
64 BADDR1 S O UT_CR_DEBUG R 407 *10K_4
GPIO01 NB SW ON# 2 9,33
29 C APSLED# 6 95 A C IN 39
LDRQ/GPIO24/HGPIO01 GPIO03 R F _ EN R 399 10K_4
GPIO06/HGPIO06
93 L ID591# 1 6,20,29 SHBM
C 240 A1A: (9/26) Remove LAN_WOL_EN 124 94
LPCPD/GPIO10/HGPIO00 GPIO07/HGPIP07 S USB# 16
* 10P_4 119 E C_FPBACK# 20
PLTRST# GPIO23
1 5,16,18,21,25,26,27,30,33 PLTRST# 7
LREST GPIO30
109 S USLED# 29 1/13 Comfirm by vendor mail :
120 PW RLED# 29 Disabled ('1') if using FWH device on LPC.
123 GPIO31 65
29 NUML ED# PWUREQ GPIO32 BATLED0# 29 Enabled ('0') if using SPI flash for both system BIOS and EC firmware
66 BATLED1# 29
S E RIRQ GPIO33
1 6,22,23,30 S ERIRQ 125 15 VR O N 35
SERIRQ GPIO36
16 M AINO N 3 6,37,38
GPIO40 E C_GPIO42 A1A: (9/26) Remove RBAYINS#
08/10 FAE: SMI DOESN'T NEED DIODE 16 K BSMI# 9
SMI GPIO42/TCK
17
ACER ID
A1A:(9/29) change from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
GPIO GPIO43/TMS
20 AMP_MUTE# 32
+ 3VPCU
21 PR_STS 33
C MX0 54 GPIO44/TDI 22 U7 C
29 MX0 KBSIN0 GPIO45 S US ON 3 7,38
MX1 55 23 2 N D_MBCLK 6 1
29 MX1 KBSIN1 GPIO46/TRST SCL A0
MX2 56 24 A1A: (9/26) Remove M/A# 2 ND _MBDATA 5 2
29 MX2 KBSIN2 GPO47/JEN0 SDA A1
MX3 57 25 3
29 MX3 KBSIN3 GPIO50/TDO D /C# 39 A2
MX4 58 26
29 MX4 KBSIN4 GPIO51 S 5_ON 3 4,38
MX5 59 27 7 8
29 MX5 KBSIN5 GPIO52/RDY WP VCC
MX6 60 28 A1A: (9/26) Remove BL/C# HW PG 4
29 MX6 KBSIN6 GPIO53 GND
61 91 D NB SW ON#_uR D 12 BAS316
29 MX7 KBSIN7 GPIO81 D NBSW ON# 16
110 24LC08 C 69
GPO82/HGPIO00/TRIS BT_POW ERON# 27
53 112 C C D_POW ERON# . 1 U_4
29 MY 0 KBSOUT0/JENK GPO84/HGPIO01/BADDR0 C C D_POW ERON 20
29 MY 1 52 T16
KBSOUT1/TCK CCD_POW ERON ACITVE LO => HI
29 MY 2 51 08/10 FAE: ADD TP FOR DEBUG
KBSOUT2/TMS
29 MY 3 50 31
KBSOUT3/TDI TA1/GPIO56
SPI FLASH
29 MY 4 49 KB 117 HIGH_ LOAD 33
KBSOUT4 TA2/GPIO20
29 MY 5 48 63 F ANS IG 3
KBSOUT5/TDO TB1/GPIO14/HGPIO4
29 MY 6 47
KBSOUT6/RDY
29 MY 7 43
KBSOUT7 TIMER A_PWM0
32 CONTRAST 20 + 3 VPCU
29 MY 8 42 118 US BON# 27
KBSOUT8 A_PWM1/GPIO21 + 3VPCU
29 MY 9 41 62 S YS _ C HARGE 33
KBSOUT9 B_PWM0/GPIO13 U2 6
29 MY1 0 40
KBSOUT10 S P I _SDI_uR
29 MY1 1 39 2 8
KBSOUT11 CRT_SENSE# R 45 SO VDD
29 MY1 2 38 84 CRT_SENSE# 1 5,19,33
KBSOUT12/GPIO64 SPI_DI/GPIO77 R F _ EN S PI_SDO_uR
F OLLOW INTEL ME-EC INTERFACE SPECIFICATION,
29 MY1 3 37
KBSOUT13/GPIO63 SPI SPI_DO/GPO76/SHBM
83 R F _ EN 27
10K_4
5
SI HOLD
7
29 MY1 4 36 82 CELL-SET 39
2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS. KBSOUT14/GPIO62 SPI_SCK/GPIO75 S PI_SCK_uR C 454
29 MY1 5 35 6 3
MY1 6 KBSOUT15/GPIO61/XOR_OUT SCK WP
29 MY1 6 34 . 1 U_4
+5V KBSOUT16/GPIO60 RSMRST#_uR 0 _6 R 104 S PI_CS0#_uR
33 75 R SMRST# 16 1 4
A1A: (9/26) Remove MY17 KBSOUT17/GPIO57/HGPIO03 IRRX1/GPIO72 CE VSS
73 S USC# 16
IRRX2_IRSL0/GPIO70 PW ROK_EC_uR R103 0_4 W 25X80VSSIG
74 PW ROK_EC 16
M BCLK IRTX/GPIO71
39 MBCLK 70 IR 113
8
6
4
2
M BDATA SCL1 SIN_CR/CIRRX/GPIO87 A1A: (9/26) Remove LAN_ON

39 MBDATA 69
SDA1 GPIO34/CIRRX2
14 1/13 Comfirm by vendor mail :
RP23 2 N D_MBCLK 67 SMB 114 A1A: (9/26) Remove EC_ME_ALERT
B 4.7KX4
3 2 ND_MBCLK
2 ND _MBDATA SCL2 CIRTX/GPIO16/HGPIO04 S O UT_CR_DEBUG R406 0_4
If the Southbridge enables 'Long Wait Abort' by default, the B
3 2 ND _MBDATA 68 111 u R_SOUT_CR 27
SDA2 SOUT_CR/GPO83/BADDR1 flash device should be 50MHz (or faster)
7
5
3
1
BUTTON ON KEYBOARD MATRIX

72 86 S P I _SDI_uR
29 TBCLK PSCLK1 F_SDI
71 87 S PI_SDO_uR
29 TBDATA PSDAT1 F_SDO
10 S PI_CS0#_uR
33 PR_KB_CLK PSCLK2/GPIO26 FIU F_CS0
90
S PI_SCK_uR MX0
33 P R_KB_DATA 11
PSDAT2/GPIO27 PS/2 F_SCK
92
MX1
MX0 29
33 PR_MS_CLK 12 MX1 29
13 PSCLK3/GPIO25 81 S W D_DEBUG R400 0_4 MX2
33 P R_MS_DATA PSDAT3/GPIO12 SWD/GPIO66 u R_SW D 27 MX2 29
MX3
MX3 29
8768_32KX1 77 30 uR_TP_CLKOUT T35 MX4
32KX1/32KCLKIN CLKOUT/GPIO55 W IRELESS_SW # 29
MX5
BLUETOOTH_SW# 29
85 VC C_POR# R 97 4 .7K_4 + 3 VPCU
VCC_POR MY1 6
VCORF
MY1 6 29
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R 101 2 0M_6 8768_32KX2 79 104 VR EF_uR R 403 0_4 + A 3VPCU

32KX2 VREF
0~AVCC power for DA pin
R 96 W PC8763LDG
power reference
5
18
45
78
89
116
103
44
33K/F_6
V CORF _uR
1
2
08/10 FAE: 08/14 FAE:

A1A: (9/25)
FAE: PUT Y6 with EC in the same side Y3 ADD ONE GAD PAD UNDER X'TAL, Please connect VREF(uRider pin104) to
3 2 . 768KHZ AND KEEP CLEANCE. +A3VPCU instead of +3VPCU.
C 130 C 131
4
3
5.6P_4 5.6P_4 C181

A1A:(9/27)change C554,C555 from 6.8p to 5.6p
+3V L 17 1 U_6
DEBUG PORTS
1/13 Comfirm by vendor mail : HZ0603B601R-00_6
INTERNAL KEYBOARD STRIP SET

A1A(10/5):Change LPC debug CONN to DFFC10FR103
Connect to AGND
8769AGND R 140
Re s e rved for LPC debug card
A + 3 VPCU A
10K_4 EC Debug Port +3V C N6
A1A: (9/26) Add HWPG_CPUIO 8769AGND + 3V 10 MY 0 R 110 10K_4
L A D0 9 10
D 18 BAS316 HW PG L A D1 9
38 HW P G_CPUIO 08/10 FAE: 1
1
8
8
S O UT_CR_DEBUG 2 L A D2 7
D 16 BAS316
L83 CAN CHANGE FROM BEAD TO S W D_DEBUG 2 L A D3 7
3 6
34 HW P G_3/5VPCU SHORT. 4
3
4 2 P CLK_DEBUG 5
6
5
PROJECT : ZU1
36 HW P G_1.05V
D 17 BAS316 BUT, PLEASE PUT AGND & 32K CAP & L F RAME# 4
C N1 0 PLTRST# 3 4
37 HW PG_1.8V
D 15 BAS316
AVCC CAP AT ONE POINT.
*ACS_88231-04001 S E RIRQ 2
3
2
1
ZS1 STILL USE BEAD FOR SAFE. 1 Size D oc um ent Num ber R ev
BOT CONTACT *ACS_88502-1001
EC (PC8763LDG)/ FLASH 1A

5 4 3 2 1

5 4 3 2 1
INT K/B C N7 TOUCH PAD

MY1 5
28 MY1 5 1 + 3 VPCU
MY1 4 MY 0
28 MY1 4
MY1 3 2 MY 1 20 MIL
28 MY1 3 3 L23
MY1 2 MY 2
28 MY1 2 4
MY1 1 MY 3 +5V_TP C 269 . 1 U-10V_4
28 MY1 1 5 +5V
MY1 0 MY 4 R P14
28 MY1 0
MY 9 6 MY 5 MX4
uR REQUEST BK2125HS330_8
28 MY 9 10 1
MY 8 7 MY 6 MX1 9 2 MX7 MY DOES NOT NEED PU.
28 MY 8 8
MY 7 MY 7 MX2 8 3 MX6 MY CAN NOT USE EMI BYPASS CAP, DUE TO FLASH.
28 MY 7 9
MY 6 MY 8 MX3 7 4 MX5
28 MY 6 10
MY 5 MY 9 MX0 6 5 R 167 R 162
28 MY 5 11
MY 4 MY1 0
D 28 MY 4 12 D
MY 3 MY1 1 10KX8 10K_4 10K_4
28 MY 3 13
MX7 MY1 2 CONNECT TO TP/B
28 MX7 14
MX6 MY1 3
28 MX6 15
MY 2 MY1 4 C N8
28 MY 2 16
MX5 MY1 5
28 MX5 17 1
MX4 MX0 L22 L ZA10-2ACB104MT_6 TP_DATA BOT CONTACT
28 MX4 18 28 TBDATA 2
MX3 MX1 L20 TP_CLK
28 MX3 19 28 TBCLK 3 6
MX2 MX2 L ZA10-2ACB104MT_6
28 MX2 20 4 5
MY 1 MX3
28 MY 1 21
MY 0 MX4 C 267 C 261
28 MY 0 22
MX1 MX5 A1A: (9/26) Refer to ZH3, change K/B matrix ACS_88502-0401
28 MX1 23
MX0 MX6 * . 1U_4 * . 1U_4
28 MX0 24 MX7
25
ACS_88502-250N
BOT CONTACT
Finger Printer
LED A1A:(9/27) Power need be confirm C N9
+ 3V +3V + 3V +3V
+ 3VSUS 4
+ 3VPCU
R 170 0 _6 BUSBP1- 3 6
15 USBP6- 2
15 USBP6+ R 171 0 _6 BUSBP1+
1 5
1 LED_G/Y_LTST-S326KGJSKT S USLED# 28
ACS_88266-04001-06
R 367 3 30_4 LED2 3 R 36 R 37 R 43 R 46
2 PW RLED# 28 10K_4
10K_4 10K_4 330_4
ID E_LED
A1A:(10/30) remove22pF*2
3
C C
D6 BAS316
26 ID E LED#
1LED_G/Y_LTST-S326KGJSKT BATLED1# 28
R 366 3 30_4 LED3 3 D5 BAS316
2
14 SATA_LED# Q11
2 BATLED0# 28
2 N7002E
1
LED Board
+3V + 3 VPCU
+3V +3V + 3 VPCU
C N1
R 41 MX3 1
28 MX3 2
R 40 R1 MY1 6
330_4 NB SW ON# 3
NUML ED 330_4 *330_4 P W RLED# 4
5
3
C APSLED E MA IL_LED NUML ED

3
3
C APSLED 6 A1A(10/5):Change Pin define (Base on Acer ID)
ID E_LED 7
Q8 S USLED# 8
28 NUML ED#
2 BOT CONTACT
2 Q7 2 Q27 9
2 N7002E 28 C APSLED# 16 E MAIL_LED# 10
2 N7002E * 2N7002E 11
12
1
1
ACS_88502-1001
A1A:(10/30) no stuff (ZU1 no support EMAIL LED)

B B
A1A:(9/27) Add LED Board CONN (10pin)
A1A:(10/26) Add SUSLED#
Function Board
SW1
28,33 NB SW ON# NB SW ON# 1 3
2 4
+ 3 VPCU A1A: (9/24) change SW CONN (follow ZC3)

C N4
MX0 1
28 MX0 2
MX1 + 3VPCU
28 MX1 3
MX2
28 MX2 4
MY1 6
28 M Y1 6 5
MR # L ED1
16,20,28 MR # 6
W IRELESS_SW # R141 3 30_4 E CPW RLED 2 1 P W RLED#
28 W IRELESS_SW # 7
BLUETOOTH_SW#
28 BLUETOOTH_SW# 8
W IRELESS_LED# A1A(10/5):Change Pin define (Base on Acer ID) LED_G_LTST-C190KGKT
27 W IRELESS_LED# 9
BT_LED
27 BT_LED 10
+3V 11
BOT CONTACT
12 A1A: (10/30) Reserved LED for debug use
13
A 14 A
Keyboard Matrix Button
ACS_88502-1401
MX0/MY16 acer EAP Buttton
A1A:(9/27) Add Function Board CONN (14pin) MX1/MY16 acer EMAIL Buttton
A1A:(10/30) add +3V for Daughter Board use MX2/MY16 acer WWW Buttton PROJECT : ZU1
MX3/MY16 acer EPM Buttton
MX4/MY16 WIRELESS Button
MX5/MY16 BLUETOOTH Button SWITCH,LED,KB,Finger,TP 1A

5 4 3 2 1

5 4 3 2 1
NS SIO PC87383
U9
P C I_CLK_SIO 42 52 P D0
14,27,28 L AD0 LAD0 PD0 PPT_PD0 33
46 50 P D1
S IO_14M
14,27,28
14,27,28
L AD1
L AD2 51
LAD1
LAD2
NS PC87383 PD1
PD2
43 P D2
PPT_PD1
PPT_PD2
33
33
53 6 P D3
14,27,28 L AD3 LAD3 PD3 PPT_PD3 33
39 P D4
PD4 PPT_PD4 33
33 37 P D5
2 ,27 P C I_CLK_SIO LCLK PD5 PPT_PD5 33
R 39 R 49 34 P D6
PD6 PPT_PD6 33
* 22_4 *22_4 22 30 P D7
14 L DRQ#0 LDRQ/XOR_OUT PD7/GPIO23 PPT_PD7 33
38 28 A CK#
1 4,27,28 L F RAME# LFRAME ACK/GPIO24 PPT_ACK# 33
D 35 57 AF D# D
1 5,16,18,21,25,26,27,28,33 PLTRST# LRESET AFD_DSTRB PPT_AFD# 33
C 55 C 84 A1A:(9/20) PPT PU 4.7k circuit exist in Docking.
* 10P_4 *10P_4 36 26 B US Y remove it.
1 6,22,23,28 S E RIRQ SERIRQ BUSY_WAIT P P T_BUSY 33
S IO_PD# 29 54 E RROR#
LPCPD/GPIO21 ERR PPT_ERR# 33
27 56 INIT #
16,28 C L K R UN# CLKRUN/GPIO22 INIT P P T_INIT# 33
58 25 PE
2 S IO_14M CLKIN PE PPT_PE 33
15 24 SLCT
GPIO00 SLCT PPT_SLCT 33
16
19 GPIO01 55 S L I N#
GPIO02 SLIN_ASTRB P PT_SLIN# 33
20
+3V GPIO03 STRB#
21 14 PPT_STB# 33
40 GPIO04 STB_WRITE
GPIO05
7
R 44 GPIO06 IR RX R 77 10K_4
41 8 +3V
10K_4 GPIO07 IRRX1
23
GPIO20 IR MODE
10
IRRX2_IRSL0/GPIO17 MCTS1#
1 PR_CTS 33
* BAS316 D7 S IO_PD# NC IRTXOUT MD CD1#
16 L PC_PD# 2 9 P R _DCD# 33
17 NC IRTX M DSR1#
HOLE 18
NC
NC
M DTR1#
P R _DSR#
P R_DTR#
33
33
47 3 MCTS1# MR I1 P R _ RI 33
48 NC CTS1/GPIO11 MRTS1#
NC PR_RTS# 33
49 59 MD CD1# M RXD1
NC DCD1/GPIO16 P R _ S IN 33
HOLE28 HOLE26 HOLE29 HOLE27 + 3V 64 MTXD1
NC P R_SOUT 33
*h-c236d236 *h-c236d236 *h-c236d236 *h-c236d236 60 M DSR1#
DSR1/GPIO15
45
VDD OPEN : 164Eh~164Fh
+ C 64 C 119 C 56 C 76
32
VDD DTR1_BOUT1/BADDR
4 M DTR1# R 76 *10K_4
LOW : 2Eh~2Fh
11
C 1 0 U_8 VDD 5 MR I1 C
RI1/GPIO10
. 1 U_4 . 1 U_4 . 1 U_4
OPEN : normal pin operation
1
44
31 VSS RTS1/GPIO13/TRIS
62 MRTS1# R 55 *10K_4
LOW : float device pin
VSS M RXD1
12 61
VSS SIN1/GPIO14
HOLE35 HOLE32 HOLE33 HOLE31
OPEN : normal Device operation
*h-c236d236 *h-c236d236 *h-c236d236 *h-c236d236 C 120 . 1 U_4 13
VCORF SOUT1/GPIO12/TEST
63 MTXD1 R 59 *10K_4
LOW : XOR pin tree
PC87383
AJ 8 73830H22
IC(64P) PC87383-VS NOPB(TQFP)
1
A1A:(10/19) EMI suggest :Add the VIN power shape

bypass cap 0.1uF x 10pcs
HOLE37 HOLE38 HOLE34 HOLE36
*h-c236d236 *h-c236d236 *h-c236d236 *h-c236d236
EMI Cap Add the +3VPCU power traces bypass cap 0.1uF x 3pcs
VIN V IN VIN VIN VIN
FIR
1
C 333 C 33 C 35 C 116 C 83
+3V
U4 0
T = 20mil
HOLE22 HOLE14 6
*h-c236d138p2 *h-c236d138p2 IRTXOUT VCC
3 7
IR RX TXD MODE C 638 C 640 C 639
4
IR MODE 5 RXD 2 1 0 U-10V_8
0 . 1U/X7R-50V_6 0 .1U/X7R-50V_6 0 .1U/X7R-50V_6 0 .1U/X7R-50V_6 0 .1U/X7R-50V_6 SD LED_C . 1 U-10V_4 1 0 U-10V_8
8 1
B GND LED_A B
VIN V IN VIN VIN VIN + 3 VPCU + 3 VPCU + 3VPCU VIS HAY_ TFDU6102_8P
1
+5V_FIR
+3V
C 443 C 103 C 32 T = 20mil
HOLE25 HOLE24 C 347 C 349 C 40 C 39 C 447
*h-c217d59p2 *h-c217d59p2 . 1 U-10V_4 . 1 U-10V_4 . 1 U-10V_4 R557 5.6_1206
R551 5.6_1206
C 641
1 0 U-10V_8
1
0 . 1U/X7R-50V_6 0 .1U/X7R-50V_6 0 .1U/X7R-50V_6 0 .1U/X7R-50V_6 0 .1U/X7R-50V_6
HOLE42 HOLE7 HOLE13

*h-c94d94n *h-o110x94d110x94n *h-o217x394d217x394n ESDPad
Non - PTH Hole P AD19 P AD18 P AD17 P AD15 P AD5 P AD14 P AD11 P AD13 P AD3 P AD16 P AD10 P AD2 P AD7 P AD1 P AD4 P AD8 P AD12 P AD6 P AD9
* E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD * E MIPAD
1
HOLE16 HOLE19 HOLE30 HOLE18 HOLE15 HOLE21 HOLE11

1
1
*h-c217d122p2*h-c217d122p2*h-c217d122p2*h-c217d122p2*h-c217d122p2*h-c217d122p2*h-c217d122p2
EMIPAD157X79 AD O GND EMIPAD142X91

1
A A
HOLE3 HOLE9 HOLE17 HOLE23 HOLE2 HOLE4 HOLE10 HOLE1 HO LE5 HOLE12 HOLE39 HOLE43 HOLE40 HOLE41 HOLE20 HOLE6 HOLE8
*h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c276d94p2 *h-c 276d94p2 *h-c 276d94p2 *h-c 276d94p2 *h-c 276d94p2 *h-c 276d94p2 *h-c 276d94p2 *h-c 276d94p2 *h-c 276d94p2
PROJECT : ZU1
1

SUPER-IO/FIR/HOLE 1A

5 4 3 2 1

5 4 3 2 1
CODEC(ALC268) LINE OUT Amplifier F RONT -L_2 R352 10K_6
A1A:(9/20) Refer to ZD1, C425 47P_4

change R580,R581 to 10k
+5V +5V_ADO U37
L61 T I321611U480_1206 R532

F RONT -L C614 F RONT -L_1 10K_6 4 5 HP L
INL - OUTL HP L 32
C567 C563 C620 C604 C608 C622 4.7U-6.3V_8 + 9
D
.1U-10V_4 10U-10V_8 .1U-10V_4 .1U-10V_4 .1U-10V_4 10U-10V_8 NC1 D
+3V_AVDD 3 11
MIC1-VREF O-R
SVDD NC2
MIC1-VREF O-R 32 15 12
R525 100K_4 PVDD NC3
+3V_AVDD 14
NC4
6 2
A D O GND SVSS SGND
MIC2-VREF O 32 + NV DD 10 13
NVDD PGND
MIC2-VREF O 32 MUT E# 1 2 17
D41 MTW355 TPAD
R482 0_6 MIC1-VREF O-L 1 2 1412MUTE# 1
+3V MIC1-VREF O-L 32 32 SECNT L SHDNR#
D42 *MT W355 16 A D O GND
R543 SHDNL#
+ 7
R483 *0_6 + AZA_VDD F RONT -R C621 F RONT -R_1 10K_6 OUTR
+1.5V 8 -
F RONT -L +5V_ADO INR
4.7U-6.3V_8
S ENSEB
F RONT -R C619 10U-25V_1206 G1412
A1A:(10/5) Refer to ZD1,
change R585,R586 to 10k
C560 C570
10U-10V_8 .1U-10V_4 A D O GND L62 C426 47P_4
36
35
34
33
32
31
30
29
28
27
26
25
+3V 1 2 +3V_AVDD
U34 BLM11A601S_6 F RONT -R_2 R358 10K_6 H PR
H PR 32
FRONT-R
NC
MIC1-VREFO-R
MIC2-VREFO
LINE1-VREFO
FRONT-L
GPIO1
MIC1-VREFO-L
AVSS1
AVDD1
VREF
Sense B
C575 C601 C616
*10U-10V_8 10U-10V_8 .1U-10V_4
37 24 L INE1-R
MONO-OUT LINE1-R L INE1-R 32
A D O GND A D O GND
+5V_ADO 38 23 LINE1-L C421 4.7U/6.3V_6
AVDD2 LINE1-L LINE1-L 32
A1A:(9/28) EMI suggest to change from AGND to GND
S U RR-L 39 22 M IC1-R + NV DD
32 S URR-L HP-OUT-L MIC1-R MIC1-R 32
C +3V + NV DD U35 C
A D O GND R521 20K_6 40 21 MIC1-L
JDREF MIC1-L MIC1-L 32
1 6
S UR R-R C602 .1U-10V_4 C606 VOUT C+
32 S UR R-R 41 20
HP-OUT-R CD-R 1412MUTE#
4.7U/6.3V_6 2 5
C594 .1U-10V_4 VIN /SHDN
A D O GND 42 19
AVSS2 CD-GND A D O GND 3 4 A1A:(9/21)
43
NC
Acer ALC268 CD-L
18 C590 .1U-10V_4
A D OGND
C- GND
refer to ZD1,
A1A:(10/18) reserve R506 to reduce ringing M IC2_EZ_R G5930
add it.
44 17 MIC2_EZ_R 32
NC MIC2-R A D OGND
Change C19 to 4.7u
45 16 MIC2_EZ_L
NC MIC2-L MIC2_EZ_L 32
D MIC-CLK R513 100_4D MIC-CLK_R 46 15 A1A:(11/1)FAE: Docking MIC share from System MIC
DMIC-CLK NC
E APD 47 14 R347 0_4 A U_ J D_MIC
DMIC-1/2/GPIO0
DMIC-3/4/GPIO3
32 E APD EAPD NC
S PDIF _OUT SPDIF _OUT _268 SDATA-OUT S E NSEA R507 20K_6
33 A U_ SPDIF 48
SPDIFO Sense A
13 MIC1_JD 32 SYS / EZ MIC
SDATA-IN
R504 0_4
PCBEEP
RESET#
BIT-CLK R501 10K_6 SYS Line-in
DVSS1
DVSS2
DVDD2
DVDD1
L INE IN_JD 32,33
SYNC
A U_ JD _ L INEIN 32,33 EZ Line-in
1
10
11
12
R492 5.1K_6 SYS/EZ Line-out
L INEOUT _JD#_OD 32,33
S E NSEB R346 *20K_6 EZ MIC (reserve) +3V R318 10K_4
+3V A U_ JD_MIC 33
+ AZA_VDD
U22
5
DMIC-12
A1A:(9/28) EMI suggest: 1 P CMSPK

B P CMSPK 22 B
Add Additional two more bridge resistor P CBEEP C399 1U-16V_6 BEEP_1 R317 10K_4 B EEP 4
between ADDGND and GND 2 P CSPK
A C Z_SPKR 16
3
SN74LVC1G86DCKR
R330 *0_6 C411 R334
R558 *0_6 100P-50V_6 1K_4
R530 *0_6
C564 C568 A1A:(10/30) change from +3V_S5 to +3V
10U-10V_8 .1U-10V_4 A1A: (9/20) Change DGND to AGND
A D O GND +1.5V +3V
A D OGND A1A:(9/20) Refer to ZD1, +3V_S5
Tied at one point only A1A: (9/26) Remove DMIC-34
MDC Add 0 ohm(Default:no stuff)
ACZ_SDIN268
BIT_CLK268
R491 R486
under the codec or C N14 *0_6 *0_6
A CZ_RST #_AUDIO 14,32
near the codec 1
GND RSV
2+1.5V_MDC
A CZ_SDOUT _MDC 3 4 C573
14 A CZ_SDOUT _MDC AC_SDO RSV
5 6 .1U-10V_4
A C Z _ S Y NC_AUDIO 14 GND 3.3V
A C Z _ S YNC_MDC 7 8
14 A C Z _ S YNC_MDC AC_SYNC GND
A1A: (9/20) Change serial R value from 22ohm to 33ohm R509 33_4 MD C _SDIN1 9 10
14 A C Z _ SDIN1 AC_SDI GND
R485 33_4 11 12
A C Z _SDIN0 14 14 ACZ_RST #_MDC AC_RST# AC_BCLK BIT _CLK_MDC 14
R484 33_4 ACS_88018-124L
B IT _CLK_AUDIO 14
+5V +5V_ADO A1A:(10/13) change R598 from 22ohm to 33 ohm A1A:(9/27)change P/N (follow ZC3)
C569 22P-50V_4
U24 C583 R508
R325 *0_6 4 3 *10P-50V_4 *22_4
VEN VOUT A C Z _SDOUT _AUDIO 14
5 C418
GND
ADJ
VIN C585
A R333 *10U-25V_1206 *10P-50V_4 A
*36K_4
2
*G961-18ADJT EU(SOT89-5)
D MIC-CLK D MIC-CLK 20
A D O GND DMIC-12
DMIC-12 20
R332
Vo=1.2*(R371+R372)/R371= 4.8V *12K_4 PROJECT : ZU1
+1.5V
+1.5V 4,9,17,27,38
A1A:(10/2) change from GND to ADOGND
Size Document Number

Quanta Computer Inc. Rev
A D O GND A U D IO (A LC268)/AMP/MDC 1A

5 4 3 2 1

5 4 3 2 1
SYSTEM LINE OUT

Speaker Amplifier + 5V _ADO
+ 3V _AVDD
C 634 1U-16V _6
C 591 C 631 A D OGND

10U-10V_8 . 1U-10V _4
S E CNTL
S E CNTL 31
A1A(10/5):Refer to ZD1, change R604~R607 to 10K A1A:(9/29)Add net name
15
14
23
A D OGND
6
8
U 36
C633 2. 2U/ 10V_8 S URR-L-1 R 546 10K_6 S URR-L-2 1 20 C N29
CT
LVDD
RVDD
NC
VDD3
SECNTL
D 31 S U RR-L LIN1 VOL D
1 7
C 596 2. 2U/ 10V_8 S U RR-R-1 R 520 10K_6 18 H PL R 363 75_4 HP L_1 L40 B K 1608LL121_6 HP L_S YS 2
31 S U R R-R RIN1 31 HPL
S U RR-R-2 6
+ 5V _ADO INS P KL+ R545 10K_6 2 13 HP R R 362 75_4 H P R_1 L39 B K 1608LL121_6 HP R_S Y S 3
LIN2 IN1/IN2 A D OGND 31 HPR
C 632 330P _4 17 4
RIN2 31, 33 L I NE OUT_JD#_OD
INS P K R+ R519 10K_6 19 INS P K R+ 8
C 592 330P _4 ROUT+ INS P K R- R 364 R365 C 434 C 433
12 5
ROUT- 24 INS P KL+ *1K _4 *1K _4 470P -50V_4 470P -50V_4 FOX_JA 6233L-L3T4-7F
R359 4. 7U/ 6. 3V_6 C 589 LOUT+ INS P K L-
A D OGND 16 7
100K_4 RBYPASS LOUT-
3
4. 7U/ 6. 3V_6 C 635 LBYPASS
THRMPAD
1441 MUTE A DOGND
GND/HS
GND/HS
GND/HS
GND/HS
1441 MUTE R 544 0_4 5
3
SHDN
Q26 R 526 0_4 11 A1A(10/9):Change (D44/Pin1) from +5V to +5V_ADO
SE/BTL A DOGND
MUTE# 2 G1441
25
22
21
10
9
A D OGND + 5V _ADO
2N7002
D 31
1
1
L I N EO U T_ J D # _ O D
A D OGND 3
A D OGND
+ 3V _A VDD 2
* DA 204U A D OGND
1 2 R 341
28 A MP _MUTE#
D 26 MTW 355 10K _4
1 2 MUTE#
31 EAPD MUTE# 31
D 28 MTW 355
14, 31 A C Z_RS T#_A UDIO 1 2 Docking LINE OUT/SPDIF

D 27 MTW 355
C C
SPEAKER
HP L_S YS R360 0_4 A U_LINE OUT_L
A U_LINE OUT_L 33
HP R_S Y S R361 0_4 A U_LINE OUT_R
C N16 A CS _85204-0400L A U _LINE OUT_R 33
INS P K L- L29 B K 1608LL121_6 INS P K L-N
INS P KL+ L30 B K 1608LL121_6 INS P K L+N 1 R549 *0_6
INS P K R- L31 B K 1608LL121_6 I NS P K R-N 25 R511 *0_6
INS P K R+ L32 B K 1608LL121_6 INS P K R+ N 36 C416 . 1U-10V_4
4 C409 1000P -50V_4
C613 C 612 C611 C 610 C437 . 1U-10V_4
A1A:(10/27) SWAP R&L channel for ME request C432 . 1U-10V_4
47P -50V_4 47P -50V_4 47P -50V_4 47P -50V_4 C427 . 1U-10V_4 A1A:(10/30) Add 0.1uF *4
C410 . 1U-10V_4
A DOGND
A D OGND
SYSTEM LINE IN SYSTEM MIC

R541 2. 2K _4 C N 31
31 MIC1-V RE FO-L
1 7
C629 2. 2U_6 MIC1_L1 L38 B K 1608LL121_6 MIC1_L 2
31 MIC1-L
6
R542 2. 2K _4 M IC1_R1 L35 B K 1608LL121_6 M IC1_R 3
31 MIC1-V RE FO-R
C N 30 31 M I C1_JD 4
1 7 C630 2. 2U_6 8
31 M IC1-R
C 417 4. 7U-6. 3V_8 LINE 1-L_1 L33 B K 1608LL121_6 L INE INL_S Y S 2 5
31 LINE 1-L
6 FOX_JA 6233L-P 3T4-7F
C 423 4. 7U-6. 3V_8 LINE 1-R_1 L34 B K 1608LL121_6 L I NE INR_S Y S 3
B 31 L INE 1-R B
4 C428 C 431
31, 33 L I N E IN_JD
8 470P -50V_4470P -50V_4
C 436 C435 5
470P -50V_4 470P -50V_4

FOX_JA 6233L-U3T4-7F A D OGND
Docking MIC A1A(10/9):Change (D50/Pin1) from +5V to +5V_ADO
A1A(10/9):Change (D48/Pin1) from +5V to +5V_ADO
A D OGND D 29
31 MIC2-V RE FO 2 1 MIC2-V R-R R342 *2. 2K_4
+ 5V _ADO *MTW 355
D 32
C 400 *2. 2U_6
31 M IC2_E Z_R A U_MIC_IN_R 33
1 C 586 *2. 2U_6
31 MIC2_E Z_L A U_MIC_IN_L 33
L IN EIN _ J D D 30
3 2 1 MIC2-V R-L R506 *2. 2K_4
31 MIC2-V RE FO
*MTW 355 C 584 C 420
2
* DA 204U *. 1U-10V _4 *. 1U-10V _4
A D OGND no stuff (reserve)
A1A(10/9):Change (D48/Pin2) from GND to ADOGND A D OGND A D OGND
MIC1_L L41 B K 1608LL121_6 A U_MIC_IN_L

Docking LINE IN M IC1_R L42 B K 1608LL121_6 A U _MIC_IN_R + 5V _ADO
D 33
A1A:(11/1)FAE: Docking MIC share from System MIC 1

M I C1_JD
L INE INL_S Y S L36 B K 1608LL121_6 A U_LINE IN_L 3
A U _LINE IN_L 33
A L I NE INR_S Y S L37 B K 1608LL121_6 A U _LINE IN_R 2 A
A U _ LINE IN_R 33
* DA 204U
A D OGND
C429 C430
A1A(10/9):Change (D50/Pin2) from GND to ADOGND
*. 1U-10V_4 *. 1U-10V_4
A D OGND A D OGND PROJECT : ZU1
Size Doc ument Number

Quanta Computer Inc. Rev
Speaker AM P / Audio JACK 1A

5 4 3 2 1
A B C D E
VA
VA
VA VA VA VA VA VA
1
+3V C 4 5 3+ C438 C 43 C 34 C 60 C442
C21 C 70
A1A: (9/20) Add .1uF *2 for VA
2
Q4 . 1 U -5 0 V _ 6 .1 U -50V_6
RHU002N06 1 0 U-2 5 V _ 1 2 1 0 .1 U -50V_6 . 1 U -5 0 V _ 6 . 1 U -5 0 V _ 6 . 1 U -5 0 V _ 6 . 1 U -5 0 V _ 6
2
C N22 A1A:(10/27) EMI suggest add 10u*1pc, 0.1u*5pcs
3 1 E Z _ DA T _ S MB 155 157
2 , 1 3 ,1 6 ,1 8 ,2 7 P DA T _ S MB P1 G1
POWER DECOUPLING 156 158
P2 G2
4 4
1 78 D E T _ G N D#
+3V A1 B1
25 1 3 9 4 T P A P0 2 79
A2 B2
25 1 3 9 4 T P A N0 3 80 1 3 9 4 T P A P1 25
Q5 A3 B3
4 81 1 3 9 4 T P A N1 25
RHU002N06 A4 B4
25 1 3 9 4 T P B P0 5 82
2
A5 B5
25 1 3 9 4 T P B N0 6 83 1 3 9 4 T P B P1 25
A6 B6
7 84 1 3 9 4 T P B N1 25
E Z _ CL K _ S MB A7 B7
2 , 1 3 ,1 6 ,1 8 ,2 7 P C L K _ S MB 3 1 15 P CIE _ T X P 1 8 85
A8 B8 E Z _ DA T _ S MB
15 P C IE _ T X N1 9 86
A9 B9 E Z _ CL K _ S MB A1A:(9/26)Add PLTRST# for (CN40/Pin88)
10 87
C 4 52 . 1 U -1 0 V _ 4 P C I E _ RX P 1 _ R11 A10 B10 P C I E _ RS T # R 2 0 8 0_6
15 P C I E _ RX P 1 88 P L T RS T # 1 5 , 1 6 , 1 8 ,2 1 ,2 5 ,2 6 ,2 7 ,2 8 ,3 0
+ 2 .5 V C451 . 1 U -1 0 V _ 4 P C I E _ R X N1 _ R12 A11 B11
15 P C I E _ RX N1 89 P C I E _ C L K RE Q# 2
A12 B12 A1A: (9/20) COPP#: reserve for ATI chipdst
13 90
A13 B13
2 P C I E _ CL K 1 + 14 91 S Y S _ C H A R G E 28
A14 B14
2 P C I E _ CL K 1 - 15 92 H I G H _ L O A D 28
R375 A15 B15
16 93
2 .2K_4 A16 B16
17 94 DV I_ D2 + 21
D V I_ DDC_ DT A17 B17
18 95 DV I_ D2 - 21
D V I_ DDC_ CK A18 B18
19 96
A19 B19
21 DV I_ DET 20 97 D V I _ C L K + 21
D V I_ DDC_ DT A20 B20
21 D O C K _ D D C _ D T 21 98 D V I _ C L K - 21
A21 B21
21 DV I_ D0 + 22 99
R373 A22 B22
21 DV I_ D0 - 23 100 L A N _ A CT L E D# 18
+ 2 .5 V 100K_4 A23 B23
24 101 L A N _ L IL E D# 18
A24 B24
21 DV I_ D1 + 25 102
A25 B25
21 DV I_ D1 - 26 103 TX2P_PR 18
A1A: (9/20) Add PL 100K for DVI_DET A26 B26
27 104 T X 2 N_ P R 18
R374 A27 B27
18 TX0P_PR 28 105
3 2 .2K_4 A28 B28 3
18 T X 0 N_ P R 29 106 TX3P_PR 18
A29 B29 V A UX _ 2 5 A1A: (9/20) change +VCC_LAN to VAUX_25
30 107 T X 3 N_ P R 18
A30 B30
18 TX1P_PR 31 108
D V I_ DDC_ CK A31 B31
21 D O C K _ D D C _ C K 18 T X 1 N_ P R 32 109
A32 B32
33 110
A1A:(11/1) Change LAN pin define A33 B33
34 111 P R _ MS _ DA T A 28
A1A: (9/20) A34 B34
35 112 P R _ M S _ CL K 28
A35 B35
(1)Remove Level-shift circuit (already in docking side) 28 P R _ K B _ DA T A 36 113
A36 B36
(2)change Power from +3V to +2.5V 28 P R _ K B _ CL K 37 114 P R _ R T S # 30
A37 B37
(3)stuff 2.2k (R520,R522) 30 P R_ S IN 38 115 P R _ C T S 30
A38 B38
30 P R _ S OUT 39 116 P R _ D T R # 30
A39 B39
30 P R_DS R# 40 117 P R _RI 30
A40 B40
30 P P T _ PE 41 118 P R _ D C D # 30
A41 B41
30 P P T _ B US Y 42 119 P P T _ INIT # 30
+ 3V_S5 A42 B42
30 P P T _ A CK # 43 120 P P T _ S L IN# 30
A43 B43
30 P P T _ E RR# 44 121 P P T _ P D0 30
A44 B44
30 P P T _ A F D# 45 122 P P T _ P D1 30
A45 B45
30 P P T _ S TB# 46 123 P P T _ P D2 30
Q6 A46 B46
47 124 P P T _ P D3 30
RHU002N06 A47 B47
19 DOC K_R 48 125 P P T _ P D4 30
2
A48 B48
49 126 P P T _ P D5 30
A49 B49
19 D O CK _G 50 127 P P T _ P D6 30
D O C K I N # _ R A50 B50 A1A:(9/28)change CONN from 2 pin to 4 pin
1 6 ,1 8 D O C K I N # 1 3 51 128 P P T _ P D7 30
A51 B51
19 D OCK _B 52 129 P P T _ S L CT 30
53 A52 B52 130 CN3
A53 B53 R I NGL
19 D O C K _ H S Y N C 54 131 D O C K _ T V _ COMP 20
A1A:(11/1) add level shift circuit, already PU 5VA_PR in docking side. A54 B54 T IP L 4
19 D O C K _ V S Y N C 55 132
A55 B55 C37 4 7 0 p -3 K V _ 1 8 08 R I NGL 3 6
19 D O CK _DDDA 56 133 D O C K _ T V _ C /R 20
A56 B56 C48 4 7 0 p -3 K V _ 1 8 08 T IP L 2
19 D O CK _DDCK 57 134
2 + 5V 58 A57 B57 135 1 5 2
1 5 , 1 9 ,2 8 C R T _ S E NS E # A58 B58 D O C K _ T V _ Y /G 20
59 136
A59 B59
32 A U _ L I N E I N_ L 60 137 A U _ S P D IF 31
A60 B60
32 A U _ L I N E I N _ R 61 138 L I N E O U T _ J D # _ OD 3 1 ,3 2
+3 V _ S 5 R31 A61 B61
62 139 A U _ J D _ L I N E I N 3 1 ,3 2
63 A62 B62 140
32 A U _ L I N E OUT _ L A63 B63
32 A U _ L I N E O UT _ R 64 141 U S B P3+ 15
10K_4 A64 B64 A1A:(10/2) change from USB5 to USB3
A U DIO _ A G ND 65 142 U S B P3- 15
R 33 A65 B65
P R _ I N S E RT _ 5 V 1 9 ,2 0 32 A U _ M I C _ IN_ L 66 143
A66 B66 P W R B T N#
32 A U _ M I C _ I N _ R 67 144
3
68 A67 B67 145

31 A U_ J D_ M IC A68 B68
1 00K_4 69 146 + 5V A1A: (9/20) change 5VS to +5V
D O CK IN# _ R A69 B69
70 147
D O CK IN# A70 B70
2
+ 3 V P CU
C 47 Q28
D E T _ G N D# 2 N 7002 76 153
.1 U -10V_4 T IP L A76 B76 R I NGL
77 154
1
A77 B77
5
1
159 163 4 N B S W O N # 2 8 ,2 9
A1A:(9/18) Refer to Acer DVR1019 G3 G7 P W R B T N# C446
160 164 2
+ 3V_S5 G4 G8 U25
161 165
3
G5 G9 *T C 7 S H 08FU . 1 U -1 0 V _ 4
162 166
R 32 R34 0 _6 G6 G10
R35 0 _6
C49 * . 1 U -1 0 V _ 4 F O X _ QL 0 1 7 7 L -D2 6 C0 2 -8 F
10K_4 C50 * 1 0 0 0 P -5 0 V _ 4 A1A: (9/20) refer to Acer Design Guide: R 3 72 0_4
P R_ S T S 28
this signal is asserted to power on the system.
1 1
3
A buffer used for PWRBTN# on the system side

A U DIO _ A G ND may be necessary to prevent the signal interfered
by the contact noise.
2
Q29 PROJECT : ZU1
2 N 7002
A1A:(9/20) Add R and C Quanta Computer Inc.
1
between AUDIO_AGND and GND

A1A:(9/20) Add Dockin circuit S ize D o c u m e n t N u mb e r R ev
Docking(ez DockII/II+) 1A
Da te : T h u r s d a y , N o v e mb e r 0 2 , 2 0 0 6 S heet 33 of 39
A B C D E

5 4 3 2 1
M A IND
M A IND 38
S US D
S US D 38
3 S Y S _ S HDN# 1 2
IS L 6 2 3 6 _3V
P R1 2 1
PL7 0_4 PL10
D V IN V IN D
H I0 8 0 5 R8 0 0 R-0 0 _ 8 VL H I0 8 0 5 R8 0 0 R-0 0 _ 8
VL
2
P C7 1
P R9 7 4 .7 U/X 7 R-1 0 V _ 8
1
3 9 0 K _4
1
3 V _ DL
P R1 2 2 P R1 0 2 P R1 0 7
3 9 K _4 0_4 P C7 5 0_4 P C 94 P C8 6
P C7 7 P C 79 P C8 4 P C7 4 1 U/1 0 V _ 6 0 .1 U/X 7 R-5 0 V _6 1 0 U/X 6 S -2 5 V _1206
1
0 .1 U/X 7 R-5 0 V _ 6 2 2 0 0 P /X 7 R-50V_4 P C7 2 1 0 U/X 6 S -2 5 V _1206 0 .1 U/X 7 R-5 0 V _6 P C 87 P C8 3
D1
D1
2
S2
G2
1 0 U/X 6 S -2 5 V _1206 P C7 6 2 2 0 0 P /X 7 R-50V_4 1 0 U/X 6 S -2 5 V_1206
.0 1 U/X 7 R-1 6 V _ 4 P C7 3
0 .1 U/X 7 R-5 0 V _6
1
3V5V_EN P Q2 3
2 1 F DS 6 9 0 0 A S
2
8
7
6
5
S1/D2
2
P R9 5 P R1 0 3 3 V _ DH OCP : 6.25A
G1
*0_4 P R1 0 9
8
7
6
5
4
3
2
1
4 5 V _ DH 1 5 0 K_4 *0_4 + 3 V P CU
8
P Q1 8 3 V _ DH PL12
REF
LDOREFIN
RTC
ONLDO
TON
LDO
VIN
VCC
OCP: 12A 2 .5 u H_ 7 .5 A
1
F DS 8 8 8 4 3 V P CU
P R1 1 2 3V_LX
+ 5 V P CU 5 V P CU9 32 2 8 7 K _4
PL11 BYP REFIN2
10 31 1 2
1
2
3
1 .5 u H_ 1 0 A OUT1 P U7 ILIM2
C 11 30 C
5 V P CU 5V_LX FB1 OUT2
1 2 12 29
P R1 1 6 2 6 7 K_4 D D P W R G D _ R13 ILIM1 IS L 6 2 36 SKIP# D DP W RGD_R P C1 0 3 P C1 4 2
28
PGOOD1 PGOOD2
2
8
7
6
5
P R1 1 4 3V5V_EN 14 27 3V5V_EN P R1 1 8 +
*0_4 EN1 EN2
15 26 0_6
DH1 DH2 0 .1 U/X 7 R-5 0 V _6 3 3 0 U/6 .3 V _ 6 X 5.7
16 25
5 V _ DL LX1 LX2
+ 4 37
P C9 2 PAD
36
SECFB
1
PAD
PGND
P C9 5 P C1 4 3
BST1
BST2
0 .1 U/X 7 R-5 0 V _ 6
GND
VDD
PAD
PAD
PAD
DL1
DL2
1 0 U/X 6 S -2 5 V_1206 P C 97 P C9 0
1
3 3 0 U/6 .3 V _ 6 X 5.7 0 .1 U/X 7 R-5 0 V _6 0 .1 U/X 7 R-5 0 V _ 6 P R1 1 5

P R1 1 3 P Q1 7 P R1 2 3 *0 _ 6
35
34
33
17
18
19
20
21
22
23
24
0_4 P R1 2 4 1_6
1
2
3
F DS 6 6 9 0 A S 1_6 1 2
1 2 3 V _ DL
2
P D6 VL
P C 82 P R1 2 5 0_6 D DP W RGD_R
2 H W P G _ 3 /5 V P CU 28
0 .1 U/X 7 R-5 0 V _ 6
P C9 9 P R1 1 9
3 1 U/1 0 V _ 6 0_6
3
1
OCP:12A C H N 2 17 P C 81
P D8 0 .1 U/X 7 R-5 0 V _6 OCP:6.25A
L(ripple current) P C 78
0 .1 U/X 7 R-5 0 V _6 2
=(19-5)*5/(1.5u*0.4M*19) L(ripple current)
2
~6A 3 P D7 =(19-3.3)*3.3/(2.5u*0.5M*19)
B B
1
B A T 5 4 -7-F ~2.18A
Iocp=12-(6/2)=9A
C H N 2 17 Iocp=6.25-(2.18/2)=5.16A
Vth=9A*15mOhm=135mV P R1 1 7 + 3 V P CU
R(Ilim)=(135mV*10)/5uA +1 5 V _ A L WP 1 2
Vth=5.16A*28mOhm=145mV
15V
1
~270K R(Ilim)=(145mV*10)/5uA
P R1 2 8 P R1 2 6
22_8 P C8 0 2 0 0 K_4 3 9 K _4
~294K
0 .1 U/X 7 R-5 0 V _ 6 P C9 6
1
2
5
6
0 .1 U/X 7 R-5 0 V _6
S US D 3 P Q2 2
+ 5 V P CU + 5 V P CU + 3 V P CU + 3 V P CU F D C 6 5 3 N_ NL
+ 3 V P CU 15V
4
+3 V S US
P C1 0 8 P C9 1 P C1 0 5 P C1 0 2
2
5
6
7
8
1
2
5
6
1
2
5
6
1
2
5
6
P Q2 4 P R1 2 7 0 .1 U/X 7 R-5 0 V _ 6 0 .1 U/X 7 R-5 0 V _6 0 .1 U/X 7 R-5 0 V _ 6 0 .1 U/X 7 R-5 0 V _ 6 P C1 0 0
P DT C1 4 3TT 1M_6 0 .1 U/X 7 R-5 0 V _6
M A IND 3 P Q2 1 M A IND 3 P Q2 9 S5D 3 P Q2 7
1 3 S5D 4 F D C 6 5 3 N_ NL F D C 6 5 3 N_ NL F D C 6 5 3 N_ NL
2 8 ,3 8 S 5 _ ON
4
4
+5V +3V +3 V _S5
P Q2 6
A A
3
2
1
F DS 6 6 9 0 A S P C9 3 P C1 0 7 P C1 0 4
0 .1 U/X 7 R-5 0 V _6 0 .1 U/X 7 R-5 0 V _ 6 0 .1 U/X 7 R-5 0 V _ 6
+5 V _S5
P C1 0 1
0 .1 U/X 7 R-5 0 V _ 6 PROJECT : ZU1
SYSTEM 5V/3V (ISL6236) 1A
5 4 3 2 1

5 4 3 2 1
PL6
HI0805R800R-00_8
VIN_6262
PL5
HI0805R800R-00_8
+1.05V
V IN
1
PR138 PR139 PR140 PR141 PR142 PR143 PR144 +
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6
2
DELAY_VR_PWRGOOD 3,6,16
Merom: VCC_CORE/ 44A
5
PC49 PC132 PC48
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 10U/X6S-25V_1206 PC43 470U/25V 0.1U/X7R-50V_6
D
6262_UG1 4 10U/X6S-25V_1206 Yonah: VCC_CORE/ 36A D
PR25 4.99K_6 VCC_CORE
1
2
3
2 1 P GD_IN VIN_6262 +3V PQ36
PWR_MON
AOL1414
PL17 0.36uH
1
for ISL6262A 6262_PH1 1 2
1
PC17 PR61 A1A:(10/27) change from 10k to 1.91k
1
0.1U/X7R-50V_6 10_6 PR47 PC130
2
4
5
10_4 PR46 *2200P/X7R-50V_4 + +
+5V_S5
A1A:(10/2) change from +5VSUS to +5V_S5 1.91K_4 A1A:(10/20) EMI suggest to add it A1A:(10/2) Remove PD10 for layout space issue
2
6262_LG1 4
1
3 P S I# PSI#
1
PR60 PC40 PQ35 PC53 PC50
1
2
3
10_6 0.1U/X7R-50V_6 PC33 0.1U/X7R-50V_6 AOL1412 470u_2V_7343 470u_2V_7343
2
PR76 PR75
22
20
48
2
1
PR52 0_8 PU3
PC41 0_6 0_6
VCC
VIN
PGOOD
3V3
1U/X7R-25V_8
1
PR70 3.65K_6
ISL6262A VSUM
21 35
GND UGATE1 PR69 2.2_6 PR74 10K_6
Close to Phase 1 Inductor 49
GND_T BOOT1
36 1 2
1
Throttling temp. PR72 1_6
+3VSUS PC46
105 degree C 0.22U/X5R-25V_8
2
34 PR71 *0_6 VIN_6262
PSI# PR33 0_4 PSI#_1 PHASE1 I SEN2
2
PSI#
32
A1A:(10/20) no stuff PR75 PR36 VR_ON PR34 *0_4 P GD_IN LGATE1
3
PGD_IN
C already have PU R in CPU side 33 C
PR31 147K_6 PGND1
4
1
*10K_4 RBIAS I SEN1
24
ISEN1
3 H_PROCHOT# 5
VR_TT#
2
PR146 PR22 6 PC44
470K_4 NTC 4.02K_4 NTC
+5V_S5 0.22U/X5R-25V_6
2
ED8-B -0623-add 2 1 PC23 7
PC26 1 15N/X7R-50V_6 SOFT PC45 A1A:(10/2) change from +5VSUS to +5V_S5 PC136 PC134
2
5
.01U/X7R-16V_4 31 1 2 10U/X6S-25V_1206 PC135 0.1U/X7R-50V_6
H_VID0 PVCC 10U/X6S-25V_1206
Panasonic 37
VID0
4 H_VID0 4.7U/X6S-25V_8
ERT-J0EV474J H_VID1 38 27 6262_UG2 4
4 H_VID1 VID1 UGATE2 PR73 2.2_6
H_VID2 39 26 1 2
4 H_VID2
1
2
3
VID2 BOOT2 PQ38
1
PSI#_1 H_VID3 40 AOL1414
4 H_VID3 VID3 PC47
H_VID4 41 0.22U/X5R-25V_8 A1A:(10/20) EMI suggest to add it PL18 0.36uH
4 H_VID4
2
VID4 6262_PH2
28 1 2
H_VID5 PHASE2
4 H_VID5 42
VID5
5
PR37 30 6262_LG2 PC131
4
H_VID6 LGATE2 *2200P/X7R-50V_4
*0_6 4 H_VID6 43
VID6
1
29
PR59 0_4 VR_ON PGND2 A1A:(10/2) Remove PD11 for layout space issue
28 V RON 44 4 + +
VR_ON I SEN2
23
PR79 499_4 DPRSLPVR ISEN2 PQ37
6,16 PM_DPRSLPVR 45
1
2
3
2
DPRSLPVR
1
DPRSLPVR AOL1412
PR55 0_4 46 PC42
3,6,14 ICH_DPRSTP# DPRSTP# 0.22U/X5R-25V_6 PC51 PC52
2
PR53 0_4 CLKEN# 47 PR77 PR78 470u_2V_7343 470u_2V_7343
16 VR_PWRGD_CK410# CLK_EN# PC25
25 2 1 0_6 0_6
PR30 1K_4 NC
1000P/X7R-50V_4
PR26 PC20 8 PR35 13.3K_4
OCSET
B 1 2 13 B
VDIFF
255_4 1000P/X7R-50V_6 19 VSUM
VSUM
PR38 ED8-B -0623-33nf to 68nf
12 PR58
1
FB2 PR57
1K_4 PC36 11K_4 2.7K_4
11
2
FB
1
68N/X7R-25V_6 PR65 3.65K_6

PC21 PC39 VSUM
PR40 97.6K_4 2 1
2
0.22U/X7R-10V_6 PR145 PR62 10K_6

470P/X7R-50V_4 10 Panasonic
PC28 COMP
2 1 ERT-J1VR103J PR67 1_6
18
220P/X7R-50V_4 PR29 6.81K_4 VO
10K _6 NTC
DROOP
9
VW
VSEN
ED8-B -0623-390p to330p I SEN1

RTN
DFB
PC27
1
1 2 PR49 PR66 *0_6

PC35 Close to Phase 1 Inductor
15
14
16
17
1000P/X7R-50V_6 1K_4 0.22U/X5R-25V_6

2
PR48
PC29 2 1 3.48K_4
ED8-B -0623-3.9k to 3.48k
.01U/X7R-16V_4
PC31
180P/NPO-50V_4
2 1 ISL6262_VO
2
PC32 PC24
.01U/X7R-16V_4 .01U/X7R-16V_4
1
Parallel
A PR41 0_4 A
VCCSENSE 4
PR43 0_4
VSSSENSE 4
PROJECT : ZU1
Custom CPU C ore ( ISL6262A ) 1A

5 4 3 2 1

1 2 3 4 5
A1A:(10/2) change from +5VSUS to +5V_S5 VIN-1.5V

PL14
V IN
+5V_S5 HI0805R800R-00_8
PR136
PC114 PC116 PC115
2
10_6 .1U/X7R-25V_8 10U/X6S-25V_120610U/X6S-25V_1206
PC126 PD10
5
PR133 PC127
*.1U_6 SW1010C PQ33
1M_6 4.7U/Y5V-10V_8 AOL1414
2
A 4 A
A1A:(10/18) Reserve .1UF PU8 PC124
1
2
3
SC411MLTRT .1U/X7R-25V_8
PR134 0_6 15 13
28,37,38 M A INON EN/PSV BST
+3V C448 16 12 DH-1.5V
VIN DH PL16 JP4 SHORT PAD 1 6A
*.1U_6 1 11 2 1
VOUT LX +1.05V
2 10 PR8 20K_6 1 R5UH-3.8mR
5
PR137 VCCA ILIM
2 1
1
*10K_6 3 9
FBK VDDP + JP5 SHORT PAD
4 8 DL-1.5V 4 PR9
28 HWPG_1.05V PGOOD DL PC7
2
6 7 PQ34 20K_6 33P/NPO-50V_6
1
2
3
VSSA PGND AOL1412
5 17 1.5V_FB
NC TPAD
14
GND
GND
GND
GND
1
1
PC125 PC123 PC120 NC PC129 PC128 PR10
0.1U/X7R-50V_6 560U/2.5V_6X5.7 10U/Y5U-10V_8 10K_6
2
18
19
20
21
1000P/X7R-50V_6 .01U/X7R-50V_6 VOUT=(1+R2/R3)*0.5
B B
C C
D D
PROJECT : ZU1
VTT 1 .05V (SC411) 1A

1 2 3 4 5

5 4 3 2 1
PL9
V IN
HI0805R800R-00_8
+1.8VSUS
PC85
5
6
7
8
PR100
PC55 2200P/X7R-50V_6
*2.2_6
10U/X6S-25V_1206 4
A1A(10/5):change net name from P U4 PQ16
+SMDDR_VTERM to SMDDR_VTERM TPS51116 PC89 PC88
1 19 F DS8884 PC70 10U/X6S-25V_120610U/X6S-25V_1206JP7 SHORT PAD
JP2 SHORT PAD VLDOIN DRVH *2200P/50V_6 2 1
2 1 2 20 PC58 0.1U/X7R-50V_6
SMDDR_VTERM VTT VBST PL8 JP6 SHORT PAD
3
2
1
PC54 PC56 4 18 2 1 +1.8VSUS
VTTSNS LL
D D
5
6
7
8
5
6
7
8
10U/X6S-25V_1206 5 17 1R5UH-3.8mR
10U/X6S-25V_1206
3
GND DRVL
16 +
MAX Current 10A
VTTGND PGND PR120
4 4
DIS_MODE 6 11 S3_1.8V PR91 0_6
MODE S3 MA INON 28,36,38
PR88 *2.2_6
7 12 S5_1.8V PR92 0_6
SMDDR_VREF VTTREF S5 S US ON 28,38
0_6 5 V IN 8 14 5 V IN C321 C322
PC60 COMP V5IN PC98 PC133 PC67
3
2
1
3
2
1
0.033U/50V_6 9 13 *.1U_6 *.1U_6 PQ19 PQ20 *2200P/50V_6 560U/2.5V_6X5.7 10U/Y5V-10V_8
A1A(10/5):change net name from PR89 VDDSNS PGOOD A1A:(10/18) Reserve .1UF F DS6690AS F DS6690AS
GND
GND
GND
GND
GND
GND
GND
+SMDDR_VREF to SMDDR_VREF 5 V IN 10 15
VDDQSET CS
0_6 PR86 PR90
21
22
23
24
25
26
27
FOR DDR II PC59 +3VPCU + 3VPCU
*1000P/50V_6 12K_6 100K/F_6
PR84 *0_6 DIS_MODE PR87

5 V IN
+5VPCU HWPG_1.8V 28
1
0_6 PC61
+1.8VSUS PR85 0_6 4.7U/X5R-6.3V_6
2
C C
A 1 A ( 1 0 / 5 ) : R emove +1.8V circuit
B B
A A
PROJECT : ZU1
Size Document Number Rev
D D R 1.8V(TPS51116) 1A

5 4 3 2 1

5 4 3 2 1
1 5
P R12 GND0 VO1 J P1 S HORT PAD
MAINO N 2 6 2 1
EN VO2 +2.5V
PQ39 F DS8884 10K_6 + 3VSUS 3 8
+ 1.8VSUS VIN1 GND1 0.5A
8 1 4 9
VIN2 GND2
ADJ
7 2
6 3
+ P C65 P C63 5
7
PC137 P U1
0 . 1 U/ Y5V-16V_41 0U/X5R-6.3V_6 AT814
4
9 3 38DRV
D 5 60U/2.5V_6X5.7
1.24V VTT-ADJ
R1 D
P R147 P C10 PC8 PC13
2
+1.5V PC9 1 0 U/ Y5 U-10V_8 1 U/ 16V_6 P R28 1 0 U/ Y5 U-10V_8 P C18
0 _6 3A 0 . 1U/X7R-50V_6 10.2K_4 0 . 1U/X7R-50V_6
+ 3V P R18 R2
+ 1.5V 4 ,9,17,27,31
P R99 100K_4 10K_4
Vout=1.24*[1+(R1/R2)]
2
REV:3A MODIFY
1
3 6 P C138
28 HW P G_CPUIO PGD DRV . 0 1U/X7R-16V_4 P R108
1
Rg 20K_6
MAINO N PR105 0_4 9 338EN 4
2 8,36,37 MAINO N EN +
5
ADJ
GND
+ 5 VPCU 1 Vout1 = (1+Rg/Rh)*0.5
VCC P R104
C 339 PC69 10K_6 + 5V
2
A1A:(10/18) Reserve .1UF P U6 Rh
* . 1U_6 0 . 1 U/Y5V-16V_4G9 3 38 ADJ P C62 P U5
0 . 1 U/ Y5V-16V_4 G966
4 1
P C140 PC141 P R94 VPP PGOOD J P3 S HORT PAD
0 . 1 U/ Y5V-16V_4 PC139 5 6 0U/2.5V_6X5.7 MAINO N 2 6 2 1
VEN VO +1.25V
1 0U/X5R-6.3V_6
10K_6 3 2A
+ 1.8VSUS VIN
8
ADJ
9 GND 5
GND NC PR82
P C64 P C66 C 323 P C57
7
19.6K_6 1 0 U/ Y5U-10V_8
1 0U/X5R-6.3V_6 * . 1U_6
0.8V
C 0 . 1 U/ Y5V-16V_4 C
A1A:(10/18) Reserve .1UF
PR83
34K_6
Vout =0.8(1+R1/R2)
=1.25V
VIN S MD DR_VREF + 1.8VSUS + 3VSUS 1 5V
PR111 P R93 PR81 P R96 P R98

1 M_6 22_6 22_6 2 2_6 1 M_6
A1A:(10/25) Add +1.5V_S5 circuit (refer to ZD1)
S US _ON_G S U SD
S USD 34
3
3
3
+ 3 VPCU SOT23-5 +1.5V_S5

2 2 2 2 2 U3 8 AT5206G-1.5V
2 8,37 S US ON P C68 200mA
PR110 PQ11 PQ10 PQ13 PQ12 *2200p_4 1 5
PQ15 1 M_6 2 N7002E 2 N7002E 2 N7002E 2 N7002E VIN VOUT
1
2
D TC144EU
1
PC147 PC144
GND
1 U/X7R-25V_8 3 4 1 U/X7R-25V_8
1
1
SH BP PR150
PC146 *0_4
2
B 470P/X7R-50V_4 P C145 B
2
*10U/X6S-25V_1206
28,34 S 5 _ON
PR149
0_4
A1A(10/5):Remove +1.8V
A1A(10/25):Add +1.25V discharge circuit
VIN +1.05V +1.25V +2.5V +3V + 5V S MDDR_VTERM +1.5V 15V
P R106 P R24
P R27 P R23 P R130 PR129 P R80 P R148 PR131
1 M_6 2 2_6 2 2_6 22_6 2 2_6 22_6 22_6 2 2_6 1 M_6
R UN_ O N_G M AIND

A M AIND 34 A
3
3
3
2 2 2 2 2 2 2 2 PC106
2 8,36,37 M AINO N *2200p_4
2
P R101 PQ6 PQ4 PQ28 PQ25 PQ9 PQ40 PQ30
PQ14 1 M_6 2 N7002E PQ5 2 N7002E 2 N7002E 2 N7002E 2 N7002E 2 N7002E 2 N7002E PROJECT : ZU1
1
D TC144EU 2 N7002E
1
1
1

1A
Discharge (1.5V/2.5V)
5 4 3 2 1

5 4 3 2 1
0.02_3720 PQ31 PQ2

VA PR132 FDS6675BZ FDS6675BZ
PJ1 HI0805R800R-00_8 V IN
SIT_2DC-G026-I06 PL2 1 1 8 1 8
1 3 1 2 2 7 2 7
2 2 3 6 3 6
3 5 5
PL1 PD9 P R7
1P
2P
PDS1040S PC3 PR1 PC110
33K_6
4
0.1U/X7R-25V_8 220K_6 0.1U/X7R-25V_8
5
4
2
HI0805R800R-00_8
PD4
D PC2 SW1010C D
PC1 .1U/X7R-25V_8 PC109 PC113 1 6 PR11
1
.1U/X7R-25V_8 .1U/X7R-25V_8 .1U/X7R-25V_8 10K_6
PR2 2 5 PR6 0_6
D /C# 28
A1A:(9/27)change CONN (Follow ZH2) 220K_6
PD5 3 4
3
PR63
A CIN_1 2 1 PQ1
28 A C IN
IMD2AT108
10K_6 2
ZD12V C S IN
PR68 PQ3
PR64 2N7002E
6.8K_6 10K_6 C SIP
1
PC38 2.2U/X5R-10V_8 V IN
1 2 PC112 10U/X6S-25V_1210
ISL6251_VDD
PR42
18_6 PR15 PL13
4.7_6 PC111 .1U/X7R-25V_8 HI0805R800R-00_8
PC30
0.1U/X7R-50V_6 PC11 4.7U/X5R-10V_8
ISL6251_VDDP 1 2
C SIN_1
PD3
19
20
15
C C
1
RB500V
PQ32
CSIN
VDD
CSIP
VDDP
PR51 2.2_6 FDS6900AS
CSOP CSOP_1 21 PR21 2.7_6 PC22 .1U/X7R-25V_8
CSOP G1
166251B_2 6251B_1 8 D1 1 VA3
BOOT
2
PC34 7 S1/D2 D1 2 PR135
1U/X7R-25V_8 17 ISL6251_UGATE PL15 0.03_3720
1
C SON UGATE G2 3 6R8UH(MPL73-6R8)
22 6
CSON 6251LR BAT-V
1 2
18 ISL6251_PHASE 5 S2 4
PHASE
1P
2P
14 ISL6251_LGATE
PC37 LGATE PC117
23
0.1U/X7R-50V_6 ACPRN .01U/X7R-50V_6
13
PGND
D C IN 24 12 V REF
DCIN GND PC119 PC118
CSOP 10U/X6S-25V_1206 10U/X6S-25V_1206
A1A:(9/27)change Pin define 11 PR19 PR13
A1A:(9/29) change footpint: BAT-250133MR007G115ZU-7P-R PR54 6251ACSET VADJ 71.5K_6 *514K_6 C SON
2
130K_6 ACSET
10
ACLIM VADJ
3 Float = 4.2V / CELL
PC4 EN
VCOMP
CELLS
ICOMP
CHLIM
PR56 ACLIM
VRFE
B MTEMP 28 B
ICM
10K_6
C N20 HI0805R800R-00_8
100P/NPO-50V_4 PL4 PR14
2 6251ICOMP 5
9
7 MBAT+ BAT-V P U2 PR16 *514K_6
6 TEMP_MBAT ISL6251A 10K_6
5
4 PL3 ISL6251_VDD 6251EN V REF
3
6251VCOMP1
HI0805R800R-00_8
2 CC-SET 28
1
PC122 PC121 PC6 PR44 10K_6

1
LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050)
SUY_250133MR007G136ZL 47P/NPO-50V_4 47P/NPO-50V_4 PR5 10K_6 6251CELLS_1
+3VPCU
2
0.1U/X7R-50V_6 PC19 PC12 CURRNT LIMIT POINT = 2.908A

1
PR3 PR39 10K_6 100P/NPO-50V_4
10m il 100_4 3.79A=1/0.02((0.05/2.365)Vaclm+0.05)
3
P R4 PR45 .01U/X7R-16V_4
PR17
100_4 MBDATA 28 10K_6 Vaclm=0.3899V
2 6251VCOMP2 IC MNT
MBCLK 28 6251CELLS_2 2
TEMP_MBAT PR20
*100_4
1
3.3K_4 ADP WATT monitor output

1
PD1 PD2 PQ7

ZD5.6V PC5 2N7002E
For 62W setting. Vicm will 1.3V
1
ZD5.6V .01U/X7R-50V_6 PR32 PC14

28 CELL-SET 2
2
100K/F_6 *3300P/X7R-50V_4
2
PQ8
PR50 2N7002E
1
100K/F_6
1
A A
PC16 PC15
*100P/NPO-50V_4 .01U/X7R-16V_4
PROJECT : ZU1
CELL-SET = Hi ----> Cells = VDD ---->4S Size D o cument Number Rev
CELL-SET = Low ----> Cells = GND ---->3S 1A
Charger (ISL6251)
5 4 3 2 1

Quanta ZU1

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5 4 3 2 1

ZU1 SYSTEM BLOCK DIAGRAM

DVI / 7307 CLOCK GENERATOR

S-VIDEO CONN FSB

MDC 1.5 10/100/1G Switch 1.8V (TPS51116)

D ate: T h u r s day, Novem ber 02, 2006 Sheet 1 of 39

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A1A:(9/24) C 542 0_6 C 294 . 1 U_4 +3V

C310 33P_4 C G_ XIN <c hec k list>

Clock Gen Differential IO power

C299 33P_4 CG_XOUT L 26

CPU Clock select

A1A: (10/23) stuff

R 440 0_4 CLK_BSEL1 0 1 1 166Mhz

R 439 *0_4 0 1 0 200Mhz

+ 1 .05V_CPU R 198 1K_4 1 1 0 400Mhz

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CPU Thermal monitor

T P_CPU_RSVD06 C3 RSVD[05] VIN VO 1 4

Me rom Ball-out Rev 1a

H_ D#4 F23 V23 H_ D#36

H_ D#9 G24 D[8]# D[40]# W22 H_ D#41 + 1 .05V_CPU

H_ D#21 M24 AC26 H_ D#53 R 174 A1A: (9/26)

D[26]# D[58]# S YS _ S HDN# 34

D ate: T h u r s day, Novem ber 02, 2006 Sheet 3 of 39

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D ate: T h u r s day, Novem ber 02, 2006 Sheet 4 of 39

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D ate: T hursday, November 02, 2006 Sheet 5 of 39

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MC H_ RSVD1 P36 U2 9C +VCC_PEG

T22 CFG_8 CRT_GREEN# PEG_TX_3

11 MC H_ CFG_9 C20 AJ47 D M I_RXP0 IN T_CRT_RED F29 R51

T29 M24 19 INT _ VS YNC AD43

E35 T37 C RESTLINE_1p0

13 PM_EXTTS#1 R 147 0_4 PM_EXTTS#1_R J36 E36 T41

T106 BK51 AN49 CL_RST#0 16 SDVOB_B- 21

T76 T P _ MCH_NC8 BK1 . 1 U_4 392_6

T77 E1 K36 S DVO_CTRLDATA 21

R 133 1K_4 S M _RCOMP_VOH

D ate: T h u r s day, Novem ber 02, 2006 Sheet 6 of 39

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M_A_DQ33 AT13 BD20 M_A_A1 M_B_DQ33 BE11 BG28 M_B_A1

M_A_DQ46 SA_DQ_45 SA_MA_13 M_B_DQ46 SB_DQ_45 SB_MA_13

Date: T hursday, November 02, 2006 Sheet 7 of 39

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+ 3 V _ V CCS Y NC + 1 . 0 5 V _ V CC_ GMCH

VCC AXM NCTF

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+ C 527 C262 VCCDQ_CRT 1 .5V G ND VC C ABG_DAC 3 .3V G ND VCCTX_LVDS G ND G ND 1 .8V

R 120 0_6 + 1 .25VM_VCCA_SM AW18 B23 + 1 .25V_VCC_AXF . 1 U_4

. 1 U_4 2 2 N_4 D8 2 1 +1.05V_SD

D ate: T h u r s day, Novem ber 02, 2006 Sheet 9 of 39

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Pin Name Strap description Configuration

CFG[2:0] FSB Frequency Select 010 = FSB 800MHz

CFG5 DMI X2 Select 0 = DMI X2

CFG7 CPU Strap 0 = Reserved

CFG8 Low power PCI Express 0 = Normal mode

CFG9 PCI Express Graphics Lane Reversal 0 = Reverse Lanes

CFG16 FSB Dynamic ODT 0 = Dynamic ODT disable

SDVO_CTRLDATA SDVO Present 0 = No SDVO Card present(Default)

10K_4 10K_4 10K_4 10K_4