Dell Optiplex 7010 - Lanikai-Mt - DT Ra00

5 4 3 2 1
1. Index / Block diagram

Lainikai - MT / DT
2. SMBus MAP
3. Clock Distribution Page 65 ~ 70
4. Power Delivery Map VRD12 / VRM / Linear CHANNEL A DDR3 SDRAM (1333/1600)
DDR3 DIMM 1
D
5. Power On Sequence Page 15, 16
D
Intel PROCESSOR DDR3 DIMM 3

6. Reset / Power Good Map
7. Strap/IRQ/IDSel Table IVY BRIDGE
XDP CHANNEL B DDR3 SDRAM (1333/1600)
8. GPIO Table Page 52 LGA1155 DDR3 DIMM 2
9-14. CPU Page 17, 18
DDR3 DIMM 4
15-16. DDR3 Conn: CHA PCIe Gen3 16x
PCIe 16x slot X1
17-18. DDR3 Conn: CHB Page 38 Page 9-14
19. TBD
FDI
DMI
20. TBD Page 35
PCIe 1x Intel NIC + USB
21-30. PCH Ports X 2
Page 34 Lewisville
31. PCH MISC Conn/BUZ/ID
32-33. SIO:SMSC5544 DP Link Port 8/9
DISPLAY PORT
34-35. LAN: INTEL LEWISVILLE Page 40
Port 2 ~ 5 Rear USB Ports
36-37 AUDIO:ALC269Q 2.0x2 3.0x2
C 38. Slot1: PCIe 16x DP Link Page 45 C
DISPLAY PORT
39. Slot4: PCIe 4x Page 41
USB Port 0/1/10/11 Front USB Ports
40. Display Port 1 VGA Page 56 2.0x2 3.0x2
41. Display Port 2 VGA CONN
Page 42 Intel Port 12/13
42. VGA Conn
43. SATA Conn PCI Slot X1
PCI PANTHER Point Page 61
Internal USB
Header X1
44. TBD Page 58
45. Rear USB
PCIe 16x Slot X1 PCIe Gen2 4x
46. TPM & TCM (wired as 4x signal)
47. Thermal Sensor Conn Page 39
Page 37
48. FAN HDA
PCIe 1x Slot X1 PCIe Gen2 1x ALC269Q Rear Audio CONN
49. PS2 Conn Page 36 Line In (MIC In)/Line Out
50. COM1 Page 59
51. SPI
XDP
B
52. XDP Page 52 Front Audio CONN B
53. Pilot Run Conn Page 21-30 HP Out/ MIC In

54. EMI Page 56
55. COM2 HDR LPC
56. Front_Panel
57. Front USB 3.0 SATA Port 0/1
SATA 3.0 CONN X2 SMSC5545 TPM/TCM
58. Slot3: PCI Page 43
59. Slot2: PCIe 1x Page 32 Page 46
SATA Port 2
60. SATA_MT SATA 2.0 CONN X1 (TCM is just reserved because
61. Flexbay USB Page 43 MRD has removed TCM requirement)
SERIAL PS2
62. TBD SATA Port 3 Port KB/MS
SATA 2.0 CONN X1 (MT)
63. Power Conn Page 60
64. Power Sequence Page 50 Page 49
65-66. Power: Linear Power
67-68. Power: Vcore PWM
SPI ROM SPI
A
69-70. Power: VCCIO/VCCSA 2M+8M
A
71. Power: DDR3/5Vdual/5VUSB Page 51
Title
DESIGN CHECK APPROVE Index / Block diagram

DWG NO Rev
A00
Hiko Hiko Ivan Lanikai _MT/DT
Date: Wednesday, June 13, 2012 Sheet 1 of 71
5 4 3 2 1
5 4 3 2 1
SMBUS DIAGRAM
SMdata2
SMdclk2
5545 SIO
Intel Lewisvillies
D D
LOM SMdata1
SMdclk1
RO31/RO32 R015/RO16
SMLINK0
SMBus SMLINK1 QO4/QO5

Controller
BUS Switch
RESUME SMBUS Main SMBUS
C
PCH C
CPU-XDP PCH-XDP
RX5/RX6 RX3/RX4 RX1/RX2 RX9/RX10
PCIE 16x SMBUS

PCIE 4x SMBUS
Mini-PCIe 1x
PCI EXPRESS 16x SLOT 1

PCIE 1x SMBUS
PCI EXPRESS 16x (wired as 4x signal) SLOT 4

B B
PCI SMBUS
PCI EXPRESS 1x SLOT 2
PCI SLOT SLOT 3
DDR3 DIMM1 CHA Address : 0 X00

DIMM SLOTS
DDR3 DIMM3 CHA Address : 0 X02
DDR3 DIMM2 CHB Address : 0 X04
A A
DDR3 DIMM4 CHB Address : 0 X06
Title
BLOCK DIAGRAM
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
H_ITPCLK/H_ITPCLK# RS204/RS205
CPU XDP
D D
RS204/RS205
DIMM 2
Channel B
DIMM 4
C_PCH_ITP/C_PCH_ITP#
DIMM 1 C_PCIEX1_1/C_PCIEX1#_1
C_PCI_SB MINI PCIe
Channel A
DIMM 3 C_PCI_SL1
25 MHZ
PCI SLOT SLOT 3
D3_MA_CLK/CLK#[0:3]
D3_MB_CLK/CLK#[0:3]
C_PCIEX16_1/C_PCIEX16#_1
C PCI EXPRESS X16 SLOT 1 C
PCH C_PCIEX1_2/C_PCIEX1#_2
32.768 KHZ
PCI EXPRESS X1 SLOT 2
Buffer Through Mode C_PCIEX4_1/C_PCIEX4#_1
PCI EXPRESS X4 SLOT 4
C_PE_100M_MCP/MCP#
CPU C_SRC1_PCH/C_SRC1_PCH#
PCH XDP
C_14M_TPM
B B
C_TPM
TPM/TCM
25 MHZ LAN 82579 C_PCIE_L1/L1#
C_LPC_TPM
LPC HEADER
C_LPC_SIO
SUPER IO C_14M_SIO
A A
Title
Clock Distribution
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
POWER DELIVERY MAP

resistor, empty
Deep Sleep : Off VCC_CORE
PSU ON NCP6153+NCP5901
Default : S0 +12V_CPU S0
2X12 0.016A VRD12 switcher, 4ph +VCORE S0
+5VSB S5,S0,S3,S4 +3V_Dual Linear P-FET ME : Mx/Moff
+5V S0 +3V_S5 SVID
Fairchild FDN340P +3V_EPW
5V 85A TDC; 112A ICCMAX
10A FAN5078D3 /N AOD452 +3V_Dual Switch
S5,S0,S3,S4 LL = 1.7m ohms
+3V S0 +/-5% DC + AC
D +3V S0 resistor, empty D
3V H=Power on H=Power on
S_SLP_S3#
2.4A S_SLP_M# L=Power off
L=Power off
+12VS0 H=Power on
resistor, empty +1P05V_VCCIO
12V resistor, empty L=Power off
7A
Deep Sleep : Off
-12VS0 Deep Sleep : Off
Default S5,S0,S3,S4 VCC_AXG
Deep -12V
Sleep : Off P-FET P-FET
Default S5,S0,S3,S4 +3V_PCIAUX ON NCP6153+NCP5901
+3V_Dual FDN340P +3V_S5 FDN340P
S5,S0,S3,S4 +3V_S5 S0=1.5A, VRD12 switcher, 1ph +1P1V_AXG S0
+5VSB Switch Switch
S3~5=0.45A SVID
5VSB 25A TDC; 35A ICCMAX
H=Power on H=Power on LL = 4.1m ohms
2X2 SLP_SUS_FET# S_SLP_S4#
L=Power off L=Power off
+12V_CPU S0 H=Power on
12V H=Power on S_SLP_S3#
S_PCIAUX_GATE L=Power off
10.6A
resistor, empty L=Power off
H=Power on
Current listed are for Deep Sleep : Off
a typical 265W PSU
+1P05V_VCCIO
L=Power off
C Default : S0 C
ME : Mx/Moff
P-FET Default S5,S0,S3,S4 +3V_S5 P-FET 0.218A VCCIO
+5VSB S5,S0,S3,S4 +3V_LAN
FDN340P +5V_S5 SI4835DDY ON NCP5230
Switch Switch Switcher, 1ph +1P05V_VCCIO S0
17A Imax
H=Power on H=Power on +/-0.5% DC, +/-4.5% AC
SLP_SUS_FET# S_SLP_LAN# 1-bit VID(1.05V/1.0V)
L=Power off L=Power off
H=Power on
0.375A +1P05V_PCH
+3V S0 LDO L=Power off
+V_1.5V_PCIE S0
NCP1117STAT3G
DDR3 DDR3 Vtt VCCSA Linear

+5VSB S5,S0,S3,S4 +5V_DUAL S0,S3
Fairchild FAN5078D3 +1P5V_SM Fairchild FAN5078D3
P SI3457CDV-T1-E3 S0,S3, ON NCP102
N AOD452 Switcher, 1ph Linear +1P5V_SM_VTT S0,S3, 8.8A Imax
+5V S0 Switch 1.5V, 25A Imax 0.75V, 1A TDC +V_VCCSA S0
+/-5% DC + AC
B
+/- 5% DC+ AC +/- 5% DC+ AC 1-bit VID(0.925V/0.85V) B
H=Power on
H = +5V S0 S_SLP_S4#
B_ATX_PWROK L=Power off H=Power on
L = +5VSB S3 S_SLP_S3#
PCH Core L=Power off
H=Power on
S_SLP_S3#
Linear OP LM358 +1P05V_PCH S0
L=Power off 1.05V,7.5A Imax H=Power on
VCCIO_PWRGD
+/- 5% DC+ AC L=Power off
H=Power on
Non-AMT
S_SLP_S3# stuff resistor, SFR
L=Power off
empty for ME Linear OP LM358
+3V S0
1.8V, 1.6A Imax +1P8V_SFR S0
+/-5% DC + AC
Deep Sleep : Off

Default S5,S0,S3,S4 Default S0
PCH ME (AMT only)
ME : Mx/Moff
A
+5V_S5 Richtek RT8068 A
+1P05V_ME
Switcher, 1ph
1.05V, 1.8A Imax
+/- 5% DC+ AC
Title
H=Power on
S_SLP_M#
L=Power off
Power Delivery Map
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
POWER ON Timing Diagram
O_PS_ON#
G3 to S4/S5 Timing Diagram
PCI/PCIe:100ms min
t226 S_SLP_S3#
VccRTC
t200 Power rails rise
0.2 – 20ms
+12V/+5V
D RTCRST# PSU: <=20ms D
t225 Power rails rise

0.2 – 20ms
+3V
VCCSUS
t201
=500ms
t202 +1P5V_SM
RSMRST#
=50ms
+1P05V_VCCIO Uncorepwrgood assertion
SUSCLK
=50ms
+1P8V_SFR MAX TBDns
T 17
SLP_S5# VCCSA VID[0] Buffers Output is
stable after VccIO Ramp VCCUSA VID[0] FINAL
H_VCCSA_VID
Uncorepwrgd must be stable (low) at this time
Ramp not to exceed 50mV/us
Recommended that VccSA ramp after VCCIO has

remped to ensure VCCSA_VID[0] is stable
VSAFINAL
=50ms VSABOOT=SNB Vmax
+V_VCCSA Typ 60us
Depends on exact SVID
Deep Sleep Entry RC VIH
T A
transactions between CPU
and VR 8T
C EN TB C
VR:5ms max CPU:
400us min
CPU SVID buffers are Hi-Z once VCCIO is A A Set VID A A GETReg A A
stable and Uncorepowergood=0 T1 MISC
C C SLOW C C status C C Pay Set VID Satus
DPWROK K K Packet K K T Packet K K load Packet Packet
SVIDs CPU: 0 1 0 1 D 0 1
(VIDSOUT/VIDCLK) 500us max VR:2ms max
TC
SUSWARN# Note5: Core and GT power supplies should not source current during this time. VR:5us max
+VCORE CPU
Packet
CPU SVID buffers are Hi-Z once VCCIO is

stable and Uncorepowergood=0 T
E
SUS_PWR_ACK
SAlert#I VR:1us max
GT
VIDALERT# Packet
T F
SLP_SUS# VR:min=Te,5ms max
VR_Ready =5ms T C
Feed into PCH PCH(t1001) VR:5us max
SYS_PWROK
RSMRST# Note5: Core and GT power supplies should not source current during this time. GT Ramp will occur after PLTRST#
+1P1V_AXG
Min 10 PCIe bclks
T 14
T13 Min 10 PCIe bclks
1.05V
+5VDUAL Srtaps=CFG[x} Strapping option
Inactive / Disable
+5V_S5/+3V_S5 Note: PCH THERMAL WATCHDOG TIMER WILL BE DISABLED WITH SNB. Enable
T 11 SNB WILL NOT EXCEED VR IMAX UNTIL THERMTRIP# IS ENABLED
S_Thermtrip# T12
CPU:[x]ms min CPU:[x]ms min
B
T10 B
CPU:1ms min
H_SM_DRAMPWRGD
(xxDRAM_PWROK)
Note:DDR spec reuqires that DDR_RESET# be

asserted during power ramp cycle BIOS will deassert DDR_RESET#
D3_RESET#
PCH t34
(1ms)
Deep Sleep Exit PSU
100ms~500ms Min 10 PCIe bclks PCH: No min/max requirement
PWRGD_3V
Feeds into PCH_PWROK
DPWROK BCLK, PCIe

PCH t573
CLKs (1, 5, 50, or 100ms)
SLP_SUS# Note4:Uncorepwergood must be at
T2 CPUPWRGOOD
a valid level during all power states CPU:5ms min, 650ms max
UNCOREPWRGOOD AND PCH t1001
(PROCPWRGD) SYS_PWROK(VR_READY) 30us, 1, 2or 5ms
RSMRST# T =PCH_PWROK & SYS_PWROK &

6
CPU:1ms min, 100ms max
t1001 Timer expired & internal_ready
S_RLTRST#
+5V_S5/+3V_S5
T?
DMI
SUSWARN# DMI training CPU_RESET_DONE

CPU_RESET_DONE_ACK
A A
SUS_PWR_ACK
+5VDUAL
Title
Power On Sequence
DWG NO Rev
Lanikai _MT/DT A00

5 4 3 2 1
5 4 3 2 1
RESET / Power Good MAP Deep Sleep Exit MAP

Sequence Signal Name: CPU-Ivy Bridge Sequence Signal Name:
UNCOREPWRGOOD
SM_DRAMPWROK
(1) (D1)
SM_DRAMRST*
O_PWRBTN#IN O_PWRBTN#IN
(2) S_SLP_S4# S_SLP_S3# S_SLP_M# (D2) S_SLP_SUS#
D D
(3) O_PSON# (D3) S_RSMRST#
RESET*
(4) B_ATX_PWROK PROCPWRGD (D4) S_SUSWARN#
(5) PCH_MEPWRGD PWROK (D5) S_SUS_PWR_ACK#
(6) S_PCH_SYSPWROK P_VR_READY > 1ms
(7) PWRGD_3V
(8) H_DRAMPWRGD D3_RESET# (9) (10)
(9) H_PWRGD
(10) S_PLTRST# H_RESET#_R S_PLTRST#_R (8) DDRIII Slots
D3_RESET#
(11) X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT Buffer (UH2)
(12) A_Z_RST#
(10) LAN
(9)
PE_RST_N
CPU-XDP (1)
(10) TPM/TCM
C
PCH-XDP (1) LRESET# C
F_TP_XDP_RST
Front Panel
O_PWRBTN#IN
(1)
PWRBTN#
PROCPWRGD
Power On Botton (1) (1) (8)

O_PWRBTN#IN PWRBTN# DRAMPWROK
(D1) PCI_RST_SYS#
(10)
PLTRST# LRESET#
ATX Power
(3)
VRD 12 PS_ON# PSON
(6) (7)
VR_RDY SYS_PWROK AND PWROK PWR_GOOD_3V
PWRGD_PS
(4)
PWROK
(2)
SLP_S3# SLP_S3#
B
PCH (2)
SIO-5545 B
SLP_S4# SLP_S4_S5# PWR_GOOD_3V

RESET BUTTON
FP_RST# SYS_RESET# (2) PWRGD_PS
SLP_A# IO_SMI#
100~120ms
HD Audio (12) RSMRST#
RESET# HDA_RST#
(D3)
SUSWARN#
SLP_SUS#
ME POWER-GOOD Sequence
SUSACK#
CIRCUIT Logic
(5) Circuit
PCH_MEPWRGD APWROK Page.64
PCH_MEPWRGD (D5) (D4) (D2)

+1P05V_ME
A
> 1ms A
+5VDUAL
Sequence +5V_S5/+3V_S5
Logic
SUSACK# Circuit SLP_SUS#
Title
Page.64
Reset / Power Good Map
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
IRQ Routing Table PCH

On-Die PLL Voltage Regulator Voltage Select Boot BIOS Destination Selection
HDA_SYNC Description
INTA# INTB# INTC# INTD# IDSEL REQn# GNTn# GNT1# SATA1GP/GP19
(IN-PU) (IN-PU) Description
High 1.5V
Slot3 C D A B 18 0 0 Low Low Flash cycle routed to LPC
Low 1.8V DEFAULT
D D
High Low Flash cycle routed to PCI
On-Die PLL Voltage Regulator
Low High Flash cycle routed to NAND
STRAPPING Table GPIO28
(IN-PU) Description
High High Flash cycle routed to SPI DEFAULT
CPU side
High Regulator is enabled. DEFAULT
CFG[17:0] Description
Low Regulator is disabled.
PCI Express static x16 1: normal Default
[2] lane numbering reversal 0: lane numbers reversed
Topblock Swap Mode Deep S4/S5 Well on-die Voltage Regulator Enable
GNT3#/GPIO55
00: 1x8, 2x4 PCI Express (IN-PU) Description DSWVRMEN Description
01: reserved
[6:5] PCI Express Bifurcation High Topblock swap mode: Disable DEFAULT High Enable DEFAULT
10: 2x8 PCI Express
11: 1x16 PCI Express
Default Low Topblock swap mode: Enable Low Disable
No Reboot Mode Digital Port C Strap

SPKR
(IN-PD) Description DDPC_CTRLDATA Description
C C
High No reboot mode: Enable High Configure Port C DEFAULT
Low No reboot mode: Disable DEFAULT Low Disable
Integrated 1.05V VRM
INTVRMEN Description
High Integrated 1.05V VRM: Enable DEFAULT

PIN NAME NET Strapping description
Low Integrated 1.05V VRM: Disable
C_CK505_33M_PCI2
1 Overclocking DISABLED DEFAULT
PCI2/TME
(PIN4) 0 Overclocking ENABLED TLS Confidentiality
C_CK505_33M_PCI4
1 SRC5 DEFAULT GPIO15
PCI4/SRC5_EN (IN-PD) Description
(PIN6) 0 CPU_STOP# and PCI_STOP#
ME Crypto TLS cipher suite
C_CK505_33M_PCI5
1 CPU_ITP High with confidentiality
PCIF5/ITP_EN
(PIN7) 0 SRC8 DEFAULT
Low
ME Crypto TLS cipher suite
with no confidentiality DEFAULT
See CFG Table DEFAULT
B
C_CK505_33M_PCI3
Low (Set SATA and SRC come from PLL4) B
PCI3/CFGP Flash Descriptor Override Strap
(PIN5) Mid See CFG Table
High See CFG Table HDA_SDO Description

Flash descriptor security
High will be override
Low Disable ME in Manufacturing Mode DEFAULT
SIO SMSC5545 DMI Rx Termination Voltage

PIN NAME NET Strapping description SPI_MOSI
(IN-PD) Description
1 Diag_En Disable
GP070 / PWM4 O_SPEAKER
(PIN127) 0 Diag_En Enable DEFAULT Low DMI Rx Termination Voltage DEFAULT
DTR1# [TEST_EN] 1 PE BOOT Loader Strap (DTR1#)= Load from SPI
/GP051 O_DTR1#_R DMI Termination Voltage
(PIN104) 0 PE BOOT Loader Strap (DTR1#)= No Load from SPI DEFAULT
NV_CLE
(IN-PU) Description
DMI and FDI Tx/Rx
High Termination Voltage DEFAULT
A A
Title
GPIO/IRQ/IDSEL Table
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
GPIO Table
DWG NO Rev
Lanikai _MT/DT A00

5 4 3 2 1
5 4 3 2 1
RH4 usage 1kOhm ; CRB 0.7-12/10/09

UH1E
Removed RH3; CRB 0.7-12/29/09
Dummy RH6 ; CRB 0.7-12/28/09
Removed RH7; CRB 0.7-12/10/09
W2 P34 +1P05V_VCCIO
27 C_PE_100M_MCP BCLK0 VCCSA_VID H_VCCSA_VID 70
W1 T2
27 C_PE_100M_MCP# BCLK0* VCCSA_SENSE H_VCCSA_SENSE 70
RO40change reference to
A36 RH7 and move from SIO to
H_VIDSCLK C37 VCC_SENSE B36 H_VCC_SENSE 67
RH2 change to 44.2 ; H_VIDSOUT B37 VIDSCLK VSS_SENSE H_VSS_SENSE 67 CPU side ; CRB *RH7 *RH4 *RH5 *RH6
**
H_VIDALERT# RH2 44.2Ohm A37 VIDSOUT AB4 0.7-12/29/09 51 Ohm 51 Ohm 51 Ohm
CRB0.7 12/07/09 1K
+/-1% VIDALERT* VCCIO_SENSE AB3 H_VCCTT_SENSE 69 Dummy Dummy Dummy
RH1 49.9 VSSIO_SENSE H_VSSTT_SENSE 69
D +1P05V_VCCIO D
Dummy +/-1% J40 L32 H_PROCHOT#
24,52,64 H_PWRGD UNCOREPWRGOOD VCCAXG_SENSE H_VCCAGX_SENSE 67
M32 H_PECI
H_RESET#_R F36 VSSAXG_SENSE H_VSSAGX_SENSE 67 +3V_S5 H_THERMTRIP#
Change net name to RESET*
H_RESET#-12/28/09 L39 H_CATERR
E38 TDO L40 H_TDO 52
23 H_PM_SYNC PM_SYNC TDI H_TDI 52
J35 M40
23,32 H_PECI
H_CATERR E37 PECI
CATERR*
TCK
TMS
L38 H_TCK
H_TMS
52
52
*RH66
220
H34 J39 +/-5%
32,67 H_PROCHOT# PROCHOT* TRST* H_TRST# 52
G35 K38 Dummy
23 H_THERMTRIP# THERMTRIP* PRDY* K40 H_PRDY# 52
AJ33 PREQ* E39 H_PREQ# 52
23,24 H_SKTOCC# SKTOCC* DBR* FP_RST# 24,52,53
H_PROC_SEL K32 C40 +1P05V_VCCIO
52 H_CFG0 PROC_SEL RSVD36 D40 H_ITPCLK 52
Add RH66 pull-up to +3V_DUAL;
******************
RSVD0 H_ITPCLK# 52
Add off-page toXDP; CRB 0.7 RH10 1.5K Dummy H_CFG0 H36
CFG0 CRB 0.7-12/10/09 Close to
12/27/09 RH11 1.5K Dummy H_CFG1 J36 H40
XDPRH18
Conn
*
RH12 1.5K Dummy H_CFG2 J37 CFG1 BPM0* H38 H_BPM#0 52 H_TDO 51 Ohm
RH13 1.5K Dummy H_CFG3 K36 CFG2 BPM1* G38 H_BPM#1 52
RH14 1.5K Dummy H_CFG4 L36 CFG3 BPM2* G40 H_BPM#2 52
RH15 1.5K Dummy H_CFG5 N35 CFG4 BPM3* G39 H_BPM#3 52
****
RH16 1.5K Dummy H_CFG6 L37 CFG5 BPM4* F38 H_BPM#4 52 H_TDI RH21 51 Ohm
RH19 1.5K Dummy H_CFG7 M36 CFG6 BPM5* E40 H_BPM#5 52 H_TMS RH23 51 Ohm
RH20 1.5K Dummy H_CFG8 J38 CFG7 BPM6* F40 H_BPM#6 52 H_TCK RH25 51 Ohm
RH22 1.5K Dummy H_CFG9 L35 CFG8 BPM7* H_BPM#7 52 H_TRST# RH27 51 Ohm
RH24 1.5K Dummy H_CFG10 M38 CFG9
CFG10
RH26 1.5K Dummy H_CFG11 N36
CFG11 RSVD1
AB6 Close to
RH28 1.5K Dummy H_CFG12 N38 AB7
RH29 1.5K Dummy H_CFG13 N39 CFG12 RSVD2 AD37 CPU
RH30 1.5K Dummy H_CFG14 N37 CFG13 RSVD3 AE6
C RH31 1.5K Dummy H_CFG15 N40 CFG14 RSVD4 AF4 C
CFG15 RSVD5
20100107:
RH32 1.5K Dummy H_CFG16 G37 AG4 Remove test points
RH33 1.5K Dummy H_CFG17 G36 CFG16 RSVD6 AJ11
CFG17 RSVD7 AJ29
A38 RSVD8 AJ30
AU40 NCTF0 RSVD9 AJ31
AW38 NCTF1 RSVD10 AN20
C2 NCTF2 RSVD11 AP20
*
D1 NCTF3 RSVD12 AT11 RH35 0 RH61 750
NCTF4 RSVD13 32 H_RESET# H_RESET#_R 52
AT14 +/-1%
AH1 RSVD14 AU10
18 H_CPU_DIMM_VREF_B
16 H_CPU_DIMM_VREF_A
AH4 FC_AH1
FC_AH4
RSVD15
RSVD16
AV34 +3V_DUAL *RH62
316
AW34 +/-1%
AV1 RSVD17 AY10
RSVD_NCTF0 RSVD18
MISC
AW2 C38 CH2 0.1uF
AY3 RSVD_NCTF1 RSVD19 C39
RSVD_NCTF2 RSVD20 D38 16V, X7R, +/-10%
RSVD21
5
H7 UH2 Change H_RESET# source from SIO
R34 RSVD22 H8 1
R36 RSVD40 RSVD23 J33
24,32,34,46,52,53 S_PLTRST#
4
directly-12/28/09
R38 RSVD41 RSVD24 J34 2 Dummy
RSVD42 RSVD25 20100104: add UH2 to prevent SIO
R40 J9
J31 RSVD43 RSVD26 K34
can't use
3
AD34 RSVD44 RSVD27 K9 74AHCT1G08GW
AD35 RSVD45 RSVD28 L31
H_PWRGD K31 RSVD46 RSVD29 L33
RSVD47 RSVD30 L34
RSVD31 L9
B
*RH58 RSVD32
RSVD33
M34
B
1K N33
RSVD34 N34
RSVD35 P33 H_VCCIO_SEL +1P8V_SFR
VCCP_SELECT P35
RSVD37 P37
RSVD38 P39
20100709: Reserve RH58 connect H_PWRGD to GND RSVD39 *RH60
5/10 2.2K
*
25 M_NVR_CLE RH17 H_PROC_SEL
4.7K
PE115527-4041-0DF CH11
0.1uF
16V, X7R, +/-10%
Dummy
+5V RH17 change to 4.7k; CRB 0.7-11/30/09

+1P05V_VCCIO 20100709: Reserve CH11 connect H_PROC_SEL to GND
*RH37
10K
RH38 * RH39 * RH40 * H_VCCIO_SEL 69
91 Ohm 110Ohm 75
+/-1% +/-1% +/-1%
Dummy *RH34
4.7K
67 H_VIDSCLK
67 H_VIDSOUT
A 67 H_VIDALERT# A
Remove CH1,CH2-12/29/09 Add H_VCCIO_SEL circuit; CRB 0.7-12/03/09

RH39 change to 110 ohm; CRB 0.7-11/30/09
Title
CPU-1: MISC
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
UH1C
38 X_1X16_RXP[15..0] X_1X16_TXP[15..0] 38
X_1X16_RXP0 B11 C13 X_1X16_TXP0
38 X_1X16_RXN[15..0] PEG_RX0 PEG_TX0 X_1X16_TXN[15..0] 38
X_1X16_RXN0 B12 C14 X_1X16_TXN0
X_1X16_RXP1 D12 PEG_RX0* PEG_TX0* E14 X_1X16_TXP1
X_1X16_RXN1 D11 PEG_RX1 PEG_TX1 E13 X_1X16_TXN1
X_1X16_RXP2 C10 PEG_RX1* PEG_TX1* G14 X_1X16_TXP2
D D
X_1X16_RXN2 C9 PEG_RX2 PEG_TX2 G13 X_1X16_TXN2
UH1D X_1X16_RXP3 E10 PEG_RX2* PEG_TX2* F12 X_1X16_TXP3
X_1X16_RXN3 E9 PEG_RX3 PEG_TX3 F11 X_1X16_TXN3
AC5 AC8 X_1X16_RXP4 B8 PEG_RX3* PEG_TX3* J14 X_1X16_TXP4
25 H_FDI_FSYNC0 FDI_FSYNC0 FDI_TX0 H_FDI_TXP0 25 PEG_RX4 PEG_TX4
AC4 AC7 X_1X16_RXN4 B7 J13 X_1X16_TXN4
25 H_FDI_LSYNC0 FDI_LSYNC0 FDI_TX0* H_FDI_TXN0 25 PEG_RX4* PEG_TX4*
AC2 X_1X16_RXP5 C6 D8 X_1X16_TXP5
FDI_TX1 H_FDI_TXP1 25 PEG_RX5 PEG_TX5
PEG
AC3 X_1X16_RXN5 C5 D7 X_1X16_TXN5
AE5 FDI_TX1* AD2 H_FDI_TXN1 25 X_1X16_RXP6 A5 PEG_RX5* PEG_TX5* D3 X_1X16_TXP6
25 H_FDI_FSYNC1 FDI_FSYNC1 FDI_TX2 H_FDI_TXP2 25 PEG_RX6 PEG_TX6
AE4 AD1 X_1X16_RXN6 A6 C3 X_1X16_TXN6
25 H_FDI_LSYNC1 FDI_LSYNC1 FDI_TX2* H_FDI_TXN2 25 PEG_RX6* PEG_TX6*
AD4 X_1X16_RXP7 E2 E6 X_1X16_TXP7
FDI_TX3 AD3 H_FDI_TXP3 25 X_1X16_RXN7 E1 PEG_RX7 PEG_TX7 E5 X_1X16_TXN7
FDI_TX3* H_FDI_TXN3 25 PEG_RX7* PEG_TX7*
FDI
AG3 X_1X16_RXP8 F4 F8 X_1X16_TXP8
25 H_FDI_INT FDI_INT PEG_RX8 PEG_TX8
AD7 X_1X16_RXN8 F3 F7 X_1X16_TXN8
FDI_TX4 AD6 H_FDI_TXP4 25 X_1X16_RXP9 G2 PEG_RX8* PEG_TX8* G10 X_1X16_TXP9
FDI_TX4* AE7 H_FDI_TXN4 25 X_1X16_RXN9 G1 PEG_RX9 PEG_TX9 G9 X_1X16_TXN9
FDI_TX5 AE8 H_FDI_TXP5 25 X_1X16_RXP10 H3 PEG_RX9* PEG_TX9* G5 X_1X16_TXP10
*
RH41 24.9 AE2 FDI_TX5* AF3 H_FDI_TXN5 25 X_1X16_RXN10 H4 PEG_RX10 PEG_TX10 G6 X_1X16_TXN10
+1P05V_VCCIO FDI_COMPIO FDI_TX6 H_FDI_TXP6 25 PEG_RX10* PEG_TX10*
+/-1% AF2 X_1X16_RXP11 J1 K7 X_1X16_TXP11
FDI_TX6* AG2 H_FDI_TXN6 25 X_1X16_RXN11 J2 PEG_RX11 PEG_TX11 K8 X_1X16_TXN11
AE1 FDI_TX7 AG1 H_FDI_TXP7 25 X_1X16_RXP12 K3 PEG_RX11* PEG_TX011 J5 X_1X16_TXP12
FDI_ICOMPO FDI_TX7* H_FDI_TXN7 25 X_1X16_RXN12 K4 PEG_RX12 PEG_TX12 J6 X_1X16_TXN12
X_1X16_RXP13 L1 PEG_RX12* PEG_TX12* M8 X_1X16_TXP13
4/10 PEG_RX13 PEG_TX13
X_1X16_RXN13 L2 M7 X_1X16_TXN13
X_1X16_RXP14 M3 PEG_RX13* PEG_TX13* L6 X_1X16_TXP14
PE115527-4041-0DF PEG_RX14 PEG_TX14
X_1X16_RXN14 M4 L5 X_1X16_TXN14
X_1X16_RXP15 N1 PEG_RX14* PEG_TX14* N5 X_1X16_TXP15
X_1X16_RXN15 N2 PEG_RX15 PEG_TX15 N6 X_1X16_TXN15
PEG_RX15* PEG_TX15*
C C
W5 V7
22 H_DMI_RXP0 DMI_RX0 DMI_TX0 H_DMI_TXP0 22
W4 V6
22 H_DMI_RXN0 DMI_RX0* DMI_TX0* H_DMI_TXN0 22
V3 W7
DMI
V4 W8
Y3 Y6
Y4 Y7
AA4 AA7
AA5 AA8
P3 P8
P4 PE_RX0 PE_TX0 P7
R2 PE_RX0* PE_TX0* T7
PE_RX1 PE_TX1
GEN
R1 T8
T4 PE_RX1* PE_TX1* R6
T3 PE_RX2 PE_TX2 R5
U2 PE_RX2* PE_TX2* U5
U1 PE_RX3 PE_TX3 U6
PE_RX3* PE_TX3*
*
B B4 RH42 24.9 B
PEG_COMPI +1P05V_VCCIO
B5 +/-1%
PEG_ICOMPO C4
PEG_RCOMPO
3/10
PE115527-4041-0DF
A A
Title
CPU-2: FDI/PCIe/DMI
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
UH1A
15,16 D3_MAA[15..0] D3_MAA0 AV27 AK3
SA_MA0 SA_DQS0 D3_DQS_A0 15,16
D3_MAA1 AY24 AK2
SA_MA1 SA_DQS0* D3_DQS_A#0 15,16
D3_MAA2 AW24
D3_MAA3 AW23 SA_MA2
D3_MAA4 AV23 SA_MA3 AJ3 D3_DQ_A0
SA_MA4 SA_DQ0 D3_DQ_A[63..0] 15,16
D3_MAA5 AT24 AJ4 D3_DQ_A1
D3_MAA6 AT23 SA_MA5 SA_DQ1 AL3 D3_DQ_A2
D3_MAA7 AU22 SA_MA6 SA_DQ2 AL4 D3_DQ_A3
D3_MAA8 AV22 SA_MA7 SA_DQ3 AJ2 D3_DQ_A4
D3_MAA9 AT22 SA_MA8 SA_DQ4 AJ1 D3_DQ_A5
D3_MAA10 AV28 SA_MA9 SA_DQ5 AL2 D3_DQ_A6
D3_MAA11 AU21 SA_MA10 SA_DQ6 AL1 D3_DQ_A7
D D
D3_MAA12 AT21 SA_MA11 SA_DQ7
D3_MAA13 AW32 SA_MA12 AP3
SA_MA13 SA_DQS1 D3_DQS_A1 15,16
D3_MAA14 AU20 AP2
SA_MA14 SA_DQS1* D3_DQS_A#1 15,16
D3_MAA15 AT20
SA_MA15
AW29 AN1 D3_DQ_A8
15,16 D3_WEA# AV30 SA_WE* SA_DQ8 AN4 D3_DQ_A9
15,16 D3_CASA# AU28 SA_CAS* SA_DQ9 AR3 D3_DQ_A10
15,16 D3_RASA# SA_RAS* SA_DQ10 AR4 D3_DQ_A11
15,16 D3_BAA[2..0] D3_BAA0 AY29 SA_DQ11 AN2 D3_DQ_A12
D3_BAA1 AW28 SA_BS0 SA_DQ12 AN3 D3_DQ_A13
D3_BAA2 AV20 SA_BS1 SA_DQ13 AR2 D3_DQ_A14
SA_BS2 SA_DQ14 AR1 D3_DQ_A15
SA_DQ15
AU29 AW4
15 D3_SCS_A#0 SA_CS0* SA_DQS2 D3_DQS_A2 15,16
AV32 AV4
15 D3_SCS_A#1 SA_CS1* SA_DQS2* D3_DQS_A#2 15,16
AW30
16 D3_SCS_A#2 AU33 SA_CS2*
16 D3_SCS_A#3 SA_CS3* AV2 D3_DQ_A16
SA_DQ16 AW3 D3_DQ_A17
AV19 SA_DQ17 AV5 D3_DQ_A18
15 D3_CKE_A0 AT19 SA_CKE0 SA_DQ18 AW5 D3_DQ_A19
15 D3_CKE_A1 AU18 SA_CKE1 SA_DQ19 AU2 D3_DQ_A20
16 D3_CKE_A2 AV18 SA_CKE2 SA_DQ20 AU3 D3_DQ_A21
16 D3_CKE_A3 SA_CKE3 SA_DQ21 AU5 D3_DQ_A22
SA_DQ22 AY5 D3_DQ_A23
AV31 SA_DQ23
15 D3_ODT_A0 AU32 SA_ODT0 AV8
15 D3_ODT_A1 SA_ODT1 SA_DQS3 D3_DQS_A3 15,16
C AU30 AW8 C
16 D3_ODT_A2 SA_ODT2 SA_DQS3* D3_DQS_A#3 15,16
AW33
16 D3_ODT_A3 SA_ODT3
AY7 D3_DQ_A24
AY25 SA_DQ24 AU7 D3_DQ_A25
15 D3_MA_CLK0 SA_CK0 SA_DQ25
DDR_A
AW25 AV9 D3_DQ_A26
15 D3_MA_CLK#0 AU24 SA_CK0* SA_DQ26 AU9 D3_DQ_A27
15 D3_MA_CLK1 AU25 SA_CK1 SA_DQ27 AV7 D3_DQ_A28
15 D3_MA_CLK#1 AW27 SA_CK1* SA_DQ28 AW7 D3_DQ_A29
16 D3_MA_CLK2 AY27 SA_CK2 SA_DQ29 AW9 D3_DQ_A30
16 D3_MA_CLK#2 AV26 SA_CK2* SA_DQ30 AY9 D3_DQ_A31
16 D3_MA_CLK3 AW26 SA_CK3 SA_DQ31
16 D3_MA_CLK#3 SA_CK3* AV37
SA_DQS4 D3_DQS_A4 15,16
AV36
SA_DQS4* D3_DQS_A#4 15,16
RH8 1 2 Dummy AW18
15,16,17,18 D3_RESET# SM_DRAMRST*
AU35
* CH47 D3_DQ_A32
*
SA_DQ32
Add RC 0.1uF
24 H_DRAMPWRGD
RH51 120Ohm AJ19
SM_DRAMPWROK SA_DQ33
AW37 D3_DQ_A33
Dummy +/-5% AU39 D3_DQ_A34
filter;CRB 16V, X7R, +/-10% SA_DQ34 AU36 D3_DQ_A35
SA_DQ35
0.7-11/30/09 H_SM_VREF AJ22
SM_VREF SA_DQ36
AW35
AY36
D3_DQ_A36
D3_DQ_A37
SA_DQ37 AU38 D3_DQ_A38
SA_DQ38 AU37 D3_DQ_A39
AV13 SA_DQ39
15,16 D3_DQS_A8 SA_DQS8
AV12 AP38
15,16 D3_DQS_A#8 SA_DQS8* SA_DQS5 D3_DQS_A5 15,16
AP39 +1P5V_SM
D3_ECC_CB_A0 AU12
B D3_ECC_CB_A1 AU14 SA_ECC_CB0 AR40 D3_DQ_A40 B
D3_ECC_CB_A2 AW13 SA_ECC_CB1
SA_ECC_CB2
SA_DQ40
SA_DQ41
AR37 D3_DQ_A41 *RH43
100 Ohm
D3_ECC_CB_A3 AY13 AN38 D3_DQ_A42 +/-1%
D3_ECC_CB_A4 AU13 SA_ECC_CB3 SA_DQ42 AN37 D3_DQ_A43
D3_ECC_CB_A5 AU11 SA_ECC_CB4 SA_DQ43 AR39 D3_DQ_A44
D3_ECC_CB_A6 AY12 SA_ECC_CB5 SA_DQ44 AR38 D3_DQ_A45 H_SM_VREF
D3_ECC_CB_A7 AW12 SA_ECC_CB6 SA_DQ45 AN39 D3_DQ_A46
SA_ECC_CB7 SA_DQ46 AN40 D3_DQ_A47
SA_DQ47
15,16 D3_ECC_CB_A[7..0]
SA_DQS6
AK38
D3_DQS_A6 15,16
* CH3
0.1uF *RH44
100 Ohm
AK39 16V, X7R, +/-10% +/-1%
RH43,RH44 is 1k
AL40 D3_DQ_A48
SA_DQ48 AL37 D3_DQ_A49 in PDG; 100 in
SA_DQ49
SA_DQ50
AJ38
AJ37
D3_DQ_A50
D3_DQ_A51
CRB
SA_DQ51 AL39 D3_DQ_A52
SA_DQ52
RH43,RH44 usage 100 Ohm follow CRB;
AL38 D3_DQ_A53 CRB 0.7-12/10/09
SA_DQ53 AJ39 D3_DQ_A54
SA_DQ54 AJ40 D3_DQ_A55
SA_DQ55
AF38
SA_DQS7 D3_DQS_A7 15,16
AF39
AG40 D3_DQ_A56
SA_DQ56 AG37 D3_DQ_A57
SA_DQ57 AE38 D3_DQ_A58
A SA_DQ58 A
AE37 D3_DQ_A59
SA_DQ59 AG39 D3_DQ_A60
SA_DQ60
1/10
AG38 D3_DQ_A61
SA_DQ63 Title
PE115527-4041-0DF
CPU-3: DDR3_CHA
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
UH1B
17,18 D3_MAB[15..0] D3_MAB0 AK24 AH7
SB_MA0 SB_DQS0 D3_DQS_B0 17,18
D3_MAB1 AM20 AH6
SB_MA1 SB_DQS0* D3_DQS_B#0 17,18
D3_MAB2 AM19
D3_MAB3 AK18 SB_MA2
D3_MAB4 AP19 SB_MA3 AG7 D3_DQ_B0
SB_MA4 SB_DQ0 D3_DQ_B[63..0] 17,18
D3_MAB5 AP18 AG8 D3_DQ_B1
D3_MAB6 AM18 SB_MA5 SB_DQ1 AJ9 D3_DQ_B2
D3_MAB7 AL18 SB_MA6 SB_DQ2 AJ8 D3_DQ_B3
D3_MAB8 AN18 SB_MA7 SB_DQ3 AG5 D3_DQ_B4
D3_MAB9 AY17 SB_MA8 SB_DQ4 AG6 D3_DQ_B5
D D
D3_MAB10 AN23 SB_MA9 SB_DQ5 AJ6 D3_DQ_B6
D3_MAB11 AU17 SB_MA10 SB_DQ6 AJ7 D3_DQ_B7
D3_MAB12 AT18 SB_MA11 SB_DQ7
D3_MAB13 AR26 SB_MA12 AM8
SB_MA13 SB_DQS1 D3_DQS_B1 17,18
D3_MAB14 AY16 AL8
SB_MA14 SB_DQS1* D3_DQS_B#1 17,18
D3_MAB15 AV16
SB_MA15
AR25 AL7 D3_DQ_B13
17,18 D3_WEB# AK25 SB_WE* SB_DQ8 AM7 D3_DQ_B9
17,18 D3_CASB# AP24 SB_CAS* SB_DQ9 AM10 D3_DQ_B11
DQ REMAPPING IMPLEMENTED
17,18 D3_RASB# SB_RAS* SB_DQ10
17,18 D3_BAB[2..0]
AP23 SB_DQ11
AL10
AL6
D3_DQ_B15 TO IMPROVE BREAKOUT AND
D3_BAB0 D3_DQ_B12
D3_BAB1 AM24 SB_BS0
SB_BS1
SB_DQ12
SB_DQ13
AM6 D3_DQ_B8 MINIMIZE CH-2-CH COUPLING
D3_BAB2 AW17 AL9 D3_DQ_B14
SB_BS2 SB_DQ14 AM9 D3_DQ_B10
SB_DQ15
AN25 AR8
17 D3_SCS_B#0 SB_CS0* SB_DQS2 D3_DQS_B2 17,18
AN26 AP8
17 D3_SCS_B#1 SB_CS1* SB_DQS2* D3_DQS_B#2 17,18
AL25
18 D3_SCS_B#2 AT26 SB_CS2*
18 D3_SCS_B#3 SB_CS3* AP7 D3_DQ_B16
SB_DQ16 AR7 D3_DQ_B17
AU16 SB_DQ17 AP10 D3_DQ_B18
17 D3_CKE_B0 AY15 SB_CKE0 SB_DQ18 AR10 D3_DQ_B19
17 D3_CKE_B1 AW15 SB_CKE1 SB_DQ19 AP6 D3_DQ_B20
18 D3_CKE_B2 AV15 SB_CKE2 SB_DQ20 AR6 D3_DQ_B21
18 D3_CKE_B3 SB_CKE3 SB_DQ21 AP9 D3_DQ_B22
C AL26 SB_DQ23 C
17 D3_ODT_B0 AP26 SB_ODT0 AN13
17 D3_ODT_B1 SB_ODT1 SB_DQS3 D3_DQS_B3 17,18
AM26 AN12
18 D3_ODT_B2 SB_ODT2 SB_DQS3* D3_DQS_B#3 17,18
AK26
18 D3_ODT_B3 SB_ODT3
AM12 D3_DQ_B24
AL21 SB_DQ24 AM13 D3_DQ_B25
17 D3_MB_CLK0 AL22 SB_CK0 SB_DQ25 AR13 D3_DQ_B26
17 D3_MB_CLK#0 AL20 SB_CK0* SB_DQ26 AP13 D3_DQ_B27
17 D3_MB_CLK1 SB_CK1 SB_DQ27
DDR_B
AK20 AL12 D3_DQ_B28
17 D3_MB_CLK#1 AL23 SB_CK1* SB_DQ28 AL13 D3_DQ_B29
18 D3_MB_CLK2 AM22 SB_CK2 SB_DQ29 AR12 D3_DQ_B30
18 D3_MB_CLK#2 AP21 SB_CK2* SB_DQ30 AP12 D3_DQ_B31
18 D3_MB_CLK3 AN21 SB_CK3 SB_DQ31
18 D3_MB_CLK#3 SB_CK3* AN29
SB_DQS4 D3_DQS_B4 17,18
AN28
SB_DQS4* D3_DQS_B#4 17,18
AR28 D3_DQ_B32
SB_DQ33 AL28 D3_DQ_B34
SB_DQ35 AP28 D3_DQ_B36
SB_DQ36 AP29 D3_DQ_B37
SB_DQ37 AM28 D3_DQ_B38
AN16 SB_DQ39
17,18 D3_DQS_B8 SB_DQS8
AN15 AP33
17,18 D3_DQS_B#8 SB_DQS8* SB_DQS5 D3_DQS_B5 17,18
AR33
B SB_DQS5* D3_DQS_B#5 17,18 B
D3_ECC_CB_B0 AL16
D3_ECC_CB_B1 AM16 SB_ECC_CB0 AP32 D3_DQ_B40
D3_ECC_CB_B2 AP16 SB_ECC_CB1 SB_DQ40 AP31 D3_DQ_B41
D3_ECC_CB_B3 AR16 SB_ECC_CB2 SB_DQ41 AP35 D3_DQ_B42
D3_ECC_CB_B4 AL15 SB_ECC_CB3 SB_DQ42 AP34 D3_DQ_B43
D3_ECC_CB_B5 AM15 SB_ECC_CB4 SB_DQ43 AR32 D3_DQ_B44
D3_ECC_CB_B6 AR15 SB_ECC_CB5 SB_DQ44 AR31 D3_DQ_B45
D3_ECC_CB_B7 AP15 SB_ECC_CB6 SB_DQ45 AR35 D3_DQ_B46
SB_ECC_CB7 SB_DQ46 AR34 D3_DQ_B47
SB_DQ47
17,18 D3_ECC_CB_B[7..0]
AL33
AM33
AM32 D3_DQ_B48
DQ REMAPPING IMPLEMENTED
SB_DQ50
SB_DQ51
AL32
AM34
D3_DQ_B51 TO IMPROVE BREAKOUT AND
D3_DQ_B54
SB_DQ52
SB_DQ53
AL31 D3_DQ_B49 MINIMIZE CH-2-CH COUPLING
AM35 D3_DQ_B53
SB_DQ55
AG35
AG34
A
AH35 D3_DQ_B56 A
SB_DQ56 AH34 D3_DQ_B57
SB_DQ57 AE34 D3_DQ_B58
SB_DQ58 AE35 D3_DQ_B59
SB_DQ59 AJ35 D3_DQ_B60
SB_DQ60 AJ34 D3_DQ_B61
SB_DQ61
2/10
AF33 D3_DQ_B62 Title

SB_DQ62 AF35 D3_DQ_B63
SB_DQ63 CPU-4: DDR3_CHB
DWG NO Rev
PE115527-4041-0DF
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+VCORE
UH1F +1P05V_VCCIO +V_VCCSA +1P1V_AXG +1P5V_SM
A12 F31
A13 VCC_1 VCC_81 F32
A16 VCC_4 VCC_84 G15 UH1G UH1H
A18 VCC_5 VCC_85 G16
D D
A24 VCC_6 VCC_86 G18 AB33 AJ13
A25 VCC_7 VCC_87 G19 A11 H10 AB34 VAXG_1 VDDQ_1 AJ14
A27 VCC_8 VCC_88 G21 A7 VCCIO_1 VCCSA_1 H11 AB35 VAXG_2 VDDQ_2 AJ20
A28 VCC_9 VCC_89 G22 AA3 VCCIO_2 VCCSA_2 H12 AB36 VAXG_3 VDDQ_3 AJ23
B15 VCC_10 VCC_90 G24 AB8 VCCIO_3 VCCSA_3 J10 AB37 VAXG_4 VDDQ_6 AJ24
B16 VCC_11 VCC_91 G25 AF8 VCCIO_4 VCCSA_4 K10 AB38 VAXG_5 VDDQ_4 AR20
B18 VCC_12 VCC_92 G27 AG33 VCCIO_5 VCCSA_5 K11 AB39 VAXG_6 VDDQ_5 AR21
B24 VCC_13 VCC_93 G28 AJ16 VCCIO_6 VCCSA_6 L11 AB40 VAXG_7 VDDQ_7 AR22
B25 VCC_14 VCC_94 G30 AJ17 VCCIO_7 VCCSA_7 L12 AC33 VAXG_8 VDDQ_8 AR23
B27 VCC_15 VCC_95 G31 AJ26 VCCIO_8 VCCSA_8 M10 AC34 VAXG_9 VDDQ_9 AR24
B28 VCC_16 VCC_96 G32 AJ28 VCCIO_9 VCCSA_9 M11 AC35 VAXG_10 VDDQ_10 AU19
B30 VCC_17 VCC_97 G33 AJ32 VCCIO_10 VCCSA_10 M12 AC36 VAXG_11 VDDQ_11 AU23
B31 VCC_18 VCC_98 H13 AK15 VCCIO_11 VCCSA_11 AC37 VAXG_12 VDDQ_12 AU27
B33 VCC_19 VCC_99 H14 AK17 VCCIO_12 AC38 VAXG_13 VDDQ_13 AU31
B34 VCC_20 VCC_100 H15 AK19 VCCIO_13 AC39 VAXG_14 VDDQ_14 AV21
C15 VCC_21 VCC_101 H16 AK21 VCCIO_14 AC40 VAXG_15 VDDQ_15 AV24
C16 VCC_22 VCC_102 H18 AK23 VCCIO_15 T33 VAXG_16 VDDQ_16 AV25
C21 VCC_25 VCC_105 H22 AK30 VCCIO_18 T36 VAXG_19 VDDQ_19 AW31
C22 VCC_26 VCC_106 H24 B9 VCCIO_19 T37 VAXG_20 VDDQ_20 AY23
VCC_27 VCC_107 VCCIO_20 VAXG_21 VDDQ_21
CPU POWER
MCH POWER
C24 H25 D10 T38 AY26
C25 VCC_28 VCC_108 H27 D6 VCCIO_21 T39 VAXG_22 VDDQ_22 AY28
C27 VCC_29 VCC_109 H28 E3 VCCIO_22 T40 VAXG_23 VDDQ_23
C28 VCC_30 VCC_110 H30 E4 VCCIO_23 U33 VAXG_24
C30 VCC_31 VCC_111 H31 G3 VCCIO_24 U34 VAXG_25
C31 VCC_32 VCC_112 H32 G4 VCCIO_25 U35 VAXG_26
C33 VCC_33 VCC_113 J12 J3 VCCIO_26 U36 VAXG_27
C C34 VCC_34 VCC_114 J15 J4 VCCIO_27 +1P8V_SFR U37 VAXG_28 C
VCC_35 VCC_115 VCCIO_28 VAXG_29
CPU POWER
C36 J16 J7 U38

D13 VCC_36 VCC_116 J18 J8 VCCIO_29 U39 VAXG_30
D14 VCC_37 VCC_117 J19 L3 VCCIO_30 U40 VAXG_31
D15 VCC_38 VCC_118 J21 L4 VCCIO_31 AK11 W33 VAXG_32
D16 VCC_39 VCC_119 J22 L7 VCCIO_32 VCCPLL_1 AK12 W34 VAXG_33
D18 VCC_40 VCC_120 J24 M13 VCCIO_33 VCCPLL_2 W35 VAXG_34
D19 VCC_41
VCC_42
VCC_121
VCC_122
J25 N3 VCCIO_34
VCCIO_35
* CH4
1uF W36 VAXG_35
VAXG_36
D21 J27 N4 16V, X5R, +/-10% W37
D22 VCC_43 VCC_123 J28 N7 VCCIO_36 W38 VAXG_37
D24 VCC_44 VCC_124 J30 R3 VCCIO_37 Y33 VAXG_38
D25 VCC_45 VCC_125 K15 R4 VCCIO_38 Y34 VAXG_39
D27 VCC_46 VCC_126 K16 R7 VCCIO_39 Y35 VAXG_40
D28 VCC_47 VCC_127 K18 U3 VCCIO_40 Y36 VAXG_41
D33 VCC_50 VCC_130 K22 V8 VCCIO_43 VAXG_44
D34 VCC_51 VCC_131 K24 W3 VCCIO_44
D35 VCC_52 VCC_132 K25 VCCIO_45
D36 VCC_53 VCC_133 K27
E15 VCC_54 VCC_134 K28
E16 VCC_55 VCC_135 K30
E18 VCC_56 VCC_136 L13
8/10
E19 VCC_57 VCC_137 L14
VCC_58 VCC_138 PE115527-4041-0DF
E21 L15
E22 VCC_59 VCC_139 L16
E24 VCC_60 VCC_140 L18
E25 VCC_61 VCC_141 L19
E27 VCC_62 VCC_142 L21 +1P05V_VCCIO +1P5V_SM
B E28 VCC_63 VCC_143 L22 B
E30 VCC_64 VCC_144 L24
E31 VCC_65 VCC_145 L25
E33 VCC_66 VCC_146 L27
E34 VCC_67
VCC_68
VCC_147
VCC_148
L28
7/10 * CH5
4.7uF * CH6
0.1uF * CH7
0.1uF * CH8
22uF * CH9
22uF
6.3V, X5R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
E35 L30 PE115527-4041-0DF
F15 VCC_69 VCC_149 M14
F16 VCC_70 VCC_150 M15
F18 VCC_71 VCC_151 M16
F19 VCC_72 VCC_152 M18
F21 VCC_73 VCC_153 M19
F22 VCC_74 VCC_154 M21
F24 VCC_75 VCC_155 M22
F25 VCC_76 VCC_156 M24
VCC_77 VCC_157
CLOSE TO CPU CLOSE TO CPU
F27 M25
F28 VCC_78 VCC_158 M27
F30 VCC_79 VCC_159 M28
VCC_80 VCC_160 M30
VCC_161
6/10
PE115527-4041-0DF
A A
Title
CPU-5: Power
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
UH1I UH1J
A17 AM27 AT8 F37

A23 VSS_1 VSS_91 AM3 AT9 VSS_171 VSS_257 F39
A26 VSS_2 VSS_92 AM30 AU1 VSS_172 VSS_258 F5
AA33 VSS_5 VSS_95 AM38 AU34 VSS_175 VSS_261 G11
D D
AA37 VSS_9 VSS_99 AM5 AV10 VSS_179 VSS_265 G23
AA38 VSS_10 VSS_100 AN10 AV11 VSS_180 VSS_266 G26
AA6 VSS_11 VSS_101 AN11 AV14 VSS_181 VSS_267 G29
AB5 VSS_12 VSS_102 AN14 AV17 VSS_182 VSS_268 G34
AC1 VSS_13 VSS_103 AN17 AV3 VSS_183 VSS_269 G7
AC6 VSS_14 VSS_104 AN19 AV35 VSS_184 VSS_270 G8
AD33 VSS_15 VSS_105 AN22 AV38 VSS_185 VSS_271 H1
AD36 VSS_16 VSS_106 AN24 AV6 VSS_186 VSS_272 H17
AD38 VSS_17 VSS_107 AN27 AW10 VSS_187 VSS_273 H2
AE3 VSS_22 VSS_112 AN34 AW6 VSS_192 VSS_278 H33
AE33 VSS_23 VSS_113 AN35 AY11 VSS_193 VSS_279 H35
AE36 VSS_24 VSS_114 AN36 AY14 VSS_194 VSS_280 H37
AF1 VSS_25 VSS_115 AN5 AY18 VSS_195 VSS_281 H39
AF40 VSS_29 VSS_119 AN9 AY8 VSS_199 VSS_285 J11
AF5 VSS_30 VSS_120 AP1 B10 VSS_200 VSS_286 J17
AG36 VSS_33 VSS_123 AP17 B17 VSS_203 VSS_289 J26
AH2 VSS_34 VSS_124 AP22 B23 VSS_204 VSS_290 J29
AH3 VSS_35 VSS_125 AP25 B26 VSS_205 VSS_291 J32
C AH33 VSS_36 VSS_126 AP27 B29 VSS_206 VSS_292 K1 C
AH36 VSS_37 VSS_127 AP30 B32 VSS_207 VSS_293 K12
AH37 VSS_38 VSS_128 AP36 B35 VSS_208 VSS_294 K13
AH38 VSS_39 VSS_129 AP37 B38 VSS_209 VSS_295 K14 UH1_B
AH39 VSS_40 VSS_130 AP4 B6 VSS_210 VSS_296 K17 UH1_1
VSS_41 VSS_131 VSS_211 VSS_297
GND
AH40 AP40 C11 K2

AH5 VSS_42 VSS_132 AP5 C12 VSS_212 VSS_298 K20
AH8 VSS_43 VSS_133 AR11 C17 VSS_213 VSS_299 K23
AJ12 VSS_44 VSS_134 AR14 C20 VSS_214 VSS_300 K26
AJ18 VSS_46 VSS_136 AR18 C26 VSS_216 VSS_302 K33 Retention Module
AJ25 VSS_48 VSS_138 AR27 C32 VSS_218 VSS_304 K37 ACA-ZIF-078-P05_A
VSS_49 VSS_139 VSS_219 VSS_305
GND
AJ27 AR30 C35 K39
AK1 VSS_52 VSS_142 AT1 D17 VSS_222 VSS_308 L10
AK31 VSS_59 VSS_149 AT2 D37 VSS_229 VSS_315 M1 <LBL>
AK32 VSS_60 VSS_150 AT25 D39 VSS_230 VSS_316 M17
VSS_63 VSS_153 VSS_233 VSS_319 2D lable
AK35 AT29 D9 M23
AK36 VSS_64 VSS_154 AT3 E11 VSS_234 VSS_320 M26
B AK37 VSS_65 VSS_155 AT30 E12 VSS_235 VSS_321 M29 B
VSS_71 VSS_161 VSS_241 VSS_327 MLH1 MLH2 MLH3 MLH4
AK8 AT36 E32 M6
AL11 VSS_73 VSS_163 AT38 E7 VSS_243 VSS_329 N8
AL14 VSS_74 VSS_164 AT39 E8 VSS_244 VSS_330 P1
AL17 VSS_75 VSS_165 AT4 F1 VSS_245 VSS_331 P2
AL36 VSS_80 VSS_170 F2 VSS_250 VSS_336 P6
AL5 VSS_81 F20 VSS_251 VSS_337 R33
VSS_82 B39 update to RSVD48; VSS_252 VSS_338
AM1 F23 R35
AM11 VSS_83 PDG 0.7-12/07/09 F26 VSS_253 VSS_339 R37
AM14 VSS_84 F29 VSS_254 VSS_340 R39
AM17 VSS_85 F35 VSS_255 VSS_341 R8
VSS_86
EDS: B39 defined "VSS_NCTF" VSS_256 VSS_342
AM2 CRB: B39 defined "RSVD" T1
AM21 VSS_87 TPH99 VSS_343 T5
AM23 VSS_88 B39 VSS_344 T6
VSS_89
Pin_B39 follow CRB pin define; RSVD48 VSS_345
AM25 CRB 0.7-12/10/09 A4 U8
VSS_90 AV39 VSS_NCTF2 VSS_346 V1
AY37 VSS_NCTF3 VSS_347 V2
9/10 VSS_NCTF4 VSS_348
B3 V33
VSS_NCTF5 VSS_349 V34
A PE115527-4041-0DF VSS_350 A
V35
VSS_351 V36
VSS_352 V37
VSS_353 V38
VSS_354 V39
VSS_355 V40 Title
VSS_356 V5
VSS_357
VSS_358
W6 CPU-6: GND
Y5
VSS_359 Y8 DWG NO Rev
10/10 VSS_360
A00
PE115527-4041-0DF Lanikai _MT/DT
5 4 3 2 1
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
CD8
CD1
0.1uF
CD13
0.1uF
CD11
4.7uF
+1P5V_SM
+1P5V_SM
+1P5V_SM
+1P5V_SM_VTT
240
Dummy
VTT
+1P5V_SM_VTT
RD3
RD1
120 68
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
* * 239
16V, X7R, +/-10%

16V, X7R, +/-10%
6.3V, X5R, +/-10%
235 VSS D3_ODT_A0
D3_ODT_A1
*
232 VSS
*
229 VSS
11
11
1K
1K
1uF
VSS
CD2
226
+/-1%
+/-1%
CLOSE TO DIMM POWER PIN
VSS
5
5
CD9
223 39 D3_ECC_CB_A0
*
0.1uF
SMB ADDRESS:000
VSS CB<0>
PLAECE CLOSE TO CH-A DIMM

220 40 D3_ECC_CB_A1
*
VSS CB<1>
CHANNEL A BANK 1
217 45 D3_ECC_CB_A2
1K
VSS CB<2>
RD2
214 46 D3_ECC_CB_A3
1K
+/-1%
VSS CB<3>
RD4
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_A4
+/-1%
208 VSS CB<4> 159 D3_ECC_CB_A5
16V, X7R, +/-10%
*
*
*
*
1uF
VSS CB<7>
CD3
199
0.1uF
CD12
166 VSS
0.1uF
CD10
163 VSS 7 D3_DQS_A0
0.1uF
CD14
160 VSS DQS0 6 D3_DQS_A#0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16 D3_DQS_A1
16V, X7R, +/-10%

16V, X7R, +/-10%

*
148 VSS DQS1
16V, X7R, +/-10%

145 VSS 25 D3_DQS_A2
*
1uF
VSS DQS2
CD4
142 24 D3_DQS_A#2
139 VSS DQS2
Change to 0.1uF; PDG 0.7-12/07/09

Dummy
2.2uF
CD51
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
127 85 D3_DQS_A4
D3_ECC_CB_A[7..0]

121 VSS DQS4
VSS 94 D3_DQS_A5
11,16
116 DQS5 93 D3_DQS_A#5
6.3V, Y5V, +80%/-20%

113 VSS DQS5
110 VSS 103 D3_DQS_A6
VSS DQS6
D3_CA_VREF_A 16
107 102 D3_DQS_A#6
D3_DQ_VREF_A 16
104 VSS DQS6
101 VSS 112 D3_DQS_A7
*
VSS DQS7
+3V
98 111 D3_DQS_A#7
4
4
Del CD52,CD53-12/29/09
95 VSS DQS7
1uF
VSS
CD6
92 43
89 VSS DQS8 42
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
16V, X5R, +/-10%

47 VSS DQS9
*
44 VSS 134
41 VSS DM1/DQS10 135
Add CD52,CD53; follow CRB 0.7-12/28/09

1uF
VSS DQS10
CD7
38
35 VSS 143
20100104: Remove CD5 10uF
CRB 0.7-12/29/09
CRB 0.7-12/10/09
29 VSS DQS11
26 VSS 152
VSS DM3/DQS12
6.3V,X5R,+/-10%
23 153
VSS DQS12
; CRB 0.7-12/10/09
20
17 VSS 203
11 VSS DQS13
SA_BS[2]-->Pin 52 (BA2)
SA_BS[0]-->Pin 71 (BA0)
VSS
SA_BS[1]-->Pin 190 (BA1)
8 212
5 VSS DM5/DQS14 213
D3_DQS_A[7..0]
VSS DQS14
D3_DQS_A#[7..0]
2
+1P5V_SM
VSS 221
DM6/DQS15
D3_DQS_A8 11,16
197 222
D3_DQS_A#8 11,16
VDDQ DQS15
11,16
194
11,16
191 VDDQ 230

189 VDDQ DM7/DQS16 231
VDDQ NC/DQS16
11
11
11
11
186
183 VDDQ 161
VDDQ DM8/DQS17
11,16 D3_BAA[2..0]
16,17,18,32,52 S_SMBCLK_MAIN
16,17,18,32,52 S_SMBDATA_MAIN
Del CD47 , CD48, CD49, CD50, CD51 and Dummy;

Add CD47 , CD48, CD49, CD50, CD51 and Dummy;
182 162
11,16 D3_MAA[15..0]
179 VDDQ DQS17
176 VDDQ 3 D3_DQ_A0
173 VDDQ DQ0 4 D3_DQ_A1
3
3
11 D3_CKE_A0
11 D3_CKE_A1
VDDQ DQ1
11 D3_SCS_A#0
11 D3_SCS_A#1
170 9 D3_DQ_A2
D3_MA_CLK0
D3_MA_CLK1
D3_MA_CLK#0
D3_MA_CLK#1

75 VDD DQ3 122 D3_DQ_A4
72 VDD DQ4 123 D3_DQ_A5
DDRIII
69 VDD DQ5 128 D3_DQ_A6

66 VDD DQ6 129 D3_DQ_A7
65 VDD DQ7 12 D3_DQ_A8
D3_BAA0
D3_BAA1
D3_BAA2
D3_MAA9
D3_MAA8
D3_MAA7
D3_MAA6
D3_MAA5
D3_MAA4
D3_MAA3
D3_MAA2
D3_MAA1
D3_MAA0
VDD DQ9
D3_MAA15
D3_MAA14
D3_MAA13
D3_MAA12
D3_MAA11
D3_MAA10 60 18 D3_DQ_A10
57 VDD DQ10 19 D3_DQ_A11
VDD DQ11
+3V
54 131 D3_DQ_A12
D3_CA_VREF_A
D3_DQ_VREF_A
51 VDD DQ12 132 D3_DQ_A13

236 VDD DQ13 137 D3_DQ_A14
VDDSPD DQ14 138 D3_DQ_A15
DQ15 21 D3_DQ_A16
67 DQ16 22 D3_DQ_A17
1 VREFCA DQ17 27 D3_DQ_A18
118 VREFDQ DQ18 28 D3_DQ_A19
238 SCL DQ19 140 D3_DQ_A20
119 SDA DQ20 141 D3_DQ_A21
237 SA2 DQ21 146 D3_DQ_A22
SA1 DQ22
000
117 147 D3_DQ_A23

SA0 DQ23 30 D3_DQ_A24
DQ24 31 D3_DQ_A25
52 DQ25 36 D3_DQ_A26
190 BA2 DQ26 37 D3_DQ_A27
71 BA1 DQ27 149 D3_DQ_A28
BA0 DQ28 150 D3_DQ_A29
DQ29 155 D3_DQ_A30
169 DQ30 156 D3_DQ_A31
50 CKE1 DQ31 81 D3_DQ_A32
CKE0 DQ32 82 D3_DQ_A33
DQ33
2
2
76 87 D3_DQ_A34
193 S1 DQ34 88 D3_DQ_A35
S0 DQ35 200 D3_DQ_A36
DQ36 201 D3_DQ_A37
64 DQ37 206 D3_DQ_A38
63 CK1/NU DQ38 207 D3_DQ_A39
185 CK1/NU DQ39 90 D3_DQ_A40
184 CK0* DQ40 91 D3_DQ_A41
CK0 DQ41 96 D3_DQ_A42
188 DQ42 97 D3_DQ_A43
181 A0 DQ43 209 D3_DQ_A44
61 A1 DQ44 210 D3_DQ_A45
180 A2 DQ45 215 D3_DQ_A46
59 A3 DQ46 216 D3_DQ_A47
58 A4 DQ47 99 D3_DQ_A48
Date:
178 A5 DQ48 100

Title
D3_DQ_A49
56 A6 DQ49 105 D3_DQ_A50
177 A7 DQ50 106 D3_DQ_A51
DWG NO
175 A8 DQ51 218 D3_DQ_A52

70 A9 DQ52 219 D3_DQ_A53
55 A10/AP DQ53 224 D3_DQ_A54
174 A11 DQ54 225 D3_DQ_A55
196 A12 DQ55 108 D3_DQ_A56
172 A13 DQ56 109 D3_DQ_A57
171 A14 DQ57 114 D3_DQ_A58
A15 DQ58 115 D3_DQ_A59
168 DQ59 227 D3_DQ_A60
74 RESET DQ60 228 D3_DQ_A61
192 CAS DQ61 233 D3_DQ_A62
Wednesday, June 13, 2012
73 RAS DQ62 234 D3_DQ_A63

WE DQ63
1
1
DDRIII
DIMM3
Sheet
Lanikai _MT/DT
D3_WEA#
15
D3_CASA#
D3_RASA#
D3_RESET#
of
D3_DQ_A[63..0]
11,16
11,16
11,16
Rev
71
11,16
11,16,17,18
A00
DDR3 Conn: CHA_1 (DIMM3)
A
B
C
D
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
4.7uF
CD19
CD15
+1P5V_SM
+1P5V_SM_VTT
240
VTT
+1P5V_SM_VTT
120 68
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
239
6.3V, X5R, +/-10%

235 VSS
D3_ODT_A2
D3_ODT_A3
*
232 VSS
*
VSS
5
5
229
11
11
1uF
SMB ADDRESS:001
226 VSS
CD16
VSS
CHANNEL A BANK 2
223 39 D3_ECC_CB_A0
0.1uF
CD20
VSS CB<3>
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_A4
16V, X7R, +/-10%

*
1uF
199 VSS CB<7>
CD17
166 VSS
163 VSS 7 D3_DQS_A0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16 D3_DQS_A1
*
148 VSS DQS1
1uF
CD18
139 VSS DQS2
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
127 85 D3_DQS_A4
D3_ECC_CB_A[7..0]

121 VSS DQS4
VSS 94 D3_DQS_A5
11,15
116 DQS5 93 D3_DQS_A#5

113 VSS DQS5
110 VSS 103 D3_DQS_A6
104 VSS DQS6
4
4
101 VSS 112 D3_DQS_A7

95 VSS DQS7
92 VSS 43
89 VSS DQS8 42
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
47 VSS DQS9
44 VSS 134
38 VSS DQS10
35 VSS 143
29 VSS DQS11
26 VSS 152
VSS DQS12
; CRB 0.7-12/10/09
20
17 VSS 203
11 VSS DQS13
SA_BS[2]-->Pin 52 (BA2)
SA_BS[0]-->Pin 71 (BA0)
VSS
SA_BS[1]-->Pin 190 (BA1)
8 212
5 VSS DM5/DQS14 213
D3_DQS_A[7..0]
VSS DQS14
D3_DQS_A#[7..0]
2
+1P5V_SM
VSS 221
DM6/DQS15
D3_DQS_A8 11,15
197 222
D3_DQS_A#8 11,15
VDDQ DQS15
11,15
11
11
11
11
194
11,15
191 VDDQ 230

186 VDDQ NC/DQS16
183 VDDQ 161
11,15 D3_MAA[15..0]
11 D3_CKE_A2
11 D3_CKE_A3
VDDQ DQS17
15 D3_CA_VREF_A
15 D3_DQ_VREF_A
11,15 D3_BAA[2..0]
15,17,18,32,52 S_SMBCLK_MAIN
11 D3_SCS_A#2
11 D3_SCS_A#3
179
3
3
D3_MA_CLK2
D3_MA_CLK3
D3_MA_CLK#2
D3_MA_CLK#3
176 VDDQ 3 D3_DQ_A0

75 VDD DQ3 122 D3_DQ_A4
72 VDD DQ4 123 D3_DQ_A5
DDRIII
69 VDD DQ5 128 D3_DQ_A6

66 VDD DQ6 129 D3_DQ_A7
D3_BAA0
D3_BAA1
D3_BAA2
D3_MAA9
D3_MAA8
D3_MAA7
D3_MAA6
D3_MAA5
D3_MAA4
D3_MAA3
D3_MAA2
D3_MAA1
D3_MAA0
VDD DQ9
D3_MAA15
D3_MAA14
D3_MAA13
D3_MAA12
D3_MAA11
D3_MAA10
60 18 D3_DQ_A10
57 VDD DQ10 19 D3_DQ_A11
VDD DQ11
+3V
54 131 D3_DQ_A12
51 VDD DQ12 132 D3_DQ_A13
236 VDD DQ13 137 D3_DQ_A14
VDDSPD DQ14 138 D3_DQ_A15
DQ15 21 D3_DQ_A16
67 DQ16 22 D3_DQ_A17
1 VREFCA DQ17 27 D3_DQ_A18
118 VREFDQ DQ18 28 D3_DQ_A19
SCL DQ19
RD6
238 140 D3_DQ_A20
*
119 SDA DQ20 141 D3_DQ_A21
237 SA2 DQ21 146 D3_DQ_A22
* 117 SA1 DQ22 147 D3_DQ_A23
16V, X7R, +/-10%

001
0.1uF
CD52
SA0 DQ23 30 D3_DQ_A24
Dummy
DQ24 31 D3_DQ_A25
*
0
52 DQ25 36 D3_DQ_A26
190 BA2 DQ26 37 D3_DQ_A27
71 BA1 DQ27 149 D3_DQ_A28
0.1uF
CD53
BA0 DQ28 150 D3_DQ_A29

Dummy
DQ29 155 D3_DQ_A30

169 DQ30 156 D3_DQ_A31
CKE1 DQ31
2
2
50 81 D3_DQ_A32
CKE0 DQ32 82 D3_DQ_A33
16V, X7R, +/-10%
76 DQ33 87 D3_DQ_A34
193 S1 DQ34 88 D3_DQ_A35
S0 DQ35 200 D3_DQ_A36
DQ36 201 D3_DQ_A37
D3_DQ_VREF_A 15
64 DQ37 206 D3_DQ_A38

H_CPU_DIMM_VREF_A
63 CK1/NU DQ38 207 D3_DQ_A39

CK1/NU DQ39
9
185 90 D3_DQ_A40
184 CK0* DQ40 91 D3_DQ_A41
CK0 DQ41 96 D3_DQ_A42
188 DQ42 97 D3_DQ_A43
181 A0 DQ43 209 D3_DQ_A44
61 A1 DQ44 210 D3_DQ_A45
180 A2 DQ45 215 D3_DQ_A46
Date:
59 A3 DQ46 216
Title
D3_DQ_A47
58 A4 DQ47 99 D3_DQ_A48
178 A5 DQ48 100 D3_DQ_A49
DWG NO
56 A6 DQ49 105 D3_DQ_A50

177 A7 DQ50 106 D3_DQ_A51
175 A8 DQ51 218 D3_DQ_A52
70 A9 DQ52 219 D3_DQ_A53
55 A10/AP DQ53 224 D3_DQ_A54
174 A11 DQ54 225 D3_DQ_A55
196 A12 DQ55 108 D3_DQ_A56
172 A13 DQ56 109 D3_DQ_A57
171 A14 DQ57 114 D3_DQ_A58
A15 DQ58 115 D3_DQ_A59
168 DQ59 227 D3_DQ_A60
74 RESET DQ60 228 D3_DQ_A61

192 CAS DQ61 233 D3_DQ_A62
73 RAS DQ62 234 D3_DQ_A63
WE DQ63
1
1
Sheet
DDRIII
DIMM1
Lanikai _MT/DT
16
D3_WEA#
D3_CASA#
D3_RASA#
D3_RESET#
of
Rev
D3_DQ_A[63..0]
11,15
11,15
11,15
71
11,15
A00
11,15,17,18
DDR3 Conn: CHA_2 (DIMM1)

A
B
C
D
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
0.1uF
CD33
0.1uF
CD31
4.7uF
CD29
CD25
+1P5V_SM
+1P5V_SM
+1P5V_SM
+1P5V_SM_VTT
240
Dummy
VTT
+1P5V_SM_VTT
120 68
RD15
RD13
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
* * 239
16V, X7R, +/-10%

16V, X7R, +/-10%
6.3V, X5R, +/-10%
235 VSS
D3_ODT_B0
D3_ODT_B1
*
232 VSS
*
229 VSS
12
12
1K
1K
1uF
VSS
5
5
226
CD26
+/-1%
+/-1%
SMB ADDRESS:010
223 VSS 39 D3_ECC_CB_B0
0.1uF
CD30
VSS CB<0>
CHANNEL B BANK 1
220 40 D3_ECC_CB_B1
*
*
VSS CB<1>
PLAECE CLOSE TO CH-B DIMM

217 45 D3_ECC_CB_B2
214 VSS CB<2> 46 D3_ECC_CB_B3
1K
1K
VSS CB<3>
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_B4
RD16
RD14
+/-1%
+/-1%
16V, X7R, +/-10%

*
*
*
1uF
199 VSS CB<7>
CD27
166 VSS
163 VSS 7 D3_DQS_B0
0.1uF
CD34
0.1uF
CD32
160 VSS DQS0 6 D3_DQS_B#0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16 D3_DQS_B1
*
148 VSS DQS1
16V, X7R, +/-10%

145 VSS 25 D3_DQS_B2
D3_DQ_VREF_B
*
1uF
CD28
139 VSS DQS2
16V, X7R, +/-10% Dummy

2.2uF
CD56
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
127 85 D3_DQS_B4
D3_ECC_CB_B[7..0]

121 VSS DQS4
VSS 94 D3_DQS_B5
12,18
116 DQS5 93 D3_DQS_B#5
6.3V, Y5V, +80%/-20%

113 VSS DQS5
110 VSS 103 D3_DQS_B6
VSS DQS6
D3_CA_VREF_B 18
107 102 D3_DQS_B#6
104 VSS DQS6
D3_DQ_VREF_B 18
101 VSS 112 D3_DQS_B7
4
4

95 VSS DQS7
Change to 0.1uF; PDG 0.7-12/07/09 Del CD54,CD5512/29/09

92 VSS 43
89 VSS DQS8 42
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
47 VSS DQS9
44 VSS 134
38 VSS DQS10

35 VSS 143
29 VSS DQS11
26 VSS 152
20 VSS DQS12
VSS
; CRB 0.7-12/10/09
17 203
11 VSS DQS13
8 VSS 212
SB_BS[2]-->Pin 52 (BA2)
SB_BS[0]-->Pin 71 (BA0)
VSS DM5/DQS14
SB_BS[1]-->Pin 190 (BA1)
5 213
D3_DQS_B[7..0]
VSS DQS14
D3_DQS_B#[7..0]
2
+1P5V_SM
VSS 221
DM6/DQS15
D3_DQS_B8 12,18
197 222
D3_DQS_B#8 12,18
VDDQ DQS15
12,18
12
12
12
12
194
12,18
191 VDDQ 230

186 VDDQ NC/DQS16
183 VDDQ 161
12,18 D3_MAB[15..0]
12 D3_CKE_B0
12 D3_CKE_B1
VDDQ DQS17
12,18 D3_BAB[2..0]
15,16,18,32,52 S_SMBCLK_MAIN
12 D3_SCS_B#0
12 D3_SCS_B#1
179
D3_MB_CLK0
D3_MB_CLK1
D3_MB_CLK#0
D3_MB_CLK#1
176 VDDQ 3 D3_DQ_B0
3
3
173 VDDQ DQ0 4 D3_DQ_B1

75 VDD DQ3 122 D3_DQ_B4
72 VDD DQ4 123 D3_DQ_B5
DDRIII
69 VDD DQ5 128 D3_DQ_B6

66 VDD DQ6 129 D3_DQ_B7
65 VDD DQ7 12 D3_DQ_B8
D3_BAB0
D3_BAB1
D3_BAB2
D3_MAB9
D3_MAB8
D3_MAB7
D3_MAB6
D3_MAB5
D3_MAB4
D3_MAB3
D3_MAB2
D3_MAB1
D3_MAB0
VDD DQ9
D3_MAB15
D3_MAB14
D3_MAB13
D3_MAB12
D3_MAB11
D3_MAB10
60 18 D3_DQ_B10
57 VDD DQ10 19 D3_DQ_B11
VDD DQ11
+3V
54 131 D3_DQ_B12
D3_CA_VREF_B
D3_DQ_VREF_B
51 VDD DQ12 132 D3_DQ_B13

236 VDD DQ13 137 D3_DQ_B14
VDDSPD DQ14 138 D3_DQ_B15
DQ15 21 D3_DQ_B16
67 DQ16 22 D3_DQ_B17
1 VREFCA DQ17 27 D3_DQ_B18
118 VREFDQ DQ18 28 D3_DQ_B19
238 SCL DQ19 140 D3_DQ_B20
119 SDA DQ20 141 D3_DQ_B21
237 SA2 DQ21 146 D3_DQ_B22
117 SA1 DQ22 147 D3_DQ_B23
010
SA0 DQ23 30 D3_DQ_B24

DQ24 31 D3_DQ_B25
52 DQ25 36 D3_DQ_B26
190 BA2 DQ26 37 D3_DQ_B27
71 BA1 DQ27 149 D3_DQ_B28
BA0 DQ28 150 D3_DQ_B29
DQ29 155 D3_DQ_B30
169 DQ30 156 D3_DQ_B31
50 CKE1 DQ31 81 D3_DQ_B32
CKE0 DQ32
2
2
82 D3_DQ_B33
76 DQ33 87 D3_DQ_B34
193 S1 DQ34 88 D3_DQ_B35
S0 DQ35 200 D3_DQ_B36
DQ36 201 D3_DQ_B37
64 DQ37 206 D3_DQ_B38
63 CK1/NU DQ38 207 D3_DQ_B39
185 CK1/NU DQ39 90 D3_DQ_B40
184 CK0* DQ40 91 D3_DQ_B41
CK0 DQ41 96 D3_DQ_B42
188 DQ42 97 D3_DQ_B43
181 A0 DQ43 209 D3_DQ_B44
61 A1 DQ44 210 D3_DQ_B45
180 A2 DQ45 215 D3_DQ_B46
59 A3 DQ46 216 D3_DQ_B47
Date:
58 A4 DQ47 99
Title
D3_DQ_B48
178 A5 DQ48 100 D3_DQ_B49
56 A6 DQ49 105 D3_DQ_B50
DWG NO
177 A7 DQ50 106 D3_DQ_B51

175 A8 DQ51 218 D3_DQ_B52
70 A9 DQ52 219 D3_DQ_B53
55 A10/AP DQ53 224 D3_DQ_B54
174 A11 DQ54 225 D3_DQ_B55
196 A12 DQ55 108 D3_DQ_B56
172 A13 DQ56 109 D3_DQ_B57
171 A14 DQ57 114 D3_DQ_B58
A15 DQ58 115 D3_DQ_B59
168 DQ59 227 D3_DQ_B60
74 RESET DQ60 228 D3_DQ_B61
192 CAS DQ61 233 D3_DQ_B62

73 RAS DQ62 234 D3_DQ_B63
WE DQ63
1
1
DDRIII
DIMM4
Sheet
Lanikai _MT/DT
17
D3_WEB#
D3_CASB#
D3_RASB#
D3_RESET#
of
D3_DQ_B[63..0]
Rev
12,18
12,18
12,18
71
12,18
11,15,16,18
A00
DDR3 Conn: CHB_1 (DIMM4)
A
B
C
D
A
B
C
D
198 79
187 FREE1 RSVD 77
*
*
49 FREE2 ODT1 195
48 FREE3 ODT0
1uF
FREE4
4.7uF
CD41
CD35
+1P5V_SM
+1P5V_SM_VTT
240
VTT
+1P5V_SM_VTT
120 68
VTT NC/PAR_IN 53
NC/ERR_OUT 167
NC/TEST4
6.3V,X5R,+/-10%
239
6.3V, X5R, +/-10%

235 VSS
D3_ODT_B2
D3_ODT_B3
*
232 VSS
*
229 VSS
12
12
1uF
226 VSS
CD36
VSS
5
5
223 39 D3_ECC_CB_B0
0.1uF
CD42
SMB ADDRESS:011

VSS CB<1>
CHANNEL B BANK 2
217 45 D3_ECC_CB_B2

VSS CB<3>
6.3V,X5R,+/-10%
211 158 D3_ECC_CB_B4
16V, X7R, +/-10%

*
1uF
199 VSS CB<7>
CD37
166 VSS
163 VSS 7 D3_DQS_B0
157 VSS DQS0
VSS
6.3V,X5R,+/-10%
154 16 D3_DQS_B1
*
148 VSS DQS1
1uF
CD38
139 VSS DQS2
130 VSS DQS3
VSS
6.3V,X5R,+/-10%
127 85 D3_DQS_B4
D3_ECC_CB_B[7..0]

121 VSS DQS4
VSS 94 D3_DQS_B5
12,17
116 DQS5 93 D3_DQS_B#5

113 VSS DQS5
110 VSS 103 D3_DQS_B6
104 VSS DQS6
101 VSS 112 D3_DQS_B7
4
4
95 VSS DQS7
92 VSS 43
89 VSS DQS8 42
86 VSS DQS8
83 VSS 125
80 VSS DM0/DQS9 126
47 VSS DQS9
DIMMs
44 VSS 134
38 VSS DQS10
35 VSS 143
VSS DQS11
; CRB 0.7-12/10/09
29
15,16,17,32,52 S_SMBCLK_MAIN
VSS
26 152
Decouple Cap for all 4
20 VSS DQS12
SB_BS[2]-->Pin 52 (BA2)
SB_BS[0]-->Pin 71 (BA0)
VSS
SB_BS[1]-->Pin 190 (BA1)

17 203
50V, NPO, +/-5% 14 VSS DM4/DQS13 204
11 VSS DQS13
8 VSS 212
5 VSS DM5/DQS14 213
22pF
D3_DQS_B[7..0]
VSS DQS14
D3_DQS_B#[7..0]
2
Dummy
+1P5V_SM
VSS 221
DM6/DQS15
D3_DQS_B8 12,17
197 222
D3_DQS_B#8 12,17
VDDQ DQS15
12,17
194
12,17
22pF
*CD39 *CD40
191 VDDQ 230

Dummy

50V, NPO, +/-5% 186 VDDQ NC/DQS16
183 VDDQ 161
12,17 D3_MAB[15..0]
179 VDDQ DQS17
176 VDDQ 3 D3_DQ_B0
3
3

VDDQ DQ2
12
12
12
12
78 10 D3_DQ_B3
75 VDD DQ3 122 D3_DQ_B4
72 VDD DQ4 123 D3_DQ_B5
DDRIII
69 VDD DQ5 128 D3_DQ_B6

66 VDD DQ6 129 D3_DQ_B7
17 D3_CA_VREF_B
17 D3_DQ_VREF_B
12 D3_CKE_B2
12 D3_CKE_B3
VDD DQ8
12,17 D3_BAB[2..0]
12 D3_SCS_B#2
12 D3_SCS_B#3
62 13 D3_DQ_B9
D3_MB_CLK2
D3_MB_CLK3
D3_MAB9
D3_MAB8
D3_MAB7
D3_MAB6
D3_MAB5
D3_MAB4
D3_MAB3
D3_MAB2
D3_MAB1
D3_MAB0
D3_MB_CLK#2
D3_MB_CLK#3
VDD DQ9
D3_MAB15
D3_MAB14
D3_MAB13
D3_MAB12
D3_MAB11
D3_MAB10
60 18 D3_DQ_B10
57 VDD DQ10 19 D3_DQ_B11
VDD DQ11
+3V
54 131 D3_DQ_B12
51 VDD DQ12 132 D3_DQ_B13
236 VDD DQ13 137 D3_DQ_B14
*
VDDSPD DQ14 138 D3_DQ_B15
DQ15 21 D3_DQ_B16
1uF
67 DQ16 22 D3_DQ_B17
CD46
1 VREFCA DQ17 27 D3_DQ_B18
Dummy
D3_DQ_VREF_B_R
118 VREFDQ DQ18 28 D3_DQ_B19
D3_BAB0
D3_BAB1
D3_BAB2
238 SCL DQ19 140 D3_DQ_B20

* 119 SDA DQ20 141 D3_DQ_B21
SA2 DQ21
6.3V,X5R,+/-10%
237 146 D3_DQ_B22
SA1 DQ22
011
117 147 D3_DQ_B23
0
SA0 DQ23 30 D3_DQ_B24
Dummy
RD19
DQ24 31 D3_DQ_B25
RD17
52 DQ25 36 D3_DQ_B26
*
190 BA2 DQ26 37 D3_DQ_B27
* 71 BA1 DQ27 149 D3_DQ_B28
BA0 DQ28 150 D3_DQ_B29
16V, X7R, +/-10%

0.1uF
CD55
Dummy DQ29 155 D3_DQ_B30

0
169 DQ30 156 D3_DQ_B31

*
50 CKE1 DQ31 81 D3_DQ_B32
CKE0 DQ32 82 D3_DQ_B33
DQ33
2
2
76 87 D3_DQ_B34
0.1uF
CD54
193 S1 DQ34 88 D3_DQ_B35

Dummy
S0 DQ35 200 D3_DQ_B36

DQ36 201 D3_DQ_B37
64 DQ37 206 D3_DQ_B38
63 CK1/NU DQ38 207 D3_DQ_B39
16V, X7R, +/-10%
185 CK1/NU DQ39 90 D3_DQ_B40

184 CK0* DQ40 91 D3_DQ_B41
CK0 DQ41 96 D3_DQ_B42
D3_DQ_VREF_B 17
188 DQ42 97 D3_DQ_B43

H_CPU_DIMM_VREF_B
181 A0 DQ43 209 D3_DQ_B44

A1 DQ44
9
61 210 D3_DQ_B45
180 A2 DQ45 215 D3_DQ_B46
59 A3 DQ46 216 D3_DQ_B47
58 A4 DQ47 99 D3_DQ_B48
Date:
178 A5 DQ48 100

Title
D3_DQ_B49
56 A6 DQ49 105 D3_DQ_B50
177 A7 DQ50 106 D3_DQ_B51
DWG NO
175 A8 DQ51 218 D3_DQ_B52

70 A9 DQ52 219 D3_DQ_B53
55 A10/AP DQ53 224 D3_DQ_B54
174 A11 DQ54 225 D3_DQ_B55
196 A12 DQ55 108 D3_DQ_B56
172 A13 DQ56 109 D3_DQ_B57
171 A14 DQ57 114 D3_DQ_B58
A15 DQ58 115 D3_DQ_B59
168 DQ59 227 D3_DQ_B60
74 RESET DQ60 228 D3_DQ_B61
192 CAS DQ61 233 D3_DQ_B62
73 RAS DQ62 234 D3_DQ_B63

WE DQ63
1
1
DDRIII
DIMM2
Sheet
Lanikai _MT/DT
D3_WEB#
18
D3_CASB#
D3_RASB#
D3_RESET#
of
D3_DQ_B[63..0]
12,17
12,17
12,17
Rev
71
12,17
11,15,16,17
A00
DDR3 Conn: CHB_2 (DIMM2)
A
B
C
D
5 4 3 2 1
D D
20100106: Remove ONFI function since not support
C C
B B
A A
Title
TBD
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
Clock GEN
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
+3V
RNK1
K_AD[31..0] 58
Change AV14 to 58 K_PAR
BH8
US1A
BF15 K_AD0
K_INTA#
K_INTB#
*1 2
BH9 PAR AD0 BF17 K_AD1 K_INTC# 3 4
K_PCIRST#_SLOT-12/28/09 58 K_DEVSEL#
BD15 DEVSEL# AD1 BT7 K_AD2 K_INTD# 5 6
27 C_PCI_SB CLKIN_PCILOOPBACK AD2 7 8
AV14 BT13 K_AD3
58 K_PCIRST#_SLOT PCIRST# AD3
BF11 BG12 K_AD4 K_INTF# change to 8.2K
58 K_IRDY# IRDY# AD4
AV15 BN11 K_AD5
58 K_PME#
BR6 PME# AD5 BJ12 K_AD6
V_DDSP_C_HPD-12/30/09 RNK2
58 K_SERR# SERR# AD6
58 K_STOP#
BC12
BA17 STOP# AD7
BU9
BR12
K_AD7
K_AD8
20100108: Remove PCIE_MINI_CPUSB_DETECT#
*1 2
58 K_LOCK#
BC8 PLOCK# AD8 BJ3 K_AD9
V_DDSP_C_HPD pull-up V_GPI_VGA_CBL_DET# 3 4
58 K_TRDY# TRDY# AD9 5 6
BM3 BR9 K_AD10 PCIE_MINI_CPPE_DETECT#
58 K_PERR# PERR# AD10 7 8
BC11 BJ10 K_AD11
58 K_FRAME# FRAME# AD11 BM8 K_AD12 8.2K
AD12
PCI
GNT [3:0] have Internal Pull-High to 3.3V BF3 K_AD13
AD13 BN2 K_AD14
****
BA15 AD14 BE4 K_AD15 K_REQ#0 RS7 8.2K +/-5%
58 K_GNT#0 K_GNT#1 AV8 GNT0# AD15 BE6 K_AD16 K_REQ#1 RS8 8.2K +/-5%
K_GNT#2 BU12 GNT1# / GPIO51 AD16 BG15 K_AD17 K_REQ#2 RS9 8.2K +/-5%
K_GNT#3 BE2 GNT2# / GPIO53 AD17 BC6 K_AD18 K_REQ#3 RS10 8.2K +/-5%
GNT3# / GPIO55 AD18 BT11 K_AD19
AD19 BA14 K_AD20
AD20 BL2 K_AD21
K_REQ#0 BG5 AD21 BC4 K_AD22 RNK4
58 K_REQ#0 REQ0# AD22
K_REQ#1
K_REQ#2
BT5
BK8 REQ1# / GPIO50 AD23
BL4
BC2
K_AD23
K_AD24
K_FRAME#
K_IRDY#
*1 2
C K_REQ#3 AV11 REQ2# / GPIO52 AD24 BM13 K_AD25 K_TRDY# 3 4 C
REQ3# / GPIO54 AD25 BA9 K_AD26 K_DEVSEL# 5 6
AD26 BF9 K_AD27 7 8
AD27 BA8 K_AD28 8.2K
BK10 AD28 BF8 K_AD29
58 K_INTA# PIRQA# AD29
BJ5 AV17 K_AD30 RNK5
58 K_INTB# PIRQB# AD30
58
58
K_INTC#
K_INTD#
BM15
BP5 PIRQC# AD31
BK12 K_AD31
K_C/BE#[3..0] 58
K_STOP#
K_LOCK#
*1 2 +3V
PCIE_MINI_CPUSB_DETECT# BN9 PIRQD# K_PERR# 3 4
AV9 PIRQE# / GPIO2 BN4 K_C/BE#0 K_SERR# 5 6
26,41 V_DDSP_C_HPD PIRQF# / GPIO3 C/BE0# 7 8
BT15 BP7 K_C/BE#1
42 V_GPI_VGA_CBL_DET# PIRQG# / GPIO4 C/BE1#
PCIE_MINI_CPPE_DETECT# BR4 BG2 K_C/BE#2 8.2K
PIRQH# / GPIO5 C/BE2#
C/BE3#
BP13 K_C/BE#3 *RS13
1/12 +3V_PCIAUX
1K
BD82Q67 Dummy
K_GNT#0
*
K_PME# RS198 8.2K +/-5%
Dummy
K_PME# add RS198 to *RS18
pull-up +3V_PCIAUX;
1K
Left bioth SATA/GPIO19 and GNT1# floating. 20100108:
CRB 0.7-12/28/09 Dummy
No pull up required for Default(SPI) Dummy RS198;
PDG 0.8
20091209: Have to check with
B Intel
20091230: Reserved RS171
B
+3V and RS201 for Boot select

GNT3# Internal pull-up.
Boot BIOS Select

*RS14 * RS171
**
1K 10K
Dummy Boot Device GNT1 SATA1GP K_GNT#2 RS15 1K
Dummy
Dummy
LPC 0 0 K_GNT#3 RS17 4.7K
Dummy
53 K_GNT#1 PCI 1 0 DG 0.7
GNT3 is top block swap mode:
23,53 S_SATA1GP NAND 0 1 connect to ground with 4.7k ohm weak
SPI 1 1 pull down resistor for top block swap mode
*RS20 *RS201 GNT2#/GPIO53:ESI strap for server platform
1K 1K
ONLY,Do not pull low.
Dummy Dummy
A A
Title
PCH-1: PCI
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
US1B 20112012 Update USB 2.0 Distrubution for match USB 3.0
D33 BF36
10 H_DMI_TXN0 DMI0RXN USBP0N U_USB0N 57
B33 BD36
10 H_DMI_TXP0 DMI0RXP USBP0P U_USB0P 57
J36 BC33
10 H_DMI_RXN0 DMI0TXN USBP1N U_USB1N 57
H36 BA33 +3V_S5
10 H_DMI_RXP0 DMI0TXP USBP1P U_USB1P 57
A36 BM33
10 H_DMI_TXN1 U_USB2N 45
*
B35 DMI1RXN USBP2N BM35 U_USB_OC_R_#6 RS82 10K
P38 BT33
R38 BU32 Dummy
B37 BR32
10 H_DMI_TXN2 DMI2RXN USBP4N U_USB4N 45
C36 BT31
H38 BN29
J38 BM30 +3V_S5
DMI
D E37 BK33 D
10 H_DMI_TXN3 DMI3RXN USBP6N
F38 BJ33
10 H_DMI_TXP3 DMI3RXP USBP6P
+1P05V_PCH M41 BF31
10 H_DMI_RXN3 DMI3TXN USBP7N
P41 BD31 RS21 RS23 RS196
10 H_DMI_RXP3
B31 DMI3TXP USBP7P BN27
U_USB8N 35
* 8.2K *8.2K *
8.2K
*
RS24 49.9 +/-1% S_DMI_COMP E31 DMI_IRCOMP USBP8N BR29 +/-5% +/-5% +/-5%
DMI_ZCOMP USBP8P U_USB8P 35
L<0.5" BR26 Dummy Dummy
USBP9N U_USB9N 35
BT27
USBP9P U_USB9P 35
P33 BK25
27 C_DMI_PCH# CLKIN_DMI_N USBP10N U_USB10N 56
R33 BJ25
27 C_DMI_PCH CLKIN_DMI_P USBP10P U_USB10P 56
BJ31 U_USB_OC_R_#1 CU1 0.1uF Dummy
***
USBP11N U_USB11N 56
USB
BK31 16V, X7R, +/-10%
USBP11P U_USB11P 56
BF27 U_USB_OC_R_#2 CU2 0.1uF Dummy
USBP12N U_USB12N 61
BD27 16V, X7R, +/-10%
USBP12P U_USB12P 61
X_1X1_RXN J20 BJ27 U_USB_OC_R_#3 CU3 0.1uF Dummy
TPS15 PERN1 USBP13N U_USB13N 61
X_1X1_RXP L20 BK27 16V, X7R, +/-10%
TPS16 PERP1 USBP13P U_USB13P 61
P20
TPS6 PERN2
R20
H17 PERP2 BM43 U_USB_OC_R_#4 CU18 0.1uF Dummy
**
59 X_2X1_RXN PERN3 OC0# / GPIO59 U_USB_OC_R_#0 57
J17 BD41 16V, X7R, +/-10%
59 X_2X1_RXP PERP3 OC1# / GPIO40 U_USB_OC_R_#1 45
P17 BG41 U_USB_OC_R_#5 CU4 0.1uF Dummy
34 X_L1X1_RXN PERN4 OC2# / GPIO41 U_USB_OC_R_#2 45
M17 BK43 16V, X7R, +/-10%
34 X_L1X1_RXP PERP4 OC3# / GPIO42 U_USB_OC_R_#3 45
N15 BP43
39 X_1X4_RXN0 PERN5 OC4# / GPIO43 U_USB_OC_R_#4 35
M15 BJ41
39 X_1X4_RXP0 PERP5 OC5# / GPIO9 U_USB_OC_R_#5 56
J15 BT45 GPO_WLOM CU6 0.1uF Dummy
*
39 X_1X4_RXN1 PERN6 OC6# / GPIO10 U_USB_OC_R_#6 61
L15 BM45 16V, X7R, +/-10%
39 X_1X4_RXP1 PERP6 OC7# / GPIO14 GPO_WLOM 59
J12
39 X_1X4_RXN2 PERN7
H12
39 X_1X4_RXP2 PERP7
H10
39 X_1X4_RXN3 PERN8
PCI-E
C J10 BP25 S_USBRBIAS_PCH RS25 22.6 C
39 X_1X4_RXP3 PERP8 USBRBIAS#
X_1X1_TXN F25 BM25 L <=200 MILS +/-1%
TPS17 PETN1 USBRBIAS
X_1X1_TXP F23
TPS26 PETP1
C22 BD38
PETN2 CLKIN_DOT_96N C_96M_PCH# 27
A22 BF38
PETP2 CLKIN_DOT_96P C_96M_PCH 27
E21
59 X_2X1_TXN
*
B21 PETN3 A32 RS26 750
59 X_2X1_TXP PETP3 DMI2RBIAS
F18 +/-1%
34 X_L1X1_TXN PETN4
E17 AG12
34 X_L1X1_TXP PETP4 L_BKLTCTL TPS8
B17 AG18
39 X_1X4_TXN0 PETN5 L_BKLTEN TPS9
C16 AG17
39 X_1X4_TXP0 PETP5 L_VDD_EN TPS10
A16
39 X_1X4_TXN1 PETN6
B15
39 X_1X4_TXP1 PETP6
F15
39 X_1X4_TXN2 PETN7
F13
39 X_1X4_TXP2 PETP7
B13
39 X_1X4_TXN3 PETN8
D13
39 X_1X4_TXP3 PETP8 2/12
BD82Q67
B B
There are 4 oc pin in Controler 1 and USB 3.0 port number

must be match USB 2.0,If 4*OC pin used for USB3.0, Port 4/5
will not has OC pin function can usage
Title
Intel A
PCH-2: DMI/PCIe/USB
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
*
S_INIT3_3VB RS27 1K
Dummy
US1C
AC56
SATA0RXN T_SATA_RXN0 43
20100107:Remove test points AE49 AB55 This signal should not be pulled low on
TP13 SATA0RXP T_SATA_RXP0 43
CLINK
AE41 AE46
TP14 SATA0TXN T_SATA_TXN0 43 EDS 0.5- Sherlock 10/27/09
AE44
SATA0TXP T_SATA_TXP0 43
20100105:Remove TestTPS45 S_CLINK_CLK_LAN BA50
CL_CLK1 SATA1RXN
AA53
T_SATA_RXN1 43
TPS46 S_CLINK_DATA_LAN BF50 AA56
Point TPS47 S_CLINK_RST_LAN# BF49 CL_DATA1 SATA1RXP AG49
T_SATA_RXP1 43
CL_RST1# SATA1TXN T_SATA_TXN1 43
D 20100107: Remove RS47, RS48 SATA1TXP
AG47
T_SATA_TXP1 43 D
BC46 AL50
and connect 66 PCH_MEPWRGD APWROK SATA2RXN AL49
T_SATA_RXN2 43
SATA2RXP T_SATA_RXP2 43
S_PCH_MEPWROK_R to SATA2TXN
AL56
AL53
T_SATA_TXN2 43
+3V
S_PCH_MEPWROK directly
20100104: Add TPS23,TPS25 and
SATA2TXP AN46
T_SATA_TXP2
T_SATA_RXN3
43
60
S_TP_CPUFAN_PWM BN21 SATA3RXN AN44
TPS23
remove RS29,RS30,RS33, RS34 TPS25 S_TP_CHAFAN1_PWM BT21 PWM0 SATA3RXP AN56
T_SATA_RXP3 60
PWM1 SATA3TXN T_SATA_TXN3 60
since TPS18 S_TP_CHAFAN2_PWM BM20 AM55
SATA
PWM2 SATA3TXP T_SATA_TXP3 60
TPS19 S_TP_CHAFAN3_PWM BN19 AN49
useless this function 31 S_GPI_CHASSIS_ID1
BT17 PWM3 SATA4RXN AN50
TPS34
TPS52
* * * * ***
BR19 TACH0 / GPIO17 SATA4RXP AT50 O_KB_RST# RS28 10K
31 S_GPI_CHASSIS_ID0 TACH1 / GPIO1 SATA4TXN TPS54
BA22 AT49 O_GA20 RS31 10K
30 S_GPI_PCH_HS_DET# TACH2 / GPIO6 SATA4TXP TPS56
BR16 AT46 F_SERIRQ# RS32 10K
31 S_GPI_SKU2 TACH3 / GPIO7 SATA5RXN TPS20
AT44
SATA5RXP TPS21
AV50 S_GPI_PCH_HS_DET# RS58 10K
SATA5TXN TPS22
FAN
BU16 AV49
31 S_GPI_BRD_REV2 TACH4 / GPIO68 SATA5TXP TPS24
BM18 AF55 RS61 10K
57 S_USB_HDR_DET# TACH5/ GPIO69 CLKIN_SATA_N / CKSSCD_N C_SATA_PCH# 27 56 A_FP_PRES#
BN17 AG56
56 S_FP_CHAS_DET# TACH6 / GPIO70 CLKIN_SATA_P / CKSSCD_P C_SATA_PCH 27
+3V RS144 10K BP15
TACH7 / GPIO71
Add RS 144 and BF57 S_TP_GPIO36 RS124 8.2K +/-5%
*
SATALED# AJ55 T_SATALED# 56 +1P05V_PCH
pull-up to +3V; CRB SATAICOMPI
check : using 37.4 ohm in DG , 49.9 ohm in CRB Dummy
*
0.7-12/07/09 TPS28
BC43
SST SATAICOMPO
AJ53 S_SATARBIAS_PCH RS36 37.4 Ohm20091209: CRB0.7 and S_TP_GPIO37 RS125 8.2K +/-5%
+/-1% 20091214:
PDG0.7 areRS36 change to 37.4
suggested
FAN control from SATA0GP / GPIO21
BC54
S_GPI_BRD_REV0 31 ohm
Dummy
SMSC 5544 SATA1GP / GPIO19
AY52
S_SATA1GP 21,53 37.4 ohm
SATA2GP / GPIO36
BB55 S_TP_GPIO36 20091209: CRB0.7 V_DDSP_C_HPD is connected
C
without using SATA3GP / GPIO37
BG53
AU56
S_TP_GPIO37
H_SKTOCC_R_# to PCH pin N2 only , no connected to C
SST SATA4GP / GPIO16 BA56
TMIN_SHIFT 32 GPIO19,check whether RS35 need stuff for meet
SATA5GP / GPIO49 +1P05V_PCH
Intel PDG ?Change to S_SATA1GP for
20091230:
*
AE54 RS37 49.9
Boot Select
*
SATA3COMPI AC52 RS38 750 +/-1%
SATA3RBIAS
GPIO
S_PCH_CONFIG_JUMPER BA53 AE52 +/-1%
A_FP_PRES# BF55 SCLOCK / GPIO22 SATA3RCOMPO
AW53 SDATAOUT0 / GPIO39
26,40 V_DDSP_B_HPD SDATAOUT1 / GPIO48
20100107:Remove test points
BE54
31 S_GPI_CHASSIS_ID2 SLOAD / GPIO38 AB18
TP8
BB57
A20GATE O_GA20 32
A54 BN56
TPS30 NC_1 INIT3_3V# S_INIT3_3VB 53
A52 BG56
TPS31 NC_2 RCIN# O_KB_RST# 32
F57 AV52
TPS32
D57 NC_3 3/12 SERIRQ E56 F_SERIRQ# 32,46
TPS33 H_THERMTRIP# 9
*
NC_4 THRMTRIP#
HOST
AY20 H48 RS39 0
NC_5 PECI H_PECI 9,32
F55 Dummy Dummy RS39; SMSC suggestion-12/08/09
PMSYNCH H_PM_SYNC 9
BD82Q67
+3V
B PCH_CONFIG +3V
B
* RS55 * RS53
1K 10K
20100107: Remove RS47, RS48 and connect
S_PCH_MEPWROK_R to S_PCH_MEPWROK directly
*
S_PCH_CONFIG_JUMPER H_SKTOCC_R_# RS57 0
H_SKTOCC# 9,24
Dummy
*RS60 *RS59
4.7K STUFF RS57 FOR ME ON CPU
Dummy 10K
Dummy PRESENT DETECTION
A A
Title
PCH-3: SATA/HOST/FAN
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
CLOCK VALIDATION STRAP
SPKR Control Option of SIO / PCH +3V +3V +3V_S5
+3V +3V
EMPTY JUMPER FOR BUFFER THROUGH MODE
* * ****
Internal pull-up RS63 1K High: Disable Intergrated Clock Chip H_SKTOCC# RS64 100K
31 S_SPKR_OUT Dummy O_IO_PME# RS68 10K
Low: Enable Intergrated Clock Chip
*RS65 *RS66 S_SPKR *RS67 Has a weak Internal Pull-High X1_WAKE# RS69 10K
10K 10K 10K S_PCIAUX_GATE RS173 10K
Pop To Enable No-Reboot
Dummy Dummy
Iinternal pull-down. 20100106: Add RS173
20091223: signal rename US1D
+3V_DUAL L_DRQ1# BA20 AW55 S_WAKE# RS79 1K
Dummy to S_SUSWARN# BK15 LDRQ1# / GPIO23 BMBUSY# / GPIO0 BP51 S_TP_GP8
S_PECI_REQ# 32
20091221: Dummy RS80 follow CRB0.7
32,46,53 F_LAD0 TPS40
* ** ***** *
RS81 10K S_SUSWARN# BJ17 FWH0 / LAD0 GPIO8 BH49 S_SUS_PWR_ACK# RS80 10K
32,46,53 F_LAD1
*
+3V_S5 BJ20 FWH1 / LAD1 SLP_LAN# / GPIO29 BU46 S_SLP_LAN# 35 S_GP27_PD RS71 1K Dummy
32,46,53 F_LAD2 FWH2 / LAD2 SUSWARN# / SUSPWRDNACK / GPIO30 S_SUSWARN# 64 Dummy
RS72 10K S_MFG_MODE_OR BG20 BK50
32,46,53 F_LAD3 FWH3 / LAD3 LAN_PHY_PWR_CTRL / GPIO12 L_LAN_DISABLE# 34
D RS83 10K S_SMLINK1_CLK BK17 BA25 D
32 F_LDRQ# X1_WAKE# 59
* * * **
RS73 10K S_SMLINK1_DATA BG17 LDRQ0# HDA_DOCK_RST# / GPIO13 BM55 S_PCH_GP15 S_PCH_GP72_PU RS174 10K
32,46,53 F_FRAME# FWH4 / LFRAME# GPIO15
20091223: BU46 signal
LPC
RS85 2.2K S_SMLINK0_CLK S_SLP_LAN# RS75 1K
RS86 2.2K S_SMLINK0_DATA AV43 Dummy
Dummy PCIECLKRQ2# / GPIO20 BP53
S_FLEXBAY_HDR_CBL_DET# 27,61 rename to S_SUSWARN#
MEM_LED / GPIO24 H_SKTOCC# 9,23
RS74 10K F_SPI_CS1#_ISOLATE P_VR_READY RS193 10K
RS76 10K X4_WAKE# 20091223: BP53 signal name Dummy
Dummy
RS89 1K BJ43 S_GP27_PD change to H_SKTOCC# . S_PCH_GP28_PU RS84 10K
A_Z_SDOUT 31,36
**
RS77 33 A_Z_BITCLK_R BU22 GPIO27 BJ55 S_PCH_GP28_PU
36 A_Z_BITCLK RS78 33 A_Z_RST#_R BC22 HDA_BCLK GPIO28 BG43 RS151 1K
36 A_Z_RST# HDA_RST# GPIO31 S_PSWD_CLR 31
AUDIO
CPT FLASH DESCRIPT OR BD22 BC56 Dummy
36 A_Z_SDIN0 HDA_SDIN0 CLKRUN#/GPIO32 S_GPI_SKU0 31
OVERRIDE.HIGH FOR OVERRIDE TPS35
BF22
HDA_SDIN1 HDA_DOCK_EN#/GPIO33
BC25
TPS38 20100106: Reserved RS151 for
BK22 BL56 PCH_GPIO34
TPS36
BJ22 HDA_SDIN2 STP_PCI# / GPIO34 BJ57 Disable 1.05V Regulator
TPS37 S_GPI_SKU1 31
**
RS90 0 A_Z_SDOUT_R BT23 HDA_SDIN3 GPIO35 BL54
31,36 A_Z_SDOUT HDA_SDO PCIECLKRQ5# / GPIO44 S_INTRUD_CBL_DET# 27,31
RS92 33 A_Z_SYNC_R BP23 AV44 High: Enable 1.05V Regulator
36 A_Z_SYNC HDA_SYNC PCIECLKRQ6# / GPIO45 O_COM_SER2_DET# 27
BP55
Dummy PCIECLKRQ7# / GPIO46 S_GPI_BRD_REV1 31 Low: Disable 1.05V Regulator
*
RS91 1K A_Z_SYNC_R Has a weak Internal Pull-High

FVS
GPIO57
BT53 S_GPIO57_PD 20091221: BD43 removed Reserved for CPU VR and TPM type
OD PLL VR SUPPLY SEL(internal pull down)
1.8V SUPPLY WHEN SAMPLED LOW 1 L_DRQ1# D53 TPS38 and rename signal
1 PROCPWRGD H_PWRGD 9,52,64
1.5V SUPPLY WHEB SAMPLED HIGH to S_SLP_SUS# ; BT37
20091216: RS87 used 1k , PDG0.7
Dummy BD43 rename S_RSMRST# to +3V_S5
SLP_SUS# S_SLP_SUS# 64,65
20091223: Add RS151, RS197 TEST POINT
SYS_PWROK
BJ53 P_VR_READY
S_PCH_DPWROK_R ; BP45
S_SUSWARN# BT43
DS mode: O_PWRBTN#IN 32,52,53,56
rename to
* *
PWRBTN# BJ48 S_PCH_GP15 RS87 1K
RI# O_IO_PME# 32
20100104: Remove RS151,
RTC
S_PCH_RTCX1 BR39 BN54 S_LPCPD# +3V_DUAL
S_SUS_PWR_ACK
C C
* RS197 S_PCH_RTCX2 BN39 RTCX1 SUS_STAT# / GPIO61 BA47
1K P.64 has same circuit BT41 RTCX2 SUSCLK / GPIO62 BE52 S_SUSCLK 32 S_GP27_PD RS88 10K
29,31,53 S_RTCRST# RTCRST# SYS_RESET# FP_RST# 9,52,53
Dummy S_SRTRST# BN37 BK48 +3V
SRTCRST# PLTRST# BC44 S_PLTRST# 9,32,34,46,52,53
**
WAKE# BM38 S_WAKE# 38 PCH_GPIO34 RS119 10K
INTRUDER# S_INTRUDER# 31
BN49 BJ38
39 X4_WAKE# SMBALERT# / GPIO11 PWROK PWRGD_3V 32,52
BT47 BK38 FP_RST# RS199 10K
32,38,39,58,59 S_SMBCLK_PCI SMBCLK RSMRST# S_RSMRST# 52,64
SMB
32,38,39,58,59 S_SMBDATA_PCI
BR49
SMBDATA INTVRMEN
BN41 S_INTVRMEN 20091224: change
GPIO_WIRELESS_DISABLE# BU49 BE56 S_SPKR_OUT
CS2 CS3 BT51 SML0ALERT# / GPIO60 SPKR BP45 S_SUS_PWR_ACK# to +3V
34 S_SMLINK0_CLK SML0CLK SUSACK# S_SUS_PWR_ACK# 64
BM50
+3V_S5
22pF
Dummy * * 22pF
Dummy
34 S_SMLINK0_DATA
31 S_MFG_MODE_OR
BR46 SML0DATA
SML1ALERT#/PCHHOT#/GPIO74 SLP_S3#
BM53
S_SLP_S3# 32,53,64,66,70,71
20100104: Dummy
50V, NPO, +/-5%
50V, NPO, +/-5%
BJ46 BN52
32 S_SMLINK1_CLK SML1CLK / GPIO58 SLP_S4# S_SLP_S4# 32,53,65,71
BK46 BH50
RF1
32 S_SMLINK1_DATA SML1DATA / GP75 SLP_S5# / GPIO63 BC41 S_PCIAUX_GATE 65 RS87; follow CRB 0.7
* 10K 20091223: BU49 signal name
SLP_A# S_SLP_M# 32,53,65,66
Dummy BR42 DSWODVREN
change to X_WLAN_WAKE# DSWVRMEN AV46 S_PCH_GP72_PU
S_GPIO57_PD BATLOW#/GPIO72 BG46
AU53 DRAMPWROK BT37 S_PCH_DPWROK H_DRAMPWRGD 11 P_VR_READY
51 F_SPI_MOSI_PRI_SEC_FLSH SPI_MOSI DPWROK 33,52,64,67 P_VR_READY
SPI
AT55
*RF2 51 F_SPI_MISO
51 F_SPI_CS0#_ISOLATE
AT57 SPI_MISO
SPI_CS0# JTAG_RST/TP12
BC49
F_PCH_JTAG_RST# 52 * RS194 CS43
AR54 BA43
47K
51 F_SPI_CLK_PRI_SEC_FLSH
51 F_SPI_CS1#_ISOLATE
AR56 SPI_CLK
SPI_CS1#
JTAG_TCK
JTAG_TDI
BC52
F_PCH_JTAG_TCK_FILTER
F_PCH_JTAG_TDI 52
52
+3V_S5 10K
Dummy * 22uF
6.3V,X5R,+/-20%
BF47 Dummy
JTAG_TDO BC50 F_PCH_JTAG_TDO 52
CLOSE TO PCH JTAG_TMS F_PCH_JTAG_TMS 52
0 OHM FOR DEFENSIVE DESIGN 4/12 20091224: S_TP_SLP_S5# change to
B
Integrated TPM 66MHZ SPI TOPOLOGY, BD82Q67 S_PEG_B_CLKREQ# * RX8 B
+3V 8.2K
High to Enable
*
1K S_PCH_DPWROK +VCCRTC
Low to Disable 32 O_RSMRST# +/-5%
*
RS112 S_INTVRMEN RS107 390KOhm

C
Dummy GPIO_WIRELESS_DISABLE#
*RF3
8.2K
Internal
pull-down
*RS113
10K
BAT54HT1G
*RS108 +/-5%
+/-5% +/-1% 1K
Dummy DS3 Dummy
Dummy +3V_S5
A
F_SPI_MOSI_PRI_SEC_FLSH Internal 1.1V and VCCME regulator +1P5V_SM

SMSC recommend S_RSMRST#
enable(high)/disable(low) PWRGD_3V
01/13/11 RS93
+VCCRTC
+5VSB
200 Ohm
+/-1%
CS72
470pF*
*
*
DSWODVREN RS114 390KOhm S_LPCPD# RO1 8.2K +/-5% Dummy
*
RS115 4.7K +/-5% Dummy H_DRAMPWRGD 50V, X7R, +/-10%
*RS116
2KOhm RTC
+/-1% *RS94
3KOhm
X'TAL CLR_SRTC
+/-1%
S_PCH_RTCX2 Dummy
*RS117
3
10K
+/-1% S_PCH_RTCX1
20091214: CS4 stuffed
QS2 recommend
SMSC RS118 10M
MMDT5551 +/-5% +VCCRTC
01/13/11
C
A
+5VSB +3V A
4
S_PCH_DPWROK B QS3
MMBT3904-7-F
Near to Pch
XTAL 32.768KHz * RS105
E
*
RS120 1K RS121 5.6K XS1 20K

1 4
* CS8 RS122
+/-1%
*RS123 S_SRTRST# * CS5
0.1uF * CS6
0.1uF * CS7
0.1uF Title
*
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

1uF 1.1KOhm 2KOhm
PCH-4: LPC/HDA/RTC/SMB/SPI
2
+/-10%
Dummy
+/-1% +/-1%
* CS9
10pF * CS10
10pF
* CS4
50V, NPO, +/-5% 50V, NPO, +/-5% 1uF DWG NO Rev
16V, X5R, +/-10% A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
20100106: Remove ONFI function since not support
S_NVR_CLE internal pull-down.

US1E
M48 AB50
R47 NV_ALE NV_DQ0 / NV_IO0 Y50
9 M_NVR_CLE NV_CLE NV_DQ1 / NV_IO1
Y41 AB49
M50 NV_RB# NV_DQ2 / NV_IO2 AB44
M49 NV_RE#_WRB0 NV_DQ3 / NV_IO3 U49
20100107:remove test points NV_RE#_WRB1 NV_DQ4 / NV_IO4
U43 R44
J57 NV_WE#_CK0 NV_DQ5 / NV_IO5 U50
NV_WE#_CK1 NV_DQ6 / NV_IO6 U46
NV_DQ7 / NV_IO7 U44
NV_DQ8 / NV_IO8 H50
NV_DQ9 / NV_IO9 20100107:remove test points
K46
NV_DQ10 / NV_IO10 L56
NV_DQ11 / NV_IO11 J55
NV_DQ12 / NV_IO12 F53
NV_DQ13 / NV_IO13 H52
NV_DQ14 / NV_IO14 E52
NV_DQ15 / NV_IO15
K50
NV_CE#0 K49
NV_CE#1 AB46
C NV_CE#2 G56 C
NV_CE#3
NVRAM Y44
NV_DQS0 L53
NV_DQS1
R50 S_TP_NV_RCOMP
NV_RCOMP TPS29
5/12
BD82Q67
US1G
C42
FDI_RXN0 H_FDI_TXN0 10
B43
FDI_RXP0 H_FDI_TXP0 10
F45
F43
H41
J41
C46
D47
B45
A46
B47
C49
J43
FDI LINK
B FDI_RXN6 H_FDI_TXN6 10 B
H43
M43
P43
B51
FDI_FSYNC0 E49 H_FDI_FSYNC0 10
FDI_LSYNC0 C52 H_FDI_LSYNC0 10
FDI_FSYNC1 D51 H_FDI_FSYNC1 10
FDI_LSYNC1 H_FDI_LSYNC1 10
H46
FDI_INT H_FDI_INT 10
7/12
BD82Q67
A A
Title
PCH-5/7: NVRAM/FDI
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
US1F
T1 AR4 V_HSYNC
23,40 V_DDSP_B_HPD DDPB_HPD CRT_HSYNC
N2 AR2 V_VSYNC
21,41 V_DDSP_C_HPD
*
S_DDPD_HPD_PD M1 DDPC_HPD CRT_VSYNC

DDPD_HPD AN6
RS128 1K R8 CRT_RED AN2 V_RED 42
40 V_DDSP_B_AUX_DP DDPB_AUXP CRT_GREEN V_GREEN 42
+/-1% Dummy R9 AM1
40 V_DDSP_B_AUX_DN DDPB_AUXN CRT_BLUE V_BLUE 42
U14
41 V_DDSP_C_AUX_DP U12 DDPC_AUXP AM6
41 V_DDSP_C_AUX_DN TP_DDPD_AUXP N6 DDPC_AUXN CRT_IRTN
TPS42 DDPD_AUXP
TP_DDPD_AUXN R6
TPS43 DDPD_AUXN
AW1
R14 CRT_DDC_DATA AW3 V_DDCA_DATA 42
C 40 V_DDSP_B_DP_0_DP R12 DDPB_0P CRT_DDC_CLK V_DDCA_CLK 42 C
40 V_DDSP_B_DP_0_DN M11 DDPB_0N AT3 V_DACREFSET RS130 1KOhm
40 V_DDSP_B_DP_1_DP M12 DDPB_1P DAC_IREF +/-0.5%
40 V_DDSP_B_DP_1_DN H8 DDPB_1N
40 V_DDSP_B_DP_2_DP K8 DDPB_2P
40 V_DDSP_B_DP_2_DN L5 DDPB_2N
40 V_DDSP_B_DP_3_DP M3 DDPB_3P
40 V_DDSP_B_DP_3_DN L2 DDPB_3N
41 V_DDSP_C_DP_0_DP J3 DDPC_0P
41 V_DDSP_C_DP_0_DN G2 DDPC_0N
41 V_DDSP_C_DP_1_DP G4 DDPC_1P
41 V_DDSP_C_DP_1_DN F3 DDPC_1N
41 V_DDSP_C_DP_2_DP F5 DDPC_2P
41 V_DDSP_C_DP_2_DN E4 DDPC_2N
41 V_DDSP_C_DP_3_DP E2 DDPC_3P
41 V_DDSP_C_DP_3_DN D5 DDPC_3N DISPLAY
B5 DDPD_0P
C6 DDPD_0N
D7 DDPD_1P
B7 DDPD_1N
C9 DDPD_2P
E11 DDPD_2N
B11 DDPD_3P
DDPD_3N AL12
DDPC_CTRLCLK AL14 V_DDPC_CTRL_CLK 41
DDPC_CTRLDATA V_DDPC_CTRL_DATA 41
U2 AL9
TP_SDVO_INTN T3 SDVO_INTP DDPD_CTRLCLK AL8
TPS62 SDVO_INTN DDPD_CTRLDATA
B TP_SDVO_STALLP W3 AL15 B
TPS64 SDVO_STALLP SDVO_CTRLCLK V_DDPB_CTRL_CLK 40
TP_SDVO_STALLN U5 AL17
TPS66 SDVO_STALLN SDVO_CTRLDATA V_DDPB_CTRL_DATA 40
TP_SDVO_TVCLKINP U8
TPS68 SDVO_TVCLKINP
TP_SDVO_TVCLKINN U9
TPS69 SDVO_TVCLKINN
6/12
BD82Q67
V_RED
**
V_GREEN V_HSYNC RS131 33

V_HSYNC_3V 42
V_BLUE V_VSYNC RS132 33
V_VSYNC_3V 42
A
*RS133
150 *RS134
+/ -1%
150 *RS135
150
+/ -1% +/ -1% *RS136
0
Dummy
*RS137
0
Dummy
Title
Intel A
PCH-6: Display
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
20100106: Remove RS96; CRB 0.7

20100106: Swap C_PCH_PCI0_R and C_PCI_SL1_R; CRB 0.7
20100106: Disconnect AT11 and left Test point; CRB 0.7
US1H
*****
RC103 22 C_LPC_R AT11 W53 C_PCH_CSI#
53 C_LPC CLKOUT_PCI0 CLKIN_GND0_N V52 C_PCH_CSI
RC97 22 C_TPM_R AN14 CLKIN_GND0_P
46 C_TPM CLKOUT_PCI1 R52
RC98 22 C_PCI_PCH_R AT12 CLKOUT_ITPXDP_N N52 C_PCH_ITP# 52
21 C_PCI_SB CLKOUT_PCI2 CLKOUT_ITPXDP_P C_PCH_ITP 52
RC99 22 C_LPC_SIO_R AT17 AE2
32 C_LPC_SIO CLKOUT_PCI3 CLKOUT_PCIE7N AF1
RC100 22 C_PCI_SL1_R AT14 CLKOUT_PCIE7P
**
58 C_PCI_SL1 CLKOUT_PCI4 P31 C_PE_100M_MCP#_R RS202 0
CLKOUT_DMI_N R31 C_PE_100M_MCP_R RS203 0 C_PE_100M_MCP# 9
20100107: Swap CLKOUTFLEX CLK out; PDG 0.8 CLKOUT_DMI_P C_PE_100M_MCP 9
S_TP_CLKOUTFLEX0 AT9 R27 C_DMI2_PCH#
TPS129
* **
RC101 22 C_14M_SIO_R BA5 CLKOUTFLEX0 / GPIO64 CLKIN_GND1_N P27 C_DMI2_PCH
32 C_14M_SIO S_TP_CLKOUTFLEX2 AW5 CLKOUTFLEX1 / GPIO65 CLKIN_GND1_P
TPS130 CLKOUTFLEX2 / GPIO66
RC102 22 C_14M_TPM_R BA2
46 C_14M_TPM CLKOUTFLEX3 / GPIO67
20100108: Change N56 S_TP_CK_DP_PCH_DN
CLKOUT_DP_N / CLKOUT_BCLK1_N TPS126
RC104 91 Ohm XCLK_RCOMP AL2 M55 S_TP_CK_DP_PCH_DP
Power Source +1P05V_PCH
+/-1% XCLK_RCOMP CLKOUT_DP_P / CLKOUT_BCLK1_P TPS125
C_14M_MCH AN8 AE6
REFCLK14IN CLKOUT_PCIE0N AC6 S_TP_CK_SRC0_PCH_DP
C CLKOUT_PCIE0P TPS124 C
AA5
CLKOUT_PCIE1N W5 C_SRC1_PCH# 52
CLKOUT_PCIE1P C_SRC1_PCH 52
AB12
CLKOUT_PCIE2N AB14 C_PCIE_L1# 34
C_XTAL_25M_OUT AJ5
CLOCK CLKOUT_PCIE2P C_PCIE_L1 34
RC107 C_XTAL_25M_IN AJ3 XTAL25_OUT AB9 S_TP_CK_SRC3_PCH_DN
TPS72
*
1M XTAL25_IN CLKOUT_PCIE3N AB8 S_TP_CK_SRC3_PCH_DP

CLKOUT_PCIE3P TPS73
XC2
+/-1% DON'T CHANGE TO 0402 Y9 S_TP_CK_SRC4_PCH_DN
CLKOUT_PCIE4N TPS74
1 2 Y8 S_TP_CK_SRC4_PCH_DP
CLKOUT_PCIE4P TPS75
**
XTAL 25MHz AF3 C_PCIEX1#_2_R RS212 0
CLKOUT_PCIE5N AG2 C_PCIEX1_2_R RS211 0 C_PCIEX1#_2 59
CLKOUT_PCIE5P C_PCIEX1_2 59
* CC36
27pF * CC37
27pF
CLKOUT_PCIE6N
AB3
AA2 C_PCIEX1_1
CLKOUT_PCIE6P TPS77
50V, NPO, +/-5%
50V, NPO, +/-5%
** **
AG8 C_PCIEX16#_1_R RS205 0
CLKOUT_PEG_A_N AG9 C_PCIEX16_1_R RS204 0 C_PCIEX16#_1 38
8/12 CLKOUT_PEG_A_P C_PCIEX16_1 38
AE12 C_PCIEX4#_1_R RS210 0
CLKOUT_PEG_B_N AE11 C_PCIEX4_1_R RS209 0 C_PCIEX4#_1 39
CLKOUT_PEG_B_P C_PCIEX4_1 39
BD82Q67
B B
C_TPM
C_14M_TPM
C_14M_SIO
C_LPC_SIO
C_PCI_SB
+3V
*
*
RC108 10K S_FLEXBAY_HDR_CBL_DET# 24,61 S_FLEXBAY_HDR_CBL_DET# RC109 10K Dummy
20091216 PCIECLKRQ1#/GPIO18 is
mobile chip only, RC110, RC111 and
signal net "S_PCIECLKREQ#1" * CC10
10pF * CC12
10pF * CC13
10pF * CC14
10pF * CC15
10pF
removed. +3V_S5 Dummy Dummy Dummy Dummy Dummy
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%
50V, NPO, +/-5%

20100106: GPO_WLOM move to GPIO14
**
RC116
RC118
10K
10K
S_INTRUD_CBL_DET# 24,31 S_INTRUD_CBL_DET#
O_COM_SER2_DET#
RC117
RC119
** 10K Dummy
10K Dummy
O_COM_SER2_DET# 24
******
RC129 10K
A 22 C_96M_PCH# A
*****
Pull-down for Integrated clock gen-11/25/09 C_14M_MCH RC120 10K

20100105: Dummy all pull-down resistors since RC130 10K
22 C_96M_PCH
C_PCH_CSI# RC121 10K
use buffer thru mode RC131 10K
22 C_DMI_PCH#
20100106: Reserved RC123,RC124; CRB 0.7 C_PCH_CSI RC122 10K
20100107: RC121,RC122 mount; PDG 0.8 RC132 10K Title
22 C_DMI_PCH
C_DMI2_PCH# RC123 10K
23 C_SATA_PCH#
RC133 10K PCH-8: Clock
C_DMI2_PCH RC124 10K
RC134 10K DWG NO Rev
23 C_SATA_PCH
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+1P05V_PCH +1P05V_PCH
US1I
+1P05V_PCH AV24 AC24
AV26 VCCIO_1 VCCCORE_1 AC26
AY25 VCCIO_2 VCCCORE_2 AC28
VCCIO_3 VCCCORE_3 * CS11
* CS15
* CS16
* CS17
16V, X5R, +/-10%
16V, X5R, +/-10%
16V, X5R, +/-10%

CS12 CS13 CS14 AY27 AC30 1uF 1uF 10uF 10uF
AC20 VCCIO_4 VCCCORE_4 AC32
* 1uF
* 1uF
* 1uF
AE20 VCCSC_1
VCCSC_2
VCCCORE_5
VCCCORE_6
AE24
16V, X5R, +/-10%
16V, X5R, +/-10%
10V, X5R, +/-10%
10V, X5R, +/-10%
D Dummy Dummy Dummy AG41 AE28 D
AL40 VCCIO_7 VCCCORE_7 AE30
AN40 VCCIO_8 VCCCORE_8 AE32
AN41 VCCIO_9 VCCCORE_9 AE34
AJ38 VCCIO_10 VCCCORE_10 AE36
Y36 VCCIO_11 VCCCORE_11 AG32
PLACE SOLDER SIDE VCCIO_12 VCCCORE_12
V36 AG34
Y28 VCCIO_13 VCCCORE_13 AJ32
AE15 VCCIO_14 VCCCORE_14 AJ34
AE17 VCCDIFFCLKN_1 VCCCORE_15 AJ36
AG15 VCCDIFFCLKN_2 VCCCORE_16 AL32
AE40 VCCDIFFCLKN_3 VCCCORE_17 AL34
BA38 VCCIO_18 VCCCORE_18 AN32
+1P05V_PCH AG38 VCCIO_19 VCCCORE_19 AN34
AG40 VCCIO_20 VCCCORE_20 AR32
AA34 VCCIO_21 VCCCORE_21 AR34
AA36 VCCIO_22 VCCCORE_22
* CS79
1uF F20 VCCIO_23
VCCIO_24 20110211 USB 3.0 Ball for PPT
16V, X5R, +/-10% F30
+1P05V_PCH +V_1.05_PCH_LR_10 V25 VCCIO_25 AE43
LS1 V27 VCCIO_26 TP15 AE50
*
V31 VCCIO_27 TP16 BA36

10uH V33 VCCIO_28 TP17 AY36
VCCIO_29 TP18 Y14
USB 3.0 Ball for PPT
Close to AL40 * CS19
10uF * CS20
1uF TP19
TP20
Y12
6.3V,X5R,+/-10% H31
TP21 USB3_RX1_PCH_DN 57
J27
10V, X5R, +/-10% J25
L22
C J31 C
TP25 USB3_RX1_PCH_DP 57
L27
L25
J22
C29
TP29 F28 USB3_TX1_PCH_DN 57
+1P05V_VCCIO TP30 C26 USB3_TX2_PCH_DN 57
TP31 B25 USB3_TX3_PCH_DN 45
E41 TP32 E29 USB3_TX4_PCH_DN 45
Dummy B41 VCCDMI_01 TP33 E27 USB3_TX1_PCH_DP 57
VCCDMI_02 TP34 B27 USB3_TX2_PCH_DP 57
* CS31
1uF
* CS21
1uF
TP35
TP36
D25 USB3_TX3_PCH_DP 45
USB3_TX4_PCH_DP 45
BP1
16V, X5R, +/-10% 16V, X5R, +/-10% POWER VSS_NCTF_14
+1P05V_PCH
P22
+V_1.05_PCH_LR_10 TP1 L31
Y24 TP2 L33
Y26 VCCIO_30 TP3 M38
+1P05V_PCH Y30 VCCIO_31 TP4 L36
Y32 VCCIO_32 TP5 Y18
*
LS2 10uH VCCSATAPLL_L_10 Y34 VCCIO_33 TP6 Y17

Dummy CS22 CS23 V22 VCCIO_34 TP7 AB17
Y20 VCCIO_35 TP9 P25
* 10uF
Dummy * 1uF
16V, X5R, +/-10% Y22 VCCIO_36
VCCIO_37
VSS_296
VSS_295
R25
10V, X5R, +/-10% Dummy AJ20 R36
VCCCLKDMI VSS_293 AL44
VSS_292 AL43
*
LS3 1uH VCCAPLLEXP_L_10 RS139 0 VSS_291 BM46

B Dummy TP10 BA27 B
TP11 P36
Dummy
* CS24
10uF
CS25
*
1uF 6.3V,X5R,+/-10% VSS_294
10V, X5R, +/-10%
Dummy Dummy U56

+1P05V_PCH VCCAPLLSATA
VCCAPLLEXP_LR_10 B53
VCCAPLLEXP
*
RS140 0 VCCFDIPLL_R_10 C54

Dummy VCCFDIPLL
A19
VCCAPLLDMI2
AL5
VCCACLK
*
LS4 1uH RS141 0 VCCAPLLDMI2_LR_10

Dummy Dummy
* CS26
10uF * CS27
1uF
9/12
10V, X5R, +/-10% Dummy
Dummy 6.3V,X5R,+/-10% BD82Q67
Intel A
*
RS142 0 VCCACLK_R_10
Dummy
Title
PCH-9: Power 1
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
Coherent with GPIO28

+5V +3V +5V_S5 +3V_S5
Delet RS144,RS146,RS149 and 1.05V power source; follow CRB 0.7-11/30
A
US1J
+REF5V AJ1 DS1 DS2
VCCVRM_1
VCCVRM_4
R2
+1P8V_SFR
+1P8V_SFR
*RS150 SD103AW *RS147 SD103AW
BF1 R54 10 +REF5V 10 Dummy +REF5V_SUS
+REF5V_SUS V5REF VCCVRM_3 R56 +1P8V_SFR
C
VCCVRM_2
+3V_S5 BT25 +1P8V_SFR
V5REF_SUS
D
AV28 T55 CS32 0.1uF Near T55
* CS33
1uF
* CS39
0.1uF
D
*
VCCSUSHDA VCCPNAND_1 T57 16V, X7R, +/-10%
VCCPNAND_2 16V, X5R, +/-10% 16V, X7R, +/-10%
* CS34
0.1uF 20100106- Dummy
16V, X7R, +/-10%
+3V
CS35,CS44,CS45; follow
+3V +3V CRB 0.8
BD17 CS35 0.1uF
* * *
AF57 VCC3P3_3 BD20 16V, X7R, +/-10% +VCCRTC
VCC3P3_1 VCC3P3_4
CS46
0.1uF * BC17
VCC3P3_2
CS36
Dummy
0.1uF Near AL38
16V, X7R, +/-10% 16V, X7R, +/-10% Near BU42
CS37
0.1uF * * CS38
0.1uF VCC3P3_5
AL38 CS40 0.1uF Near A12
* CS41
1uF * CS42
0.1uF
6.3V,X5R,+/-10%
Close to AF57 16V, X7R, +/-10% 16V, X7R, +/-10% AN38 16V, X7R, +/-10% 16V, X7R, +/-10%
VCC3P3_6 AU22
20100104- Change to VCC3P3_7
Close to BC17 A12
0.1uF; follow CRB 0.8 VCC3P3_8 AU20 CS44 0.1uF
*
VCC3P3_9 16V, X7R, +/-10%
Dummy for Cost down-11/23 Dummy
AV20
VCC3P3_10 CS45 0.1uF
Delet LS5,RS151,CS46,CS47; follow CRB 0.7-11/30
*
16V, X7R, +/-10%
Dummy
+3V Near AU20 +3V
C * CS73
1uF * CS75
1uF
+1P8V_SFR
C
16V, X5R, +/-10% 16V, X5R, +/-10%
Dummy Dummy
20100104- Add CS78,CS80 and CS76,CS77
change to 0403; follow CRB 0.8
* CS48
1uF
16V, X5R, +/-10%
Dummy
+1P05V_ME 20100104- CS73,CS75 change to
Near AJ24,AN22
POWER
1uF; follow CRB 0.8
Near AV30 20100104- Remove CS49,CS50 follow
U31
* CS71
1uF * CS80
10uF * CS78
1uF * CS77
1uF * CS76
1uF
+1P05V_ME
VCCSUS3P3_1
+3V_S5 20100104- CS56 change to
2.2uF; follow CRB 0.8
CRB 0.8
6.3V, X5R, +/-20%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy AU32 AV30

VCCASW_1 VCCSUS3P3_2
16V, X5R, +/-10%
AV36 AV32 CS51 NEAR U31

AU34 VCCASW_2 VCCSUS3P3_3 AY31
AG24 VCCASW_3
VCCASW_4
VCCSUS3P3_4
VCCSUS3P3_5
AY33 * CS51
0.1uF * CS56
2.2uF
CS56 NEAR AV30,AT40
VBAT
AG26 BJ36 25V, X7R, +/-10% 6.3V, Y5V, +80%/-20%
+3V AG28 VCCASW_5 VCCSUS3P3_6 BK36
AJ24 VCCASW_6 VCCSUS3P3_7 BM36
AJ26 VCCASW_7 VCCSUS3P3_8 AT40 +VCCRTC_SIO +3V_DUAL
AJ28 VCCASW_8 VCCSUS3P3_9 AU38 CS52 0.1uF QS4 QS5 +VCCRTC
L<100 MILS
*
FBS1 RS152 AL24 VCCASW_9 VCCSUS3P3_10 BT35 16V, X7R, +/-10% BAT54C BAT54C
*
1 S_VCCADAC_LR_10 AL28 VCCASW_10 VCCSUS3P3_11 1 1

VCCASW_11 Near BT35
FB 600 Ohm AN22 3 3
AN24 VCCASW_12 2 2
20100106:- FBS1 * CS53
2.2uF * CS54
10uF * CS55
0.1uF AN26 VCCASW_13
*
CS57
1uF
change to FB: VCCASW_14 *RS153
6.3V, Y5V, +80%/-20%
10V, X5R, +/-10%
16V, X7R, +/-10%
16V, X5R, +/-10%

AN28 +1P05V_VCCIO 20100104- Remove 20K
B
PDG 0.8 AR24 VCCASW_15
VCCASW_16 CS74 follow CRB
BATTERY_1 *RS154 B
AR26 CS58 4.7uF 1K
***
AR28 VCCASW_17 6.3V, X5R, +/-10% 0.8 S_RTCRST#
VCCASW_18 S_RTCRST# 24,31,53
AR30 CS59 0.1uF LITHIUM BATT
VCCASW_19
+
AR36
+3V_DUAL AR38 VCCASW_20
VCCASW_21
CS60
16V, X7R, +/-10%
0.1uF BATTERY * CS61
1uF
AU30 16V, X7R, +/-10% Battery Battery Holder 10V, X5R, +/-10%
AU36 VCCASW_22
Near D55
-
VCCASW_23 D55
* CS70
0.1uF
+3V_DUAL
AV40
VCCDSW3_3
V_PROC_IO_1
V_PROC_IO_NCTF_1
B56
16V, X7R, +/-10% +3V_EPW +VCCRTC
+1P05V_PCH Close to AV40 AN52
AT1 VCCSPI BU42
VCCADAC VCCRTC BT56 CS62 0.1uF 16V, X7R, +/-10% Near BR54
*
LS6 DCPRTC_NCTF BR54
*
S_VCCADPLLA_LR_10 AB1 DCPRTC AA32

VCCADPLLA DCPSUS_1 TPS117
10uH AT41 Change to 1uF; follow CRB 0.7-12/03
ECS1 DCPSUS_2 TPS118
A39
CS64
* CS63 0.1uF 16V, X7R, +/-10% 20100104: Change to 0.1uF; follow PDG 0.8
**
DCPSUS_3
RS156
0 ** 220uF 1uF
16V, +/-20%16V, X5R, +/-10%
AC2
VCCADPLLB DCPSUSBYP
DCPSST
AV41
BA46
TPS119
CS65 Dummy
0.1uF 16V, X7R, +/-10%
Dummy
10/12
LS7 BD82Q67
*
S_VCCADPLLB_LR_10
10uH
ECS2
* 220uF
CS66
1uF * +3V_EPW
16V, +/-20%16V, X5R, +/-10%
A
S_VCCADAC_LR_10
* CS29
1uF
A
6.3V,X5R,+/-10%
Near AN52
* CS81
22uF * CS82
22uF * CS83
22uF * CS84
22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
Title
Dummy Dummy
PCH-10: Power 2
20100104: CS29 change to 1uF; DWG NO Rev
A00
follow PDG 0.8
Lanikai _MT/DT
5 4 3 2 1
A
B
C
D
2011_1115
M6
M8 VSS_246 AE56 BB52
M9 VSS_247 BR36 VSS_1 VSS_122 BB6
VSS_248 VSS_2 VSS_123
5
5
N4 C12 BC14
N54 VSS_249 AY22 VSS_3 VSS_124 BC15
R11 VSS_250 A26 VSS_4 VSS_125 BC20
R15 VSS_251 A29 VSS_5 VSS_126 BC27
R17 VSS_252 A42 VSS_6 VSS_127 BC31
R22 VSS_253 A49 VSS_7 VSS_128 BC36
R4 VSS_254 A9 VSS_8 VSS_129 BC38
R41 VSS_255 AA20 VSS_9 VSS_130 BC47
R43 VSS_256 AA22 VSS_10 VSS_131 BC9
VSS_257 AA24 VSS_11 VSS_132 BD25
AA26 VSS_12 VSS_133 BD33
A4 AA28 VSS_13 VSS_134 BF12
A6 VSS_NCTF_1 AA30 VSS_14 VSS_135 BF20
B2 VSS_NCTF_2 U15 AA38 VSS_15 VSS_136 BF25
BM1 VSS_NCTF_3 VSS_263 U17 AB11 VSS_16 VSS_137 BF33
BM57 VSS_NCTF_4 VSS_264 U20 AB15 VSS_17 VSS_138 BF41
BP57 VSS_NCTF_5 VSS_265 U22 AB40 VSS_18 VSS_139 BF43
BT2 VSS_NCTF_6 VSS_266 AB41 VSS_19 VSS_140 BF46
BU4 VSS_NCTF_7 AB43 VSS_20 VSS_141 BF52
BU52 VSS_NCTF_8 U25 AB47 VSS_21 VSS_142 BF6
BU54 VSS_NCTF_9 VSS_267 U27 AB52 VSS_22 VSS_143 BG22
BU6 VSS_NCTF_10 VSS_268 U33 AB57 VSS_23 VSS_144 BG25
D1 VSS_NCTF_11 VSS_269 U36 AB6 VSS_24 VSS_145 BG27
F1 VSS_NCTF_12 VSS_270 U38 AC22 VSS_25 VSS_146 BG31
20091209: CRB0.7 pin

VSS_NCTF_13 VSS_271 R46 AC34 VSS_26 VSS_147 BG33
A4,BM57 are test points

VSS_272 U53 AC36 VSS_27 VSS_148 BG36
AU2 VSS_273 V20 AC38 VSS_28 VSS_149 BG38
VSSADAC VSS_274 V38 AC4 VSS_29 VSS_150 BH52
VSS_275 V6 AC54 VSS_30 VSS_151 BH6
VSS_276 W1 AE14 VSS_31 VSS_152 BJ1
VSS_277 W55 AE18 VSS_32 VSS_153 BJ15
VSS_278 W57 AE22 VSS_33 VSS_154 BK20
GND VSS_279 Y11 AE26 VSS_34 VSS_155 BK41
4
4
VSS_280 Y15 AE38 VSS_35 VSS_156 BK52

VSS_281 Y38 AE4 VSS_36 VSS_157 BK6
U41 VSS_282 Y40 AE47 VSS_37 VSS_158 BM10
U47 VSS_258 VSS_283 R49 AE8 VSS_38 VSS_159 BM12
T52 VSS_259 VSS_284 Y43 AE9 VSS_39 VSS_160 BM16
T6 VSS_260 VSS_285 Y46 AF52 VSS_40 VSS_161 BM22
U11 VSS_261 VSS_286 Y47 AF6 VSS_41 VSS_162 BM23
VSS_262 VSS_287 Y49 AG11 VSS_42 VSS_163 BM26
VSS_288 Y52 AG14 VSS_43 VSS_164 BM28
VSS_289 AG20 VSS_44 VSS_165 BM32
AG22 VSS_45 VSS_166 BM40
Y6 AG30 VSS_46 VSS_167 BM42
VSS_290 AG36 VSS_47 VSS_168 BM48
AG43 VSS_48 VSS_169 BM5
12/12 AG44 VSS_49 VSS_170 BN31
AG46 VSS_50 VSS_171 BN47
AG5 VSS_51 VSS_172 BN6
VSS_52 VSS_173
US1L
AG50 BP3
AG53 VSS_53 VSS_174 BP33
BD82Q67
AH52 VSS_54 VSS_175 BP35
AH6 VSS_55 VSS_176 BR22
AJ22 VSS_56 GND VSS_177 BR52
VSS_57 VSS_178
By Dell request remove US1_1 PCH heatsink detect for RTCSRST net spacing
AJ30 BU19
AJ57 VSS_58 VSS_179 BU26
AK52 VSS_59 VSS_180 BU29
Pin Y6 connect to GND-11/27

AK6 VSS_60 VSS_181 BU36
AL11 VSS_61 VSS_182 BU39
AL18 VSS_62 VSS_183 C19
AL20 VSS_63 VSS_184 C32
AL22 VSS_64 VSS_185 C39
AL26 VSS_65 VSS_186 C4
AL30 VSS_66 VSS_187 D15
AL36 VSS_67 VSS_188 D23
3
3
AL41 VSS_68 VSS_189 D3

AL46 VSS_69 VSS_190 D35
AL47 VSS_70 VSS_191 D43
AM3 VSS_71 VSS_192 D45
AM52 VSS_72 VSS_193 E19
AM57 VSS_73 VSS_194 E39
AN11 VSS_74 VSS_195 E6
AN12 VSS_75 VSS_196 E9
AN15 VSS_76 VSS_197 F10
AN17 VSS_77 VSS_198 F12
AN18 VSS_78 VSS_199 F16
AN20 VSS_79 VSS_200 F22
AN30 VSS_80 VSS_201 F26
AN36 VSS_81 VSS_202 F32
AN4 VSS_82 VSS_203 F33
AN43 VSS_83 VSS_204 F35
AN47 VSS_84 VSS_205 F36
AN54 VSS_85 VSS_206 F40
AN9 VSS_86 VSS_207 F42
AR20 VSS_87 VSS_208 F46
AR22 VSS_88 VSS_209 F48
AR52 VSS_89 VSS_210 F50
AR6 VSS_90 VSS_211 E54
AT15 VSS_91 VSS_212 F8
AT18 VSS_92 VSS_213 G54
AT43 VSS_93 VSS_214 H15
AT47 VSS_94 VSS_215 H20
AT52 VSS_95 VSS_216 H22
AT6 VSS_96 VSS_217 H25
AT8 VSS_97 VSS_218 H27
AU24 VSS_98 VSS_219 H33
AU26 VSS_99 VSS_220 H6
VSS_100 VSS_221
2
2
AU28 J1
AU5 VSS_101 VSS_222 J33
AV12 VSS_102 VSS_223 J46
AV18 VSS_103 VSS_224 J48
AV22 VSS_104 VSS_225 J5
AV34 VSS_105 VSS_226 J53
AV38 VSS_106 VSS_227 K52
AV47 VSS_107 VSS_228 K6
AV6 VSS_108 VSS_229 K9
AW57 VSS_109 VSS_230 L12
AY38 VSS_110 VSS_231 L17
AY6 VSS_111 VSS_232 L38
B23 VSS_112 VSS_233 L41
BA11 VSS_113 VSS_234 L43
BA12 VSS_114 VSS_235 M20
BA31 VSS_115 VSS_236 M22
Title
BA41 VSS_116 VSS_237 M25

BA44 VSS_117 VSS_238 M27
DWG NO
BA49 VSS_118 VSS_239 M31

BB1 VSS_119 VSS_240 M33
BB3 VSS_120 VSS_241 M36
VSS_121 VSS_242 M46
VSS_243 M52
VSS_244 M57
VSS_245
11/12
Date: Wednesday, June 13, 2012
US1K
BD82Q67
1
1
Sheet
PCH-11: GND
Lanikai _MT/DT
30
of
Rev
71
A00
A
B
C
D
5 4 3 2 1
Clear Password CLR_CMOS Chassis Intruder

+3V_DUAL
1-2: NORMAL +VCCRTC

Header_1X2
EMPTY: CLEAR PASSWORD *RS159
8.2K
24,29,53 S_RTCRST#
2
+/-5% 1
D
PSWD *RS158 Header_1X3
D
24 S_PSWD_CLR
1
2
RTCRST Jumper Type 1M
3
* 4.7K
Dummy Default
24,27 S_INTRUD_CBL_DET#
2 3
*
RS166 RS160 10K 1 2
Header_1X2 24 S_INTRUDER# 1
Pop CLR_CMOS INTRUDER
PSWD_JUMPER(1-2)
* CS67
0.1uF
16V, X7R, +/-10%
Jumper_2P_Blu Dummy
SERVICE_MODE
BEEP
+3V_S5 +3V_S5
C
*RS206
1K
*RS161
C
+/-5% 1K
+/-5% +5VSB
E
QS6 RNS1 BEEP

24 S_MFG_MODE_OR
RS162 10K B MMBT3906
SERVICE_MODE
*1 2
+
*
1 3 4
BUZZER
C
2 5 6 -
24,36 A_Z_SDOUT 7 8
100 Ohm Buzzer
Header_1X2
C
**
B
24 S_SPKR_OUT
RS164 1K +/-1% QS7
MMBT3904-7-F * CS68
1uF
RS165 1K +/-1% 25V, X5R, +/-10%
32,33 O_SPEAKER
E
B
SKU ID Chassis ID BOARD ID B
+3V +3V_S5 +3V
+3V
* RS95 * RS96 * RS106 ** RS40 * RS41

RS97 10K 10K 10K
10K 10K 10K Dummy Dummy Dummy
@Z @N Dummy
23 S_GPI_BRD_REV2
23 S_GPI_SKU2
Rev2 Rev1 Rev0 Type 24 S_GPI_BRD_REV1
24 S_GPI_SKU1
check : need to update table +3V
0 0 0 Default 23 S_GPI_BRD_REV0
24 S_GPI_SKU0
0 0 1 Reserved RS111 ** RS42* RS43
* RS100 * RS98 * RS99
0 1 0 Reserved 20100106: change
220
+/-5%
1K 10K
220 220 220
+/-5% +/-5% +/-5%
ID2 ID1 ID0 Type
* RS44 * RS45 * RS46
0 1 1 Reserved
to 1k since have
@S,J,N @S,Z,J 10K 10K 10K
internal pull-up
Dummy Dummy Dummy
1 0 0 Reserved 10k
1 0 1 SFF 23 S_GPI_CHASSIS_ID0
1 0 1 Reserved
23 S_GPI_CHASSIS_ID1
1 1 0 Reserved
SKU ID 1 0 0 Comoros 23 S_GPI_CHASSIS_ID2
1 1 1 Reserved
A A
SKU1 SKU0 Type 0 0 0 MT/DT * RS49* RS50* RS51

0 0 TPM 1K 1K 10K
0 1 TCM 0 1 1 USFF
Title
1 0 non TPM/TCM PCH MISC Conn/BUZ/ID

1 1 Reserved
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_DUAL
Delet RO2; SMSC suggestion-12/08/09 PWRGD_3V
+VCCRTC_SIO
Reserved for pin 24,34,57,79,106,122
+3V Delet RO6; SMSC
CO1
100pF * *RO3
8.2K
RO8 CO2 CO3 CO4 CO5 CO6 CO7 CO8 50V, NPO, +/-5% +/-5%
+3V_DUAL * 2MOhm
* CO10 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
suggestion-12/08/09
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

close to Pin 6 +3V_DUAL +/-5% 1uF
close to Pin 47 16V, X5R, +/-10%
+3V_DUAL 20100107: change to
CO9
0.1uF 0.1uF +3V_DUAL for layout
16V, X7R, +/-10% CO11
D
* D
122
106
UO1 16V, X7R, +/-10% RO107
79
57
34
24
23
47
6
+5V Add SMBus 10K
+/-1%
VBAT
VTR_6
VTR_5
VTR_4
VTR_3
VTR_2
VTR_1
VCC
HVTR
T_ESATA_DET# 78 switch
GP42 / DRVDEN0 RNO4
circuit-11/25/09
33 O_INDEX#
76
INDEX# SLCT
80 O_SLCT
8 7 20100105: Mount
4
75 81 O_PE
S_SMBDATA_PCI 74 MTR0# PE 82 O_BUSY 6 5 SMBus control MMDT5551
GP40 / SMBDAT1 BUSY 4 3 QO16 +12V
73 83 O_ACK#
circuit by
DS0# ACK# 2 1
*
Floppy
S_SMBCLK_PCI 72 84
71 GP36 / SMBCLK1 PD7 85 B_ATX_PWROK
70 DIR# PD6 86 1K
* RO106
3
68 STEP# PD5 87 +/-5%
67 WDATA# PD4 88 8.2K
Parallel Port
66 WGATE# PD3 / TMS 89 S_SMB_SW
33 O_TRK0# TRK0# PD2 / TDO
65 SCH5545-NS 90 RO108 10K
33 O_WPT# WRTPRT# PD1 / TDI 63,71 B_ATX_PWROK
64 91
*
33 O_RDATA# RDATA# PD0 / TCK
63 93
HDSEL# SLCTIN# RO53
62 94
33 O_DSKCHG#
*
DSKCHG# INIT# 95 O_ERR#
ERROR# 96
9 ALF# 97 1K+/-5% S_SMB_SW
27 C_14M_SIO CLOCKI STROBE#
10 QO4
G
24,46,53 F_LAD0 LAD0
11 2N7002
24,46,53 F_LAD1 LAD1
12 98
24,46,53 F_LAD2 LAD2 DCD1# / GP43 O_DCD1#_R 50
13 99 S D S_SMBCLK_PCI 24,38,39,58,59
24,46,53 F_LAD3 LAD3 DSR1# / GP44 O_DSR1#_R 50 15,16,17,18,52 S_SMBCLK_MAIN
LPC
14 100
Serial Port 1
24,46,53 F_FRAME# LFRAME# RXD1 / GP45 O_RXD1_R 50
15 101 O_RTS1#_R 50
24 F_LDRQ# LDRQ# RTS1# / GP46
C 16 102 S_SMB_SW C
9,24,34,46,52,53 S_PLTRST# LRESET# GP47 / TXD1 O_TXD1_R 50
17 103 QO5
G
SPI_DO / GP04 CTS1# / GP50 O_CTS1#_R 50
18 104 2N7002
27 C_LPC_SIO PCICLK DTR1# [TEST_EN] /GP51 O_DTR1#_R 33,50
1 105
23,46 F_SERIRQ# SER_IRQ RI1# / GP52 O_RI1#_R 50
77 S D S_SMBDATA_PCI 24,38,39,58,59
24 O_IO_PME# GP41 / IO_PME# 15,16,17,18,52 S_SMBDATA_MAIN
107
GP53 / DCD2# O_DCD2#_R 55
108
GP54 / DSR2# O_DSR2#_R 55
109
Serial Port 2
GP55 / RXD2 O_RXD2_R 55
SMB SPI
27 110 O_RTS2#_R
24 S_SMLINK1_DATA SMBDAT2 / GP10 GP56 / RTS2# +12V_CPU
28 111
24 S_SMLINK1_CLK SMBCLK2 / GP11 GP57 / TXD2 O_TXD2_R 33,55
SPI_DI 29 112 +3V
SPI_DI / GP12 GP60 / CTS2# O_CTS2#_R 55
30 113
SPI_CK / GP13 GP61 / DTR2#
GP62 / RI2#
114
O_DTR2#_R
O_RI2#_R
33
55
*RO23
Delet RO33,RO34; SMSC suggestion-12/08/09 8.2K
4
GP00
+/-5% *RO19
5 30K
7 GP01 121 +/-1%
GP02 GP64 / A20M O_GA20 23
8 120 O_RTS2#_R
24,52,53,56 O_PWRBTN#IN 36 GP03 GP63 / KBDRST# 118
O_KB_RST# 23 *RO28
KB / MS
PWRBTN# / GP15 MDAT O_MS_DATA 49
6
117 698
MCLK O_MS_CLK 49 MMDT5551
21 116 +/-1%
24 S_SUSCLK CLK32 KDAT O_KB_DATA 49 QO2
25 115
56 O_YELLOW# YELLOW# / GP06 KCLK O_KB_CLK 49 +3V_DUAL
26
56 O_GREEN# GREEN# / GP07 +3V_DUAL
Miscellaneous
52
56 O_FP_CBL_DET# GP25 / BC_DAT
X_PLTRST_PCIE_SLOT#_R 53
1
54 PCI_RST_SYS# / GP26
9 H_RESET#
*
55 PCI_RST_SLOTS# / GP27 RO12 30K
63 O_PSON# PS_ON# / GP30
37 O_AUD_PCSPKR_DET# 56 39 +/-1%
B GP31 / BC_INT# TACH1 / GP17 O_SEN_CPUFAN 48 B
58 40 20100111:
SPI_CS# / GP32 TACH2 / GP20 O_SEN_CHAFAN 48
59 41
24,52 PWRGD_3V
60 PWR_GOOD_3V / GP33 TACH3 / GP21 49
Remove PSU
24 O_RSMRST# RSMRST# GP22 / PWM1 O_CPUFAN_PWM 48 PWM control
Net change to 24,53,64,66,70,71 S_SLP_S3# 123 50
O_CHAFAN_PWM 48
* * **
124 SLP_S3# GP23 / PWM2 51 RO20 8.2K +/-5% O_AUD_PCSPKR_DET#
DO1 change to RO109; SMSC
HW Monitor
H_RESET#-12/28/09 24,53,65,71 S_SLP_S4# 125 SLP_S4_S5# / GP66 GP24 / PWM3 RO21 8.2K +/-5% O_BC_CLK
63,71 B_ATX_PWROK
TRST# 126 PWRGD_PS 22 O_PECI_REQ# RO1091 2 suggestion-12/08/09
S_PECI_REQ# 24
*
127 TRST# GP05 / PECI_REQUEST# 48 O_CPUFAN_ID RO29 8.2K +/-5% RO22 8.2K +/-5% SPI_DI
31,33 O_SPEAKER SPEAKER/GP70 V_IN
128
24,53,65,66 S_SLP_M# GP71 / IO_SMI# 43 RO38 100K+/-5% T_ESATA_DET#
+1P05V_VCCIO REMOTE1+ O_TR_CPU+ 47
44 Dummy
REMOTE1- O_TR_CPU- 47
33 45
33 O_GP73_PU O_TR_MB+ 47
*
PECI_READY/ LVSMB_DAT1 REMOTE2a+/REMOTE2b-

PECI
RO35 33+/-5% H_PECI_R 32 46 +3V

GP35/BC_CLK
9,23 H_PECI PECI / LVSMB_CLK1 REMOTE2a-/REMOTE2b+ O_TR_MB- 47

31 35
****
PECI VREF GP14 38 Delet RO36,RO37 and connect Tmin_Shift to PCH directly; SMSC suggestion-12/08/09 RO24 4.7K +/-5% S_SMBDATA_MAIN
CO12 PROCHOT_IN# /PROCHOT_OUT# RO25 4.7K +/-5% S_SMBCLK_MAIN
Reserved RO35; SMSC suggestion-12/08/09
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
TMIN_SHIFT 23
HVSS
AVSS
CAP1
0.1uF RO26 30K +/-1% O_TXD1_R

H_PROCHOT# 9,67
16V, X7R, +/-10% RO27 8.2K +/-5% TMIN_SHIFT
+3V_S5
69
2
3
19
37
61
92
119
42
20
+3V_DUAL
**
O_BC_CLK RO13 4.7K +/-5% S_SMBDATA_PCI
RO14 4.7K +/-5% S_SMBCLK_PCI
* CO13
4.7uF O_TR_MB+
5
6.3V, X5R, +/-10% UO4

VCC
1
A
OE#
Dummy
22 Ohm * CO14 50V, NPO, +/-5%
100pF A
*
4 RO41 O_TR_MB-
Y X_PLTRST_PCIE_SLOT# 38,39,59
Place Near close to 5544 pin45,46
+12V_CPU S_SLP_S3# X_PLTRST_PCIE_SLOT#_R 2 +/-1%
TRST#
SIO pin.123 A
GND O_TR_CPU+
Title
CO15
* RO39
* CO16 74LVC1G125GW
3
0.1uF 1K 1nF
Dummy +/-5% 50V, X7R, +/-10%
* CO17 50V, NPO, +/-5% SIO-SCH5544-1
16V, X7R, +/-10% Dummy 100pF
O_TR_CPU- DWG NO Rev
close to 5544 pin43,44 A00
Lanikai _MT/DT
*
RO40 0 +/-5%

5 4 3 2 1
5 4 3 2 1
SCH5544 Decoupling
+3V +3V
+3V_DUAL +VCCRTC_SIO +3V

RO43
* 30K *RO44
30K
+/-1% +/-1%
* CO18
0.1uF * CO19
0.1uF * CO20
0.1uF * CO21
0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% O_TXD2_R O_DTR2#_R
D Dummy Dummy D
+1P05V_VCCIO +3V
+3V_DUAL +3V_DUAL
* RO45 +5V
8.25K RO46 RO48
+/-1% * 8.2K * 8.2K
+/-5% +/-5%
32,55 O_TXD2_R Dummy Dummy
20100107: Remove RO47, RO53 and
+3V
* O_RTS1#_R strapping, SMSC
6
4
RO49 RNO1
*RO50
2
4
6
8
MMDT5551 O_SPEAKER 31,32 suggestion O_DTR1#_R 32,50
7.15K 1K 1K
RO51 QO6 +/-1% +/-5%
* +/-5%
* 13
5
7
2KOhm
+/-1% RO52 RO54
* 8.25K * 30K
O_INDEX# 32
1
O_TXD2_R +/-1% +/-1%
*RO55 +3V_EPW
O_DSKCHG# 32
33KOhm
O_TRK0# 32
+/-1%
O_WPT# 32
C SPEAKER DTR1# O_RDATA# 32 C

Diag_En Flash_en
+1P05V_PCH +3V
PULL
HIGH Disable Flash Enable
* RO56
8.25K
+/-1%
PULL
O_TXD2_R Enable Parallel
LOW
Enable
* SIO STRAPING
6
RO57
MMDT5551 6.8K
+1P05V_MEQO7 +/-1%
1
O_TXD2_R
B B
+1P5V_SM +3V
20100104: Removed useless dummied
* RO58
components, and only left O_PECI_READY pull-up
8.25K
+/-1%
O_TXD2_R
+1P05V_VCCIO
*
6
+3V RO61
MMDT5551 10K
QO9 +/-1% * RO60
1K
* RO62
30K
1
+/-1%
O_GP73_PU 32
O_DTR2#_R 32
24,52,64,67 P_VR_READY
A 5544 PRE-POST DIAG PG GENERATION A
Title
SIO-SCH5544-2 (MISC)
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
+3V_LAN
20091216 Intel 82579 schematic check list 0.5:

Change net name from CLK_REQ_N to S_FLEXBAY_HDR_CBL_DET#
*RL1
D 10K UL1 D
20100105: Remove RL2 and S_FLEXBAY_HDR_CBL_DET#
48 13
connection since useless; PDG 0.8 36 CLK_REQ_N MDI_PLUS_0 14 L_MDI_0+ 35
9,24,32,46,52,53 S_PLTRST# PE_RST_N MDI_MINUS_0 L_MDI_0- 35
near the PCIe transmitter. 44 17
27 C_PCIE_L1 PE_CLKP MDI_PLUS_1 L_MDI_1+ 35
45 18
27 C_PCIE_L1# PE_CLKN MDI_MINUS_1 L_MDI_1- 35
CL1 0.1uF
****
22 X_L1X1_RXP
MDI
16V, X7R, +/-10% X_L1X1_RXP_C 38 20
PCIE
CL3 0.1uF X_L1X1_RXN_C 39 PETP MDI_PLUS_2 21 L_MDI_2+ 35 +3V_LAN
22 X_L1X1_RXN 16V, X7R, +/-10% PETN MDI_MINUS_2 L_MDI_2- 35
CL2 0.1uF X_L1X1_TXP_C 41 23
22 X_L1X1_TXP PERP MDI_PLUS_3 L_MDI_3+ 35
16V, X7R, +/-10% X_L1X1_TXN_C 42 24
CL4 0.1uF PERN MDI_MINUS_3 L_MDI_3- 35
22 X_L1X1_TXN
16V, X7R, +/-10% *RL4 *RL5
6 3.3K 3.3K
28 RSVD_NC
24 S_SMLINK0_CLK SMB_CLK
SMBUS
31 1
24 S_SMLINK0_DATA SMB_DATA RSVD_1/VCCP3P3_1 2
RSVD_2/VCCP3P3_2 5
VDD3P3_IN +3V_LAN Place near pin
L_LAN_DISABLE# 3
LAN_DISABLE_N 4 VDD3P3
VDD3P3_OUT
26 15
35
35
L_ACTLEDN
L_LINK100#
27 LED0 VDD3P3_1 19 * CL5
1uF * CL6
1uF 6.3V,X5R,+/-10%
LED
25 LED1 VDD3P3_2 29 Dummy
35 L_LINK10# LED2 VDD3P3_3
ALWAYS DUMMY 6.3V,X5R,+/-10%
+3V_LAN 47
*
+3V_LAN RL6 10K 32 VDD1P0_7 46 +1P05V_PCH
C Dummy 34 JTAG_TDI VDD1P0_8 37 C
JTAG
TPL1
**
RL7 10K Dummy 33 JTAG_TDO VDD1P0_9 +3V_LAN
Dummy 35 JTAG_TMS 43
20091216 CRB0.7 :Connect a series CL24 JTAG_TCK VDD1P0_1
RL8 10K Place close
(10 pF) capacitor to XTAL_OUT (pin 9).
*
Dummy 11 RL9
RL15 0 9
XTAL_OUT
VDD1P0_2 to PHY 0 *RL10
10 40 +/-5% 10K
XL1 XTAL_IN VDD1P0_3 22 Dummy
less than 325 mils VDD1P0_4
1 2 16
VDD1P0_5 8 VDD1P0
24 L_LAN_DISABLE#
*
XTAL 25MHz RL12 1K L_LAN_TESTEN 30 VDD1P0_6
TEST_ENABLE LL1
*
7
* CL7
* CL8 L_LAN_1P0_CTRL 4.7uH
*RL14
*
33pF 33pF RL13 3.01K 12 CTRL_1P0
+/-1% RBIAS 49 10K
VSS_EPAD
50V, NPO, +/-10%
50V, NPO, +/-10%
21040FE00-187-G * CL9
22uF * CL10
0.1uF
Dummy
16V, X7R, +/-10%

Net VDD1P0 and 6.3V,X5R,+/-20%
L1_LAN_1P0_CTRL
keep short and wide 20100107: Dummy RL9 and
Mount LL1; CRB 0.7
B B
Close to PIN5 (VDD)
+3V_LAN 20091216 follow CRB0.7 and 82579 cheklist: does not require
any MDI termination.(delete => RL15, RL16, RL17, RL18, RL19,
RL20, RL21, RL22, CL11, CL12, CL13, CL14)
* CL24
10uF * CL15
22uF * CL16
0.1uF
10V, X5R, +/-10% 16V, X7R, +/-10%
Dummy 6.3V,X5R,+/-20%
A A
Title
DWG NO
LAN:Intel Lewisvillies Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
LAN CONNECTOR VCT

+5V_DUAL_USBKB USBPWR6_F_50
FU1
*
1 2
* CL17
1uF * RU1 10K
+/-1% 1
U_USB_OC_R_#4 22
25V, X5R, +/-10% Fuse 2A * ECU1
470uF * CU7
0.1uF RU2
+3V_LAN 6.3V, +/-20% 16V, X7R, +/-10% 15K
+/-1%
2
D
* CL18
0.1uF D
* CL19
0.1uF
16V, X7R, +/-10%
NIC_USB
16V, X7R, +/-10% LU1
U_USB8N_R 1 4
U_USB8N 22
USBPWR6_F_50
28 U_USB8P_R 2 3
U_USB8P 22
14 29
GRN_LED
ORG_LED
30 Common Choke 90 Ohm
31
USB-2
USB-1
**
34 L_LINK10# RL23 150 +/ -1% 13
**
34 L_LINK100# RL24 150 +/ -1% 15 RU3 0
16 Dummy
6 20 RU4 0
2
CL20
* * CL21
34 L_MDI_0+
Dummy
RJ45-MJ2
470pF 470pF 3 17 U_USB9N_R
34 L_MDI_0-
50V, X7R, +/-10% 50V, X7R, +/-10% 4 21 U_USB8N_R
34 L_MDI_1+
5 LU2
34 L_MDI_1-
7 18 U_USB9P_R U_USB9N_R 1 4
34 L_MDI_2+ U_USB9N 22
8 22 U_USB8P_R
34 L_MDI_2-
9 U_USB9P_R 2 3
34 L_MDI_3+ U_USB9P 22
10 19
34 L_MDI_3-
1 23 Common Choke 90 Ohm
YLW_LED
+3V_LAN
**
12 24 RU5 0
*
34 L_ACTLEDN RL25 150 11 25 Dummy
+/ -1% 26 RU6 0
27
C
CL22
470pF * * CL23
470pF
Dummy
C
50V, X7R, +/-10% 50V, X7R, +/-10%
USBPWR6_F_50
CONN-USBX2_RJ45
UU1
U_USB8N_R 1 6 U_USB8P_R
2 5
U_USB9N_R 3 4 U_USB9P_R
IP4220CZ6
LAN POWER
+3V_S5 +3V_LAN
B +5V_S5 SI4835DDY-T1-E3 B
QL1
3 8
* RL26 2 7
1K 1 6
5
L_VREG_LANDUAL_PCH
1
* ECL1
* CL25
4
120uF 0.1uF
C
16V, +/-20% 16V, X7R, +/-10%

*
2
24 S_SLP_LAN# RL29 4.7K B QL2
MMBT3904-7-F
RL30
E
*RL31
100K
L_VREG_Gate
Dummy 1K
+/-1%
* CL26
1uF
6.3V,X5R,+/-10%
+3V +3V_S5
Title
Intel A
* CL27
* CL28 LAN Power & LAN/USB Conn
1uF 1uF
16V, X5R, +/-10% 16V, X5R, +/-10% DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+5V Amplifer Power from 5V +5VA

FBA1
*
A_BIAS_MIC1_L CA5 10uF 6.3V, X5R, +/-20% VCC_AUD +5V_S5
*
FB 600 Ohm close to pin 39
* CA1
10uF * CA2
0.1uF * CA3
10uF * CA4
0.1uF
close to pin 28
6.3V, X5R, +/-20%
16V, X7R, +/-10%
6.3V, X5R, +/-20%
16V, X7R, +/-10%
FBA2
A_GND
D D
*
FB 600 Ohm
Front HP
Cap-saving, if HP-OUT port no use A_FRONT_L 37
Dummy Dummy
A_FRONT_R 37
6.3V, Y5V, +80%/-20%
6.3V, Y5V, +80%/-20%

A_BIAS_MIC1_L_VB 37
A_BIAS_MIC1_R 37 40 mils
A_BIAS_MIC2 37
A_BIAS_MIC1_L 37
*CA6 *CA7 * CA9
0.1uF * CA10
10uF
16V, X7R, +/-10%
6.3V, X5R, +/-20%

2.2uF 2.2uF VCC_AUD
* CA8
10uF
6.3V, X5R, +/-20%

A_GND
A_GND UA1 A_GND A_GND
36
35
34
33
32
31
30
29
28
27
26
25
A_GND
CBP
CPVEE
HP-OUT-L
CPVREF
MIC2-VREFO
CBN
HP-OUT-R
MIC1-VREFO-L
VREF
MIC1-VREFO-R
AVSS1
AVDD1
Dummy
Dummy
A_GND 37 24
AVSS2 LINE1-R
VCC_AUD 38 23
AVDD2 LINE1-L
+5VA 39 22
PVDD1 MIC1-R A_MIC1_R 37
C Front MIC C
40 21
37 CLASSD_R+ SPK-L+ MIC1-L A_MIC1_L 37
VCC_AUD decouple
41 20 TPA1
37 CLASSD_R- SPK-L- MONO-OUT VCC_AUD
*
42
PVSS1 JDREF
19 RA8 20K +/-1% A_GND close to
43 18 pin 38
PVSS2 Sense-B B_SENSE 37
close to * CA17
* CA18
* CA19
44 17 0.1uF 0.1uF 10uF
TPA2 SPK-R- MIC2-R A_MIC2_R 37
Rear pin 25
+3V +3V_VA 45 16
TPA3 SPK-R+ MIC2-L A_MIC2_L 37
16V, X7R, +/-10%
16V, X7R, +/-10%
6.3V, X5R, +/-20%

Digital Power from 3V +5VA 46
PVDD2 LINE2-R
15
A_LOUT_R 37
A_GND A_GND A_GND
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
47 14
TPA4 SPDIFO2/EAPD LINE2-L A_LOUT_L 37
48 13
SDATA-OUT
TPA5 SPDIFO Sense A A_SENSE 37
FBA4
SDATA-IN
*
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
ANALOG
DVSS2
SYNC
49
PD#
GND
close to pin 1
* CA12
0.1uF
FB 600 Ohm
* CA16
0.1uF * CA14
10uF * CA15
0.1uF
DIGITAL
16V, X7R, +/-10%
16V, X7R, +/-10%
6.3V, X5R, +/-20%
16V, X7R, +/-10%
ALC269Q-VB3-GR
1
10
11
12
Dummy
+3V_VA
A_Z_SDIN0_R
BIT_CLK
B PD#
TPA6 TPA7 TPA8
A_Z_RST# 24
B
24,31 A_Z_SDOUT A_Z_SYNC 24
24 A_Z_BITCLK +3V_VA
*
RA13 33+/-5%
A_Z_SDIN0 24
* CA20
22pF
Dummy
50V, NPO, +/-5%
*
A_Z_RST# RA9 0 +/-5% PD#

Dummy
+3V_VA
*
RA10 0 +/-5% PD#

Dummy
+3V_S5 +5V_S5
Pop RA10: always H
Pop RA11 : control by BIOS (GPIO)
Pop RA9 : for De-pop during powr on.
PD#= L : Power down Class D SPK amplifer * RA41
QA1 1K
PD#= H : Power up Class D SPK amplifer
G
2N7002
A_Z_RST# S D PD#
A A
+3V_VA
* RA12
*
RA14 4.7K +/-5% A_Z_RST# 10K

Dummy Dummy
Pop is RST signal glitched Title
Audio ALC269Q
DWG NO Rev
A00
RA12 reserved for co-layout ALC269-VC Lanikai _MT/DT
5 4 3 2 1
Front Audio Rear Audio Jack
36 A_BIAS_MIC1_R
36 A_BIAS_MIC1_L
Audio Jack
close to codec
*
36 A_BIAS_MIC1_L_VB CA21 10uF A_LOUT_L_C RA15 75+/-1% A_LOUT_L_L
36 A_LOUT_L
*
25V,+/-20%
*RA17 *RA18 *RA19
2.2KOhm 2.2KOhm 2.2KOhm
*
+/-1% +/-1% +/-1% 36 A_LOUT_R CA22 10uF A_LOUT_R_C RA20 75+/-1% A_LOUT_R_L LINE_OUT
*
Dummy 25V,+/-20% D
D Front MIC
Rear Line In / Mic D
6.3V, X5R, +/-10% LINE_IN / MIC_IN
**
CA23 1 2 4.7uF A_MIC1_R_C RA22 1K +/-1% 36 A_BIAS_MIC2
36 A_MIC1_R close to codec C
**
A_MIC1_R_L 56
3
36 A_MIC1_L CA24 1 2 4.7uF A_MIC1_L_C RA24 1K +/-1% DA3
A_MIC1_L_L 56
BAT54A
6.3V, X5R, +/-10%
AUDIO
*CA25 *CA26
2
22 INSULATOR
470pF 470pF 23
50V, X7R, +/-10%
50V, X7R, +/-10%

A_JD_LOUT 24
RA26 * *RA27 25
4.7KOhm 4.7KOhm 26
+/-1% +/-1% 27
6.3V, X5R, +/-10% 28
*
A_GND A_GND 36 A_MIC2_L CA27 1 2 4.7uF A_MIC2_L_C RA28 1K A_MIC2_L_L 29
*
+/-1% 2
Improve HP-OUT 32-Ohm’s Cross-Talk and THD+N 3
It can be reserved if A_JD_MIC2 4
*
CA28 1 2 4.7uF A_MIC2_R_C RA30 1K A_MIC2_R_L 5
output de-coupled 36 A_MIC2_R
*
+/-1% 1
cap used SMD type. Front HP 6.3V, X5R, +/-10%
CA29
* * CA30 CA31
* * CA32 CONN-Audio Port A_GND
**
36 A_FRONT_R RA32 22 Ohm +/-1% 470pF 470pF 470pF 470pF

A_FRONT_R_L 56
50V, X7R, +/-10%
50V, X7R, +/-10%

CA35 10nF
50V, X7R, +/-10%

50V, X7R, +/-10%
*
36 A_FRONT_L RA34 22 Ohm +/-1% 25V, X7R, +/-10%
A_FRONT_L_L 56
C Port A Support Capless HP

A_GND
A_GND C
Change to 22ohm; follow * CA33
* CA34 CA36 10nF
*
470pF 470pF 25V, X7R, +/-10%
Wembley-12/25/09
50V, X7R, +/-10%
50V, X7R, +/-10%

A_GND
CPA2 A_GNDA_GND A_GNDA_GND
CA37 10nF 2 1
*
25V, X7R, +/-10% A_LOUT_L_L A_MIC2_L_L
COPPER
A_GND Dummy A_LOUT_R_L A_MIC2_R_L
A_GND A_GND CPA4
CA38 10nF 2 1
*
25V, X7R, +/-10%
2
COPPER
A_GND Dummy DA5 DA4
**
RA36 39.2K +/-1% Front HP CPA5 PESD5V0L2BT PESD5V0L2BT

36 A_SENSE A_JD_FRONT 56 CA39 10nF 2 1
*
RA37 20K +/-1% Front MIC 25V, X7R, +/-10% Dummy Dummy
A_JD_MIC1 56 COPPER
A_GND Dummy
Close to A_GND
3
Pin 33
A_GND A_GND
A_MIC1_R_L A_FRONT_R_L
**
A_MIC1_L_L A_FRONT_L_L RA38 20K +/-1% A_JD_MIC2 Rear MIC In/LINE IN
B 36 B_SENSE B
RA39 39.2K +/-1% A_JD_LOUT Rear Line out
1
Close to Pin 33
DA6 DA7
PESD5V0L2BT PESD5V0L2BT
Dummy Dummy
3
A_GND A_GND
Place connector CHASSIS

* CA42
100pF SPEAKER
Place near
Audio Chip
* CA41
1nF
50V, NPO, +/-5%
Dummy
50V, X7R, +/-10%
INT_SPKR Header 1x5 cut2
CLASSD_R- 1
36 CLASSD_R-
Pin.1--> Left-
A CA43 1uF 3 Pin.2--> NC key A
*
4 Pin.3--> GND
32 O_AUD_PCSPKR_DET#
Dummy 10V, X5R, +/-10% CLASSD_R+ 5 Pin.4--> SPK det#
36 CLASSD_R+
Pin.5--> Left+
close to AR12, AR13
* CA45
1nF
Header_1X5_K2
Title
50V, X7R, +/-10%
* CA44
100pF Audio Conn
50V, NPO, +/-5%
Dummy DWG NO Rev
A00
Place connector Lanikai _MT/DT
5 4 3 2 1
20100513: RNX1 pin1 change

connection to GND and pin5
change connection to +3V
X_1X16_RXP[15..0] 10
20100108: Swap pin for layout
+3V
Dummy X_1X16_RXN[15..0] 10
RNX1
10 X_1X16_TXP[15..0] 2010317: Slot1 change to Blue,

*1 2
X16_TRST
X16_TDI
3 4 X16_TMS
+3V_PCIAUX +3V +12V
Foxconn P/N: 34030EK00-600-G +12V +3V 5 6 X16_TCLK
10 X_1X16_TXN[15..0] 7 8
D SLOT1 4.7K Ohm D
+/-5%
B1 A1
B2 12V1 PRSNT1# A2
B3 12V2 12V3 A3
B4 RSVD8 12V4 A4
**
RX1 0 Dummy B5 GND1 GND68 A5 X16_TRST +12V
24,32,39,58,59 S_SMBCLK_PCI SMCLK JTAG2
RX2 0 Dummy B6 A6 X16_TDI
24,32,39,58,59 S_SMBDATA_PCI SMDAT JTAG3
B7 A7
B8 GND2 JTAG4 A8 X16_TMS
X16_TCLK B9 3.3V3 JTAG5 A9
B10 JTAG1 3.3V1 A10
B11 3.3VAUX 3.3V2 A11
24 S_WAKE# WAKE# PWRGD X_PLTRST_PCIE_SLOT# 32,39,59
KEY
* ECX1
470uF * CX1
0.1uF * CX2
0.1uF
B12 A12 16V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
B13 RSVD1 GND67 A13
GND3 REFCLK+ C_PCIEX16_1 27
X_1X16_TXP0 CX36 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DP0 B14 A14
C_PCIEX16#_1 27
**
X_1X16_TXN0 CX37 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DN0 B15 HSOP0 REFCLK- A15

B16 HSON0 GND66 A16 X_1X16_RXP0
B17 GND4 HSIP0 A17 X_1X16_RXN0
B18 PRSNT2_B17# HSIN0 A18
GND5 GND65 +3V

** ** **
X_1X16_TXN1 CX35 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DN1 B20 HSOP1 RSVD7 A20 Dummy
HSON1 GND64
B21
B22 GND6 HSIP1
A21
A22
X_1X16_RXP1
X_1X16_RXN1
* ECX2
470uF * CX8
0.1uF * CX9
0.1uF
C X_1X16_TXP2 CX32 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DP2 B23 GND7 HSIN1 A23 +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10% C
X_1X16_TXN2 CX33 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DN2 B24 HSOP2 GND63 A24
X_1X16_TXP3 CX30 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DP3 B27 GND9 HSIN2 A27
B31 RSVD2 HSIN3 A31
B32 PRSNT2_B31# GND59 A32 +3V_PCIAUX
GND11 RSVD6
** ** ** **
X_1X16_TXN4 CX29 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DN4 B34 HSOP4 RSVD5 A34

HSON4 GND58
B35
B36 GND12 HSIP4
A35
A36
X_1X16_RXP4
X_1X16_RXN4
* ECX3
470uF * CX16
0.1uF
X_1X16_TXP5 CX26 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DP5 B37 GND13 HSIN4 A37 +/-20% 16V, X7R, +/-10%
GND17 HSIN6
20100121: update footprint
X_1X16_TXP7 CX22 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DP7 B45 A45 20100204: Need to update part #
HSON7 GND52
20100317: Link 2EG00211-T7L-4F from M disk
B47 A47 X_1X16_RXP7
B49 PRSNT2_B48# HSIN7 A49 SLOT1_LATCH
GND19 GND51
B B
G G
** ** ** ** ** ** ** **
X_1X16_TXN8 CX21 220nF 16V,X7R,+/-10% X_EXP_A_TX_C_DN8 B51 HSOP8 RSVD4 A51

HSON8 GND50
2
B52 A52 X_1X16_RXP8
B53 GND20 HSIP8 A53 X_1X16_RXN8 Retention Module
2
A GND33 HSIN14 A
RSVD3 GND35 Title
Slot-PCIE-16X
340303U00-600-G Slot1: PCIe 16x
340304R00-278-G DWG NO Rev
340304J00-317-G
A00
340306Y00-GRS-G Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+3V
RNX2
*1 2
X4_TDI
X4_TMS
3 4 X4_TCLK
5 6 X4_TRST
7 8
Change SLOT4 for Cost
4.7K Ohm down-12/07/09
+/-5%
+3V_PCIAUX +3V +12V +12V +3V
Dummy
D SLOT4 D
B1 A1
B2 12V1 PRSNT1# A2
B3 12V2 12V3 A3
RX4 B4 RSVD8 12V4 A4
**
0 Dummy B5 GND1 GND68 A5 X4_TRST
Dummy ECX4,CX38 for Cost
0 Dummy B6 A6 X4_TDI +12V down-11/23/09
24,32,38,58,59 S_SMBDATA_PCI SMDAT JTAG3
B7 A7
RX3 B8 GND2 JTAG4 A8 X4_TMS
X4_TCLK B9 3.3V3 JTAG5 A9
B10 JTAG1 3.3V1 A10
B11 3.3VAUX 3.3V2 A11
24 X4_WAKE# WAKE# PWRGD X_PLTRST_PCIE_SLOT# 32,38,59
B12
KEY
A12
* ECX4
470uF * CX38
0.1uF * CX39
0.1uF
B13 RSVD1 GND67 A13 16V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
GND3 REFCLK+ C_PCIEX4_1 27
CX47 0.1uF 16V, X7R, +/-10% X_1X4_TXP0_C B14 A14 Dummy Dummy
22 X_1X4_TXP0 C_PCIEX4#_1 27
**
CX49 0.1uF 16V, X7R, +/-10% X_1X4_TXN0_C B15 HSOP0 REFCLK- A15
22 X_1X4_TXN0 HSON0 GND66
B16 A16 X_1X4_RXP0 22
B17 GND4 HSIP0 A17
PRSNT2_B17# HSIN0 X_1X4_RXN0 22
B18 A18
GND5 GND65
CX40 0.1uF 16V, X7R, +/-10% X_1X4_TXP1_C B19 A19

22 X_1X4_TXP1
** ** **
CX41 0.1uF 16V, X7R, +/-10% X_1X4_TXN1_C B20 HSOP1 RSVD7 A20
B21 A21 X_1X4_RXP1 22 +3V
B22 GND6 HSIP1 A22
GND7 HSIN1 X_1X4_RXN1 22
C CX42 0.1uF 16V, X7R, +/-10% X_1X4_TXP2_C B23 A23 Dummy ECX5 for Cost C
22 X_1X4_TXP2 HSOP2 GND63
CX43 0.1uF 16V, X7R, +/-10% X_1X4_TXN2_C B24 A24 down-11/23/09
B25
B26 GND8 HSIP2
A25
A26
X_1X4_RXP2 22
X_1X4_RXN2 22
* ECX5
470uF * CX46
0.1uF * CX48
0.1uF
CX44 0.1uF 16V, X7R, +/-10% X_1X4_TXP3_C B27 GND9 HSIN2 A27 6.3V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10%
22 X_1X4_TXP3 HSOP3 GND61
CX45 0.1uF 16V, X7R, +/-10% X_1X4_TXN3_C B28 A28 Dummy
B29 A29 X_1X4_RXP3 22
B30 GND10 HSIP3 A30
RSVD2 HSIN3 X_1X4_RXN3 22
B31 A31
B32 PRSNT2_B31# GND59 A32
GND11 RSVD6
B33 A33
B34 HSOP4 RSVD5 A34
B35 HSON4 GND58 A35 +3V_PCIAUX
B36 GND12 HSIP4 A36
B37 GND13 HSIN4 A37
B38 HSOP5 GND57 A38
B39 HSON5 GND56 A39
B40 GND14
GND15
HSIP5
HSIN5
A40 * CX50
0.1uF
B41 A41 16V, X7R, +/-10%
B42 HSOP6 GND55 A42
B43 HSON6 GND54 A43
B44 GND16 HSIP6 A44
B45 GND17 HSIN6 A45
B46 HSOP7 GND53 A46
B47 HSON7 GND52 A47
B48 GND18 HSIP7 A48
GND19 GND51
B B
B50 A50
B51 HSOP8 RSVD4 A51
B52 HSON8 GND50 A52
B53 GND20 HSIP8 A53
B54 GND21 HSIN8 A54
B55 HSOP9 GND49 A55
B56 HSON9 GND48 A56
B57 GND22 HSIP9 A57
B58 GND23 HSIN9 A58
B59 HSOP10 GND47 A59
B60 HSON10 GND46 A60
B61 GND24 HSIP10 A61
B62 GND25 HSIN10 A62
SLOT4_LATCH B71 HSOP13 GND41 A71
G G B75 HSOP14 GND39 A75
HSON14 GND38
1
B76 A76
Retention Module B77 GND32 HSIP14 A77
A A
1

RSVD3 GND35 Title
Slot-PCIE-16X
Slot4: PCIe 4x
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
CV41 0.1uF 16V, X7R, +/-10% V_DPB_TX0_DP

26 V_DDSP_B_DP_0_DP
**
CV35 0.1uF 16V, X7R, +/-10% V_DPB_TX0_DN DP_PORT1
26 V_DDSP_B_DP_0_DN Dummy for Cost down-11/23/09
23 22
UV9 HOLE3 HOLE2
10 1 V_DPB_TX0_DP 1
9 O1 IN1 2 2 ML_Lane0_P
8 O2 IN2 3 V_DPB_TX0_DN 3 GND1
CV40 0.1uF 16V, X7R, +/-10% V_DPB_TX1_DP 7 GND_2 GND_1 4 V_DPB_TX1_DP 4 ML_Lane0_N
26 V_DDSP_B_DP_1_DP
* ** *
6 O3 IN3 5 5 ML_Lane1_P
CV43 0.1uF 16V, X7R, +/-10% V_DPB_TX1_DN O4 IN4 V_DPB_TX1_DN 6 GND2
26 V_DDSP_B_DP_1_DN ML_Lane1_N
CV48 0.1uF 16V, X7R, +/-10% V_DPB_TX2_DP RCLAMP0524P.TCT Dummy V_DPB_TX2_DP 7
26 V_DDSP_B_DP_2_DP ML_Lane2_P
10 1 8
CV34 0.1uF 16V, X7R, +/-10% V_DPB_TX2_DN 9 O1 IN1 2 V_DPB_TX2_DN 9 GND3
D 26 V_DDSP_B_DP_2_DN D
8 O2 IN2 3 V_DPB_TX3_DP 10 ML_Lane2_N
7 GND_2 GND_1 4 11 ML_Lane3_P
6 O3 IN3 5 V_DPB_TX3_DN 12 GND4
O4 IN4 DPB_P13 13 ML_Lane3_N
RCLAMP0524P.TCT Dummy 14 GND5
CV47 0.1uF 16V, X7R, +/-10% V_DPB_TX3_DP UV10 V_DPB_AUX_DP 15 GND6
26 V_DDSP_B_DP_3_DP
**
16 AUX_CH_P
CV27 0.1uF 16V, X7R, +/-10% V_DPB_TX3_DN V_DPB_AUX_DN 17 GND7
26 V_DDSP_B_DP_3_DN AUX_CH_N
V_DPB_HPD_SINK 18
19 H_P_DETECT
20 RETURN
*RV52
1M *RV55 V_DPB_PWR
DP_PWR
UV7 100K 24 21
V_DPB_AUX_DN 6 1 V_DPB_AUX_DN HOLE4 HOLE1
O2 IN1 CONN - Display port
V_DPB_AUX_DP 5 2 V_DPB_AUX_DP
O1 IN2
Close to Connector
4 3
GND_2 GND_1
RCLAMP0522P.TCT
Dummy
UV8
DPB_P13 6 1 DPB_P13
O2 IN1
V_DPB_HPD_SINK 5 2 V_DPB_HPD_SINK
O1 IN2
4 3
C GND_2 GND_1 C
RCLAMP0522P.TCT
Dummy
V_DDPB_CTRL_CLK V_DDPB_CTRL_DATA V_DDSP_B_AUX_DP_C V_DDSP_B_AUX_DN_C
3
Dummy for Cost down-11/23/09
QV1 QV3
DPB_P13_POS 2 5 DPB_P13_POS DPB_P13_INV 2 5 DPB_P13_INV

2N7002DW 2N7002DW
CV42 0.1uF 16V, X7R, +/-10% V_DDSP_B_AUX_DN_C
26 V_DDSP_B_AUX_DN
4
**
CV39 0.1uF 16V, X7R, +/-10% V_DDSP_B_AUX_DP_C

26 V_DDSP_B_AUX_DP
Close to Connector
* RV11 *RV47 * RV59 *RV54
1M 1M 1M 1M
4
+/-5% +/-5% +/-5% +/-5%
2 52N7002DW 2 52N7002DW
+3V +3V
+3V
QV5 QV7
FV2 V_DPB_PWR
* * *
3
RV45 RV57
FUSE_1.1A
* CV44
1uF
* CV26
10uF * CV36
470pF * CV38
22uF
2.2K
+/-5%
2.2K
+/-5% V_DPB_AUX_DP V_DPB_AUX_DN V_DPB_AUX_DP V_DPB_AUX_DN
16V,X5R,+/-20% Dummy 50V, X7R, +/-10% 6.3V,X5R,+/-20%
10V,X5R,+/-20%
+12V
+12V
B
26 V_DDPB_CTRL_CLK
V_DDPB_CTRL_CLK RV58 * * RV40 B
4.7K 8.2K
V_DDPB_CTRL_DATA +/-5% +/-5%
26 V_DDPB_CTRL_DATA
DPB_P13_POS
+5V
DPB_P13_INV
* RV41
6
1K
Dummy QV10
Display Port Hotplug Detect 2N7002DW
*
DPB_P13 RV46 8.2K 5 2
+5V +/-5%
1
V_DPB_HPD_SINK * RV53 * CV37
RV50 1M 0.1uF
* 1K +3V +3V_DUAL +3V +/-5% 16V, X7R, +/-10%
Dummy
+5V
*RV56 * RV48 * RV51

D
100KOhm 100KOhm 100KOhm

V_DPB_HPD_SINK QV21 +/-1% +/-1% +/-1%
A Dummy Dummy A
G
FDV301N V_DPB_AUX_DN
S
V_DPB_AUX_DP
*RV43 Title
100K
* RV42
* RV44 DVI-D+VGA Conn
100KOhm 100KOhm
V_DDSP_B_HPD 23,26 +/-1% DWG NO Rev
+/-1%
Dummy A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
UV1
CV1 0.1uF 16V, X7R, +/-10% V_DPC_TX0_DP V_DPC_TX0_DP 10 1 V_DPC_TX0_DP
26 V_DDSP_C_DP_0_DP
** ** ** **
V_DPC_TX0_DN 9 O1 IN1 2 V_DPC_TX0_DN
CV2 0.1uF 16V, X7R, +/-10% V_DPC_TX0_DN 8 O2 IN2 3 DP_PORT2
26 V_DDSP_C_DP_0_DN GND_2 GND_1
V_DPC_TX1_DP 7 4 V_DPC_TX1_DP 23 22
V_DPC_TX1_DN 6 O3 IN3 5 V_DPC_TX1_DN HOLE3 HOLE2
CV3 0.1uF 16V, X7R, +/-10% V_DPC_TX1_DP O4 IN4 V_DPC_TX0_DP 1
26 V_DDSP_C_DP_1_DP ML_Lane0_P
RCLAMP0524P.TCT Dummy 2
CV4 0.1uF 16V, X7R, +/-10% V_DPC_TX1_DN V_DPC_TX0_DN 3 GND1
26 V_DDSP_C_DP_1_DN ML_Lane0_N
V_DPC_TX1_DP 4
V_DPC_TX2_DP 10 1 V_DPC_TX2_DP 5 ML_Lane1_P
CV5 0.1uF 16V, X7R, +/-10% V_DPC_TX2_DP V_DPC_TX2_DN 9 O1 IN1 2 V_DPC_TX2_DN V_DPC_TX1_DN 6 GND2
26 V_DDSP_C_DP_2_DP O2 IN2 ML_Lane1_N
D 8 3 V_DPC_TX2_DP 7 D
CV6 0.1uF 16V, X7R, +/-10% V_DPC_TX2_DN V_DPC_TX3_DP 7 GND_2 GND_1 4 V_DPC_TX3_DP 8 ML_Lane2_P
26 V_DDSP_C_DP_2_DN O3 IN3 GND3
V_DPC_TX3_DN 6 5 V_DPC_TX3_DN V_DPC_TX2_DN 9
O4 IN4 V_DPC_TX3_DP 10 ML_Lane2_N
CV7 0.1uF 16V, X7R, +/-10% V_DPC_TX3_DP RCLAMP0524P.TCT Dummy 11 ML_Lane3_P
26 V_DDSP_C_DP_3_DP GND4
UV2 V_DPC_TX3_DN 12
CV8 0.1uF 16V, X7R, +/-10% V_DPC_TX3_DN DP_P13 13 ML_Lane3_N
26 V_DDSP_C_DP_3_DN GND5
14
V_DPC_AUX_DP 15 GND6
16 AUX_CH_P
V_DPC_AUX_DN 17 GND7
UV3 V_DPC_HPD_SINK 18 AUX_CH_N
V_DPC_AUX_DN 6 1 V_DPC_AUX_DN 19 H_P_DETECT
O2 IN1 20 RETURN
V_DPC_AUX_DP 5
O1 IN2
2 V_DPC_AUX_DP *RV1
1M *RV2 V_DPC_PWR
DP_PWR
100K 24 21
4 3 HOLE4 HOLE1
GND_2 GND_1 CONN - Display port
RCLAMP0522P.TCT
Dummy Close to Connector
UV4
DP_P13 6 1 DP_P13
O2 IN1
V_DPC_HPD_SINK 5 2 V_DPC_HPD_SINK
O1 IN2
4 3
GND_2 GND_1
RCLAMP0522P.TCT
C Dummy C
V_DDPC_CTRL_CLK V_DDPC_CTRL_DATA V_DDSP_C_AUX_DP_C V_DDSP_C_AUX_DN_C
3
QV2 QV4
DP_P13_POS 2 5 DP_P13_POS DP_P13_INV 2 5 DP_P13_INV

2N7002DW 2N7002DW
CV9 0.1uF 16V, X7R, +/-10% V_DDSP_C_AUX_DN_C
26 V_DDSP_C_AUX_DN
4
**
CV10 0.1uF 16V, X7R, +/-10% V_DDSP_C_AUX_DP_C

26 V_DDSP_C_AUX_DP
Close to Connector
* RV3 *RV4 * RV5 *RV6
1M 1M 1M 1M
4
+/-5% +/-5% +/-5% +/-5%
2 52N7002DW 2 52N7002DW
+3V +3V
+3V
QV6 QV8
FV1 FUSE_1.1A V_DPC_PWR
* * *
3
B RV7 RV8 B
* CV11
1uF
* CV12
10uF
CV13
470pF * * CV14
22uF
2.2K
+/-5%
2.2K
+/-5% V_DPC_AUX_DP V_DPC_AUX_DN V_DPC_AUX_DP V_DPC_AUX_DN
16V,X5R,+/-20% Dummy 50V, X7R, +/-10% 6.3V,X5R,+/-20%
10V,X5R,+/-20%
+12V +12V
26 V_DDPC_CTRL_CLK
V_DDPC_CTRL_CLK * *
RV9
4.7K
RV10
8.2K
V_DDPC_CTRL_DATA +/-5% +/-5%
26 V_DDPC_CTRL_DATA DP_P13_POS
+5V
Display Port Hotplug Detect
+5V
V_DPC_HPD_SINK * RV12
6
RV15 1K
* 1K +3V +3V_DUAL +3V Dummy QV9
Dummy 2N7002DW
*
DP_P13 RV13 8.2K 5 2 DP_P13_INV
+5V +/-5%
*RV16 * RV17 * RV18
1
* *
D
100KOhm 100KOhm 100KOhm RV14 CV15

V_DPC_HPD_SINK QV11 +/-1% +/-1% +/-1% 1M 0.1uF
A
+/-5% 16V, X7R, +/-10% A
G Dummy Dummy
FDV301N V_DPC_AUX_DN
S
V_DPC_AUX_DP
*RV19 Title
100K
* RV20
* RV21 Display Port
100KOhm 100KOhm
V_DDSP_C_HPD 21,26 +/-1% DWG NO Rev
+/-1%
Dummy A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
VGA Connector +3V
* CV16
0.1uF
+5V Change to short pad and remove VC19, 16V, X7R, +/-10%
+3V +3V
CV22,CV25 for cost down-11/23/09
D D
2
DV1 LV1 RV22
1N4148W V_RED 1 2 47ohm 100MHz Dummy1 2 3 QV12
26 V_RED
BAV99
*RV23
C
+5V_DDC
2.2K
1
+/-5%
*RV24 *RV25
150
* CV17
* CV18
* CV19
2.2K +/ -1% 3.3pF 3.3pF 10pF
G
+/-5% 50V, NPO, +/-0.25pF 50V, NPO, +/-0.25pF 50V, NPO, +/-5%
Dummy
S D V_DDCA_CLK_5V
26 V_DDCA_CLK
2
QV13
2N7002 LV2 RV26
V_GREEN 1 2 47ohm 100MHz Dummy1 2 3 QV14
26 V_GREEN
+3V +3V BAV99
1
*RV27
150 * CV20
3.3pF * CV21
3.3pF * CV22
10pF
+5V_DDC +/ -1% 50V, NPO, +/-0.25pF 50V, NPO, +/-0.25pF 50V, NPO, +/-5%
*RV28 Dummy
2.2K
+/-5%
*RV29
2
C 2.2K LV3 RV30 C
G
+/-5% V_BLUE 1 2 47ohm 100MHz Dummy1 2 3 QV15

26 V_BLUE
BAV99
S D V_DDCA_DATA_5V
26 V_DDCA_DATA
1
QV16
2N7002
*RV31
150 * CV23
3.3pF * CV24
3.3pF * CV25
10pF
+/ -1% 50V, NPO, +/-0.25pF 50V, NPO, +/-0.25pF 50V, NPO, +/-5%
Dummy
+5VSB +5V
+5V
FV4 VGAPWR_F_20
*
2
Dummy for Cost
down-11/23/09
3 QV17 3 QV20 3 QV18 3 QV19 * CV45FUSE_1.1A
0.1uF * CV32
0.1uF
BAV99 BAV99 BAV99 BAV99 16V, X7R, +/-10% 16V, X7R, +/-10%
1
+3V VGA_SERIALA
VGA
+5V V_DDCA_CLK_5V RV33 100 +/-1% B15 SCL GND B5
B10 GND
**
B14 VSYNC ID0 B4
B *RV36
4.7K
V_VSYNC_5V RV32 0
B9 NC
V_GPI_VGA_CBL_DET# 21 B
B13 HSYNC B B3
+/-5%
* CV29
0.1uF
V_HSYNC_5V RV34 0
B8 GND
V_BLUE_R
5
UV5 16V, X7R, +/-10% V_DDCA_DATA_5V RV35 100 +/-1% B12 SDA G B2 V_GREEN_R
1 B7 GND
4 V_VSYNC_5V B11 ID1 R B1 V_RED_R * CV28
100pF
2 B6 GND 50V, NPO, +/-5%
26 V_VSYNC_3V
74AHCT1G08GW CONN - Dual port
*RV37
3
1
2
100
+/-5% CV31 CV46
Dummy
* CV30
100pF * 12pF
*
+/-5%
12pF
+/-5% * CV33
100pF
50V, NPO, +/-5%
50V, NPO, +/-5%

+3V
*RV38
4.7K +5V
+/-5%
5
UV6
1
4 V_HSYNC_5V
2
26 V_HSYNC_3V
74AHCT1G08GW
A
*RV39 A
3
100
+/-5%
Dummy
Title
VGA Conn
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
SATA x 3
SATA0
CT1 10nF 25V, X7R, +/-10% T_SATA_TXP0_C 2
23 T_SATA_TXP0
** **
TX+
D CT2 10nF 25V, X7R, +/-10% T_SATA_TXN0_C 3 D
23 T_SATA_TXN0 TX-
8
CT3 10nF 25V, X7R, +/-10% T_SATA_RXN0_C 5 NC#8
23 T_SATA_RXN0 RX-
CT4 10nF 25V, X7R, +/-10% T_SATA_RXP0_C 6
23 T_SATA_RXP0 RX+ 9
NC#9
1
4 GND
7 GND#4
GND#7
CONN-SATA
SATA1
23 T_SATA_TXP1
** **
TX+
CT6 10nF 25V, X7R, +/-10% T_SATA_TXN1_C 3
23 T_SATA_TXN1 TX-
8
23 T_SATA_RXN1 RX-
NC#9
C 1 C
4 GND
7 GND#4
GND#7
CONN-SATA
Just SATA port 0/1 support Gen3 ; PDG0.7

SATA2
23 T_SATA_TXP2
** **
TX+
23 T_SATA_TXN2 TX-
8
23 T_SATA_RXN2 RX-
NC#9
1
4 GND
7 GND#4
GND#7
CONN-SATA
B B
A A
Title
SATA Conn
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
TBD
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+5V_DUAL_USBKB USBPWR3_F_50
FU3
*
1 2 RU27 10K
* +/-1% 1
U_USB_OC_R_#1 22
Fuse 2A * ECU3
470uF * CU9
0.1uF RU44
USBPWR5_F_50
6.3V, +/-20% 16V, X7R, +/-10% 15K

+/-1%
2
USB
+5V_DUAL_USBKB USBPWR4_F_50 D1
U_USB5N_R D2 VBUS1
D D
U_USB5P_R D3 D-1
FU5
UP
*
1 2 RU30 10K D4 D+1
* +/-1% 1
U_USB_OC_R_#2 22 GND1
Fuse 2A * ECU5
470uF * CU12
0.1uF RU63
6.3V, +/-20% 16V, X7R, +/-10% 15K C1
+/-1% U_USB4N_R C2 VBUS2
2 U_USB4P_R C3 D-2
C4 D+2
GND2 Second
USBPWR3_F_50
B1
+5V_DUAL_USBKB USBPWR5_F_50 U_USB2N_R B2 VBUS3
LU3 U_USB2P_R B3 D-3
1 4 U_USB2N_R B4 D+3
22 U_USB2N FU9
*
1 2 RU36 10K USB3_RX3_ESD_DN B5 GND3
22 U_USB2P
2 3 U_USB2P_R * +/-1% 1
U_USB_OC_R_#3 22 USB3_RX3_ESD_DP B6 STDA_SSRX-1
STDA_SSRX+1 Third
Common Choke 90 Ohm
Fuse 2A * ECU9
470uF * CU13
0.1uF RU35 USB3_TX3_ESD_DN
B7
B8 GND_DRAIN1
6.3V, +/-20% 16V, X7R, +/-10% 15K USB3_TX3_ESD_DP B9 STDA_SSTX-1
+/-1% STDA_SSTX+1
**
RU8 0 2 USBPWR4_F_50
Dummy
RU7 0 A1
Dummy U_USB3N_R A2 VBUS4
U_USB3P_R A3 D-4
A4 D+4
C LU4 USB3_RX4_ESD_DN A5 GND4 1 C
22 U_USB3N
1 4 U_USB3N_R USB3_RX4_ESD_DP A6
A7
STDA_SSRX-2
STDA_SSRX+2 Down GND5
GND6
2
3
2 3 U_USB3P_R USB3_TX4_ESD_DN A8 GND_DRAIN2 GND7 4
22 U_USB3P STDA_SSTX-2 GND8
USB3_TX4_ESD_DP A9 5
Common Choke 90 Ohm STDA_SSTX+2 GND9 6
GND10
CONN-USBX4
**
RU12 0
Dummy
RU11 0
Dummy
LU24
3 2 U_USB4P_R
22 U_USB4P
4 1 U_USB4N_R
22 U_USB4N
Common Choke 90 Ohm

**
RU48 0 Dummy
RU50 0 Dummy UU9

USB3_RX3_ESD_DP9 1 USB3_RX3_ESD_DP
I/O
B LU14 USB3_RX3_ESD_DN8 2 USB3_RX3_ESD_DN B
2 3 U_USB5N_R Common Choke 67 Ohm I/O
22 U_USB5N **
GND
0.1uF CO77 USB3_TX3_PCH_DP_C 3 4 USB3_TX3_ESD_DP 3
28 USB3_TX3_PCH_DP
1 4 U_USB5P_R
22 U_USB5P
0.1uF CO75 USB3_TX3_PCH_DN_C 2 1 USB3_TX3_ESD_DN USB3_RX4_ESD_DP7 4 USB3_RX4_ESD_DP
28 USB3_TX3_PCH_DN I/O
Common Choke 90 Ohm
LU5 USB3_RX4_ESD_DN6 5 USB3_RX4_ESD_DN
*
I/O
**
RU13 0 0 RU84 ESD3V3U4ULC

Dummy
RU28 0 Dummy
Dummy Common Choke 67 Ohm UU7
3 4 USB3_RX3_ESD_DP USB3_TX4_ESD_DN 9 1 USB3_TX4_ESD_DN
28 USB3_RX3_PCH_DP I/O
2 1 USB3_RX3_ESD_DN USB3_TX4_ESD_DP 8 2 USB3_TX4_ESD_DP
28 USB3_RX3_PCH_DN I/O
LU16
GND
USBPWR3_F_50 3
*
0 RU83 USB3_TX3_ESD_DN 7 4 USB3_TX3_ESD_DN
UU8 I/O
U_USB2N_R 1 6 U_USB2P_R Dummy USB3_TX3_ESD_DP 6 5 USB3_TX3_ESD_DP
Common Choke 67 Ohm I/O
**
2 5 0.1uF CO76 USB3_TX4_PCH_DP_C 3 4 USB3_TX4_ESD_DP ESD3V3U4ULC

28 USB3_TX4_PCH_DP
U_USB3N_R 3 4 U_USB3P_R 0.1uF CO74 USB3_TX4_PCH_DN_C 2 1 USB3_TX4_ESD_DN
28 USB3_TX4_PCH_DN
IP4220CZ6 LU6
U_USB4N_R 1
UU3
USBPWR5_F_50
6 U_USB4P_R 3
0
*
Dummy
RU86
Common Choke 67 Ohm

4 USB3_RX4_ESD_DP Title
Intel A
28 USB3_RX4_PCH_DP
2 5
28 USB3_RX4_PCH_DN
2 1 USB3_RX4_ESD_DN Rear USB
U_USB5N_R 3 4 U_USB5P_R LU15 DWG NO Rev
*
A00
IP4220CZ6 0 RU85 Lanikai _MT/DT
Dummy Date: Wednesday, June 13, 2012 Sheet 45 of 71
5 4 3 2 1
5 4 3 2 1
+12V
TPM, TCM (TCM is just reserved

because MRD has removed TCM requirement)
+3V
(Default) *RF4
ST Micro POP S CF4 8.2K
+/-1%
ZTE POP Z CF2,CF4,CF7,RF10,RF19,RF20,RF21 * CF1
0.1uF * CF2
0.1uF * CF3
0.1uF * CF4
10uF
@S,Z,J
G
Jetway POP J CF2,CF8,RF10,RF16,RF21 16V, X7R, +/-10% 16V, X7R, +/-10% 6.3V, X5R, +/-20%
@Z,J @S,Z
close to Pin 10
D S S_PLTRST#_R
close to Pin 19
16V, X7R, +/-10% 9,24,32,34,52,53 S_PLTRST#
D D
QF1
2N7002
@S,Z,J *RF5
8.2K
*
RF6 33 +/-1%
close to Pin 24 Dummy @S,Z,J
+3V +3V
20100510: UF1 TPM IC change to ST33ZP24

20100519: UF1 TPM IC change to SB19NP18ER28PVMT
20101001: UF1 usage TCM_SSX44-B-D-T +12V
10
24
C UF1 C
* CF5
* CF6
VPS1
VPS2
21 0.1uF 0.1uF
27 C_TPM LCLK 15 F_TPM_CLKRUN# Dummy Dummy
22 GPIO5 9 F_TPM_PIN9 16V, X7R, +/-10%
24,32,53 F_FRAME# LFRAME# GPIO4 7 F_TPM_PIN7 16V, X7R, +/-10%
PP TPF1
S_PLTRST#_R 16 6 F_TPM_PIN6 +3V
LRESET# GPIO3 TPF2
3 F_TPM_PIN3
VNC TPF3
17 2 F_TPM_PIN2
24,32,53 F_LAD3 LAD3 GPIO2 TPF4
20 1 F_TPM_PIN1
24,32,53 F_LAD2 LAD2 GPIO1 TPF5
+3V 23 5 F_TPM_PIN5
24,32,53 F_LAD1 LAD1 NC1
26 8 F_TPM_PIN8
24,32,53 F_LAD0 LAD0 NC2 TPF6
12 F_TPM_PIN12 20101001: add UF2 usage TPM_SB19NP18ER28PVMK
NC3 TPF7
13 RF16 0
*
NC4 C_14M_TPM 27
*
RF27 4.7K F_PWRDWN# 28 14 @J +/-5% RF17
*
@S,Z,J +/-5% LPCPD# NC5 19 0 UF2
*
27 NC6 25 RF10 0
23,32 F_SERIRQ# SERIRQ NC7 @Z,J +/-5%
* CF7
1uF
Dummy
GPIO5
15
GND3
GND2
GND1
6.3V,X5R,+/-10% 1
@Z GPIO1
SSX44-B-D-T
18
11
@Z
B B
ST33ZP24AR28PVSH
@S,J
A A
F_TPM_PIN5 F_TPM_PIN9 F_TPM_PIN3 F_TPM_CLKRUN#
* CF8 *RF19 *RF20

1K *RF21 Title
0.1uF 1K @Z 4.7K
16V, X7R, +/-10% @Z +/-5% TPM & TCM
@J @Z,J
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
For B00 test only
*
RO103 0
Header_1X2 O_TR_CPU+ 32
Dummy
2
1 * CO25
330pF
Dummy
*
THRM_3 RO104 0
O_TR_CPU- 32
Dummy 50V, NPO, +/-5% Dummy
*
RO105 0
Header_1X2 O_TR_CPU+ 32
Dummy
2
1 * CO23
330pF
C Dummy
C
*
THRM_2 RO110 0
O_TR_CPU- 32
Dummy 50V, NPO, +/-5% Dummy
Dummy THRM2,CO23; ME suggestion-12/04/09
O_TR_MB+
Header_1X2 O_TR_MB+ 32
2
1 * CO24
330pF
50V, NPO, +/-5%
THRM_1 O_TR_MB-
O_TR_MB- 32
THERMAL SENSOR
B B
A A
Title
Thermal Sensor Conn

DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
CPU Fan +3V
+3V
*RO72 *RO73 *RO74 *RO75

4.7K 4.7K 1K 4.7K
+/-5% +/-5% +/-5% +/-5%
*
RO76 0
D Dummy +/-5% D
QO11
*
RO77 220 6 1
32 O_SEN_CPUFAN
*
2 RO78 4.7K
5 +/-5% +12V
32 O_CPUFAN_PWM
4 3 * CO29
0.1uF
16V, X7R, +/-10%
FAN_CPU
MMDT5551 +12V
1
2
3
*
O_CPUFAN_PWM_R RO80 100 Ohm 4
+/-1% 5
1
Header-1X5
* ECO1
120uF
+/-20%
2
CO31
4.7uF ** CO32
0.1uF
16V, X7R, +/-10%

25V,Y5V,+80/-20%
Dummy
Dummy
C C
+3V
+3V
+12V
SYS Fan *RO86
*RO83 *RO84 *RO85 4.7K
4.7K 4.7K 1K +/-5%
1
+/-5% +/-5% +/-5% * ECO2
*
RO87 0 120uF
Dummy +/-5% +/-20%
2
QO13
*
RO88 220 6 1
32 O_SEN_CHAFAN
*
2 RO89 4.7K
5 +/-5% +12V
32 O_CHAFAN_PWM
4 3 * CO34
0.1uF
16V, X7R, +/-10%
FAN_SYS
MMDT5551
B 1 B
2
3
*
O_CHAFAN_PWM_R RO90 100 4
+/-5% 5
Header-1X5
CO35
4.7uF *
25V,Y5V,+80/-20%
Dummy
A A
Title
FAN
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
KB/MS
D D
+5V_DUAL_USBKB
*
C C
FUSE_1.1A * CO36
0.1uF
FO1 16V, X7R, +/-10%
+5V_DUAL_USBKB
Close to Pin 10 (EMI) Close to Pin 4 (EMI)

RNO3 KYBD_MOUSE
* CO37
* CO38
8
6
4
2
2K 0.1uF 0.1uF
+/-5% 13 16V, X7R, +/-10% 16V, X7R, +/-10%
7
5
3
1
16
*
****
FBO1 FB 600 Ohm O_MS_DATA_L 12 6

32 O_MS_DATA
10 4
FBO2 FB 600 Ohm O_MS_CLK_L 8 2
32 O_MS_CLK
O_MS_DATA_L 7 14
FBO3 FB 600 Ohm O_KB_CLK_L 9 1 O_KB_DATA_L
32 O_KB_CLK
O_MS_CLK_L 11 3
FBO4 FB 600 Ohm O_KB_DATA_L 5 O_KB_CLK_L
32 O_KB_DATA
17
CNO3 15
180pF UP DOWN
B * 50V, NPO, +/-10% CONN - KB_MS B
Dummy
+5V_DUAL_USBKB
UO3 Dummy
O_MS_DATA_L 1 6 O_MS_CLK_L
2 5
O_KB_DATA_L 3 4 O_KB_CLK_L
IP4220CZ6
A A
Title
PS2 Conn
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
Serial Port 1
D D
VGA_SERIALB
O_DCD1# T1
O_DSR1# T6
O_RXD1 T2
UO2 O_RTS1# T7
+5V 20 1 +12V O_TXD1 T3
VCC +12V O_CTS1# T8
16 5 O_RTS1# O_DTR1# T4
32 O_RTS1#_R DA1 DY1
15 6 O_DTR1# O_RI1# T9
32,33 O_DTR1#_R DA2 DY2
C 13 8 O_TXD1 T5 C
32 O_TXD1_R DA3 DY3
19 2 O_RI1#
32 O_RI1#_R RY1 RA1
18 3 O_CTS1# 3
32 O_CTS1#_R RY2 RA2
17 4 O_DSR1#
32 O_DSR1#_R RY3 RA3
14 7 O_RXD1 CONN - Dual port
32 O_RXD1_R RY4 RA4
12 9 O_DCD1#
32 O_DCD1#_R RY5 RA5
11 10 -12V
GND -12V
GD75232
20100326: UO2 will be changed

TI/GD75232DBR to main source in X00 build.
O_DCD1#
O_DSR1#
O_RXD1
O_RTS1#
O_TXD1
O_CTS1#
O_DTR1#
+12V -12V +5V O_RI1#
* *
* CO41
0.1uF * CO42
0.1uF * CO43
0.1uF
CNO4
180pF
CNO5
180pF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 50V, NPO, +/-10% 50V, NPO, +/-10%
Dummy Dummy
B B
placed near connector
A A
Title
COM1
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_S5
SPI
* CF10
0.1uF
16V, X7R, +/-10%
SPI_1
1 8
24 F_SPI_CS1#_ISOLATE CS# VCC
D F_SPI_CLK_PRI_SEC_FLSH_R1 6 7 F_SPI_HOLD1# D
SCK HOLD#
20091225: Change net F_SPI_MOSI_PRI_SEC_FLSH_R1 5
SI WP#
3 F_SPI_WP1#
F_SPI_MISO_R1 2 4
name for Dual SPI SO GND
SPI SOCKET
@PR
+3V_S5
CLOSE TO SPI
SPI1
20110530: Change to 4M If socket not use ,need change to SMD Tpye

* CF11
1uF * CF12
0.1uF
6.3V,X5R,+/-10% 16V, X7R, +/-10%
+3V_S5
MX25L3206EM2I-12G
*
RNF1
7
5
3
1
1K
+/-5%
** ** **
8
6
4
2
24 F_SPI_MISO RF22 33 F_SPI_MISO_R
RF23 33 F_SPI_MISO_R1
F_SPI_HOLD#
F_SPI_WP#
C
24 F_SPI_CLK_PRI_SEC_FLSH RF28 33 F_SPI_CLK_PRI_SEC_FLSH_R F_SPI_HOLD1# C
F_SPI_WP1#
RF29 33 F_SPI_CLK_PRI_SEC_FLSH_R1
24 F_SPI_MOSI_PRI_SEC_FLSH RF30 33 F_SPI_MOSI_PRI_SEC_FLSH_R
RF31 33 F_SPI_MOSI_PRI_SEC_FLSH_R1
SPI_2 20091225: Change net
20091225: RF23 change to 33ohm for Dual SPI F_SPI_HOLD# 1
HOLD# C
16 F_SPI_CLK_PRI_SEC_FLSH_R
name for Dual SPI
20091225: Add RF28, RF29,RF30,RF31 for Dual SPI +3V_S5 2
VCC D
15 F_SPI_MOSI_PRI_SEC_FLSH_R
3 14
4 DU1 DU8 13
5 DU2 DU7 12
6 DU3 DU6 11
7 DU4 DU5 10
24 F_SPI_CS0#_ISOLATE S# VSS
F_SPI_MISO_R 8 9 F_SPI_WP#
Q W#
ACA-SPI-006-K01
@PR
SPI2
20100309: SPI2 Package Type
change to DIP from SMD, , when SPI_3
usage SPI_2 socket F_SPI_CS0#_ISOLATE 1
CS# VCC
8 +3V_S5
20091225: Change net F_SPI_CLK_PRI_SEC_FLSH_R 6
SCK HOLD#
7 F_SPI_HOLD#
20100930: SPI2 change to name for Dual SPI
F_SPI_MOSI_PRI_SEC_FLSH_R 5
SI WP#
3 F_SPI_WP#
F_SPI_MISO_R 2 4
B MXIC_MX25L6445EMI-10G SO GND B
MX25L6445EMI-10G SPI SOCKET

Dummy
A A
Title
SPI
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
For debugging
XDP Connector - CPU
+1P05V_VCCIO XDP_CPU
+1P05V_VCCIO
Remove RH46 and
43 55
44 VCC_OBS_AB TCK1 57 option connection to
VCC_OBS_CD TCK0 H_TCK 9
TDO
52
54
H_TDO 9 H_TAPPWRGOOD;
9 H_PREQ#
3
OBSFN_A0
TRSTn
TDI
56
H_TRST#
H_TDI
9
9
follow CRB0.7-12/27/09 *RH47 *RH49 * RH70
5 58 1.5K 3.3K 0
9 H_PRDY# OBSFN_A1 TMS H_TMS 9
9 @PR Dummy Dummy Dummy
9 H_BPM#0
**
OBSDATA_A_0
9 H_BPM#1
11
OBSDATA_A_1 HOOK0
39 F_XDP_PWRGD RH45 249 Ohm
H_PWRGD 9,24,64 Add RH68 to F_XDP_PWRGD
D 15 41 F_XDP_PLTRST# D
9 H_BPM#2
17 OBSDATA_A_2 HOOK1 45 H_TAPPWRGOOD RH68 1K @PR H_CFG0; follow
9 H_BPM#3 OBSDATA_A_3 HOOK2 H_CFG0 9
HOOK3
47 RH67 1 2
P_VR_READY 24,33,64,67 CRB0.7-12/27/09 F_XDP_PLTRST#
21
OBSFN_B0 ITPCLK/HOOK4
40 H_ITPCLK_R Dummy Pin 47 add RH67 to
23 42 H_ITPCLK#_R @PR
P_VR_READY;
*
27 OBSFN_B1 ITPCLKB/HOOK5 46 F_RSTOUT_XDP_N RH50 1K H_TAPPWRGOOD
9 H_BPM#4 OBSDATA_B_0 RESETB/HOOK6 H_RESET#_R 9
9 H_BPM#5
29
OBSDATA_B_1 DBRB/HOOK7
48
FP_RST# 9,24,53 follow CRB 20091209: CRB0.7 empty RH47 and RH45 use
33
9 H_BPM#6
35 OBSDATA_B_2
Remove RH51 Change net name to 0.7-12/27/09
Dummy RH52,RH53; follow 249
Add ohm
RH70 to
9 H_BPM#7 OBSDATA_B_3 1 -12/29/09 H_RESET#_R -12/28/09
51 GND1 7 CRB 0.7-12/27/09 +1P05V_VCCIO; follow
** **
SDA GND2
15,16,17,18,32 S_SMBCLK_MAIN
53
4 SCL GND3
13
19
H_ITPCLK_R
H_ITPCLK#_R
RH52
RH53
0 Dummy
0 Dummy
CRB0.7-12/27/09
H_ITPCLK 9
OBSFN_C0 GND4 H_ITPCLK# 9
6 25
10 OBSFN_C1 GND5 31 RH54 0 @PR
OBSDATA_C_0 GND6 C_PCH_ITP 27
12 37 Remove RH58,RH59 RH55 0 @PR
OBSDATA_C_1 GND7 C_PCH_ITP# 27
16 49 -12/29/09
18 OBSDATA_C_2 GND8 59
OBSDATA_C_3 GND9 2
GND10 8
GND11
22
OBSFN_D_0 GND12
14 20100226:
24 20
28 OBSFN_D_1 GND13 26 Change clock
OBSDATA_D_0 GND14
30
34 OBSDATA_D_1 GND15
32
38
source form
PCH
* *
36 OBSDATA_D_2 GND16 50 RH69 3.3K
OBSDATA_D_3 GND17 O_PWRBTN#IN 24,32,53,56
@PR
60
GND18_XDP_PRESENTB F_XDP_PLTRST# RH48 1K
S_PLTRST# 9,24,32,34,46,53
C
XDP @PR Dummy C
Add RH69 to O_PWRBTN#IN and dummy RH48; follow

CRB0.7-12/27/09
XDP Connector - PCH For debugging

20091230:TP8,TP9 XDP_PCH
change to Test Point; 20091230: Remove all
20091230:Add
follow CRB 0.7 pull-up to TPS133
TP_0 10
TP_0 BPM1_0/TP_13#
17
USB OC connection;
TP_1 12 15
+1P05V_PCH; follow CRB 0.7 TPS134
TP_2 16 TP_1 BPM1_1/TP_12# 11
follow CRB 0.7
TPS135 TP_2 BPM1_2/TP_11#
TP_3 18 9
TPS136 TP_3 BPM1_3/TP_10#
TP_4 28 5
TPS137 TP_4 BPM1_4#
TP_5 30 3
TPS138 TP_5 BPM1_5#
TP_6 34
TPS139 TP_6
TP_7 36 35
TPS140 TP_7 BPM2_0#/TP_17
TP_8 4 33
TP_9 6 29
@PR 27
*
RS200 0 F_SINAI_JTAG_VREF 40 BPM2_3#/TP_14

+1P05V_PCH XDP_H_CLK_DP
42 60 +3V_S5
XDP_H_CLK_DN XDP_PRESENT# @PR
27 C_SRC1_PCH
45
47 100M_CLK_DP PROC_VTT_1
43
44
RS172 * 0
B 27 C_SRC1_PCH# 100M_CLK_DN PROC_VTT_2 B
20091230: change to 20091221: updated JTAG stuffing table
51 1
53 SDA GND1 2 0ohm pull-up to +3_DSW
15,16,17,18,32 S_SMBCLK_MAIN SCL GND2 7
GND3
20091231: Add TPS120
F_TP_XDP_PWRGD 39
PWRGOOD GND4
8 20100105: Mount RS175 and change to
RS35 pull-up to TPS121
F_TP_XDP_RST 46
RESET# GND5
13 20100709:
0ohm; CRBReserve
0.7 RS207 for 20091221: RS184 change to 20k ; Stuff-up RS177, RS178,
48 14
9,24,53 FP_RST# S_RSMRST# connect to RS185 follow JTAG Enable option.
*
DBR# GND6
+1P05_PCH; +1P05V_PCH RS35 51 Ohm 41
TESTINB GND7
19 +3V_S5
@PR 20 20100712: Removed RS207 and
F_TP_XDP_RST 20100503: RS177, RS179, RS181
CRB 0.7 52 GND8 25
24 F_PCH_JTAG_TDO
56 TDO GND9 26 S_RSMRST# RS175 0 * * * F_TP_XDP_RST pull-up change to +3V_S5, follow
24 F_PCH_JTAG_TDI TDI GND10 24,32,53,56 O_PWRBTN#IN
24 F_PCH_JTAG_TMS
F_PCH_FILTER_TCK
58
57 TMS GND11
31
32
Dummy
@PR
CRB1.0 @PR
*
***
*****
F_PCH_JTAG_RST# RS208 0 F_PCH_JTAG_RST#_R 54 TCK GND12 37 RS176 1K RS177 200Ohm +/-5% F_PCH_JTAG_TDO RS178 100 Ohm +/-1%
TRST# GND13 9,24,32,34,46,53 S_PLTRST#
Dummy 38 Dummy @PR @PR
21 GND14 49 @PR RS179 200Ohm +/-5% F_PCH_JTAG_TDI RS180 100 Ohm +/-1%
22 NC_1 GND15 50 RS207 1K @PR @PR
NC_2 GND16 24,64 S_RSMRST#
23 59 RS181 200Ohm +/-5% F_PCH_JTAG_TMS RS182 100 Ohm +/-1%
NC_3 GND17
20091221: Rename 24
NC_4
@PR CLOSE TO PCH
55 +3V_S5 F_PCH_FILTER_TCK RS183 51 Ohm+/-5%
F_PCH_JTAG_RST#_NC to NC_5 @PR
*
F_PCH_JTAG_RST#_R XDP @PR RS184 20K
+/-1%
F_PCH_JTAG_RST# RS185 10K +/-1%
*
RS186 0 F_PCH_JTAG_RST# 24
@PR
+3V
20091231: RS188 cahnge to 1k and
pullup to +3V_DSW; CRB 0.7
A A
US2 @PR
1
NC VCC
5 RS188
* * 1K +3V_S5
*
F_PCH_FILTER_TCK RS187 0 2
Dummy A F_TP_XDP_PWRGD RS189 1K Title
PWRGD_3V 24,32
3 4 RS190 140Ohm Dummy
GND
SN74LVC1G17DCKR
Y Dummy +/-1% F_PCH_JTAG_TCK_FILTER 24
*RS192 XDP
*RS191 CS69
Dummy *
Dummy 0 0.1uF 0 DWG NO Rev
16V, X7R, +/-10% Dummy A00
Dummy Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
Power Bottom Reset Bottom

+3V_DUAL
RO99
D
* 1K @PR For debugging D
20091216: Signal name +/-5%
@PR For debugging
change to O_PWRBTN#IN @PR PWR_SWH
*
RO100 0 RO101 100 SYS_PWRBT# @PR
24,32,52,56 O_PWRBTN#IN
*
@PR +/-5% RO102 100 Ohm
9,24,52 FP_RST#
+/-1% @PR
5
RST_SWH
5
1 2 @PR
20101118: Dummy RO101 3 4
CONN-Switch * CO49 1 2
470pF 3 4 CONN-Switch
6
20101118: Dummy RO102, CO49
20101118: Stuffed RO102, CO49
LPC DEBUG APS Connector

C C
+3V +5V
For debugging
20101118: Dummy RF24 @PR
LPC_DEBUG
@PR
*
**
RF24 0 1 2 RF25 0
27 C_LPC S_INIT3_3VB 23
+/-5% 3 4 @PR
9,24,32,34,46,52 S_PLTRST#
5 6 RF26 0 F_LPC_DEBUG
24,32,46 F_LAD0
7 8 @PR
24,32,46 F_LAD1
9 X
24,32,46 F_LAD2
24,32,46 F_LAD3
11 12 20101118: Dummy RF25, RF26
13 14
24,32,46 F_FRAME#
Header_2X7_K10
@PR @PR +3V_DUAL+3V_S5
CF15
22pF * CF16
10nF +3V_S5
50V, NPO, +/-5% 25V, X7R, +/-10% METS @PR
*** ***
***
RF34 0 @PR 1 2 RF32 0 @PR
S_SLP_S3# 24,32,64,66,70,71
RF33 0 @PR 3 4 RF35 0 @PR
20100909: Dummy CF15 24,32,65,71 S_SLP_S4#
RF36 0 @PR 5 6 RF37 0 @PR
S_SLP_M# 24,32,65,66
20101118: Dummy CF16 7 8
B 20101118: Stuffed CF16 24,29,31 S_RTCRST#
RF38 0 @PR 9 10
B
RF39 0 @PR 11 12
24,32,52,56 O_PWRBTN#IN
RF40 0 @PR 13 14
9,24,52 FP_RST#
Header_2X7
+3V
Dummy
* CF14 @PR
*
0.1uF F_LPC_DEBUG RS11 8.2K +/-5%

16V, X7R, +/-10% *@PR
RS12 20100512: change RS12, RS16 to 1k
1K
S_SATA1GP +/-5%
21,23 S_SATA1GP
3
QS1
+5V MMDT5551
A 20100512: change RS12, RS16 to 1k @PR A
@PR
*
Dummy RS16 1K K_GNT#1

K_GNT#1 21
* CF13
0.1uF
+/-5%
@PR
*
16V, X7R, +/-10% RS19 8.2K +/-5% F_LPC_DEBUG Title

CS1
* 1uF
+/-10%
Pilot Run Conn
@PR DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
Dummy Dummy Dummy Dummy

Dummy +5V Dummy FD1 FD2 FD3 FD4
IMPEDANCE_1 IMPEDANCE_2 FMARK FMARK FMARK FMARK
1 1 FD40 FD40 FD40 FD40
2 2
Header_1X2 Header_1X2
1
Dummy +5V Dummy
IMPEDANCE_3 IMPEDANCE_4
D 1 1 D
2 2 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
FD5 FD6 FD7 FD8 FD9 FD10 FD11 FD12
Header_1X2 Header_1X2 FMARK FMARK FMARK FMARK FMARK FMARK FMARK FMARK
FD40 FD40 FD40 FD40 FD40 FD40 FD40 FD40
Dummy
Dummy IMPEDANCE_6
1
IMPEDANCE_5 1
DIFF_5/5+ 1 2
DIFF_5/5- 2
Header_1X2
Header_1X2
MH1 MH2 MH3 MH4 MH5 MH6 MH7 MH8

Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole Mounting Hole
6
5
6
5
6
5
6
5
6
5
6
5
6
5
6
5
7 4 7 4 7 4 7 4 7 4 7 4 7 4 7 4 +1P05V_PCH +5V +1P05V_PCH +1P05V_PCH +1P05V_VCCIO +3V
8 3 8 3 8 3 8 3 8 3 8 3 8 3 8 3
9 2 9 2 9 2 9 2 9 2 9 2 9 2 9 2
1
1
C mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell mh40x80_8_dell * CP287
0.1uF * CP284
0.1uF * CP283
0.1uF * CP288
0.1uF * CP289
0.1uF * CP239
0.1uF C
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
Dummy Dummy Dummy Dummy Dummy Dummy
A_GND
+12V
20100108: Add for EMI
+5V
+3V
+1P05V_VCCIO +1P05V_VCCIO +1P05V_VCCIO +5V +3V +3V
* CP222
* CP224
* CP225
* CP228
* CP237
* CP236 * CP238
0.1uF * CP242
0.1uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 16V, X7R, +/-10% 16V, X7R, +/-10%
+3V +1P05V_PCH
+12V
A_GND +5V
+3V +5V
+3V +3V +3V +5V +1P05V_PCH +1P05V_ME
B B
* CP229
0.1uF * CP230
0.1uF * CP231
0.1uF * CP232
0.1uF
* CP233
* CP235
* CP240
* CP247
* CP251
* CP249
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
+3V +3V +3V_S5
+1P05V_PCH +1P05V_PCH +12V +1P05V_PCH +12V
+5V_DUAL_USBKB +5V_DUAL_USBKB +12V +5V_DUAL_USBKB * CP291

0.1uF * CP276
0.1uF * CP255
0.1uF * CP250
0.1uF * CP248
0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
Dummy Dummy
* CP285
0.1uF * CP268
0.1uF * CP246
0.1uF * CP244
0.1uF
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% +3V
A A
+3V_S5
Title
EMI
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
Move PWR_SW conn to

page56 20091126
C C
Serial Port 2 Header
+3V
RO93 RO94 RO95 RO96 RO97

B * * * * * B
2.2K 2.2K 2.2K 2.2K 2.2K

+/-5% +/-5% +/-5% +/-5% +/-5%
O_DCD2#_R
O_DSR2#_R
O_RXD2_R
O_CTS2#_R
O_RI2#_R
A
+12V -12V +5V A
32 O_DCD2#_R
32 O_DSR2#_R
32 O_RXD2_R
* CO44
* CO45
* CO46
*
RO33 0 +/-5% 0.1uF 0.1uF 0.1uF

32,33 O_TXD2_R Dummy 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10%
32 O_CTS2#_R Dummy Dummy Dummy Title
O_RI2#_R 32
COM2 HDR
* CO22
10pF DWG NO Rev
Dummy Dummy Serial Port2 header from X01 A00
50V, NPO, +/-5% Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
Front USB/LED Header

+5V_DUAL_USBKB
+5V_DUAL_USBKB
1
*
USBPWR7_F_50
*RU29
0 FU6
+/-5% Fuse 2A
Dummy
2
*
RU31 10K +/-1%
22 U_USB_OC_R_#5
D 1 D
Pitch 2.0mm 20110212 Change to 2x13 for Front USB x2 port.

CU14
0.1uF * RU33
15K
* ECU6
470uF * CU15
0.1uF
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10%
+3V 2
20110212 Change to 2x13 for Front USB x2 port.
RNO2 MT/DT CHASSIS

2
4
6
8
8.2KOhm
+/-5%
* 13
5
7
FP_CHAS_DET# MT/DT
O_FIO_SATA_LED# 0 MT
T_SATALED# 1 DT
OQ14_C
S_FP_CHAS_DET#
** **
RU38 0 Dummy U_USB10N_R

22 U_USB10N
RU39 0 Dummy U_USB10P_R
22 U_USB10P
C
22 U_USB11N
RU41 0 Dummy U_USB11N_R
CU16
0.1uF * * CU17
0.1uF
C
RU42 0 Dummy U_USB11P_R 16V, X7R, +/-10% 16V, X7R, +/-10%

22 U_USB11P
FRONTPANEL
1 2
37 A_MIC1_L_L 1 2 A_MIC1_R_L 37
3 4 +5V
37 A_JD_MIC1 3 4 A_JD_FRONT 37
5 6
A_FRONT_R_L 37
*
37 A_FRONT_L_L 7 5 6 8 RO71 1K
7 8 A_FP_PRES# 23 23 T_SATALED#
O_FIO_SATA_LED# 9 10
11 9 10 12 O_FIO_SATA_LED#
USBPWR7_F_50 11 12 USBPWR7_F_50
13 14
U_USB10N_R
13 14
U_USB11N_R
* CO50
3
U_USB10P_R 15 16 U_USB11P_R 0.1uF
17 15 16 18 16V, X7R, +/-10%
17 18 20
20 S_FP_CHAS_DET# 23 QO10
Header_2X10_K19 MMDT5551
4
OQ14_C
B A_FP_PRES# 23 B
* CA40
0.1uF
Dummy 16V, X7R, +/-10%
O_FIO_SATA_LED#
UU5
POWER SWITCH Header

1 6
U_USB11N_R U_USB11P_R CO53
470pF * +5VSB
2 5 +3V_DUAL Dummy
USBPWR7_F_50
50V, X7R, +/-10%

3 4
U_USB10N_R U_USB10P_R
+5VSB +5VSB * CO26
0.1uF
IP4220CZ6 16V, X7R, +/-10%
*RO70
8.2K
RO37 +/-5%
LU11 RO34 * * 499 O_FP_CBL_DET#
U_USB10P_R 1 4 499 +/-1%
U_USB10P 22 +/-1% O_GREEN#
Intel
U_USB10N_R 2 3 O_YELLOW#
U_USB10N 22 PWR_SW O_PWRBTN#IN
A A
Common Choke 90 Ohm
*
RO67 100 +/-5% 1 2

24,32,52,53 O_PWRBTN#IN 3 4
LU12
32 O_GREEN#
X
6
O_FP_CBL_DET# 32
O_YELLOW# 32
CO27
470pF * CO54
470pF * CO52
470pF *
50V, X7R, +/-10%

U_USB11N_R 2 3 Dummy Dummy
U_USB11N 22
50V, X7R, +/-10%
50V, X7R, +/-10%

Title
U_USB11P_R 1 4 Header_2X3_K5
U_USB11P 22 Front_Panel
Common Choke 90 Ohm
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
Front USB/LED Header

+3V_DUAL
RU34
10K
*
+5V_DUAL_USBKB
+/-1% USBPWR1_F_50 USBPWR2_F_50
22 U_USB_OC_R_#0 +5VSB
1
*
USBPWR1_F_50
BAT54A FU7 * CO51
0.1uF
DU2 Fuse 2A 16V, X7R, +/-10% FRONT_USB
D 1 D
2
USB3_RX2_ESD_DN 2 19
2
USB3_RX2_ESD_DP 3 18 USB3_RX1_ESD_DN
RU54
+3V 4 17 USB3_RX1_ESD_DP
*
USB3_TX2_ESD_DN 5 16
6 15
2KOhm *RU87
8.2K
USB3_TX2_ESD_DP
7 14
USB3_TX1_ESD_DN
USB3_TX1_ESD_DP
CU19
0.1uF * * RU58
3.01K +/-1%
* ECU7
470uF * CU20
0.1uF
+/-5% U_USB1N_R
U_USB1P_R
8
9
13
12 U_USB0N_R
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10% 10 11 U_USB0P_R
23 S_USB_HDR_DET#
PUB200-2017-B5-10-HF
+5V_DUAL_USBKB
2
USBPWR2_F_50
FU10
Fuse 2A
1
*
RU67
*
2KOhm
*
C
CU23
0.1uF * * RU66
3.01K +/-1%
* ECU10
470uF * CU24
0.1uF
RU56 0
C
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10%
Common Choke 67 Ohm
**
0.1uF CO78 USB3_TX2_PCH_DN_C 3 4 USB3_TX2_ESD_DN
28 USB3_TX2_PCH_DN
0.1uF CO81 USB3_TX2_PCH_DP_C 2 1 USB3_TX2_ESD_DP
28 USB3_TX2_PCH_DP
Dummy LU20
*
LU13 RU60 0
2 3 U_USB1P_R
22 U_USB1P
*
1 4 U_USB1N_R
22 U_USB1N
0 RU82
Common Choke 90 Ohm UU12
USB3_RX2_ESD_DN9 1 USB3_RX2_ESD_DN
I/O Common Choke 67 Ohm
**
RU51 0 USB3_RX2_ESD_DP8 2 USB3_RX2_ESD_DP 3 4 USB3_RX2_ESD_DP

I/O 28 USB3_RX2_PCH_DP
Dummy
GND
RU52 0 3 2 1 USB3_RX2_ESD_DN
28 USB3_RX2_PCH_DN
Dummy
USB3_RX1_ESD_DN7 4 USB3_RX1_ESD_DN Dummy LU21
LU19
*
I/O
3 2 U_USB0N_R USB3_RX1_ESD_DP6 5 USB3_RX1_ESD_DP 0 RU81
22 U_USB0N I/O
4 1 U_USB0P_R ESD3V3U4ULC
22 U_USB0P
*
RU61 0
B Common Choke 90 Ohm B
UU10 Common Choke 67 Ohm
**
USB3_TX2_ESD_DP 9 1 USB3_TX2_ESD_DP 0.1uF CO83 USB3_TX1_PCH_DN_C 4 3 USB3_TX1_ESD_DN
28 USB3_TX1_PCH_DN
**
RU55 0 Dummy I/O

USB3_TX2_ESD_DN 8 2 USB3_TX2_ESD_DN 0.1uF CO80 USB3_TX1_PCH_DP_C 1 2 USB3_TX1_ESD_DP
I/O 28 USB3_TX1_PCH_DP
RU59 0 Dummy
LU18
GND
3 Dummy
*
RU62 0
USB3_TX1_ESD_DN 7 4 USB3_TX1_ESD_DN
I/O
UU13 USB3_TX1_ESD_DP 6 5 USB3_TX1_ESD_DP
*
U_USB1N_R 1 6 U_USB1P_R I/O
ESD3V3U4ULC 0 RU57
2 5 USBPWR1_F_50
U_USB0P_R 3 4 U_USB0N_R Common Choke 67 Ohm
4 3 USB3_RX1_ESD_DN
IP4220CZ6 28 USB3_RX1_PCH_DN
1 2 USB3_RX1_ESD_DP
28 USB3_RX1_PCH_DP
Dummy LU17
*
0 RU53
Title
Intel A
TBD
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+5V For pci slot used

IRQ: CDAB
IDSEL: AD18 RNK3
REQ/GNT: 0
*1 2
K_TDI
K_TMS
3 4 K_TCK
5 6 K_TRST
D D
+3V +5V -12V +12V +5V +3V +3V_PCIAUX 7 8
4.7K Ohm
SLOT3 +/-5%
B1 A1 K_TRST
K_TCK B2 -12V TRST# A2
TCK +12V Moved fromDummy
PCH section-12/30/09
B3 A3 K_TMS
B4 GND1 TMS A4 K_TDI
B5 TDO TDI A5
B6 +5V1 +5V2 A6
+5V3 INTA# K_INTC# 21
B7 A7
21 K_INTD# INTB# INTC# K_INTA# 21
B8 A8
21 K_INTB# INTD# +5V4
B9 A9
B10 PRSNT1# RSV1 A10
B11 RSV2 +5V5 A11
B12 PRSNT2# RSV3 A12
B13 GND2 GND3 A13
B14 GND4 GND5 A14
RSV4 SB3V K_AD[31..0] 21
B15 A15
GND6 RESET# K_PCIRST#_SLOT 21
B16 A16
27 C_PCI_SL1 CLK +5V6 K_C/BE#[3..0] 21
B17 A17
GND7 GNT# K_GNT#0 21
B18 A18
21 K_REQ#0 REQ# GND8
B19 A19
+5V7 PCI_PME# K_PME# 21
K_AD31 B20 A20 K_AD30
K_AD29 B21 AD(31) AD(30) A21
B22 AD(29) +3.3V1 A22 K_AD28
K_AD27 B23 GND9 AD(28) A23 K_AD26
K_AD25 B24 AD(27) AD(26) A24
B25 AD(25) GND10 A25 K_AD24
*
C K_C/BE#3 B26 +3.3V2 AD(24) A26 RK1 330 K_AD18 C
K_AD23 B27 C/BE#(3) IDSEL A27 +/-1%
B28 AD(23) +3.3V3 A28 K_AD22
K_AD21 B29 GND11 AD(22) A29 K_AD20
K_AD19 B30 AD(21) AD(20) A30
B31 AD(19) GND12 A31 K_AD18
K_AD17 B32 +3.3V4 AD(18) A32 K_AD16
K_C/BE#2 B33 AD(17) AD(16) A33
B34 C/BE#(2) +3.3V5 A34
GND13 FRAME# K_FRAME# 21
K_IRDY# B35 A35
21 K_IRDY# IRDY# GND14
B36 A36
+3.3V6 TRDY# K_TRDY# 21
K_DEVSEL# B37 A37
21 K_DEVSEL# DEVSEL# GND15
B38 A38
GND16 STOP# K_STOP# 21
K_LOCK# B39 A39
21 K_LOCK#
**
K_PERR# B40 LOCK# +3.3V7 A40 RK4 0 Dummy
21 K_PERR# PERR# SDONE S_SMBCLK_PCI 24,32,38,39,59
B41 A41 RK5 0 Dummy
+3.3V8 SBO# S_SMBDATA_PCI 24,32,38,39,59
K_SERR# B42 A42
21 K_SERR# SERR# GND17
B43 A43
+3.3V9 PAR K_PAR 21
K_C/BE#1 B44 A44 K_AD15
K_AD14 B45 C/BE#(1) AD(15) A45
B46 AD(14) +3.3V10 A46 K_AD13
K_AD12 B47 GND18 AD(13) A47 K_AD11
K_AD10 B48 AD(12) AD(11) A48
B49 AD(10) GND19 A49 K_AD9
GND20 AD(9)
K_AD8 B52 A52 K_C/BE#0

K_AD7 B53 AD(8) C/BE#(0) A53
B54 AD(7) +3.3V11 A54 K_AD6
B K_AD5 B55 +3.3V12 AD(6) A55 K_AD4 B
K_AD3 B56 AD(5) AD(4) A56
B57 AD(3) GND21 A57 K_AD2
+5V K_AD1 B58 GND22 AD(2) A58 K_AD0 +5V
B59 AD(1) AD(0) A59
RK2 2.7K B60 +5V8 +5V9 A60 RK3 2.7K
B61 ACK64# REQ64# A61
B62 +5V10 +5V11 A62
+5V12 +5V13
Slot-PCI
+5V
ECK1 ECK2 CK1 CK2 CK3 CK4

1
* 470uF *
6.3V, +/-20%
120uF
16V, +/-20% * 0.1uF
*
16V, X7R, +/-10%
0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10%
Dummy Dummy Dummy Dummy Dummy
2
+3V +12V -12V +3V_PCIAUX

A A
ECK3 CK5 CK6 CK7 ECK4 CK10

1
* 470uF
*
6.3V, +/-20%
0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * CK8
0.1uF
* 120uF
16V, +/-20%
CK9
0.1uF * * 0.1uF
16V, X7R, +/-10%
25V, X7R, +/-10% 25V, X7R, +/-10% Title
2
Slot3: PCI
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+3V
D D
***
RX17 4.7K +/-5% X1_TDI
RX18 4.7K +/-5% X1_TRST
RX19 4.7K +/-5%
Dummy X1_TCLK
Dummy
Dummy
+3V_PCIAUX +3V
+12V +12V +3V
SLOT2
B1 A1
B2 +12V#B1 PRSNT1# A2
B3 +12V#B2 +12V#A2 A3
B4 RSVD#B3 +12V#A3 A4
**
RX6 0 Dummy B5 GND#B4 GND#A4 A5 X1_TRST
RX5 0 Dummy B6 A6 X1_TDI
24,32,38,39,58 S_SMBDATA_PCI SMDAT JATG3
B7 A7 20100111: Remove net X_WIRELESS_LED#
*
B8 GND#B7 JATG4 A8 RX7 0 Dummy
+3.3V#B8 JATG5 GPO_WLOM 22
X1_TCLK B9 A9
B10 JTAG1 +3.3V#A9 A10
B11 3.3Vaux +3.3V#A10 A11
24 X1_WAKE# WAKE# PERST# X_PLTRST_PCIE_SLOT# 32,38,39
B12 Mechanical Key A12
B13 RSVD#B12 GND#A12 A13
GND#B13 REFCLK+ C_PCIEX1_2 27
CX51 0.1uF 16V, X7R, +/-10% X_2X1_TXP_C B14 A14
22 X_2X1_TXP C_PCIEX1#_2 27
**
CX52 0.1uF 16V, X7R, +/-10% X_2X1_TXN_C B15 PETp0 REFCLK- A15
22 X_2X1_TXN PETn0 GND#A15
C B16 A16 C
GND#B16 PERp0 X_2X1_RXP 22
B17 A17
PRSNT2#B17 PERn0 X_2X1_RXN 22
B18 A18
GND#B18 GND#A18
Slot-PCIE-1X
+3V +3V_PCIAUX
CX53 CX54 CX55

B B
* 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10% * 0.1uF
16V, X7R, +/-10%
Dummy Dummy Dummy
A A
Title
Slot2: PCIe 1x
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
SATA port 3 only for MT

SATA3
23 T_SATA_TXP3
** **
@MT TX+
23 T_SATA_TXN3 TX-
@MT
8
23 T_SATA_RXN3 @MT RX-
A
CT16 10nF 25V, X7R, +/-10% T_SATA_RXP3_C 6 A
23 T_SATA_RXP3 @MT RX+ 9
NC#9
1
4 GND
7 GND#4
GND#7 Title
CONN-SATA
@MT SATA_MT
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
FLEXBAY
D D
+5V_DUAL_USBKB
1
*
FU4 USBPWR8_F_50
Fuse 2A
2
*
RU19 10K +/-1%
C 22 U_USB_OC_R_#6 C
1
CU10
0.1uF * RU20
15K
* ECU4
470uF * CU11
0.1uF
25V, X7R, +/-10% +/-1% 6.3V, +/-20% 16V, X7R, +/-10%
2
INT_USB
1 2
**
**
RU21 0 +/-5% U_USB12N_R 3 4 U_USB13N_R RU22 0 +/-5% Dummy
22 U_USB12N RU23 0 +/-5% U_USB12P_R 5 6 U_USB13P_R RU24 0 +/-5% Dummy U_USB13N 22
22 U_USB12P 7 8 U_USB13P 22
X 10
S_FLEXBAY_HDR_CBL_DET# 24,27
Header_2X5_K9
Pitch 2.54mm
B B
Dummy
LU7
U_USB12N_R 1 4
U_USB12N 22
U_USB12P_R 2 3
U_USB12P 22
Common Choke 90 Ohm
UU4
U_USB13N_R 1 6 U_USB13P_R LU8
U_USB13N_R 1 4
2 5 U_USB13N 22
USBPWR8_F_50
U_USB13P_R 2 3
U_USB12P_R 3 4 U_USB12N_R U_USB13P 22
Common Choke 90 Ohm
IP4220CZ6
CO-LAY with 4 Serial resistors RU21, RU22, RU23, & RU24

stuff on 20100723-EMC request
A
Title
Intel A
Flexbay USB_MT
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
PRT Port
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
ATX POWER CONNECTOR
+5VSB -12V +5V +3V

D
+3V +5V +12V +5VSB +5V D
RP3 POWER
* 4.7K 13
+3.3V3 +3.3V1
1 *RP1
+/-5% 14 2 1K
15 -12V +3.3V2 3
GND4 GND1 +/-1%
32 O_PSON# 16 4
17 PSON +5V1 5
18 GND5 GND2 6
19 GND6 +5V2 7
20 GND7 GND3 8
RSVD PWR0K B_ATX_PWROK 32,71
21 9
* CP3
0.1uF 22 +5V3 +5V_AUX
+5V4 +12V_1
10
16V, X7R, +/-10% 23 11
24 +5V5 +12V_2 12
Dummy
GND8 +3.3V4 * CP1
0.1uF
Header_2x12 @PR 16V, X7R, +/-10%
*
RP4 Dummy
330
+/-1%
A
AUX_PWR
LED_Yellow
@PR
C
C C
-12V +12V
+5V +3V +5VSB
+3V
* CP4
0.1uF * CP5
0.1uF * CP6
0.1uF * CP7
0.1uF * CP8
0.1uF
* ECP1
470uF * CP9
0.1uF * CP10
0.1uF * CP11
0.1uF
* ECP2
470uF
* ECP3
470uF
* ECP4
470uF
25V, X7R, +/-10% 25V, X7R, +/-10% 25V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 6.3V, +/-20% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 6.3V, +/-20% 6.3V, +/-20% 6.3V, +/-20%
Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
B B
A A
Title
Power Conn
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
For Deep Sleep

+5VSB
+5VSB
*RP680 *RP669
10K
1K
RP674
*
3SUS_WARN_5VDUAL
10K
D * RP681 *RP677 D
10K
10K Dummy
+5VSB
+5VSB
1
2
1
*RP678 MMDT5551
*RP666
MMDT5551 10K
10K QP100
QP99
6
4
6
S_SUS_PWR_ACK# 24
*
SUS_ACK_CTRL
24 S_SUSWARN# *RP675
20K * CP522
0.1uF
RP682 16V, Y5V, +80%/-20%
+5VSB 10K * RP683 +5V_DUAL Dummy
5.6K
+/-1%
SLP_SUS_R
S_RSMRST#_R
*
*
QP76 RP673
*RP685
D
24 S_SUSWARN# S_SUS_PWR_ACK# 24
2N7002 10K
1K RP695
*
0
G Dummy
RP679
* RP684
* CP524
C
1K 10K 0.1uF
*
S
B QP96 +/-1% Dummy
16V, Y5V, +80%/-20%

24,65 S_SLP_SUS# MMBT3904-7-F
C Dummy C
RP687
E
4.7K
RESUME RESET Logic VR_READY DEFENSIVE
*
+5VSB +5VSB +5VSB +5VSB +5VSB
24,32,53,66,70,71 S_SLP_S3# P_CORE_EN 67
1 RP16 CP12
RP273 1 1 1
10K
* 1uF
+/-10%
22K Dummy
*
3
+/-5% RP277 RP280 RP282 RP284
2 22K 0 22K 22K
+/-5% +/-5% +/-5%
2 2 2 QP6
SLP_SUS_FET 65
3
MMDT5551
*
RP279 RP283 +3V_S5
S_RSMRST# 24,52
*
4
B B
MMDT5551 QP18 RP289
1
QP17 10K MMBT3906 QP20 10K 10K
* RP19 * RP17
C
C
B B
MMBT3906
*RP288
4
1 2 QP27 10K 10K

24,65 S_SLP_SUS#
CP529 CP530 MMDT5551 4.7K
*
*
RP274 RP278
22K * RP275 * RP276 1M * 1uF
+/-10% * 2.2uF
*RP281
18K
+/-5%
Dummy
6
+/-5% 1M 1M +/-5% +/-1% RP18
+/-5% +/-5% 6.3V, Y5V, +80%/-20% 10K
*
Dummy Dummy Dummy
1 2 P_VR_READY 24,33,52,67
24,65 S_SLP_SUS#
3
1 RP20
RP285 RP286 100 Ohm
22K 15K +/-1%
+/-5% +/-1% QP7
MMDT5551
2
4
*
+3V_DUAL
9,24,52 H_PWRGD
RP21
100 Ohm
+/-1% * RP23
+3V_S5
* CP269
0.1uF
Dummy 10K
16V, X7R, +/-10%

5
*RP711
24.9KOhm
UP3
VCC
+/-1% 1
A OE# A
*
4 RP290 33
Y S_RSMRST# 24,52
S_RSMRST#_R 2
A
CP282 GND
* 1uF SN74LVC1G17DCKR Title
3
+/-10%
Power Sequence
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+3V_S5 +3V_S5
+3V_EPW
*RP24
10K
S
CP27 CP42 +12V
G * 4.7uF * 0.1uF
QP8 Dummy Dummy
C
FDN340P
16V, X7R, +/-10%

6.3V, X5R, +/-10%
*
B
D 24,32,53,66 S_SLP_M# D
CP18 QP10 CP16
D
RP27
* 1uF MMBT3904-7-F
* 1uF +3V_EPW
E
+3V_S5 10K +/-10% +/-10%
C
Dummy
*
B QP49
* RP211
71 5VDUAL_S3#O MMBT3904-7-F *RP177
0
CP156 RP175 Dummy
E
4.7uF 1K
0
Dummy
* Dummy +/-1%
6.3V, X5R, +/-10% RP176
+3V_EPW 33 Ohm * +12V_UP1
+/-1%
+5VSB
*RP667
10K Dummy
*
RP676 10K
*
+/-1% SLP_SUS_FET_R SLP_SUS_FET
D
C Dummy C
RP672 CP523
DP10
QP95 1K * 0.47uF
C A G 2N7002 10V, X5R, +/-10%
24,64 S_SLP_SUS#
Dummy
Dummy
Dummy
+3V_PCIAUX(FOR PCI/PCIE SLOT)
CP165
S
BAT54HT1G 1uF
* +/-10% +5VSB +3V_S5 +3V_PCIAUX
Dummy
Dummy
+3V_S5 +3V_DUAL
*RP170
10K
CP132 CP45 RP172
* 0.1uF * 4.7uF 0
S
Dummy Dummy
G G CP43 CP44
SLP_SUS_FET
* *
16V, X7R, +/-10%
6.3V, X5R, +/-10%

64 SLP_SUS_FET
RP178 4.7uF 0.1uF
QP50 QP53 0 Dummy Dummy
FDN340P FDN340P Dummy 16V, X7R, +/-10%
6.3V, X5R, +/-10%
Dummy
D
S
B +3V_S5 B
*
G
QP73
RP171 FDN340P
20K CP151 CP152
CP157 +/-1% *RP600 * 4.7uF
* 22uF
D
4.7uF 1K Dummy
*
6.3V, X5R, +/-10%

Dummy CP144
6.3V,X5R,+/-20%
+5VSB 6.3V, X5R, +/-10% 1uF
+5V_S5 * +/-10%
3
QP71
CP146 CP130 2 5
* 4.7uF * 0.1uF
24 S_PCIAUX_GATE
RP262 Dummy Dummy 2N7002DW
4
S
0
16V, X7R, +/-10%
6.3V, X5R, +/-10%
SLP_SUS_FET G Dummy
QP61
FDN340P +5V_S5
24,32,53,71 S_SLP_S4#
D
A A
Title
CP120
* 4.7uF
Dummy
Power-1:Linear Power-1
6.3V, X5R, +/-10% DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+V_1.05_PCH
+V_1.05_ME +3V_S5
+3V +12V_UP1 +1P5V_SM +1P5V_SM
*RP32
16.2K
*
CP24
4.7uF
*
CP25
0.1uF
* RP36
30.1KOhm
D
+/-1% Dummy
1.05V/1.8A
6.3V, X5R, +/-10%

CPP33 +/-1%
8
QP11
16V, X7R, +/-10%

P_1P05V_PCH_ADJ 5 2 1
+ 23 PCH_MEPWRGD
7 P_1P05V_PCH_OUT G CP33
CP30 6 AOD452AL
D - +5V_S5 COPPER * 0.47uF LP1 +1P05V_ME
D
*RP35 * 1uF UP1B
10V, X5R, +/-10%

80mil
*
S
7.5K +/-10% LM358DR Dummy UP2 P_1P05V_ME_LX_80 1 2
P_1P05V_PCH_COMP
4
+/-1% PCH_MEPWRGD_RT80684 1
*
PGOOD LX1
CP32 FBP7 9 2 2.2uH * CP22
22uF * CP23
22uF * CP26
10uF
220pF RP37
1.065V/6.2A * PVIN1 LX2 6.3V,X5R,+/-10%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
10 3
+/-10% 1K
*
*
PVIN2 LX3
*RP295
0
+/-1% +1P05V_PCH CP28 30 Ohm@100MHz
22uF 10K
Dummy *RP43 8
SVIN FB
6 P_1P05V_ME_FB
RP33 CPP34
6.3V,X5R,+/-20% +/-1%
240mil
*
7 2 1
NC
RP41 5 11 7.5K +/-1%
24,32,53,65 S_SLP_M#
1K CP34 CP35 ECP6 CP29 EN EP_GND COPPER
+/-1%
* 0.1uF
* 4.7uF * 470uF
* 1uF Dummy
*
+/-20% +/-10% RT8068AZQW
16V, X7R, +/-10%
6.3V, X5R, +/-10%

CP31
Dummy
*RP39
10K
33pF
50V, NPO, +/-5%
+/-1%
+3V_S5
+5V_S5
C
+V_1.05_PCH *RP55
10K
Dummy
C
P_1P05V_PCH_ADJ +1P05V_PCH +1P05V_ME +/-1%

ENABLE CIRCUIT * RP47 RNP1
10K *
1 2
D
1
3 4
5 6 Dummy QP14
C
QP15 7 8 MMDT5551
*
B G 2N7002
24,32,53,64,70,71 S_SLP_S3#
QP16 0
RP48 MMBT3904-7-F +/-5%
E
6
10K Dummy
RP49
Dummy PCH_MEPWRGD
24,32,53,65 S_SLP_M#
*
CP37
10K * 1uF
+/-10%
+/-1% Dummy
+V_1P8_SFR
+3V_S5
B
+3V
+12V_UP1 *RP51
0 B
+3V Dummy
CP13
RP25
12.7KOhm * 1uF
+/-10% RP52
*RP53
D
+/-1%
* CP14
* CP15 33K +/-5% 5.6K +/-1%
8
QP9 4.7uF 0.1uF Dummy Dummy

1P8V_SFR_ADJ 3 6.3V, X5R, +/-10% 16V, X7R, +/-10%
+
1 1P8V_SFR_OUT G Dummy PCH_MEPWRGD
CP17 2 AOD452AL +1P05V_ME CP41 PCH_MEPWRGD 23
1 -
RP28
* 1uF UP1A 100pF CP38
S
*
15K +/-10% LM358DR
* Dummy * 0.1uF
50V, NPO, +/-5%

*
4
4
+/-1% Dummy
16V, X7R, +/-10%

RP54
2 RP29 30.1KOhm *RP56
301KOhm
*
CP40
0.47uF QP19
1P8V_SFR_COMP
1K
1.812V/1.8A Dummy Dummy MMDT5551
10V, X5R, +/-10%

+/-1%
+/-1% Dummy Dummy
*
+1P8V_SFR
3
RP296 CP19
* 0 1nF
80mil
50V, X7R, +/-10%
*
RP31
1K ECP5
+/-1%
* CP20
0.1uF * CP21
10uF
* 220uF
16V, +/-20%
6.3V,X5R,+/-10%
16V, X7R, +/-10%
A Dummy A
Title
Power-2:Linear Power-2
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+1P05V_VCCIO
Maho Bay VR12 POWER - 4+1 PHASE
+3V
RP59 +5V +12V_CPU +1P05V_VCCIO PWM ADDRESS
*
VCC_CORE RP58
1K
+/-5%
SVID SVID
* 1K RP60 *RP61 RESISTOR ADDRESS FOR ADDRESS FOR
+/-5% 2.2 1K
+/-5% +/-1% VALUE VCORE RAIL V_GT RAIL
D P_CORE_EN 64 CP51 CP48
*RP137 * *RP62
110Ohm *RP63
54.9 *RP64
91 Ohm 10K 0000 0001 D
*
CP47
0.1uF
* * 4.7uF
6.3V, X5R, +/-10%
10nF 1K Dummy
50V,X7R,+/-10% +/-1%
+/-1% +/-1% +/-1%
Dummy 25K 0010 0011
Dummy CP46
0.1uF NCP6151_GND
16V, X7R, +/-10%

45K 0100 0101
10
12
16V, X7R, +/-10% UP4 NCP6151_GND
NCP6153MNTWG
4 70K 0110 0111
VCC
VRMP
SDIO H_VIDSOUT 9
9 5
ENABLE SCLK H_VIDSCLK 9
6 95K 1000 1001
ALERT# H_VIDALERT# 9
P_VR_READY 7 33 125K 1010 1011
24,33,52,64 P_VR_READY VR_RDY DRON P_DRVON 68
32
PWM1/ADDR P_PWM1 68
DIFFOUT 52 35 P_CSN1 165K 1100 1101
P_CSN1 68
* * * * * * * *
DIFFOUT CSN1 34
*RP70 CP80 CP82 RP69
* CP204 P_CSP1
P_CSP1 68
*
680pF RP71 2.2nF COMP 48 CSP1 100KOhm 0.1uF
*
*
*
50V, X7R, +/-10% 4.99K+/-1% 50V, X7R,+/-10% COMP P_CSP1 RP72 +/-1% Dummy
47 RP73 CP53 CP49 47nF Dummy 16V, X7R, +/-10%
+/-5%
* 68pF 30 13.7K +/-1% 16V,X7R,+/-10%
P_PWM2 68
*
50V,NPO,+/-5% FB 49 PWM2/VBOOT 39 NCP6151_GND P_CSN2
P_CSN2 68
*
FB CSN2 38
+VCORE 1K RP74 CP52 RP75
*CP205 P_CSP2
P_CSP2 68
*
+/-1% * RP66 402 Ohm RP67 4.7nF CSP2 100KOhm 0.1uF
*
RP181 402KOhm +/-1% TRBST 50 P_CSP2 RP68 +/-1% Dummy
50V, X7R, +/-10%

TRBST BOOT VOLTAGE
* RP76 NCP6151_GND
+/-1%
24.9KOhm * CP90 1.2KOhm
PWM3/IMAX
31 13.7K +/-1%
CP58 47nF Dummy
16V,X7R,+/-10%
16V, X7R, +/-10%
P_PWM3 68
100 Ohm +/-1% 5.6nF +/-1% 37 NCP6151_GND P_CSN3
CPP26 CSN3 P_CSN3 68
36
9 H_VCC_SENSE
+/-1%
2 1 NCP6151_GND
50V,X7R,+/-10%
VSP 1 CSP3
RP77
100KOhm *CP206
0.1uF
P_CSP3
P_CSP3 68 RESISTOR
VALUE
BOOT
VOLTAGE
*
VSP
COPPER
* CP50
1nF
P_CSP3 RP79
CP54
+/-1%
47nF Dummy
Dummy
16V, X7R, +/-10%
Dummy 51 29 13.7K +/-1% 16V,X7R,+/-10% +5V 10K 0V
9 H_VSS_SENSE Dummy VSN PWM4 P_PWM4 68
CP55 50V, X7R, +/-10% 40 NCP6151_GND P_CSN4
C
* RP80 * 0.1uF
* CP56 CSN4
CSP4
41 RP81
*CP223 P_CSP4
P_CSN4
P_CSP4
68
68 3PHASE 25K 0.9V C
100 Ohm Dummy 0.1uF 100KOhm 0.1uF
OPTION
*
+/-1% 16V, X7R, +/-10% Dummy P_CSP4 RP82 +/-1% Dummy 45K 1.0V
16V, X7R, +/-10% CP57 47nF Dummy 16V, X7R, +/-10% RP83
13.7K +/-1% 16V,X7R,+/-10% 0 * 70K 1.1V
**** ****
RP88 NCP6151_GND NCP6151_GND NCP6151_GND 44 CSSUM NCP6151_GND RP84 32.4K Ohm P_CSP1 Dummy
*
43 CSSUM +/-1%
+5V 95K 1.2V
* ** *
IOUT 7X7 SINGLE 45 CSCOMP RP85 30.1KOhm RP86 80.6kohm RP87 32.4K Ohm P_CSP2
0 RP90 CSCOMP +/-1% RTP1 +/-1% +/-1%
ROW QFN 135K 1.35V
Dummy
** CP59 RP91 100K CP71 5.6nF RP89 32.4K Ohm P_CSP3
*
30.1KOhm 0.1uF +3V 40.2K +/-1% 50V,X7R,+/-10% +/-1% P_PWM4 165K 1.5V
T
+/-1% 47 ILIM CP60 120pF RP92 32.4K Ohm P_CSP4
16V, X7R, +/-10%
ILIM 50V,NPO,+/-5% +/-1%

+/-1% *RP188
CP61 1 2150pF P_CSN1
*RP95
1K *RP96
3.83KOhm
1K
+/-1% 50V, NPO, +/-5%
RP94 10 Ohm
+/-1%
+/-5% VCORE PORTION +/-1% CP207 RP97 10 Ohm P_CSN2
NCP6151_GND CP62 * 1nF

50V, X7R, +/-10% RP99
+/-1%
10 Ohm P_CSN3
P_PWM2 P_PWMA
* 0.1uF 46 DROOP +/-1%
*
Dummy Dummy DROOP RP98 13.7K RP100 10 Ohm P_CSN4
16V, X7R, +/-10% 42 CSREF +/-1% +/-1%
CSREF
* CP63 VCORE *RP102 V_GT *RP103
*
P_VR_READY VR_RDYA 8 1nF 10K 27.4K

VR_RDYA 50V, X7R, +/-10% VBOOT SET +/-1% IMAX SET +/-1%
RP101 DIFFOUTA 17
DIFFOUTA
AT 0V AT 35A
0 RP104 CP64 RP105 28
P_PWMA 68
*
Dummy 680pF 4.32K Ohm CP65 COMPA 19 PWMA/IMAXA 26 NCP6151_GND

P_CSNA 68
*
*
50V, X7R, +/-10% +/-1% 2.2nF COMPA CSNA 25 RP106 100KOhm
VCC_AXG 47 CP66 22pF 50V, X7R,+/-10% CSPA Dummy

**
+/-5% RP107 50V, NPO, +/-5% RP108 +/-1% NCP6151_GND NCP6151_GND

*
*
B +/-1% FBA 16 P_CSPA CP67 B
*
+1P1V_AXG RP109 CP68 FBA 0.1uF RP112
*
*
1K RP110 402 Ohm 4.7nF 50V, X7R, +/-10% 24 CSSUMA 6.8K 16V, X7R, +/-10% P_CSPA
P_CSPA 68
*
RP208 150KOhm +/-1% RP111 TRBSTA 18 CSSUMA +/-1%

TRBSTA 22
*RP115
100 Ohm
+/-1%
24.9KOhm * CP69
5.6nF
1.2KOhm
+/-1% CSCOMPA
CSCOMPA RP113 150KOhm
+/-1%
RP114 200KOhm
+/-1%
20K
+/-1%
+/-1% NCP6151_GND
Dummy +/-1% 50V,X7R,+/-10% RTP3 100K CP70 P_PWM1 P_PWM3
CPP27
*
RP117 +/-1% 2.2nF
**
T
2 1 NCP6151_GND VSPA 15 60.4K 50V, X7R,+/-10%
9 H_VCCAGX_SENSE
*
VSPA 20
COPPER
* CP92
1nF ILIMA
ILIMA CP72 1.2nF
+/-10% VCORE
Dummy 14 +/-1% RP203
9 H_VSSAGX_SENSE
*RP120
Dummy CP74 50V, X7R, +/-10% VSNA RP118
*
* 1K
PWM
ADDRESS
*RP122
10K IMAX SET *RP123
93.1K
*
* 0.1uF
* CP75 7.5K +/-1% CP73 680pF P_CSNA
P_CSNA 68
+/-1% AT 120A +/-1%
*
100 Ohm Dummy 0.1uF +/-1% CP208
+/-1% 16V, X7R, +/-10% Dummy
16V, X7R, +/-10%
V_GT PORTION * 560pF
+/-10%
50V, X7R, +/-10% RP121
10 Ohm
21 +/-1%
*
*
NCP6151_GND NCP6151_GND NCP6151_GND 23 DROOPA DROOPA
+5V IOUTA RP124 5.36KOhm NCP6151_GND NCP6151_GND
*
27
RP125
0
+5V
RP126
1K
VBOOTA
VBOOTA
+/-1%
* CP76
1nF
Dummy +/-1% RP129 3 VRHOT# 50V, X7R, +/-10%
* VR_HOT#
ROSC
EPAD
Dummy 10K 2 TSENSE

13 TSENSE
RP128 ** CP77
0.1uF
+/-1%
*RP130
TSENSEA
TSENSEA *RP131
3.3KOhm NCP6151_GND
H_PROCHOT# 9,32
34.8KOhm 16V, X7R, +/-10% 3.3KOhm +/-1%
11
53
+/-1% +/-1%
NCP6151_GND
ROSC
*
CP78
* *
A NCP6151_GND NCP6151_GND
RTP6 * CP79 0.1uF
*RP133 T RTP4
CPP11 A
T 10K *RP132
7.5K
0.1uF
16V, X7R, +/-10% *RP134
12KOhm NCP6151_GND
16V, X7R, +/-10% 7.5K
+/-1%
10K
+/-1% 2 1
+/-1% +/-1% +/-1% BOTTOM PAD
COPPER
CONNECT TO Dummy
GND Through
NCP6151_GND 4 VIAs NCP6151_GND NCP6151_GND Title
NCP6151_GND NCP6151_GND NCP6151_GND
Power-3: Vcore PWM
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+12V_CPU
+12V_CPU +12V_VIN
+12V_VIN RP136
RP135 25V, X7R, +/-10% 2.2 HG2_25 69
2.2 220nF CP85
+/-5% CP84 CP190 CP183 CP184 CP185
*
* 10uF
* 10uF
* CP81
* 10uF
* 10uF
* CP83
*
CP263 0.1uF RP138 220nF CP264 0.1uF
16V,X5R,+/-10%
16V,X5R,+/-10%
16V,X5R,+/-10%
16V,X5R,+/-10%
VCC2_20
D
RP271
2.2 QP21 5 * 3.3nF
+/-10%
Dummy
16V, X7R, +/-10%
2.2
+/-5%
25V, X7R, +/-10%
QP22 5 * 3.3nF
+/-10%
Dummy
16V, X7R, +/-10%
D
VCC1_20
+/-5% BST1_25 +/-5% D BST2_25 +/-5% D LL=1.7m ohms

UP5 2.2 UP6 2.2
1
RP139 4 G RP183 RP140 4 G RP184
* * 0.25V~1.55V/112A MAX
4 8HG1_25 HG1_R_25 S 1 1 4 8 HG2_25 HG2_R_25 S 1 1
BST
BST
VCC DRVH 2 +/-5% VCC DRVH 2 +/-5%
67 P_PWM2 TDC=85A
*
3 LP2 3 LP3 OS-CON
7 SW1_25 2 1 7 SW2_25 2 1
67 P_PWM1 SW +VCORE SW +VCORE
*
2 GND RP141 5NTMFS4927NT1G
5 Choke 300nH 2 RP142 5NTMFS4927NT1G
5 Choke 300nH
GND
PAD
PAD
*
*
P_DRVON 3 PWM 5 D D 3 PWM 5LG2_25 D
CP86 EN DRVL
10K
Dummy
CP87
*
3.3nF
P_DRVON
CP88 EN DRVL
10K
Dummy
D CP89
*
3.3nF *
ECP9
820uF *
ECP10
820uF *
ECP8
820uF *RP182
220
RP143 4 4 4 4
* 1uF NCP5901BMNTBG LG1_25 50V, X7R, +/-10% RP145
* 1uF NCP5901BMNTBG 50V, X7R, +/-10% +/-20% +/-20% +/-20% +/-5%
9
6
2
2
2.2Ohm +/-10% G S 1 G S 1 2.2Ohm +/-10% G S 1 G S 1 Dummy
+/-1% QP23 2 QP24 2 RP144 CPP1 CPP2 +/-1% QP25 2 QP26 2 RP146 CPP3 CPP4
3 3 1 * COPPER COPPER 3 3 1 * COPPER COPPER
BOTTOM PAD +/-1% Dummy Dummy BOTTOM PAD +/-1% Dummy Dummy
1
CONNECT TO NTMFS4925NT1GNTMFS4925NT1G CONNECT TO NTMFS4925NT1GNTMFS4925NT1G
GND Through GND Through
ECP12 ECP11
4 VIAs 4 VIAs
* 820uF
+/-20%
* 820uF
+/-20%
67 P_CSP2
+12V_CPU 67 P_CSP1 +12V_CPU
67 P_CSN2
67 P_CSN1 +12V_VIN Ceramic / 0805/X5R
+12V_VIN
RP147 RP148 CP96 CP115 CP116 CP99 CP118
2.2 2.2
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
CP181 CP182 CP186 CP187
*
*
C
RP149 CP94 CP265 * 10uF
* 10uF
* CP91
0.1uF RP150 CP95 CP266 * 10uF
* 10uF
* CP93
0.1uF
C
16V,X5R,+/-10%
16V,X5R,+/-10%
16V,X5R,+/-10%
16V,X5R,+/-10%
2.2
+/-5%
220nF
25V, X7R, +/-10% QP29 5 * 3.3nF
+/-10%
Dummy
16V, X7R, +/-10%
2.2
+/-5%
220nF
25V, X7R, +/-10% QP30 5 * 3.3nF
+/-10%
Dummy
16V, X7R, +/-10%

VCC3_20
BST3_25 +/-5% D BST4_25 +/-5% D
VCC4_20
UP7 2.2 UP8 2.2
1
1
RP151 4 G 4 G
4 8 HG3_25 HG3_R_25 S 1 *RP185
1 4 8 HG4_25
RP152
HG4_R_25 S 1 *RP186
1
*
CP102
22uF
*
CP103
22uF
*
CP104
22uF
*
CP105
22uF
*
CP114
22uF
BST
BST
VCC DRVH 2 +/-5% VCC DRVH 2 +/-5%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
67 P_PWM4
*
*
3 LP4 3 LP5
67 P_PWM3
7 SW3_25 2 1 7 SW4_25 2 1
SW +VCORE SW
*
2 RP153 5NTMFS4927NT1G
5 Choke 300nH 2 RP154 5NTMFS4927NT1G
5 Choke 300nH
GND
GND
PAD
PAD
*
*
P_DRVON 3 PWM 5 D D 3 PWM 5 D D
CP106 EN DRVL
10K
Dummy
CP107
3.3nF * P_DRVON
CP108 EN DRVL
10K
Dummy
CP109
3.3nF *
4 4 4 4
RP155
* 1uF NCP5901BMNTBG LG3_25 50V, X7R, +/-10% RP157
* 1uF NCP5901BMNTBG LG4_25 50V, X7R, +/-10%
9
6
2
2
2.2Ohm +/-10% G S 1 G S 1 2.2Ohm +/-10% G S 1 G S 1
+/-1% QP31 2 QP32 2 RP156 CPP5 CPP6 +/-1% QP33 2 QP34 2 RP158 CPP7 CPP8 CP110 CP111 CP112 CP113
3 3 1 * COPPER COPPER 3 3 1 * COPPER COPPER
* 22uF
* 22uF
* 22uF
* 22uF
BOTTOM PAD +/-1% Dummy Dummy BOTTOM PAD +/-1% Dummy Dummy
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
1
1
CONNECT TO NTMFS4925NT1GNTMFS4925NT1G CONNECT TO NTMFS4925NT1GNTMFS4925NT1G
GND Through GND Through
4 VIAs 4 VIAs
67 P_CSP4
67 P_CSP3 67 P_CSN4
Inside processor socket
67 P_CSN3 +VCORE CP97 CP98 CP100 CP119
+12V_CPU
Bottom side * 22uF
* 22uF
* 22uF
* 22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
B B
CP117 CP101 CP162 CP161
RP159 +12V_VIN * 22uF

Dummy * 22uF
Dummy * 22uF
Dummy * 22uF
Dummy
2.2
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
CP188 CP189
*
CP122 * 10uF
* 10uF
* CP121
0.1uF
16V,X5R,+/-10%
16V,X5R,+/-10%
Dummy Dummy Dummy Dummy
RP160 220nF CP267 Dummy
2.2
+/-5%
25V, X7R, +/-10%
QP36 5 QP62 5 * 3.3nF
+/-10%
16V, X7R, +/-10% LL=4.1m ohms
0.25V~1.55V/35AMax
VCCA_20
BSTA_25 +/-5% D D +1P1V_AXG TDC=25A

UP9 2.2
1
RP161 4 G 4 G RP187
4 8HGA_25 HGA_R_25 S 1 S 1 * 1
BST
VCC DRVH 2 2 +/-5% CP124 CP125 CP126 CP178 CP160 CP153

3 3
67 P_PWMA
ECP17 ECP18 ECP19 ECP20 ECP22 ECP27
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
*
7 * 820uF * 820uF * 820uF * 820uF * 820uF * 820uF

*RP179
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
2 SW NTMFS4927NT1GNTMFS4927NT1G +/-20% +/-20% +/-20% +/-20% +/-20% +/-20% 220
GND
PAD
*
P_DRVON 3 PWM 5 RP162 SWA_25 2 LP71 Dummy Dummy +/-5%

67 P_DRVON
CP127 EN DRVL
*
10K 5 5 Choke 470nH Dummy
RP163
* 1uF NCP5901BMNTBG Dummy D D
* CP128
9
2.2Ohm +/-10% 3.3nF

+/-1% LGA_25 4 4 50V, X7R, +/-10%
2
+12V_CPU +12V_VIN G S 1 G S 1
LP6 QP37 2 QP38 2
BOTTOM PAD
*RP164 CPP9 CPP10
*
1 2 CONNECT TO 3 3 1 COPPER COPPER

GND Through +/-1% Dummy 1 Dummy
1
A 12V_PWRCONN Choke 1uH NTMFS4925NT1GNTMFS4925NT1G A
ECP14 ECP15 ECP16 4 VIAs +1P1V_AXG
4 3
* CP123
0.1uF
* 470uF * 470uF * 470uF Bottom side
2 1 16V, X7R, +/-10% 16V, +/-20% 16V, +/-20% 16V, +/-20% 67 P_CSPA CP131 CP210
22uF 22uF
67 P_CSNA
Header_2X2 * Dummy
* Dummy Title
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
Power-4: Vcore Driver
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+3V +5V +5V
+1P05V_VCCIO
* RP180 1.05V or 1.0V/17A MAX
10K RP167 RP350 Bottom side
2.2 2.2 Dummy Dummy Dummy Dummy Dummy Dummy Dummy Dummy
+/-5% +/-5% CP147 CP148 CP149 CP241 CP262 CP252 CP270 CP271
+12V_VIN
D * 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
D
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
70 VCCIO_PWRGD
VCCIO_VCCP
VCCIO_VCC
* CP138
0.1uF * CP133
1uF * CP350
1uF
16V, X7R, +/-10% 16V, X5R, +/-10% 16V, X5R, +/-10% CP134 CP135 ECP21
* 0.1uF
* 10uF * 470uF
16V,X5R,+/-10%
Dummy +/-20%
16V, X7R, +/-10%

15
68 HG2_25
1
UP10 Ceramic / 0805/X5R
VCCIO_PWRGD 6 4 VCCIO_BST_25
* RP355
VCCP
VCC
PGOOD BOOT CP258 CP261 CP256 CP260 CP259 CP257 CP275 CP254 CP274
39.2K
CP139 * QP39 5 * 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
+/-1%
Dummy 0.1uF 25V, X7R, +/-10% D
VCCIO_SYN 7 NCP5230MNTWG 5 VCCIO_UG_25 RP190 2.2VCCIO_UG_R_25 4 G

SYNCH UG +/-5% 1
S
2
* RP356 * RP191 3
0 VCCIO_ROSE/EN 14 10K
ROSC/EN LP9
+/-5% Dummy NTMFS4927NT1G
3 VCCIO_LX_25 2 1 Bottom side
LX
*
+1P05V_PCH +5VSB Dummy Dummy Dummy
5 ECP13 ECP23 ECP26 ECP24 ECP25 CP280 CP277 CP272
QP69 * RP351
49.9K
D
* CP142
330nH
* 820uF
+/-20%
* 820uF
+/-20%
* 820uF
+/-20%
* 820uF
+/-20%
* 820uF
+/-20% * 22uF
* 22uF
* 22uF
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
2N7002 +/-1% 16 2 VCCIO_LG_25 4 2.2nF Dummy Dummy
* *RP199
D
GND LG
1
RP200 G S 1 50V, X7R, +/-10%
C 10K 17 QP40 2 CPP12 CPP13 C
1K Thermal PAD
+/-1% +/-1% 3 RP195 COPPER COPPER
G 13 VCCIO_CSP 2.2 Dummy Dummy
2
CSP NTMFS4925NT1G +/-5%
* CP137
*RP166
C
B
0.1uF
Dummy
2.1KOhm
+/-1%* CP351
0.1uF
RP357
12KOhm Bottom side
16V, X7R, +/-10%
16V, X7R, +/-10%
*
8
CP136
* QP70 VCCIO_COMP Dummy Dummy Dummy Dummy Dummy
E
0.1uF MMBT3904-7-F COMP 12 VCCIO_CNS +/-1% CP278 CP279 CP281 CP273 CP253
CSN/VO
Dummy
* 22uF
* 22uF
* 22uF
* 22uF
* 22uF
VSEN
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
FBG
16V, X7R, +/-10%
* CP380 RP193
FB
0.1uF 4.53K Ohm

+/-1%
*
CP143
100pF * CP301
0.1uF
9
10
11
16V, X7R, +/-10% 50V, NPO, +/-5%
Dummy 16V, X7R, +/-10%
VCCIO_FB
VCCIO_VSEN
* CP141
0.1uF VCCIO_FBG +1P05V_VCCIO
16V, X7R, +/-10% +1P05V_VCCIO
Bottom side
*
RP168 0 RP354 0 +/-5% CP214 CP215 CP216 CP217

*
+/-5% Dummy
* RP202 * 22uF
Dummy * 0.1uF
Dummy * 0.1uF
Dummy * 0.1uF
Dummy
RP353
6.3V,X5R,+/-20%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

* 100 Ohm
VCCIO VID control RP212
0 +/-1%
+/-5% CPP29
17.4kohm RP194
*
B +5V +5V 1K Dummy 2 1COPPER B

H_VCCTT_SENSE 9
+/-1%
+/-1%
CPP28
Dummy RP192 CP140
*RP206 *RP209
*
100 Ohm 1nF 2 Dummy1

H_VSSTT_SENSE 9
*
10K 10K QP46 +/-1% 50V, X7R, +/-10% CP218 CP219 CP221 CP220
D
Dummy Dummy
QP74
Dummy 2N7002
RP205 COPPER * 0.1uF
Dummy * 0.1uF
Dummy * 0.1uF
Dummy * 0.1uF
Dummy
MMDT5551 * 3.16K Dummy * RP198
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%
16V, X7R, +/-10%

G +/-1%, 100 Ohm
+/-1%
3
* CP150
0.1uF
Dummy Dummy *RP207
0
16V, X7R, +/-10%
4
Dummy
RP226
17.4kohm
*
VCCIO_VSEN
+/-1%
Dummy
D
QP48
G 2N7002
A Dummy A
S
RP201
1K
*
H_VCCIO_SEL 9
VCCIO_FBG
+/-1% Title
Dummy
Power-5: VCCIO
H_VCCIO_SEL High ->+1P05V_VCCIO=1.05V
DWG NO Rev
H_VCCIO_SEL Low ->+1P05V_VCCIO=1.0V
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
VCCSA sequencing circuit

D D
+5V_S5
*
+5V
RP217
3
10K
*RP297 QP44
10K MMDT5551
Dummy
4
10K
RP230
VCCSA_COMP_EN
S_SLP_S3# 24,32,53,64,66,71
* *
+5V_S5
RP218
3
10K
QP45
+12V MMDT5551
4
+1P05V_VCCIO
* RP213
2.2
VCCIO_PWRGD
VCCIO_PWRGD 69
CP191 CP158
C UP11 * 1uF
+/-10% * CP163
0.1uF * 10uF
c0805h14
VCCSA VID control C
D
6.3V,X5R,+/-10% +5V +5V RP233
16V, X7R, +/-10%
*
VCCSA_COMP_EN 1 6 QP41 VCCSA_FB
EN VCC RP196
*
2 5 G Dummy 35.7KOhm
1
*RP219
D
GND DRV AOD452AL RP216
VCCSA_FB 3 4 CP164 100 Ohm
0.929V or 0.855V/8.8A 15K 10K +/-1% Dummy
S
FB SOFT-S
*
CP192
15nF * 100pF +/-1%
50V, NPO, +/-5% * CP159
22nF +V_VCCSA
+/-1%
2 Dummy
Dummy
G
NCP102SNT1G +/-10% Dummy 16V, X7R, +/-10% RP225
*
Dummy QP42
S
RP238 * CP359 CP362 ECP41 CP360 100 Ohm * CP155
0.1uF
2N7002
Dummy
1
10K
Dummy
RP236
3.24K Ohm
RP221 * 10uF
* 10uF * 820uF
+/-20% * 10uF
+5V
+/-1% Dummy
16V, X7R, +/-10%

*
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
6.3V,X5R,+/-10%
Dummy
+/-1% 100 Ohm +/-1%
RP263 QP43
*
20.5K *RP220 MMDT5551
6
+/-1% 10K Dummy
Dummy
RP222
CPP30
*
9 H_VCCSA_VID
2 1 H_VCCSA_SENSE 9
100
COPPER
*RP224 +/-5%
1K Dummy
Dummy +/-1%
Dummy
B B
A A
Title
Power-6: VCCSA
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1
5 4 3 2 1
+5V +5V_DUAL +5VSB +5VSB +1P5V_SM
+V_1.5_SM Power(DDRIII)
*RP241 *RP242
1
* CP227
0.1uF * CP226
0.1uF * CP292
0.1uF * CP293
0.1uF
3.24K Ohm
+/-1%
8.2K
+/-5% CPP31
16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% 16V, X7R, +/-10% Dummy COPPER
Dummy Dummy Dummy Dummy Dummy
2
VT_5078_PG 13 8 VT_5078_BOOT_25 VT_5078_PHASE_25
CPP35
*
PGOOD BOOT CP174
1 2 4 9
32,63 B_ATX_PWROK
VT_5078_5VMAIN
5V_MAIN UGATE
VT_5078_HDRV_25 CP173
0.1uF * 470pF
Dummy
D 14 10 16V, X7R, +/-10% 50V, X7R, +/-10% D
COPPER VCC PHASE RP250
*RP252
*
Dummy CPP361 2COPPER VT_5078_S3#I 17 11 VT_5078_ISNS 1.27K
24,32,53,64,66,70 S_SLP_S3# S3I# ISNS
Dummy +/-1% RP253
24,32,53,65 S_SLP_S4#
18
EN LGATE
12 VT_5078_LDRV_25 4.99K *
1K
+/-1% +/-1%
Dummy
+3V_DUAL
5VDUAL_SBSW 3
5VSB_DRV FB
23 VT_5078_FB * CP175
4.7nF
50V, X7R, +/-10% CP176 RP255
3.3V/1.5A MAX 15
3VSB_OUT COMP
22 VT_5078_COMP
* 47pF 33K *RP256
1.82KOhm
+/-5% +/-1%
50V, NPO, +/-5%

5VDUAL_S3#O 16 RP254 Dummy
65 5VDUAL_S3#O VCC_EN * 18K
+/-1%
5VDUAL_USBSW 1 7
5VUSB_DRV VDDQ_IN
24,32,53,65 S_SLP_S4#
2
S4ST# REF_IN
24
6
VT_5078_REF_IN
*
CP196
10nF
Dummy
* RP257
1K
+V_SM_VTT Power(DDR VTT)
VTT_OUT 25V, X7R, +/-10% +1P5V_SM_VTT
+/-1%
5 VT_5078_VTT_SNS
VTT_SNS
C * CP166
10uF * CP167
0.1uF * CP168
4.7uF * CP169
1uF * CP170
0.1uF * CP171
4.7uF
0.75V/1.5A MAX C
Dummy 6.3V, X5R, +/-10%
* CP197
16V, X7R, +/-10%
16V, X5R, +/-10%
16V, X7R, +/-10%

6.3V, X5R, +/-10%
* RP258
6.3V,X5R,+/-10%
Dummy Dummy 10nF

Dummy 1K
VT_5078_ILIM 20 19 25V, X7R, +/-10% +/-1%
ILIM GND
VT_5078_SS 21 25 * CP198
0.1uF * CP199
4.7uF
* ECP36
470uF
SS GND1 *RP260
16V, X7R, +/-10%
6.3V, X5R, +/-10%

Dummy 100 Ohm
6.3V, +/-20%
RP248 +/-5%
+5VSB 200KOhm
* CP172 Dummy
+5V_DUAL_USB +/-1% 0.1uF

16V, X7R, +/-10%
UP12
CPP32
RT9646AZQW 1 2
4
RP267
*
5VDUAL_USBSW 3 QP64
+5V_DUAL_USBKB COPPER
1M SI3457CDV-T1-E3 Dummy
+/-5% +5V_DUAL
+V_1.5_SM Power(DDRIII)
1
2
5
6
2
3 CP177
*
1 2.2nF
*
50V, X7R, +/-10%
D
DP3 QP59 QP60

BAT54C *RP268
1K *RP269
1K FBP3 FBP2 FBP1 FBP4Dummy
+/-1% +/-1% 30 Ohm@100MHz 30 Ohm@100MHz
5VDUAL_S3#O G G 30 Ohm@100MHz 30 Ohm@100MHz
B AOD452AL AOD452AL CP200 CP201 ECP29 ECP30 B
S
* 1uF
* 10uF * 470uF * 470uF
6.3V,X5R,+/-10%
6.3V, +/-20%
6.3V, +/-20%
16V, X5R, +/-10%
QP52 5
D Dummy
+5V VT_5078_HDRV_25 4 G +1P5V_SM
+5VDUAL +5VSB +12V +3V

S 1
2
3 LP12
VT_5078_PHASE_25 NTMFS4927NT1G 2 1
1.5V/25A MAX
4
*
5VDUAL_SBSW 3 QP65 ECP40 CP243 Choke 1uH
*RP270 * 1000uF
* 10uF
*
ECP31
*
ECP32
*
ECP33
*
ECP35 CP129 CP211 CP213
*
ECP34
*
ECP43
SI3457CDV-T1-E3 8.2K Dummy Dummy
* CP202 1000uF 820uF 1000uF 1000uF
* 22uF
* 22uF
* 22uF 820uF 820uF
6.3V,X5R,+/-10%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
+/-5% 2.2nF +/-20% +/-20% +/-20%
6.3V, +/-20%
6.3V, +/-20%
6.3V, +/-20%
6.3V, +/-20%
+5V_DUAL 5 5 50V, X7R, +/-10% Dummy
S
1
2
5
6
CP179 D D
G
*
VT_5078_LDRV_25 4 4
2.2nF AOD452AL G S 1 G S 1
D
50V, X7R, +/-10%

*RP265 *RP266 CP180 * ECP37 QP75 QP55 2
3
QP56 2
3
+1P5V_SM
1K 1K
* 4.7uF 470uF
D
+/-1% +/-1% RP261

6.3V, +/-20%
Bottom side
6.3V, X5R, +/-10%
5VDUAL_S3#O G NTMFS4925NT1G NTMFS4925NT1G 2.2

QP67 +/-5%
AOD452AL * ECP38 CP203 CP212 CP209
S
A
470uF
* 22uF
Dummy * 22uF
Dummy * 22uF
Dummy
A
6.3V, +/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
6.3V,X5R,+/-20%
+3V_DUAL
+5V
Title
Max. output current = 1.5A
Power-7: DDR3/5Vdual/5VUSB
DWG NO Rev
A00
Lanikai _MT/DT
5 4 3 2 1

Dell Optiplex 7010 - Lanikai-Mt - DT Ra00

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Dell Optiplex 7010 - Lanikai-Mt - DT Ra00

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5 4 3 2 1

1. Index / Block diagram

Intel PROCESSOR DDR3 DIMM 3

53. Pilot Run Conn Page 21-30 HP Out/ MIC In

71. Power: DDR3/5Vdual/5VUSB Page 51

DESIGN CHECK APPROVE Index / Block diagram

SMBus SMLINK1 QO4/QO5

PCIE 16x SMBUS

PCI EXPRESS 16x SLOT 1

PCI EXPRESS 16x (wired as 4x signal) SLOT 4

PCI EXPRESS 1x SLOT 2

PCI SLOT SLOT 3

DDR3 DIMM1 CHA Address : 0 X00

DDR3 DIMM3 CHA Address : 0 X02

DDR3 DIMM2 CHB Address : 0 X04

DDR3 DIMM4 CHB Address : 0 X06

25 MHZ LAN 82579 C_PCIE_L1/L1#

POWER DELIVERY MAP

DDR3 DDR3 Vtt VCCSA Linear

Deep Sleep : Off

POWER ON Timing Diagram

t225 Power rails rise

Recommended that VccSA ramp after VCCIO has

CPU SVID buffers are Hi-Z once VCCIO is

Note:DDR spec reuqires that DDR_RESET# be

DPWROK BCLK, PCIe

RSMRST# T =PCH_PWROK & SYS_PWROK &

SUSWARN# DMI training CPU_RESET_DONE

Lanikai _MT/DT A00

Date: Wednesday, June 13, 2012 Sheet 5 of 71

RESET / Power Good MAP Deep Sleep Exit MAP

Power On Botton (1) (1) (8)

SLP_S4# SLP_S4_S5# PWR_GOOD_3V

PCH_MEPWRGD (D5) (D4) (D2)

IRQ Routing Table PCH

No Reboot Mode Digital Port C Strap

High No reboot mode: Enable High Configure Port C DEFAULT

Low No reboot mode: Disable DEFAULT Low Disable

Integrated 1.05V VRM

High Integrated 1.05V VRM: Enable DEFAULT

High See CFG Table HDA_SDO Description

Low Disable ME in Manufacturing Mode DEFAULT

SIO SMSC5545 DMI Rx Termination Voltage

Lanikai _MT/DT A00

Date: Wednesday, June 13, 2012 Sheet 8 of 71

RH4 usage 1kOhm ; CRB 0.7-12/10/09

+5V RH17 change to 4.7k; CRB 0.7-11/30/09

Remove CH1,CH2-12/29/09 Add H_VCCIO_SEL circuit; CRB 0.7-12/03/09

AF33 D3_DQ_B62 Title

UH1F +1P05V_VCCIO +V_VCCSA +1P1V_AXG +1P5V_SM

C36 J16 J7 U38

6.3V, X5R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

A17 AM27 AT8 F37

AH40 AP40 C11 K2

16V, X7R, +/-10%

PLAECE CLOSE TO CH-A DIMM

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

16V, X7R, +/-10%

Change to 0.1uF; PDG 0.7-12/07/09