Generating the Frame Check Sequence (FCS) Field:

The FCS generated for the AX.25 frame is generated according to the recommendations
in the HDLC reference document, ISO 3309.
For 16-bit FCS, a polynomial of degree 16 is used. For HDLC (ISO-3309 recommendations)
polynomial used is called CRC-CCIT. It is given by:

Actually, its corresponding binary sequence will be a 17-bit long but we discard the MSB.
This MSB is discarded 1 0001 0000 0010 0001
Hex Representation: 1 0 2 1
Corresponding shift-registers representation for this polynomial is shown in figure 01.

Figure 1: Shift Registers for the generator polynomial

Initial value in this assembly of shift registers is all ones. FCS is the bit-inversion of the
final value of the shift registers after we input the last bit.
Procedure:
All bits other then the flag bits are used to generate the FCS field for AX.25 frame. The
generator polynomial is bit reversed and we get the following bit pattern:
0001 0000 0010 0001 is bit reversed to 1000 0100 0000 1000
Hex Representation: 8 4 0 8
Now for the count of the total bits used for FCS generation a loop is run. Before first and
after every increment MSB of the shift registers is shifted out and contents of the shift
registers are shifted one bit (which is 0 in this case) to the right.