Mini project 2020

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Floating-point multiplication unit with 16-bit significant and 8-bit

exponent
 Floating-point multiplication unit with 16-bit significant and 8-bit exponent

1. Introduction

The Aim of the project is to design a floating-point multiplier in VHDL and implement the design
in Xilinx FPGA. As like in a micro controller we can’t handle floating point number as such. Since
FPGAs are works on bit level it is intended to study the standard representation of floating-point
notations used in bit level.
2. Representation of Floating-Point Numbers
A simple representation of a floating-point (or real) number (N) uses a fraction (F), base (B), and
exponent (E), where N = F X BE. The fraction and the exponent can be represented in many
formats. For example, they can be represented by 2’s complement formats, sign-magnitude
form, or another number representation. There are a variety of floating-point formats
depending on how many bits are available for F and E, what the base is, and how negative
numbers are represented for F and E. The base can be implied or explicit. In this project we have
chosen IEEE 754 Floating point representation and customized it to 16 bit significant and 8 bit
exponent, total 24 bit.

3. IEEE 754 Standard Floating-point numbers

The IEEE 754 is a floating-point standard established by IEEE in 1985. There are different format
of IEEE 754 formats are available depending on the number of bits used to represent the floating
point numbers.
1. Half precision – 16bit representation
2. Single precision – 32 bit representation
3. Double precision – 64 bit representation
4. Quadruple precision – 128 bit representation
5. Octuple precision – 256 bit representation
Here we will see the format of IEEE754 single precision format and then we will convert it to 24-
bit format which is required for the project.

4. IEEE 754 Standard Single precision Floating-point format.

The IEEE 754 standard specifies a binary 32-bit format as having
Sign bit – 1 bit
Exponent width – 8 bits
Significant precision/Mantissa – 24 (23 explicitly stored)
Sign bit determines the sign of the number. Exponent is an 8-bit signed integer from -127 to
+128 or an 8-bit unsigned integer from 0 to 255, which is the accepted biased form in IEEE754
32 bit standard. For this case an exponent value of 127 represent actual zero. The true
significant include 23 fraction bits to the right of the binary point and an implicit leading bit (to
the left of the binary point) with value 1. Thus only 23 fraction bits of the significant appears in
memory format but the total precision is 24 bits. If sign bit =1 for negative numbers sign bit = 0
for positive numbers
Th format is more clearly as shown in Figure 1.

sign Exponent (8 bits) Fraction (23 Bits)

31 30 23 22 0
Fig 1. IEEE754 Standard 32-bit representation

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 Floating-point multiplication unit with 16-bit significant and 8-bit exponent

The real value assumed by a given 32-bit data with a given biased exponent e and a 23-bit
fraction is
Value = (-1) sign (1+∑23 -i
𝑖=1(𝑏-i) 2 ) X 2
(e-127)

Here the 1 in the summation part (given in red) is not explicitly used in significant part.
It is hidden
The single precision binary floating point is encoded using an offset binary representation with
zero offset being 127 also known as the Exponent Bias (e) . So that the exponent can be
represented as unsigned binary format. The standard treats zero and infinity as follows
If the exponent is zero the value of the floating-point number is zero
If the exponent is FFH then the value of the floating-point number is +/- infinity.

As an example
0x41258794 = (0 10000010 01001011000011110010100)2 = 10.3456
0xc1a45810 = (1 10000011 01001000101100000010000)2 = – 20.543

5. Floating point representation using 24-bit format – 16 bits significant and 8 bit exponent

sign Exponent (8 bits) Fraction (15 Bits)

23 22 15 14 0
Fig 2. Floating point 24-bit representation
Here in the 16-bit fraction or significant bits only 15 bits are one 16 th bit is hidden in the
algorithm.
6. The floating-point Multiplication Algorithm
Consider two floating point numbers given the followings
X1=(-1)s1(M1x2E1)
S1 E1 (8 bits) M1 (15 Bits)
23 22 15 14 0
X2=(-1)s2(M2x2E2)
S2 E2 (8 bits) M2 (15 Bits)
23 22 15 14 0
Fig 3. Floating point 24-bit representation example

Let X3 = X1.X2
X3 = (-1) s1(M1x2E1) * (-1) s2(M2x2E2)

X3 = (-1)s3(M3x2E3)
7. Algorithm flow
1. The sign bit S3 = S1 XOR S2;
2. The Mantissa M3 is found by multiplying M1 and M2 with the hidden ‘1’ padded to M1
and M2.
M3_int = 1.M1*1.M2;
1.M1 => 16 bits
1.M2 =>16 bits
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 Floating-point multiplication unit with 16-bit significant and 8-bit exponent

So M3_int =>32 bits

Since in the standard M3 also be 15 bits we need to normalize the result to 15 bits.
If M3_int (31) =1 then add 1 to the exponent else do nothing. Since it is equivalent to
multiplying by 2. After that take the 15 Most significant result from M3_int (ie,M3_int((29
downto 15)) and save it to M3.
3. E3 =E1+E2 – bias +Normalized exponent from step 2

8. Implementation
The above algorithm is implemented in VHDL and targeted for Xilinx Artix-7 XC7A35T-
ICPG236C FPGA.The Multi plier and Multiplicand are loaded in to the Floating-point
multiplier in the above-mentioned format when ‘load’ signal is High. Then in the next clock
cycle the normalized mantissa is calculated. Then in the third clock cycle the exponent and
result is calculated.
A flow diagram of the circuit is as shown in figure.

multplcnd_in (23 downto 0)

multiplier (23 downto 0) result (23 downto 0)

FP_MUL
load
clk
rst

Fig 4. Floating point Multiplier Block diagram

The design is tested for various values and verified with a IEEE754 converter from on line
https://www.h-schmidt.net/FloatConverter/IEEE754.html .

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 Floating-point multiplication unit with 16-bit significant and 8-bit exponent

9. Flow diagram of the Floating-point Multiplier Designed

RESET
Count=0;
Result= X”000000” rst=0

i
If (load = ‘1’ and Count=0)
load multiplier and multiplicand, M1
and M2; Count= count +1; load=0

exp: of result =X”00”, count =0;

i
If (Count=1) exp: of result =X”FF”, count
i Calculate sign bit; =0;

If ((exp: of multiplier OR exp: of multiplicand) = X”FF”) i

i

If ((exp: of multiplier OR exp: of multiplicand) = X00)

i
Calculate mantissa_interm = 1&M1 *1&M2
Count = count +1
i
Calculate exponent
result(22 downto 15)<=
i
multplr(22 downto 15)+multplcnd(22 downto 15)-127+ mantissa_interm(31) ;
result = upper 15 bit of normalized mantissa_interm(31)
Count = 0;

Fig 5. Flow diagram of the Multiplier Designed

i

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 Floating-point multiplication unit with 16-bit significant and 8-bit exponent

10. Simulation Results

Multiplier Multiplicand Multiplier in Multiplicand in Result in 24- Result
24-bit format 24-bit format bit format
5.98 10.64 0x40bf5D 0x412a3e 0x427e84 63.6272
10.456 10.64 0x41274b 0x412a3e 0x42de80 111.25
-1098.25 256.890 0xC48948 0x438072 0xc889c2 -282129.00
0 876.64 0x000000 0x445b29 0x000000 0
-96.75 -54.8769 0xc2c180 0xc25b82 0x45a5ea 5309.25
inf -678.59 0x7ff000 0xc429a6 0xffffff -inf

11. Simulation waveform

12. Resource Utilization

Resource Utilization Available Utilization %
LUT 14 20800 0.35
Flip-Flop (FF) 20 41600 0.23
DSP 1 90 1.11
Slice 46 8150 0.56

13. Conclusion
The Floating-point multiplier is designed in 24-bit format. The Multiplier is capable of handling
floating point multiplication in all cases. It explicitly handles zero and infinity also. For high
modulus values it is found that the precision decreases. To increase the resolution, it is suggested
to increase the number of bits from 24. The design is tested with 50 MHz clock frequency. Once
the data is loaded, the result will be available in the second clock cycle.
References
1. “Computer Architecture A Quantitative Approach”. By John L Hennessy & David A Patterson

2. “Digital Systems Design Using VHDL”. By Charles H Roth

3. https://www.rfwireless-world.com/Tutorials/floating-point-tutorial.html

4. https://steve.hollasch.net/cgindex/coding/ieeefloat.html

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