LTC1065

DC Accurate, Clock-Tunable
Linear Phase 5th Order Bessel
Lowpass Filter
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FEATURES DESCRIPTIO
■ Clock-Tunable Cutoff Frequency The LTC®1065 is the first monolithic filter providing both
■ 1mV DC Offset (Typical) clock-tunability with low DC output offset and over 12-bit
■ 80dB CMR (Typical) DC accuracy. The frequency response of the LTC1065
■ Internal or External Clock closely approximates a 5th order Bessel polynomial. With
■ 50µVRMS Clock Feedthrough appropriate PCB layout techniques the output DC offset is
■ 100:1 Clock-to-Cutoff Frequency Ratio typically 1mV and is constant over a wide range of clock
■ 80µVRMS Total Wideband Noise frequencies. With ±5V supplies and ±4V input voltage
■ 0.004% Noise + THD at 2VRMS Output Level range, the CMR of the device is typically 80dB.
■ 50kHz Maximum Cutoff Frequency The filter cutoff frequency is controlled either by an inter-
■ Cascadable for Faster Roll-Off nal or external clock. The clock-to-cutoff frequency ratio is
■ Operates from ±2.375 to ±8V Power Supplies 100 : 1. The on-board clock is nearly power supply inde-
■ Self-Clocking with 1 RC pendent and it is programmed via an external RC. The
■ Available in 8-Pin DIP and 16-Pin SW Packages 50µVRMS clock feedthrough of the device is considerably
U lower than other existing monolithic filters.
APPLICATIO S The LTC1065 wideband noise is 80µVRMS and it can
■ Audio process large AC input signals with low distortion. With
■ Strain Gauge Amplifiers ±7.5V supplies, for instance, the filter handles up to
■ Anti-Aliasing Filters 4VRMS (94dB S/N ratio) while the standard 1kHz THD is
■ Low Level Filtering below 0.005%; 87dB dynamic range (S/N + THD) is ob-
■ Digital Voltmeters tained with input levels between 2VRMS and 2.5VRMS.
■ Smoothing Filters
■
The LTC1065 is available in 8-pin miniDIP and 16-pin SW
Reconstruction Filters
packages. For a Butterworth response, see LTC1063 data
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents sheet. The LTC1065 is pin compatible with the LTC1063.
including 4857860.

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TYPICAL APPLICATIO Frequency Response
10
3.4kHz Single 5V Supply Bessel Lowpass Filter
0
5V –10

VIN 1 8 –20
4.99k
–30
GAIN (dB)

2 7
VOUT
+ 1µF LTC1065 –40
4.53k 0.1µF 3 6
TANT 5V –50
4 5 0.1µF
–60
–70
13k* 200pF* –80
* SELF-CLOCKING SCHEME
1065 TA01 –90
1 10 100
FREQUENCY (kHz)
1065 TA01b

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LTC1065
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ABSOLUTE AXI U RATI GS
(Note 1)
Total Supply Voltage (V + to V –) .......................... 16.5V Operating Temperature Range (Note 7)
Power Dissipation ............................................. 400mW LTC1065C .............................................. 0°C to 70°C
Voltage at Any Input .... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V) LTC1065I ........................................... – 40°C to 85°C
Burn-In Voltage ...................................................... 16V LTC1065M (OBSOLETE) .................. – 55°C to 125°C
Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C

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PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART TOP VIEW ORDER PART
VIN 1 8 VOS ADJ NUMBER NC 1 16 VOS ADJ NUMBER
GND 2 7 VOUT VIN 2 15 NC
– 6 V + GND 3 14 VOUT
V 3
LTC1065CN8 NC 4 13 NC LTC1065CSW
CLK OUT 4 5 CLK IN
LTC1065IN8 V– 5 12 V+ LTC1065ISW
N8 PACKAGE NC 6 11 NC
8-LEAD PLASTIC DIP
TJMAX = 100°C, θJA = 110°C/W (N) NC 7 10 NC

J8 PACKAGE CLK OUT 8 9 CLK IN

8-LEAD CERAMIC DIP LTC1065MJ8
TJMAX = 150°C, θJA = 100°C/W (J) SW PACKAGE
16-LEAD PLASTIC SO WIDE
OBSOLETE PACKAGE TJMAX = 100°C, θJA = 85°C/W
Consider the N Package for an Alernate Source
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Clock-to-Cutoff Frequency Ratio (fCLK / fC) ±2.375V ≤ VS ≤ ±7.5V 100 ±0.5
Maximum Clock Frequency (Note 2) VS = ±7.5V 5 MHz
VS = ±5V 4 MHz
VS = ±2.5V 3 MHz
Minimum Clock Frequency (Note 3) ±2.5V ≤ VS ≤ ±7.5V, TA < 85°C 30 Hz
Input Frequency Range 0 0.9fCLK
Filter Gain VS = ±5V, fCLK = 25kHz, fC = 250Hz
fIN = 250Hz ● – 3.5 – 3.1 – 2.7 dB
fIN = 1kHz ● – 43.0 – 41.0 – 39.0 dB
VS = ±5V, fCLK = 500kHz, fC = 5kHz
fIN = 100Hz 0 dB
fIN = 1kHz = 0.2fC ● – 0.215 – 0.175 – 0.135 dB
fIN = 2.5kHz = 0.5fC ● – 1.1 – 0.972 – 0.84 dB
fIN = 4kHz = 0.8fC ● – 2.35 – 2.13 – 1.9 dB
fIN = 5kHz = fC ● – 3.35 – 3.1 – 2.7 dB
fIN = 10kHz = 2fC ● – 14.5 – 14.15 – 13.0 dB
fIN = 20kHz = 4fC ● – 43.0 – 41.15 – 39.0 dB
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 LTC1065
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Filter Gain VS = ±2.375V, fCLK = 500kHz, fC = 5kHz
fIN = 1kHz ● – 0.225 – 0.185 – 0.145 dB
fIN = 2.5kHz ● – 1.1 – 1.0 – 0.83 dB
fIN = 4kHz ● – 2.35 – 2.15 – 1.9 dB
fIN = 5kHz ● – 3.35 – 3.1 – 2.7 dB
fIN = 10kHz ● – 14.5 –14.1 –13.0 dB
Clock Feedthrough ±2.375V ≤ VS ≤ ±7.5V 50 µVRMS
Wideband Noise (Note 4) ±2.375V ≤ VS ≤ ±7.5V, 1Hz < f < fCLK 80 µVRMS
THD + Wideband Noise (Note 5) VS = ±7.5V, fC = 20kHz, fIN = 1kHz, – 87 dB
2VRMS ≤ VIN ≤ 2.5VRMS
Filter Output ± DC Swing VS = ±2.375V 1.5/– 2.0 1.7/– 2.2 V
● 1.3/– 1.8 V
VS = ±5V 4.0/– 4.5 4.3/– 4.8 V
● 3.8/– 4.3 V
VS = ±7.5V 6.5/– 7.0 6.8/– 7.3 V
● 6.3/– 6.8 V
Input Bias Current 10 nA
Dynamic Input Impedance 800 MΩ
Output DC Offset (Note 6) VS = ±2.375V 2 mV
VS = ±5V 0 ±5 mV
VS = ±7.5V –4 mV
Output DC Offset Drift VS = ±2.375V 10 µV/°C
VS = ±5V 20 µV/°C
VS = ±7.5V 25 µV/°C
Self-Clocking Frequency (fOSC) R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF
VS = ±2.375V 99 103 112 kHz
LTC1065C ● 95 103 112 kHz
LTC1065M ● 92 100 112 kHz
VS = ±5V 100 106 112 kHz
LTC1065C ● 98 106 114 kHz
LTC1065M ● 97 105 114 khz
VS = ±7.5V 102 106 114 kHz
LTC1065C ● 101 109 116 kHz
LTC1065M ● 100 108 116 kHz
External CLK Pin Logic Thresholds VS = ±2.375V Min Logical “1” 1.43 V
Max Logical “0” 0.47 V
VS = ±5V Min Logical “1” 3 V
Max Logical “0” 1 V
VS = ±7.5V Min Logical “1” 4.5 V
Max Logical “0” 1.5 V
Power Supply Current VS = ±2.375V, fCLK = 500kHz 2.5 4.0 mA
LTC1065C ● 5.5 mA
LTC1065M ● 6.0 mA
VS = ±5V, fCLK = 500kHz 5.5 9 mA
LTC1065C ● 11 mA
LTC1065M ● 12 mA
VS = ±7.5V, fCLK = 500kHz 7.0 12.0 mA
LTC1065C ● 14.5 mA
LTC1065M ● 16.0 mA

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 LTC1065
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life Note 5: To properly evaluate the filter’s harmonic distortion an inverting
of a device may be impaired. output buffer is recommended. An output buffer (although recommended)
Note 2: The maximum clock frequency is arbitrarily defined as the is not necessarily needed when measuring output DC offset or wideband
frequency at which the filter AC response exhibits ≥ 1dB of gain peaking. noise (see Figure 3).
Note 3: At limited temperature ranges (i.e., TA ≤ 50°C) the minimum clock Note 6: The output DC offset is optimized for ±5V supply. The output DC
frequency can be as low as 10Hz. The typical minimum clock frequency is offset shifts when the power supplies change; however, this phenomenon
arbitrarily defined as the clock frequency at which the output DC offset is repeatable and predictable.
changes by more than 1mV. Note 7: The LTC1065C is guaranteed to meet the specified performance
Note 4: The wideband noise specification does not include the clock from 0°C to 70°C and is designed, characterized and expected to meet
feedthrough. specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LTC1065I is guaranteed to meet
specified performance from –40°C to 85°C.

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TYPICAL PERFOR A CE CHARACTERISTICS
Output Offset vs Clock, Output Offset vs Clock,
Self-Clocking Frequency vs R Low Clock Rates Medium Clock Rates
110 50 5
100 45 VS = ±5V 4
LTC1065 VS = ±7.5V
90 4 5 40 A. TA = 25°C 3

OUTPUT OFFSET (mV)

B. TA = 85°C
OUTPUT OFFSET (mV)

80 2
R PINS 4 TO 5 (kΩ)

35
R C
70 C = 200pF 1
fOSC ≅ 1/RC
30
VS = ±5V
60 25 0
50 20 –1
40 15 –2
30 10 –3
VS = ±2.5V
20 5 B –4
A
10 0 –5
100 300 500 10 110 210 0 500 1000
FREQUENCY (kHz) EXTERNAL CLOCK FREQUENCY (Hz) EXTERNAL CLOCK FREQUENCY (kHz)
1065 G01 1065 G02 1065 G03

Gain vs Frequency; VS = ±2.5V Gain vs Frequency; VS = ±5V Gain vs Frequency; VS = ±7.5V

10 10 10

0 0 0
D
–10 –10 –10
–20 A B C E
–20 –20

–30 –30 –30

GAIN (dB)

GAIN (dB)
GAIN (dB)

A B C A B C D
–40 –40 –40 A. fCLK = 1MHz
A. fCLK = 1MHz B. fCLK = 2MHz
–50 A. fCLK = 0.5MHz –50 B. fCLK = 2MHz –50 C. fCLK = 3MHz
B. fCLK = 1MHz –60 C. fCLK = 3MHz –60 D. fCLK = 4MHz
–60
C. fCLK = 2MHz D. fCLK = 4MHz E. fCLK = 5MHz
–70 –70 –70
VIN = 750mVRMS VIN = 1.4VRMS VIN = 1.4VRMS
–80 –80 TA = 25°C –80
TA = 25°C TA = 25°C
–90 –90 –90
1 10 100 200 1 10 100 200 1 10 100 200
INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz)
1065 G04 1065 G05 1065 G06

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 LTC1065
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TYPICAL PERFOR A CE CHARACTERISTICS
THD + Noise vs Input Voltage; THD vs Frequency; THD + Noise vs Input Voltage;
VS = Single 5V, AGND = 2V VS = Single 5V, AGND = 2V VS = ±5V
1 1 1
fIN = 1kHz, TA = 25°C VIN = 0.75VRMS, S/N = 80dB fIN = 1kHz, TA = 25°C
fC = 5kHz, fCLK = 500kHz
TA = 25°C

0.1

THD + NOISE (%)

0.1
THD + NOISE (%)

0.1

THD (%)
B

B
0.01 A 0.01 0.01
A

A. fC = 5kHz, fCLK = 0.5MHz A. fC = 10kHz, fCLK = 1MHz

B. fC = 10kHz, fCLK = 1MHz B. fC = 20kHz, fCLK = 2MHz
0.001 0.001 0.001
0.1 1 5 1 2 3 4 5 0.1 1 5
INPUT (VRMS) FREQUENCY (kHz) INPUT (VRMS)
1065 G07 1065 G08 1065 G09

THD + Noise vs Input Voltage; THD vs Frequency;

THD vs Frequency; VS = ±5V VS = ±7.5V VS = ±7.5V
1 1 1
VIN = 1.5VRMS fIN = 1kHz VIN = 2.5VRMS, S/N = 90dB
fC = 10kHz, fCLK = 1MHz TA = 25°C fC = 10kHz, fCLK = 1MHz
TA = 25°C TA = 25°C

0.1
THD + NOISE (%)

0.1 0.1
THD (%)

THD (%)

B
0.01 0.01 0.01
A

A. fC = 10kHz, fCLK = 1MHz

B. fC = 20kHz, fCLK = 2MHz
0.001 0.001 0.001
1 5 10 0.1 1 5 1 5 10
FREQUENCY (kHz) INPUT (VRMS) FREQUENCY (kHz)
1065 G10 1065 G11 1065 G12

Passband Gain and Phase Typical Phase Matching Power Supply Current vs
vs Input Frequency Device to Device Power Supply Voltage
1 40 0.6 15
±2.5V ≤ VS ≤ ±7.5V, TA = 25°C VS = ± 7.5V
VIN = 1VRMS –40°C
0 0 0.5
POWER SUPPLY CURRENT (mA)

fC = 20kHz 12
PHASE MISMATCH (±DEG)

fCLK = 2MHz
–40
PASSBAND GAIN (dB)

–1
0.4 25°C
PHASE (DEG)

A A B B 9
–2 –80
PHASE PHASE 0.3 85°C
–3 –120 6
0.2
–4 fC =1kHz fC =10kHz –160
fCLK =100kHz fCLK =1MHz 3
–200 0.1
–5

–6 –240 0 0
100 1k 10k 100k 0 2 4 6 8 10 12 14 16 18 20 22 24 0 2 4 6 8 10 12 14 16 18 20
INPUT FREQUENCY (Hz) INPUT FREQUENCY (kHz) TOTAL POWER SUPPLY VOLTAGE (V)
1065 G13 1065 G14 1065 G15

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LTC1065
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TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response Group Delay
45

40

35

GROUP DELAY (µs)

30

25

20

15

10

5 VS = ±5V
fC = 10kHz
0
HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV 0 3 6 9 12 15 18 21
VS = ±5V, fC = 10kHz, VIN = 1kHz ±3VP INPUT FREQUENCY (kHz)
SQUARE WAVE 1065 G17

1065 G16

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PI FU CTIO S
Power Supply Pins (Pins 6, 3, N Package)
The positive and negative supply pin should be bypassed
with a high quality 0.1µF ceramic capacitor. In applications
where the clock pin (5) is externally swept to provide
several cutoff frequencies, the output DC offset variation
is minimized by connecting an additional 1µF solid tanta-
lum capacitor in parallel with the 0.1µF disc ceramic. This
technique was used to generate the graphs of the output
DC offset variation versus clock; they are illustrated in the
Typical Performance Characteristics section.
When the power supply voltage exceeds ±7V, and when
V – is applied before V + (if V+ is allowed to go below
ground) connect a signal diode between the positive
supply pin and ground to prevent latch-up (see Typical
Applications).
Ground Pin (Pin 2, N Package)
The ground pin merges the internal analog and digital
ground paths. The potential of the ground pin is the
reference for the internal switched-capacitor resistors,
and the reference for the external clock. The positive input
of the internal op amp is also tied to the ground pin.
For dual supply operation, the ground pin should be
connected to a high quality AC and DC ground. A ground
plane, if possible, should be used. A poor ground will
degrade DC offset and it will increase clock feedthrough,
noise and distortion.
A small amount of AC current flows out of the ground pin
whether or not the internal oscillator is used. The fre-
quency of the ground current equals the frequency of the
clock. The average value of this current is approximately
55µA, 110µA, 170µA for ±2.5V, ±5V and ±7.5V supplies
respectively.
For single supply operation, the ground pin should be
preferably biased at half supply (see Typical Applications).
VOS Adjust Pin (Pin 8, N Package)
The VOS adjust pin can be used to trim any small amount
of output DC offset voltage or to introduce a desired output
DC level. The DC gain from the VOS adjust pin to the filter
output pin equals two.
Any DC voltage applied to this pin will reflect at the output
pin of the filter multiplied by two.
If the VOS adjust pin is not used, it should be shorted to the
ground pin. The DC bias current flowing into the VOS adjust
pin is typically 10pA.
The VOS adjust pin should always be connected to an AC
ground; AC signals applied to this pin will degrade the filter
response.
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 LTC1065
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PI FU CTIO S
Input Pin (Pin 1, N Package) 100:1. The high (VHIGH) and low (VLOW) clock logic
threshold levels are illustrated in Table 2. Square wave
Pin 1 is the filter input and it is connected to an internal
clocks with duty cycles between 30% and 50% are strongly
switched-capacitor resistor. If the input pin is left floating,
recommended. Sinewave clocks are not recommended.
the filter output will saturate. The DC input impedance of
pin 1 is very high; with ±5V supplies and 1MHz clock, the
Table 2. Clock Pin Threshold Levels
DC input impedance is typically 1GΩ. A resistor RIN in
series with the input pin will not alter the value of the filter’s POWER SUPPLY VHIGH VLOW
DC output offset (Figure 1). RIN should however, be limited VS = ±2.5V 1.5V 0.5V
VS = ±5V 3V 1V
to a maximum value (Table 1), otherwise the filter’s pass-
VS = ±7.5V 4.5V 1.5V
band will be affected. Refer to the Applications Information VS = ±8V 4.8V 1.6V
section for more details. VS = 5V, 0V 4V 3V
VS = 12V, 0V 9.6V 7.2V
RIN 1 8 VS =15V, 0V 12V 9V
VIN
2 7
VOUT
– 3
LTC1065
6
Clock Output Pin (Pin 4, N Package)
V V+
4 5 f
CLK
Any external clock applied to the clock input pin appears
1065 F01 at the clock output pin. The duty cycle of the clock output
Figure 1. equals the duty cycle of the external clock applied to the
clock input pin. The clock output pin swings to the power
Table 1. RIN(MAX) vs Clock and Power Supply supply rails. When the LTC1065 is used in a self-clocking
mode, the clock of the internal oscillator appears at the
RIN(MAX)
clock output pin with a 30% duty cycle. The clock output
VS = ±7.5V VS = ±5V VS = ±2.5V
pin can be used to drive other LTC1065s or other ICs. The
fCLK = 4MHz 1.82k – –
maximum capacitance, CL(MAX), the clock output pin can
fCLK = 3MHz 3.01k 2.49k – drive is illustrated in Figure 2.
fCLK = 2MHz 4.32k 3.65k 2.37k
fCLK = 1MHz 9.09k 8.25k 7.5k
fCLK = 500kHz 17.8k 16.9k 16.9k 200
180 VS = ±2.5V TA = 25°C
fCLK = 100kHz 95.3k 90.9k 90.9k
MAXIMUM LOAD CAPACITANCE (pF )

160
140
Output Pin (Pin 7, N Package) 120

Pin 7 is the filter output. This pin can typically source over 100 VS = ±5V

20mA and sink 2mA. Pin 7 should not drive long coax 80 VS = ±7.5V

cables, otherwise the filter’s total harmonic distortion will 60

degrade. The maximum load the filter output can drive and 40
20
still maintain the distortion levels, shown in the Typical
0
Performance Characteristics, is 20k. 1 2 3 4 5 6 7 8 9 10
CLOCK FREQUENCY (MHz)
1065 F02
Clock Input Pin (Pin 5, N Package)
An external clock, when applied to pin 5, tunes the filter Figure 2. Maximum Load Capacitance at the Clock Output Pin
cutoff frequency. The clock-to-cutoff frequency ratio is

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LTC1065
TEST CIRCUIT
+
LT1022 VOUT

1 8 –
VIN
2 7 50k 50k

LTC1065
3 6
V+
V– 0.1µF 20pF
4 5

0.1µF
CLOCK IN 1065 F03

Figure 3. Test Circuit for THD

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APPLICATI S I FOR ATIO
Self-Clocking Operation
The LTC1065 features an internal oscillator which can be
tuned via an external RC. The LTC1065’s internal oscillator
is primarily intended for generation of clock frequencies
below 500kHz. The first curve of the Typical Performance
Characteristics section shows how to quickly choose the
value of the RC for a given frequency. More precisely, the
frequency of the internal oscillator is equal to:
fCLK = K/RC
For clock frequencies (fCLK) below 100kHz, K equals 1.07.
Figure 4b shows the variation of the parameter K versus
clock frequency and power supply. First choose the de-
sired clock frequency (fCLK < 500kHz), then through Figure
4b pick the right value of K, set C = 200pF and solve for R.
U
Note a 4pF parasitic capacitance is assumed in parallel
with the external 200pF timing capacitor. Figure 5 shows
the clock frequency variation from – 40°C to 85°C. The
200kHz clock of Example 1 will change by –1.75% at 85°C.
For a limited temperature range, the internal oscillator of
the LTC1065 can be used to generate clock frequencies
above 500kHz (Figures 6 and 7). The data of Figure 6 is
derived from several devices. For a given external (RC)
value, the observed device-to-device clock frequency varia-
tion was ±1% (VS = ±5V), and ±1.25% for VS = ±2.5V.
Example 2: fCUTOFF = 20kHz, fCLK = 2MHz, VS = ±7.5V,
TA = 25°C, C = 10pF
from Figure 6, K = 0.575,
and, R = (0.575)/(2MHz × 14pF) = 20.5k.

Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = ±5V, 1.25

TA = 25°C, K = 1.0, C = 200pF 1.20
fCLK = K/RC
C = 200pF
then, R = (1.0)/(200kHz × 204pF) = 24.5k. 1.15 TA = 25°C

1.10
1.05
1.00 VS = ±7.5V
K

VIN
1 8 VS = ±5V
0.95
2 7
VOUT 0.90
LTC1065 VS = ±2.5V
3 6 0.85
V– V+
0.80
4 5
0.75
100 200 300 400 500
R C INTERNAL CLOCK FREQUENCY (kHz)
1065 F04b
1065 F04a

Figure 4a. Figure 4b. fCLK vs K

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 LTC1065
UO U W U
APPLICATI S I FOR ATIO
4
C = 200pF A 4pF parasitic capacitance is assumed in parallel with the
external 10pF capacitor. A ±1% clock frequency variation
3 TA = –40°C

VS = ±5V
fCLK CHANGE NORMALIZED

2 VS = ±2.5V from device to device can be expected. The 2MHz clock

TO ITS 25°C VALUE (%)

1
VS = ±7.5V
frequency designed above will typically drift to 1.74MHz at
0 70°C (Figure 7).
TA = 85°C
–1 The internal clock of the LTC1065 can be overridden by an
VS = ±7.5V
–2 external clock provided that the external clock source can
–3 VS = ±2.5V VS = ±5V drive the timing capacitor C, which is connected from the
–4
clock input pin to ground.
0 100 200 300 400 500
CLOCK FREQUENCY (kHz) Output Offset
1065 F05

The DC output offset of the LTC1065 is trimmed to

Figure 5. fCLK vs Temperature
typically less than ±1mV. The trimming is done at VS =
±5V. To obtain optimum DC offset performance, appropri-
0.80 ate PC layout techniques should be used and the filter IC
0.75
fCLK = K/RC
C = 10pF
should be soldered to the PC board. A socket will degrade
TA = 25°C the output DC offset by typically 1mV. The output DC offset
0.70
is sensitive to the coupling of the clock output pin 4 (N
0.65
VS = ±7.5V
package) to the negative power supply pin 3 (N package).
0.60 The negative supply pin should be well decoupled. When
K

VS = ±5V
0.55 the surface mount package is used, all NC pins should be
0.50 grounded. When the output DC voltage is measured with
VS = ±2.5V
0.45
a voltmeter, the filter output pin should be buffered. Long
test leads should be avoided.
0.40
0.5 1.0 1.5 2.0 2.5 3.0
CLOCK FREQUENCY (MHz)
With fixed power supplies, the output DC offset should not
1065 F06 change by more than ±100µV over 10Hz to 1MHz clock
Figure 6. fCLK vs K
frequency variation. When the filter clock frequency is
fixed, the output DC offset will typically change by – 4mV
(2mV) when the power supply varies from ±5V to ±7.5V
0.80 (±2.5V). See Typical Performance Characteristics.
fCLK = K/RC
0.75 C = 10pF

0.70
TA = 70°C Common Mode Rejection
0.65 The common mode rejection is defined as the change of
0.60
the output DC offset with respect to the DC change of the
K

VS = ±7.5V
input voltage applied to the filter.
0.55
VS = ±5V
0.50 CMR = 20log (∆VOS OUT /∆VIN)(dB)
0.45
VS = ±2.5V
Table 3 illustrates the common mode rejection for three
0.40 power supplies and three temperatures. The common
0.5 1.0 1.5 2.0 2.5 3.0
CLOCK FREQUENCY (MHz)
mode rejection improves if the output offset is adjusted to
1065 F07 approximately 0V. The output offset can be adjusted via
pin 8 (N package). See Typical Applications.
Figure 7. fCLK vs K
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9
LTC1065
UO U W U
APPLICATI S I FOR ATIO
Table 3. CMR Data, fCLK = 100kHz
25°C
POWER SUPPLY ∆VIN – 40°C 25°C 85°C (VOS Nulled)
±2.5V ±1.8V 84dB 83dB 80dB 83dB

5mV/DIV
±5V ±4V 82dB 78dB 77dB 78dB
±7.5V ±6V 80dB 77dB 76dB 80dB
The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for
VS = ±2.5V, ±5V, ±7.5V respectively.

Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock 2µs/DIV
1065F08
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW
frequency and its harmonics which are present at the
filter’s output pin. The clock feedthrough is tested with the Figure 8. LTC1065 Output Clock Feedthrough + Noise
filter input grounded and it depends on the quality of the
PC board layout and power supply decoupling. Any para-
sitic switching transients during the rise and fall of the
incoming clock, are not part of the clock feedthrough
specifications; their amplitude strongly depends on scope
probing techniques as well as ground quality and power
supply bypassing. For a power supply VS = ±5V, the clock
0.5mV/DIV

feedthrough of the LTC1065 is 50µVRMS; for VS = ±7.5V,

the clock feedthrough approaches 75µVRMS. Figures 8
and 9 show a typical scope photo of the LTC1065 output
pin when the input pin is grounded. The filter cutoff
frequency was 1kHz, while scope bandwidth was chosen
to be 1MHz so that switching transients above the 100kHz
2µs/DIV
clock frequency would show. 1063 F09
fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW

Wideband Noise
The wideband noise data is used to determine the operat-
ing signal-to-noise ratio at a given distortion level. The
wideband noise (µVRMS) is nearly independent of the value
of the clock frequency and excludes the clock feedthrough.
The LTC1065’s typical wideband noise is 80µVRMS. Figure
9 shows the same scope photo as Figure 8 but with a more
sensitive vertical scale. The clock feedthrough is imbed-
ded in the filter’s wideband noise. The peak-to-peak wide-
band noise of the filter can be clearly seen; it is approxi-
mately 420µVP-P. Note that 420µVP-P equals the 80µVRMS
wideband noise of the part multiplied by a crest factor
of 5.25.
Figure 9. LTC1065 Output Clock Feedthrough + Noise
Aliasing
Aliasing is an inherent phenomenon of sampled data
filters. It primarily occurs when the frequency of an input
signal approaches the sampling frequency. For the
LTC1065, an input signal whose frequency is in the range
of fCLK ±6% will generate an alias signal into the filter’s
passband and stopband. Table 4 shows details.
Example: LTC1065, fCLK = 20kHz, fC = 200kHz,
fIN = (19.6kHz, 100mVRMS)
fALIAS = (400Hz, 3.16mVRMS)

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10
 LTC1065
UO U W U
APPLICATI S I FOR ATIO
Table 4. Aliasing Data An input RC can be used to attenuate incoming signals
OUTPUT AMPLITUDE close to the filter clock frequency (Figure 10). A Bessel
REFERENCED TO passband response will be maintained if the value of the
INPUT FREQUENCY OUTPUT FREQUENCY INPUT SIGNAL input resistor follows Table 1.
0.9995 fCLK 0.0005 fCLK – 0.01 dB
0.995 fCLK 0.005 fCLK – 0.98 dB R 1 8
VIN
0.99 fCLK 0.01 fCLK – 3.13 dB
C 2 7
0.9875 fCLK 0.0125 fCLK – 4.79 dB VOUT
LTC1065
0.985 fCLK 0.015 fCLK – 7.21 dB V–
3 6
V+
0.9825 fCLK 0.0175 fCLK – 10.43 dB 4 5
0.1µF fCLK 0.1µF
0.98 fCLK 0.02 fCLK – 14.14 dB
0.975 fCLK 0.025 fCLK – 21.84 dB fCLK 1 f
≤ ≤ CLK
0.97 fCLK 0.03 fCLK – 28.98 dB 20 2πRC 10 1065 F10

0.965 fCLK 0.035 fCLK – 35.31 dB

0.96 fCLK 0.04 fCLK – 40.94 dB Figure 10. Adding an Input Anti-Aliasing RC
0.955 fCLK 0.045 fCLK – 45.96 dB
0.95 fCLK 0.05 fCLK – 50.46 dB
0.94 fCLK 0.06 fCLK – 58.29 dB
0.93 fCLK 0.07 fCLK – 64.90 dB
0.9 fCLK 0.1 fCLK – 80.20 dB

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11
LTC1065
U
TYPICAL APPLICATIO S

Cascading Two LTC1065s for Steeper Roll-Off Sharing Clock for Multichannel Applications

1 8 1 8
VIN VIN
2 7 2 7
VOUT
LTC1065 LTC1065
3 6 3 6
–5V 5V –5V 5V

0.1µF 4 5 0.1µF 0.1µF 4 5 0.1µF

R C R C

1 8 1 8
VIN
2 7 2 7
VOUT VOUT
LTC1065 LTC1065
3 6 3 6
–5V 5V –5V 5V

0.1µF 4 5 0.1µF 0.1µF 4 5 0.1µF

1065 TA03

fC ≅ (1/RC)(1/100)
WIDEBAND NOISE = 110µVRMS
ATTENUATION AT f = 2fC = 60dB 1065 TA02

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12
 LTC1065
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)

CORNER LEADS OPTION .405

(4 PLCS) (10.287)
.005 MAX
(0.127)
MIN
8 7 6 5
.023 – .045
(0.584 – 1.143)
HALF LEAD
OPTION .025 .220 – .310
.045 – .068 (0.635) (5.588 – 7.874)
(1.143 – 1.650) RAD TYP
FULL LEAD
OPTION
1 2 3 4 .200
.300 BSC
(5.080)
(7.62 BSC) MAX

.015 – .060
(0.381 – 1.524)

.008 – .018
0° – 15°
(0.203 – 0.457)

.045 – .065
.125
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143 – 1.651)
OR TIN PLATE LEADS 3.175
.014 – .026 MIN
.100
(0.360 – 0.660) (2.54)
BSC J8 0801

OBSOLETE PACKAGE

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13
LTC1065
U
PACKAGE DESCRIPTIO
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)

.400*
(10.160)
MAX

8 7 6 5

.255 ± .015*
(6.477 ± 0.381)

1 2 3 4

.300 – .325 .045 – .065 .130 ± .005

(7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127)

.065
(1.651)
.008 – .015 TYP
(0.203 – 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 –.015

( )
.100 .018 ± .003 MIN
+0.889
8.255 (2.54) (0.457 ± 0.076)
–0.381 N8 1002
BSC
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

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14
 LTC1065
U
PACKAGE DESCRIPTIO
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)

.030 ±.005 .050 BSC .045 ±.005 .398 – .413

TYP (10.109 – 10.490)
NOTE 4
N 16 15 14 13 12 11 10 9

.420 .325 ±.005

MIN
NOTE 3 .394 – .419
(10.007 – 10.643)

1 2 3 N/2 N/2

RECOMMENDED SOLDER PAD LAYOUT

1 2 3 4 5 6 7 8

.291 – .299
(7.391 – 7.595)
NOTE 4 .037 – .045
.093 – .104
.010 – .029 × 45° (0.940 – 1.143)
(2.362 – 2.642)
(0.254 – 0.737)
.005
(0.127)
RAD MIN 0° – 8° TYP

.050
.009 – .013 (1.270) .004 – .012
(0.229 – 0.330) NOTE 3 BSC (0.102 – 0.305)
.014 – .019
.016 – .050
(0.356 – 0.482)
(0.406 – 1.270)
TYP
NOTE:
INCHES
1. DIMENSIONS IN S16 (WIDE) 0502
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

1065fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15
LTC1065
U
TYPICAL APPLICATIO S
Single 5V Supply Operation (fC = 3.4kHz) Adjusting VOS(OUT) for
±7.5 Supply Operation
7.5V
5V

1 8 10k
VIN
4.99k
2 7 10k
VOUT
+ 1µF LTC1065 LT1009
4.53k 0.1µF 3 6
TANT 5V 1 8
0.1µF VIN
4 5 ≅2.5mV
2 7
VOUT
LTC1065
13k 200pF V– 3 6 V+
–7.5V 7.5V
1065 TA04
+ 4 5 fCLK
1µF 0.1µF 0.1µF *
TANT
* OPTIONAL, 1N4148
1065 TA05

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1063 Clock Tunable, 5th Order Bessel Low Pass Internal or External Clock, 1mVDC Offset, Cascadable
LTC1064-1/2/3/4/7 Clock Tunable, 8th Order Low Pass Elliptic, Butterworth, Bessel, Cauer or Linear Phase
LTC1164-5/6/7 Clock Tunable, Low Power, 8th Order Low Pass Butterworth, Bessel or Elliptic, FO Max = 20KHz
LTC1264-7 Clock Tunable, 8th Order Low Pass Flat Group Delay, FO Max = 200KHz, Steeper Roll-Off than Bessel
LTC1569-6/7 Clock Tunable, 10th Order Low Pass Internal or External Clock, Root Raised Cosine Response

1065fb

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