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  • Sheet1: Inverter Chain Delay Analysis With Various Values of Width

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    Shiva Prasad
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    This document analyzes the delay of an inverter chain with various width values from 85um to 2000um. It shows that the delay decreases from 3.7ns to 3.5ns as the width increases from 85um to 185um, but remains around 3.8ns as the width further increases to 2000um. It also lists system parameters like rise/fall times and pulse times. Finally, it examines power consumption ranging from 80pW to 450pW for the 350nm CMOS inverter chain.

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    Delay Model

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    This document analyzes the delay of an inverter chain with various width values from 85um to 2000um. It shows that the delay decreases from 3.7ns to 3.5ns as the width increases from 85um to 185um, but remains around 3.8ns as the width further increases to 2000um. It also lists system parameters like rise/fall times and pulse times. Finally, it examines power consumption ranging from 80pW to 450pW for the 350nm CMOS inverter chain.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd
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    7 views3 pages

    Sheet1: Inverter Chain Delay Analysis With Various Values of Width

    Uploaded by

    Shiva Prasad
    This document analyzes the delay of an inverter chain with various width values from 85um to 2000um. It shows that the delay decreases from 3.7ns to 3.5ns as the width increases from 85um to 185um, but remains around 3.8ns as the width further increases to 2000um. It also lists system parameters like rise/fall times and pulse times. Finally, it examines power consumption ranging from 80pW to 450pW for the 350nm CMOS inverter chain.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as XLS, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 3

    Sheet1

    INVERTER CHAIN DELAY ANALYSIS WITH VARIOUS VALUES OF WIDTH

    SI.NO 1 2 3 4 5 6 7 8 9

    WIDTH(um) 85 150 185 190 200 285 500 1000 2000

    DELAY(ns) 3.7 3.56 3.5 3.81 3.81 3.83 3.81 3.8 3.84

    Page 1

    Sheet1

    SYTEM PARAMETERS Length Rise time of I/p signal Fall time of I/p signal ON time of input pulse OFF time of input pulse

    POWER(pWS) 80 135 160 170 176 200 450

    CMOS TECHNOLOGY =350nm

    Page 2

    Sheet1

    VALUE 0.35um 10ns 10ns 1us 1us

    LOGY =350nm

    Page 3

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