BSC3153 Nokia GSM/EDGE BSS, Rel. BSS13, BSC and TCSM, Rel. S13, Product Documentation, v.

AS7-C

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The information in this document is subject to change without notice and describes only the product defined in the introduction of this documentation. This documentation is intended for the use of Nokia Siemens Networks customers only for the purposes of the agreement under which the document is submitted, and no part of it may be used, reproduced, modified or transmitted in any form or means without the prior written permission of Nokia Siemens Networks. The documentation has been prepared to be used by professional and properly trained personnel, and the customer assumes full responsibility when using it. Nokia Siemens Networks welcomes customer comments as part of the process of continuous development and improvement of the documentation. The information or statements given in this documentation concerning the suitability, capacity, or performance of the mentioned hardware or software products are given as is and all liability arising in connection with such hardware or software products shall be defined conclusively and finally in a separate agreement between Nokia Siemens Networks and the customer. However, Nokia Siemens Networks has made all reasonable efforts to ensure that the instructions contained in the document are adequate and free of material errors and omissions. Nokia Siemens Networks will, if deemed necessary by Nokia Siemens Networks, explain issues which may not be covered by the document. Nokia Siemens Networks will correct errors in this documentation as soon as possible. IN NO EVENT WILL NOKIA SIEMENS NETWORKS BE LIABLE FOR ERRORS IN THIS DOCUMENTATION OR FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO SPECIAL, DIRECT, INDIRECT, INCIDENTAL OR CONSEQUENTIAL OR ANY LOSSES, SUCH AS BUT NOT LIMITED TO LOSS OF PROFIT, REVENUE, BUSINESS INTERRUPTION, BUSINESS OPPORTUNITY OR DATA, THAT MAY ARISE FROM THE USE OF THIS DOCUMENT OR THE INFORMATION IN IT. This documentation and the product it describes are considered protected by copyrights and other intellectual property rights according to the applicable laws. The wave logo is a trademark of Nokia Siemens Networks Oy. Nokia is a registered trademark of Nokia Corporation. Siemens is a registered trademark of Siemens AG. Other product names mentioned in this document may be trademarks of their respective owners, and they are mentioned for identification purposes only. Copyright Nokia Siemens Networks 2008. All rights reserved.

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Contents

Contents
Contents 3 List of tables 4 List of figures 5 Summary of changes 7 1 2 3 3.1 3.2 3.3 4 5 6 7 AS7-C overview 9 Capacity and performance of AS7-C 11 Structure of AS7-C 13 Mechanical structure 13 Logical structure 13 Interfaces 19 Operation of AS7-C 25 Power consumption of AS7-C 29 AS7-C C105007 31 Connector maps of AS7-C 35

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List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. I/O Bridge address ranges 17 20 26

Interface signals of the AS7-C

AS7-C front panel LED indicators Power Consumption of AS7-C SW1 switch settings. 32 29

Interchangeability code settings of AS7-C P5 connector P4 connector P1 connector 35 36 37

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List of figures

List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Operational environment of the AS7-C plug-in unit. Block diagram of the AS7-C plug-in unit. Interfaces of the AS7C. AS7-C front panel. 26 31 20 14 10

DIP switches of the plug-in unit AS7-C

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Summary of changes

Summary of changes

Changes between document issues are cumulative. Therefore, the latest document issue contains all changes made to previous issues.

Changes between issues 1-3 and 1-4

Ethernet interface information removed.

Changes between issues 1-2 and 1-3

Added a table for setting the SW1 interchangeability switch.

Changes between issues 1-1 and 1-2

Section AS7-C C105007 updated.

Changes between issues 1-0 and 1-1

AS7-B corrected to AS7-C in figure Operational environment of the AS7-C plug-in unit.

Issue 1-0
First issue.

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AS7-C overview

AS7-C overview
The AS7-C preprocessing unit for multichannel signalling is a general purpose peripheral slot computing plug-in unit. The AS7-C plug-in unit fulfils various telecommunications protocols of the Nokia network elements such as SS7, LAPD and X.25. Purpose of the AS7-C The AS7-C plug-in unit functions as a general purpose peripheral slot computing engine with the necessary hardware to handle 256 HDLC, PPP or transparent (TMA) channels in the Nokia network element. The plug-in unit provides the hardware required by the DMX operating system and application software such as the boot memory, SDRAM, interrupt handling, process timing and V.24/V.28 based serial interfaces for service terminals. The unit is connected to the back plane CompactPCI bus. Operational environment of the AS7-C The following figure illustrates the operational environment of the AS7-C plug-in unit.

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PCM CIRCUIT (TO SWITCHING NETWORK) AS7-C 8M, 8k (FROM CLOCK SYSTEM)

COMPACTPCI BUS

MASTER UNIT
DN03514383

Figure 1.

Operational environment of the AS7-C plug-in unit.

Notice that there are two V.24/V.28 based serial interfaces for service terminals to provide an interface for controlling and monitoring the AS7-C plug-in unit. Data can be transferred between the AS7-C and the host processor unit of the same cartridge via the CompactPCI bus on the back plane. The AS7-C is connected to the CompactPCI bus with an Embedded PCI/PCI Bridge. In addition to the CompactPCI connection, the unit also has two interrupt lines to the host processor unit connected via the back plane. The AS7-C plug-in unit is connected to the GSW0/1 via five (4+1) duplicated 4.096 Mbit/s full duplex PCM line interfaces. The unit gets the +5V, -5V and +3.3V supply voltages through back connectors. V(I/O) pins are used for 3.3V supply.

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Capacity and performance of AS7-C

Capacity and performance of AS7-C

The AS7-C plug-in unit replaces up to four AS7-A plug-in units in M98 mechanics. Processor and memory
.

650 MHz Mobile Intel Celeron in a micro FCBGA-479 package. 256 MB SDRAM, assembled directly on PWB, 100 MHz bus, CL=2. 256 kB L2 cache on processor die, running at the processor frequency. 8 MB boot FLASH.

PCI Buses The unit has two internal PCI buses. The other bus is a 33 MHz, 32 bit PCI bus and it is used as a compatibility PCI bus. Boot memory is located in this bus, which is referred to as 'bus 0' in this document. The other PCI bus is a 33/66MHz, 32 bit PCI bus. This bus is referred to as 'bus 2' in this document. Serial interfaces
.

Two V.24/V.28 based maintenance terminal connections are connected to the back plane. Typical data transfer rate used is 9600 bit/s or 19200 bit/s. Maximum 38 400 bit/s.

PCM interfaces The AS7-C has five (4+1) duplicated 4.096 Mbit/s full duplex PCM line interfaces. Four PCMs are connected directly (behind the slot) to the GSW0/1 and one is connected to the GSW0/1 via a PCM connector of the cartridge.

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The HDLC controller

.

Munich 256 in a P-BGA388 package. Implements HDLC, PPP and transparent (TMA) protocol processing for 256 channels.

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Structure of AS7-C

3
3.1

Structure of AS7-C
Mechanical structure
The size of the AS7-C PWB is 233.4 x 220 mm and its nominal thicknes is 1.6 mm. The unit connects to the back plane with two shielded (P1, P4) and one nonshielded (P5) 2 mm Hard Metric connectors. The front panel contains two LEDs that indicate the state of the unit, and it is fastened to the PWB with four M2.5 screws. The holes for the screws are copper plated to ground the front panel to the PWB. The front panel has cooling fins and a heat pipe is also connected to it. The other end of the heat pipe is attached to a heat sink that covers the processor.

3.2

Logical structure
The AS7-C unit has a Mobile Celeron processor with an internal speed of 650 MHz and a 100 MHz front side bus. The processor has 256KB L2 cache integrated on the same die, running with full processor core frequency. The Mobile Celeron uses the Tualatin technology (0.13 s process). The processor is connected to RadiSys 82600 north bridge. In addition to the front side bus, the 82600 contains a 33 MHz, 32 bit PCI bus and a 33/ 66 MHz, 32 bit PCI bus. The first PCI bus (33 MHz, 32 bit), bus 0, is used as the compatibility PCI bus (the South bridge is located on this bus). The compatibility PCI bus of the North bridge contains the South bridge ASIC (interface to the unit I/O and Boot Flash) and AS7 specific FPGA. The PCI/PCI bridge to the CompactPCI is also located on the compatibility PCI bus. The second PCI bus, bus 2, contains the HDLC controller.

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The HDLC controller and PCI/PCI Bridge need to be able to act as bus masters on PCI buses they are connected to. The I/O Bridge can be target only. The following block diagram illustrates the logical structure of the AS7C. The components of the diagram are explained in more detail below.
82600 Estacada North Bridge Ethernet 82544EI MAC+PHY Embedded PCI/PCI Bridge CompactPCI Bus

Celeron Processor

SDRAM

33/66MHz, 32bit PCI-bus 2

33MHz, 32bit PCI-bus 0

10/100/1000 Mbit Ethernet

10/100/1000 Mbit Ethernet

Ethernet 82544EI MAC+PHY

I/O Bridge ("South Bridge") Including: -DMX specific I/O

Interrupts V.24/V.28 etc

I/O Bus ("Universal" non-multiplexed bus) Boot Flash

HDLCController

10 2 Mbit/s full duplex PCM Alarm 2 Int

AS7specific FPGA 8K 8M 5 4 Mbit/s full duplex internal PCM

DN03275349

Figure 2.

Block diagram of the AS7-C plug-in unit.

The AS7-C has two internal PCI buses. The compatibility bus of the 82600 is a 33 MHz, 32 bit PCI bus (the ISA bridge is located behind this bus). The secondary PCI bus is a 33/66 MHz, 32 bit PCI bus. The compatibility bus of the 82600 is configured as bus 0. The secondary PCI bus is configured as bus 2.

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82600 configuration registers are located on the bus 0, device 0. The host bridge, memory controller configuration registers and compatibility PCI bus registers are located in function 0. The secondary PCI configuration registers are located in function 1. The devices on PCI buses are identified with device number. The device number is defined by PCI bus ADXX signal connected to device IDSEL signal. A device that can act as a master in the PCI bus has a unique request and grant signal pair. The count of these masters on the bus 0 is limited to four and on the bus 2 to seven by the bus arbiter, in addition to the 82600. Celeron processor The unit contains a Mobile Intel Celeron Processor with internal/bus frequencies of 650/100 MHz and RadiSys 82600 Embedded Host Bridge. The processor has 256 kB L2 cache integrated on the same die, running with full processor core frequency. SDRAM The unit has 256 MB synchronous DRAM assembled directly on PWB. The memory technology used is 256 Mbit technology. The memory bus operates at 100 MHz speed. HDLC controller The HDLC controller of the AS7-C is the Munich 256 by Infineon. It is a highly integrated protocol controller that implements HDLC, PPP and transparent (TMA) protocol processing for 256 bidirectional channels. The HDLC controller has a connection to the AS7-C internal PCI bus 2 (32Bit, 33/66 MHz) for transmitting data using DMA. It is able to act as bus master. The HDLC controller on bus 2 uses AD20 as the IDSEL signal and is device 4. It uses the REQ/GNT pair 0. The serial line interface of the HDLC controller is configured in a 16-port mode. The HDLC controller is connected to AS7CL-FPGA via ten 2.048 Mbit/s serial lines. The interrupt controller has an interrupt request line reserved for the HDLC controller.

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AS7CL-FPGA The AS7CL-FPGA is implemented with an FPGA designed by Nokia, containing AS7-specific registers and devices. The FPGA takes care of PCM line interfaces and clock supervision. It includes Time Slot Selection, ANSI and JT1 registers for all 2.048 Mbit/s PCM lines. There are 128 application-specific interrupt timers for SS7 links and two general purpose interrupt timers. In addition to these there are various status and control registers. The AS7CL-FPGA on bus 0 uses as the AD15 IDSEL signal and is device 4. It uses the REQ/GNT pair 1. The AS7CL-FPGA can only be a PCI target so the arbitration signals are connected just in case more functionality is needed in some other application in the future. The device used for AS7CL-FPGA is Xilinx XC2S150 in PBGA256 package. PCI/PCI Bridge The PCI/PCI Bridge of the AS7-C is Intel 21555. The Embedded Non-Transparent PCI/PCI bridge on bus 0 uses the AD14 signal as IDSELand is device 3. It uses the REQ/GNT pair 0. Secondary PCI bus INTA signal (CPCI_INT) of the PCI/PCI Bridge is connected to the interrupt controller of the unit. Primary PCI bus INTA signal of the PCI/PCI Bridge is connected to back connector pin P1A3 via 0 ohm resistor and to AS7CL-FPGA. The interrupt signal is connected to AS7CL-FPGA just in case more functionality is needed in some other applications in the future. I/O Bridge The I/O bridge is connected to bus 0 and uses the AD18 signal as IDSEL and is device 7. The I/O Bridge can only be a PCI Bus target. The I/O bridge controls the boot FLASH and the DMX related I/O devices. The I/O bridge is implemented using the South Bridge ASIC by RadiSys.

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Structure of AS7-C

The various functions are implemented as addresses in one device. The flash memory is implemented in the memory space, the memory address range being 32 Mbytes. There are two separate I/O address ranges. The primary I/O range is 512 bytes in size. This range includes the legacy DMX functions (timers, interrupt controllers, serial interfaces and various status and control registers) and the I2 C Interface. The secondary I/O range includes the host CPU warm reset register and the AS7CL-FPGA configuration register. This secondary I/O range is 2 kB in size.

Table 1. Range
Memory Primary I/O

I/O Bridge address ranges Size

32 MB 512 kB 2 kB

Description
Boot Flash. Legacy DMX functions. The host CPU warm reset register and AS7CL-FPGA configuration register.

Secondary I/O

The primary I/O range contains devices with both 8 and 16 bit interface to the data bus. In most cases the 8 bit devices are connected to even addresses. The exceptions are the 16550 UART and the interrupt controller. In these cases all the bytes in the 32 bit DWORD are connected to the device (address bit A0 is also connected). Boot Memory range The boot memory is 8 Mbytes. The primary I/O range contains the DMX related I/O devices. There are three 82C54 compatible timers. The timer clocks are mostly generated from an onboard 20 MHz oscillator. In AS7-C there are 17 internal interrupt signals. In addition to these signals the interrupt signals from the PMC connectors are connected to the interrupt controller. The interrupt controller is implemented within the South Bridge ASIC. The two serial interfaces are of the V.24/V.28 (RS-232) type. The interfaces use 16550 compatible UARTs. The UART clock generator input is to be connected to the 1.25 MHz clock signal divided from the unit 20 MHz clock oscillator. The connection is 1.25 MHz to XTAL1 and BAUDOUT to RCLK.

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In addition to these there are various status and control registers. The secondary I/O range contains 8 bit registers needed for host CPU warm reset and the interface to down load AS7CL-FPGA code. Reset Logic The AS7-C unit is reset due to the following reasons:
.

power up / power fail (cold reset) initial hardware watchdog (cold reset) programmable watchdog (warm reset) the CompactPCI bus reset signal goes active (warm reset) the host CPU performs an AS7-C specific warm reset operation (warm reset) the host CPU performs an AS7-C specific hard reset operation (cold reset) emulator reset (cold reset).

The programmable watchdog is implemented with an 82C54 compatible timer (timer 0 counter 0). The counter is reset with a read operation to an I/ O address. There must be an additional control circuitry (initial hardware watchdog) that will cause a new reset if the watchdog counter is not reset within 419 ms after the CPU has been reset. This initial watchdog must generate a cold reset restarting the whole plug-in unit (including the host bridge). This prevents the unit from ending up in a hang situation. The reset from CompactPCI is the input signal _RST (pin P1C21). This signal is received with an RC circuitry and schmitt trigger input. The values for R and C are chosen so that RC value is 0.00001 (for example R=1 kohm, C=10 nF). The host CPU can reset the AS7-C in two different ways. The normal operation is a warm reset that is performed by the host CPU writing to a register in secondary I/O range of PCI/IO Bridge. The host CPU can also cause a hard reset to the AS7-C unit. This is done by writing to the Reset Control register within the embedded PCI/PCI Bridge. This operation causes a total hard reset, as in power up. In addition to the actual reset signal the processor uses also the INIT signal depending on the type of restart.

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Power feed AS7-C gets the +5V, -5V and +3.3V supply voltages from the back plane. All other voltages needed in the unit must be generated in the unit. Back plane V(I/O) pins are used for 3,3V supply. Processor voltages must be generated from 5V to divide the load of power supply voltages. The power up order of +5V and 3.3V of the cartridge power source is not specified. The AS7-C has current limiting electronics when it is plugged into a powered on cartridge.

3.3

Interfaces
The connections of the AS7-C with the system are presented in the following figure. The meanings of the interface signals are presented in the table below.

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CLK _RST AD[31:0] C/_BE[3:0]

COMPACTPCI BUS INTERFACE

DR00B, DR00A...DR03B, DR03A DR10B, DR10A...DR13B, DR13A DT00B, DT00A...DT03B, DT03A DT10B, DT10A...DT13B, DT13A R0A, R0B R1A, R1B T0A, T0B T1A, T1B RxD0, RxD1 TxD0, TxD1 CPU_INT0 CPU_INT1
AS7-C CSA, CSB

SERIAL BUS INTERFACE

PAR _FRAME _IRDY _TRDY _STOP IDSEL _DEVSEL _PERR _SERR _REQ _GNT _INTA 8M0A, 8M0B 8K0A, 8K0B

SERIAL TERMINAL INTERFACE INTERRUPT CHANGEOVER

TR0 X3_N, TR0 X3_P TR0 X2_N, TR0 X2_P TR0 X1_N/R-, TR0 X1_P/R+ TR0 X0_N/T-, TR0 X0_P/T+ +5V -5V 0V +3,3V
DN00249545

ETHERNET

CLOCK SYSSTEM INTERFACE JTAG

POWER SUPPLY

Figure 3.

Interfaces of the AS7C.

Table 2. Signal
CLK _RST AD[31:0]

Interface signals of the AS7-C Meaning

Bus timing signal Reset signal Address and data signals Command and byte enable signals Parity signal Bus frame beginning and length Master ready signal Target ready signal Target stop signal Selection signal for target of configuration Target has recognized its address

C/_BE[3:0]PAR PAR _FRAME _IRDY _TRDY _STOP IDSEL _DEVSEL

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Table 2. Signal
_PERR _SERR _REQ _GNT _INTA JTAG

Interface signals of the AS7-C (cont.) Meaning

Bus parity error Bus system error Master or target requests the bus to itself CompactPCI arbitration grants the bus to requester Interrupt signal The plug-in unit's JTAG interface Basic timing signals Serial bus signals (received data)

8M0A, 8M0B, 8K0A, 8K0B R0A, R0B, R1A, R1B

T0A, T0B T1A, T1B Serial bus signals (sent data) DR00B, DR00A, DR01B, DR01A, DR02B, DR02A, DR03B, DR03A, DR10B, DR10A, DR11B, DR11A, DR12B, DR12A, DR13B, DR13A DT00B, DTR00A, DT01B, DTR01A, DT02B, DT02A, DT03B, DT03A, DT10B, DT10A, DT11B, DT11A, DTR12B, DT12A, DT13B, DT13A RxD0, RxD1 TxD0, TxD1 CPU_INT0, CPU_INT1 CSA, CSB Serial bus signals (received data)

Serial bus signals (sent data)

Serial terminal interface (received data) Serial terminal interface (sent data) Interrupt Changeover signals

+5V, -5V, 0V, +3.3V Operating voltages

Serial Interfaces The AS7-C has two serial terminal interfaces which are connected to the back connector P4.

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Compact PCI bus AS7-C is connected to the back plane CompactPCI bus. The back plane connector pin assignment supports 32 bit CompactPCI bus only. The connector P1 is used for CompactPCI bus. The P2 connector is not assembled. 5V signalling is used on CompactPCI bus. However, V(I/O) is connected to 3.3V on the back plane. V(I/O) pins are used for 3.3V supply. These V(I/O) pins are not used as specified in CompactPCI Specification. Changeover signal The LM311 comparator is used in the change over signal interface as a receiver. There are 100 k serial resistors in the inputs of the differential side selection signal. 100 k and 100 pF RC circuit is used for filtering the noise in the signal. Interface to basic timing signals The AS7-C interfaces to 8,192 MHz and 8 kHz basic timing signals. The 75107-type receiver is used in the interfaces. One k serial resistors are used in the basic timing signal inputs. PCM line interfaces The AS7-C interfaces with five 4,096 Mbit/s serial lines (internal PCM lines) in the back plane. Four of these internal PCM lines (DT/DR) are connected directly to the GSW0/1 and one of these PCM lines (T/R) are shared with other AS7 plug-in units in the same cartridge so the termination resistors of this PCM line are not in AS7-C. The interface logic (AS7CL-FPGA) multiplex/demultiplex a 4,096 Mbit/s serial line to two 2,048 Mbit/s PCM lines connected to the HDLC controller. The PCM line interfaces are duplicated. The AS7-C transmits on both sides of the PCM lines and it receives data from the side selected by the change over signal. If the change over signal is set low then PCM lines from the GSW0 are selected in receive direction. Type 75110 transmitter and type 75107 receiver is used in the 4,096 Mbit/s PCM line interfaces. There are 2.2 k pull-ups in the A-line of the differential inputs of PCM line receivers.

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In the PCM lines, which are directly connected to the GWS, there are 68 pull-down termination resistors in the differential inputs/outputs of PCM line receivers/transmitters. Other signals The following signal are connected to the P5 back connector:
.

output interrupt signal AS7_INT0 driven by the AS7CL-FPGA output interrupt signal AS7_INT1 driven by the AS7CL-FPGA the alarm signal and the alarm test signal (_AL, ALTEST), ALTEST with 100 k pull down, 10 k serial resistor, 100 pF capacitor to ground + schmitt trigger , _AL with MBT3904 + 68 ohm resistor.

Power Feed AS7-C gets its +5V, -5V and +3.3V power feed from the back plane. All other voltages need to be generated within the unit. V(I/O) pins are used for 3,3V supply. These pins are connected to the 3.3V PWB layer on the back plane. The +5V and +3.3V supplies are controlled by a power control unit. This provides the following capabilities for the AS7-C:
.

overcurrent protection power up ramping and inrush current limitation check for threshold value to reset the unit if supply voltages are too low.

The lack of -5V power is read from the I/O bridge status register. The AS7-C may be unpowered due to a failure on the unit power supply controller or a short circuit on the unit. However, even an unpowered AS7 C does not prevent CompactPCI bus transactions between host CPU and other peripheral units as the embedded PCI/PCI Bridge is powered directly (via fuse) from the back plane supply voltages. The embedded PCI/PCI Bridge resets if the AS7-C internal supply voltages are off. The embedded PCI/PCI Bridge tri-states its buses if the primary reset input is asserted. This ensures that the CompactPCI bus is not disturbed by AS7-C in this situation. The power up order of +5V and 3.3V of the cartridge power supply unit is not specified.

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Operation of AS7-C

Operation of AS7-C
Front panel The AS7-C plug-in unit has two software-controlled LED indicators (red and yellow) on its front panel. The red LED indicator is lit when the plug-in unit is in start state; otherwise the LED indicators are software-controlled, as indicated in the table below. The size of the front panel is 20 x 262 mm. The front panel of the AS7C looks like this:

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AP

DN03275434

Figure 4.

AS7-C front panel.

Table 3. LED

AS7-C front panel LED indicators Colour

Red

Function
The LED is turned on after power-up and when processor reset is activated. The LED is turned off after power-up and when processor reset is activated.

AP

Yellow

Back plane connectors The back plane has the following connectors:

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P5 type: B(22), female 2mm Hard Metric connector, unshielded P4 type: A(22), female 2mm Hard Metric connector, shielded P1 type: A(22), female 2mm Hard Metric connector, shielded

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AS7-C

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Power consumption of AS7-C

AS7-C gets +3.3 V, +5 V and -5 V supply voltages through its back plane connectors.

Table 4. State
Idle

Power Consumption of AS7-C +3.3

8,98W

+5 V
2,75W 5,61W 5,87W

5 V
1,02W 1,02W 0,87W

Total
12,75W 18,02W 16,46W

Memory test 11,39W Boot up 9,72W

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AS7-C C105007

6
J2

AS7-C C105007

SW1 P5

P4

SW1 OFF ON 1 2 3 4 5 6 12 11 10 9 8 7

P1
DN03309124

Figure 5.

DIP switches of the plug-in unit AS7-C

Altera Bit Blaster header J2 The J2 (Altera Bit Blaster) pin header is used for reprogramming the Altera CPLD. No jumpers are installed.

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AS7-C

Interchangeability code settings The Interchangeability Switch Block consists of a 6position DIP switch. This switch contains the four interchangeability code bits. The interchangeability lines drive to '0' when the switches are OFF.

Note
'OFF' is GND, 'ON' is VCC.

Table 5. Switch 1
1-12 2-11 3-10 4-9 5-8 6-7

SW1 switch settings. Setting

OFF*) OFF*) OFF*) OFF*) OFF OFF

Meaning
Interchangeability code bit 3 (MSB) Interchangeability code bit 2 Interchangeability code bit 1 Interchangeability code bit 0 (LSB) Not in use Not in use.

*) The first interchangeability code A corresponds to all switches OFF, after which the settings start to roll for each interchangeability code change. The table below presents the setting of the interchangeability code.

Table 6. ICC code Meaning

SW 1: 112 (MSB) A B C D E F OFF OFF OFF OFF OFF OFF

Interchangeability code settings of AS7-C

SW 1: 211 OFF OFF OFF OFF ON ON

SW 1: 310 OFF OFF ON ON OFF OFF

SW 1: 49 (LSB) OFF ON OFF ON OFF ON

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Table 6. ICC code

G H J K L M N P R

Interchangeability code settings of AS7-C (cont.)

Meaning
OFF OFF ON ON ON ON ON ON ON ON ON OFF OFF OFF OFF ON ON ON ON ON OFF OFF ON ON OFF OFF ON OFF ON OFF ON OFF ON OFF ON OFF

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AS7-C

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Connector maps of AS7-C

Connector maps of AS7-C

P5 connector Connector P5 type: B(22), female 2mm Hard Metric connector, unshielded.

Table 7. CPCI ROW NUMBERS

1 2 3 4 5 PCM to/ from GSW0 PCM to/ from GSW1 6 GND GND GND GND GND GND

P5 connector

+5V +5V -5V 8M0B CGSB R04B

+5V +5V -5V 8M0A CGSA R04A

+5V +5V -5V

+5V +5V -5V 8k0B _AS7_IN T1 T04B

+5V +5V -5V 8k0A _AS7_IN T0 T04A

GND GND GND GND GND GND

GND

R14B

R04A

T14B

T14A

GND

8 9 Direct PCMs to/ from GSW0 10 11 12 13 14 15 16 17

GND GND GND GND GND GND GND GND GND GND

_AL

ALTST

GND GND

DR00B DR01B DR02B DR03B

DR00A DR01A DR02A DR03A

DT00B DT01B DT02B DT03B

DT00A DT01A DT02A DT03A

GND GND GND GND GND GND GND GND

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AS7-C

Table 7. CPCI ROW NUMBERS

18 19 20 21 22 GND GND GND GND GND F

P5 connector (cont.)

GND GND GND GND GND E D C B A Z

P4 connector Connector P4 type: A(22), female 2mm Hard Metric connector, shielded

Table 8. CPCI ROW NUMBERS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND GND GND GND GND GND GND GND GND GND GND GND GND GND

P4 connector

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

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Connector maps of AS7-C

Table 8. CPCI ROW NUMBERS

Direct PCMs to/ from GSW1 15 16 17 18 19 20 21 22 RS232 for 23 UART0 RS232 for 24 UART1 25 GND GND GND GND GND GND GND GND GND GND GND F

P4 connector (cont.)

DR10B DR11B DR12B DR13B

DR10A DR11A DR12A DR13A

DT10B DT11B DT12B DT13B

DT10A DT11A DT12A DT13A

GND GND GND GND GND GND GND GND

TxD0 TxD1

GND* GND*

GND* GND*

RxD0 RxD1

GND GND GND

Note
GND-signals marked as GND* are connected to ground only in AS7-C plug-in unit (not back plane).

P1 connector Connector P1 type: A(22), female 2mm Hard Metric connector, shielded.

Table 9. CPCI ROW NUMBERS

1 2 3 4 5 GND GND GND GND GND 5V _ACK64 AD[2] AD[5] C/_BE[0]

P1 connector

3.3V AD[0] 5V AD[6] M66EN

_ENUM V(I/O) AD[3] 3.3V AD[8]

_REQ64 5V AD[4] GND AD[9]

5V AD[1] 3.3V AD[7] 3.3V

GND GND GND GND GND

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AS7-C

Table 9. CPCI ROW NUMBERS

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND F C/_BE[2] AD[19] AD[22] AD[24] AD[27] AD[31] _GNT INTS _INTD TDI 5V E AD[10] AD[13] C/_BE[1] _PERR _LOCK _TRDY

P1 connector (cont.)

AD[11] GND PAR GND _STOP GND

V(I/O) AD[14] 3.3V _SBO V(I/O) _IRDY CODING AREA

GND AD[15] GND SDONE GND _FRAME

AD[12] 3.3V _SERR 3.3V

GND GND GND GND

_DEVSEL GND 3.3V GND GND GND GND

GND AD[20] GND AD[25] GND CLK0 GND INTP 5V TDO +12V D

AD[16] 3.3V AD[23] V(I/O) AD[28] 3.3V _RST V(I/O) _INTC TMS _TRST C

AD[17] GND IDSEL GND AD[29] GND BRSV2 GND _INTB 5V -12V B

AD[18] AD[21] C/_BE[3] AD[26] AD[30] _REQ BRSV1 BRSV0 _INTA TCK 5V A

GND GND GND GND GND GND GND GND GND GND GND Z

Note
+12V and -12V are not used in the cartridge. These pins are unused. CompactPCI Bus signals V(I/O) are used for 3.3V voltage supply. They are not to be used as the supply voltage pins for the CompactPCI Bus signal interface.

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