Valid Chips KEY The numbers of chips that are identical in function for this lab appear here.

Truth Table

Pin Diagram

The Truth Table for the Gate(s) on the chip appears here.

A diagram of the chip appears here.

Pin Type (Gate Number & Gate In/Output Identification) Chip Pin Number

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 3A 3B 3Y 4A 4B 4Y

Gate Diagrams

7400 Quadruple 2-Input NAND Gates N7400N N74H00N Input N74S00N N74LS00N A N7400F N74H00F L L N74S00F N74LS00F
H H

Input B L H L H

Output Y H H H L

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 3A 3B 3Y 4A 4B 4Y

7402 Quadruple 2-Input NOR Gates N7402N N74S02N N74LS02N N7402F N74S02F N74LS02F

Input A L L H H

Input B L H L H

Output Y H L L L

1Y 1B 1A 2Y 2B 2A GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 3Y 3B 3A 4Y 4B 4A

7404 Six Inverters N7404N N74H04N N74S04N N74LS04N N7404F N74H04F N74S04F N74LS04F

Input A L H

Output Y H L

1A 1Y 2A 2Y 3A 3Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 6A 6Y 5A 5Y 4A 4Y

2/20/02EI

Valid Chips 7408 Quadruple 2-Input AND Gates N7408N N74H08N N74S08N N74LS08N N7408F N74H08F N74S08F N74LS08F

Truth Table

Pin Diagram

Input A L L H H

Input B L H L H

Output Y L L L H

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 3A 3B 3Y 4A 4B 4Y

7410 Triple 3-Input NAND Gates N7410N N74H10N N74S10N N74LS10N N7410F N74H10F N74S10F N74LS10F

Input A L L L L H H H H

Input B L L H H L L H H

Input C L H L H L H L H

Output Y H H H H H H H L

1A 1B 2A 2B 2C 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 1C 1Y 3A 3B 3C 3Y

7411 Triple 3-Input AND Gates N7411N N74H11N N74S11N N74LS11N N7411F N74H11F N74S11F N74LS11F

Input A L L L L H H H H

Input B L L H H L L H H

Input C L H L H L H L H

Output Y L L L L L L L H

1A 1B 2A 2B 2C 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 1C 1Y 3A 3B 3C 3Y

7420 Double 4-Input NAND Gates N7420N N74H20N Input N74S20N N74LS20N A N7420F N74H20F L L N74S20F N74LS20F L
L L L L L H H H H H H H H

Input B L L L L H H H H L L L L H H H H

Input C L L H H L L H H L L H H L L H H

Input D L H L H L H L H L H L H L H L H

Output Y H H H H H H H H H H H H H H H L

1A 1B 1C 1D 1Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 2A 2B 2C 2D 2Y

2/20/02EI

Valid Chips 7421 Double 4-Input AND Gates N7421N N74H21N Input N74LS21N A N7421F N74H21F L L N74LS21F
L L L L L L H H H H H H H H

Truth Table

Pin Diagram

Input B L L L L H H H H L L L L H H H H

Input C L L H H L L H H L L H H L L H H

Input D L H L H L H L H L H L H L H L H

Output Y L L L L L L L L L L L L L L L H

1A 1B 1C 1D 1Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 2A 2B 2C 2D 2Y

7425 Double 4-Input NOR Gates w/Enable N7425N Input Input Input N7425F A B C
L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H

Input D L H L H L H L H L H L H L H L H

Output Y H L L L L L L L L L L L L L L L

1A 1B 1En 2C 1D 1Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 2A 2B 2En 2C 2D 2Y

7427 Triple 3-Input NOR Gates N7427N N74LS27N N7427F N74LS27F

Input A L L L L H H H H

Input B L L H H L L H H

Input C L H L H L H L H

Output Y H L L L L L L L

1A 1B 2A 2B 2C 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 1C 1Y 3A 3B 3C 3Y

2/20/02EI

Valid Chips

Truth Table

Pin Diagram

7430 8-Input NAND Gate N7430N Input Input Input Input Input Input N74H30N A B C D E F N74LS30N H H H H H H All Other Cases N7430F N74H30F N74LS30F

Input Input Output G H Y H H L H

1A 1B 1C 1D 1E 1F GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 1G 1H

1Y

7432 Quadruple 2-Input OR Gates N7432N N74H32N N74S32N N74LS32N N7432F N74H32F N74S32F N74LS32F

Input A L L H H

Input B L H L H

Output Y L H H H

1A 1B 1Y 2A 2B 2Y GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

Vcc 3A 3B 3Y 4A 4B 4Y

7473 Dual JK Master-Slave Flip-Flop N7473N N74H73N Input Input N74LS73N N7473F J K N74H73F N74LS73F X X

Clear Output Q(t+1) 0 0 0 0 1 Q(t) 0 1 1 0 1 0 1 1 1 1 1 Q(t) Q(t) Input Input Output J K Q(t+1) 0 0 X 0 0 1 X 1 1 X 1 0 1 X 0 1 X = Dont Cares

Output Q(t+1) 1 Q(t) 1 0 Q(t) Output Q(t+1) 1 0 1 0

1CP 1R 1K Vcc 2CP 2R 2J

1 2 3 4 5 6 7

J Q >CP K Q R ^

K Q >CP J Q R ^

14 13 12 11 10 9 8

1J 1Q 1Q GND 2K 2Q 2Q

Note: In order for this flip-flop to work, clock should start low, transition to high, and then back to low while all inputs remain the same. 7483 4-Bit Full Adder N7483N N74LS83N N7483F N74LS83F

Carry Input Input Output Output Ci Ai Bi Ci+1 i 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 i=0 through 3

A4 3 A3 B3 Vcc 2 B2 A2

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

B4 4 Cout Cin GND B1 A1 1

Note:
2/20/02EI

Cin should be set to

Valid Chips

Truth Table low when no carry in is intended and 1 when subtracting.

Pin Diagram

74107 Dual JK Master-Slave Flip-Flop N74107N N74LS107N Input Input N74107F N74LS107F

Clear J K X X 0 0 0 1 0 1 1 1 0 1 1 1 1 Q(t) Input Input J K 0 0 X 0 1 X 1 X 1 1 X 0 X = Dont

Output Q(t+1) 0 Q(t) 0 1 Q(t) Output Q(t+1) 0 1 0 1 Cares

Output Q(t+1) 1 Q(t) 1 0 Q(t) Output Q(t+1) 1 0 1 0

1J 1Q 1Q 1K 2Q 2Q GND

1 2 3 4 5 6 7

14 13 12 11 10 9 8

VCC 1R 1CP 2K 2R 2CP 2J

Note: In order for this flip-flop to work, clock should start low, transition to high, and then back to low while all inputs remain the same. 74138 3X8 Decoder N74138N N74LS138N N74138F N74LS138F

J >CP K R ^

Q Q

Input S0 S1 S2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

Y0 0 1 1 1 1 1 1 1

Y1 1 0 1 1 1 1 1 1

Y2 1 1 0 1 1 1 1 1

Output Y3 Y4 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1

Y5 1 1 1 1 1 0 1 1

Y6 1 1 1 1 1 1 0 1

Y7 1 1 1 1 1 1 1 0

S0 S1 S2 E1 E2 E3 Y7 GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

Vcc Y0 Y1 Y2 Y3 Y4 Y5 Y6

Note: E1 & E2 are active low enable. E3 is active high enable

I n p u t s

3x8 Y0 Decoder Y1 Y2 S0 Y3 S1 Y4 S2 Y5 Y6 E1 E2 E3 Y7

O u t p u t s

2/20/02EI

Valid Chips

Truth Table

Pin Diagram

74148 3X8 Encoder N74148N N74148F

Output Y0 Y1 Y2 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 I0 0 1 1 1 1 1 1 1 I1 1 0 1 1 1 1 1 1 I2 1 1 0 1 1 1 1 1 Input I3 I4 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 I5 1 1 1 1 1 0 1 1 I6 1 1 1 1 1 1 0 1 I7 1 1 1 1 1 1 1 0

I4 I5 I6 I7 EI Y2 Y1 GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

Vcc E0 GS I3 I2 I1 I0 Y0

Note: EI is active low enable. GS and EO are not used in this lab.

I n p u t s

I0 8x3 I1 Encoder I2 I3 Y0 I4 Y1 I5 Y2 I6 I7 EI

O u t

74151 8-Input Multiplexer N74151N Select N74S151N S0 S1 S2 N74LS151N 0 0 0 N74151F 0 0 0 0 0 1 N74S151F 0 0 1 N74LS151F 0 1 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1

I0 0 1 X X X X X X X X X X X X X X

I1 X X 0 1 X X X X X X X X X X X X

Input I2 I3 I4 I5 X X X X X X X X X X X X X X X X 0 X X X 1 X X X X 0 X X X 1 X X X X 0 X X X 1 X X X X 0 X X X 1 X X X X X X X X X X X X X X X X X = Dont Cares

I6 X X X X X X X X X X X X 0 1 X X

I7 X X X X X X X X X X X X X X 0 1

Output Y Y 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

I3 I2 I1 I0 Y Y E GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

Vcc I4 I5 I6 I7 S0 S1 S2

Note:

E is active low enable.

I0 8 Input I1 Mux I2 I3 I4 Y I5 Y I6 I7 S2 S1 S0

74153 Dual 4-Input Multiplexer N74153N N74S153N Select N74LS153N N74153F S0 S1 E N74S153F X X 1 N74LS153F 0 0 0
0 0 0 1 1 1 1 2/20/02EI 0 1 1 0 0 1 1 0 0 0 0 0 0 0

I0 X 0 1 X X X X X X

Input I1 I2 X X X X X X 0 X 1 X X 0 X 1 X X X X

I4 X X X X X X X 0 1

Output Y 0 0 1 0 1 0 1 0 1

AE S1 AI3 AI2 AI1 AI0 AY GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

Vcc BE SO BI3 BI2 BI1 BI0 BY

Valid Chips Note:

Truth Table
X = Dont Cares

Pin Diagram

E is active low enable.

AI0 AI1 AI2 AI3

AE AY

S0 2x4 Input S1 Mux BI0 BI1 BI2 BI3 BY BE

2/20/02EI