Memorijski Sustavi

SEMICONDUCTOR MEMORIES
Digital Integrated Circuits
Memory
Prentice Hall 1995
Chapter Overview
Memory Classification Memory Architectures The Memory Core Periphery Reliability
Memory
Prentice Hall 1995
Semiconductor Memory Classification

RWM NVRWM ROM
Random Access
Non-Random Access FIFO LIFO Shift Register CAM
EPROM E2PROM FLASH
Mask-Programmed Programmable (PROM)
SRAM DRAM
Memory
Prentice Hall 1995
Memory Architecture: Decoders

M bits S0 S1 S2 N Words S0 Word 0 Word 1 Word 2 Storage Cell A0 A1 A K-1 Word N-2 Word N-1 Decoder Word 0 Word 1 Word 2 Storage Cell M bits
SN-2 SN_1
Word N-2 Word N-1
Input-Output (M bits)
Input-Output (M bits)
N words => N select signals Too many select signals

Digital Integrated Circuits Memory
Decoder reduces # of select signals K = log2N

Prentice Hall 1995
Array-Structured Memory Architecture

Problem: ASPECT RATIO or HEIGHT >> WIDTH
2 AK AK+1 AL-1
L-K
Bit Line Storage Cell
Row Decoder
Word Line
M.2 Sense Amplifiers / Drivers A0 A K-1 Input-Output (M bits)

Amplify swing to rail-to-rail amplitude Selects appropriate word
Column Decoder
Prentice Hall 1995
Hierarchical Memory Architecture

Row Address Column Address Block Address
Global Data Bus Control Circuitry Block Selector Global Amplifier/Driver I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings
Digital Integrated Circuits Memory Prentice Hall 1995
Memory Timing: Definitions

Read Cycle READ Read Access WRITE Write Access Data Valid DATA Data Written Read Access Write Cycle
Memory
Prentice Hall 1995
Memory Timing: Approaches

MSB LSB
Address Bus RAS
Row Address Colum n Address Address Bus
Address Address transition initiates memory operation
CAS
RAS-CAS timing
DRAM Timing Multiplexed Adressing

SRAM Timing Self-timed

Prentice Hall 1995
MOS NOR ROM

VDD Pull-up devices WL[0] GND WL[1]
WL[2] GND WL[3]
BL[0]
BL[1]
Memory
BL[2]
BL[3]
Prentice Hall 1995
MOS NOR ROM Layout

Metal1 on top of diffusion WL[0] GND (diffusion) WL[1] Polysilicon Basic cell 10 x 7 WL[2] WL[3] Metal1 2
Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps
MOS NOR ROM Layout

BL[0] BL[1] BL[2] BL[3] Threshold raising implant WL[0] Basic Cell 8.5 x 7 WL[1] Polysilicon WL[2] GND (diffusion) Metal1 over diffusion
WL[3]
Threshold raising implants disable transistors

MOS NAND ROM

VDD Pull-up devices BL[0] WL[0] BL [1] BL[2] BL[3]
WL[1]
WL[2]
WL[3]
All word lines high by default with exception of selected row

MOS NAND ROM Layout

Diffusion Polysilicon Basic cell 5 x 6
Threshold lowering implant
No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM
Equivalent Transient Model for MOS NOR ROM

VDD
Model for NOR ROM
WL cword
rword
BL Cbit
Word line parasitics Resistance/cell: (7/2) x 10 /q = 35 Wire capacitance/cell: (7 2) (0.6)2 0.058 + 2 (7 0.6) 0.043 = 0.65 fF Gate Capacitance/cell: (4 2) (0.6)2 1.76 = 5.1 fF. Bit line parasitics: Resistance/cell: (8.5/4) x 0.07 /q = 0.15 (which is negligible) Wire capacitance/cell: (8.5 4) (0.6)2 0.031 + 2 (8.5 0.6) 0.044 = 0.83 fF Drain capacitance/cell: ((3 4) (0.6)2 0.3 + 2 3 0.6 0.8) 0.375 + 4 0.6 0.43 = 2.6 fF
Memory
Prentice Hall 1995
Equivalent Transient Model for MOS NAND ROM

VDD BL CL rbit
Model for NAND ROM

WL cword
Word line parasitics: Resistance/cell: (6/2) x 10 /q = 30 Wire capacitance/cell: (6 2) (0.6)2 0.058 + 2 (6 0.6) 0.043 = 0.56 fF Gate Capacitance/cell: (3 2) (0.6)2 1.76 = 3.8 fF. Bit line parasitics: Resistance/cell: 10 k , the average transistor resistance over the range of interest. Wire capacitance/cell: Included in diffusion capacitance Source/Drain capacitance/cell: ((33 ) (0.6)2 0.3 + 2 3 0.6 0.8) 0.375 + ( 3 2) (0.6)2 1.76 = 5.2 fF
rword
cbit
Memory
Prentice Hall 1995
Propagation Delay of NOR ROM

Word line delay Consider the 512512 case. The delay of the distributed rc-line containing M cells can be approximated using the expressions derived in Chapter 8.
2 2 tword = 0.38 (rword cword ) M = 0.38 (35 (0.65 + 5.1) fF) 512 = 20 nsec
Bit line delay Assume a (2.4/1.2) pull-down device and a (8/1.2) pull-up transistor. The bit line switches between 5 V and 2.5 V. Cbit = 512 (2.6 + 0.8) fF = 1.7 pF IavHL = 1/2 (2.4/0.9) (19.6 10 -6)((4.25)2/2 + (4.25 3.75 - (3.75) 2/2)) 1/2 (8/0.9) (5.3 10-6 ) (4.25 1.25 - (1.25)2/2) = 0.36 mA tHL = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec The low-to-high response time can be computed using a similar approach. tLH = (1.7 pF 1.25 V) / 0.36 mA = 5.9 nsec
Decreasing Word Line Delay

Driver WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides

Metal bypass
WL
K cells
Polysilicon word line
(b) Using a metal bypass (c) Use silicides

Precharged MOS NOR ROM

pre VDD Precharge devices WL[0] GND WL[1]
WL[2] GND WL[3]
BL[0] BL[1]
BL[2] BL[3]
PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.
Floating-gate transistor (FAMOS)

Floating gate Source tox tox n
+ p
Gate D Drain
Substrate
(a) Device cross-section

(b) Schematic symbol

Prentice Hall 1995
Floating-Gate Transistor Programming

20 V 0V 5V
10 V 5 V S
20 V
5V S
0V
2.5 V S
5V
Avalanche injection.
Removing programming voltage leaves charge trapped.
Programming results in higher V T.
Memory
Prentice Hall 1995
FLOTOX EEPROM
Floating gate Source 20-30 nm n+ n+ 10 nm Gate Drain 10 V 10 V Substrate p VGD I
(a) Flotox transistor
(b) Fowler-Nordheim I-V characteristic

BL
WL
VDD
(c) EEPROM cell during a read operation

Flash EEPROM
Control gate Floating gate
erasure n+ source
Thin tunneling oxide n+ drain
programming p-substrate
Memory
Prentice Hall 1995
Cross-sections of NVM cells
Flash
Courtesy Intel
Memory
EPROM
Prentice Hall 1995
Characteristics of State-of-the-art NVM
Memory
Prentice Hall 1995
Read-Write Memories (RAM)

STATIC (SRAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential
DYNAMIC (DRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
6-transistor CMOS SRAM Cell

WL VDD M2 M4 Q Q M5 M6
M1
M3
BL
BL
Memory
Prentice Hall 1995
CMOS SRAM Analysis (Write)

WL VDD M4 Q=0 M5 M1 VDD BL = 1 BL = 0 Q=1 M6
kn
,M6 (
DD
2 2 VDD VDD VDD VDD VTn )----------- ----------- = k p M4 VDD VTp )----------- ----------- ( , 2 2 8 8
(W/L)n,M6 0.33 (W/L)p,M4 (W/L)n,M5 10 (W/L)n,M1

Prentice Hall 1995
k n M5 V VDD 2 V DD V 2 , DD DD ------------------------- VTn ----------- = k n M1 ( VDD VTn )----------- ----------, 2 2 2 2 8
Memory
CMOS SRAM Analysis (Read)

WL VDD BL Q=0 M5 M1 Q=1 M4 M6 BL
VDD Cbit
V DD
VDD C bit
2 VDD V DD k n,M5 VDD V DD 2 ----------- V ------------ = k ( V --------------Tn 2 n,M1 DD V Tn )----------- ------------ 2 2 2 8
(W/L)n,M5 10 (W/L)n,M1
(supercedes read constraint)

Memory Prentice Hall 1995
6T-SRAM Layout
VDD
M2 M4
Q
M1 M3
GND
M5 M6
WL
BL
BL
Prentice Hall 1995
Resistance-load SRAM Cell

WL VDD RL Q M3 BL M1 M2 RL Q M4 BL
Static power dissipation -- Want RL large Bit lines precharged to VDD to address t p problem
3-Transistor DRAM Cell

BL1 WWL BL2 WWL RWL RWL X M1 CS BL2 VDD -VT V M2 BL1 M3 X VDD VDD -VT
No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = VWWL -VTn
3T-DRAM Layout
BL2 BL1 GND
RWL
M3 M2
WWL
M1
Memory
Prentice Hall 1995
1-Transistor DRAM Cell

BL WL WL M1 CS X
GND Write "1" Read "1"
VDD VT VDD
BL CBL VDD /2
sensing
VDD /2
Write: CS is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance
CS V = VBL V PRE = ( V BIT V PRE )-----------------------C S + CBL
Voltage swing is small; typically around 250 mV.

DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD .
1-T DRAM Cell

Capacitor Metal word line
SiO2 poly n+ poly n+

Inversion layer induced by plate bias Field Oxide Diffused bit line
M1 word line
(a) Cross-section
Polysilicon Polysilicon plate gate
(b) Layout
Used Polysilicon-Diffusion Capacitance Expensive in Area

SEM of poly-diffusion capacitor 1T-DRAM
Memory
Prentice Hall 1995
Advanced 1T DRAM Cells

Word line Insulating Layer Cell plate Capacitor dielectric layer
Cell Plate Si
Transfer gate Isolation Storage electrode
Capacitor Insulator
Refilling Poly
Storage Node Poly Si Substrate 2nd Field Oxide
Trench Cell
Stacked-capacitor Cell
Prentice Hall 1995
Periphery
Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry
Row Decoders
Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder
NOR Decoder
Memory
Prentice Hall 1995
Dynamic Decoders
Precharge devices GND GND VDD WL3 WL3 VDD WL2
WL2 WL1 WL0
VDD
VDD
WL1
WL0
V DD
A0
A0
A1
A1
A0
A0
A1
A1
Dynamic 2-to-4 NOR decoder
2-to-4 MOS dynamic NAND Decoder
Propagation delay is primary concern

A NAND decoder using 2-input predecoders

WL 1
WL 0
A0A1 A0 A1 A0A1 A0A 1
A 2A3 A2 A3 A2A3 A2A3
A1 A 0
A0
A1
A3 A2
A2
A3
Splitting decoder into two or more logic layers produces a faster and cheaper implementation
4 input pass-transistor based column decoder

BL 0 S0 S1 S2 S3 BL1 BL 2 BL3
A0
A1
2 input NOR decoder
Advantage: speed (t pd does not add to overall memory access time) only 1 extra transistor in signal path Disadvantage: large transistor count
4-to-1 tree based column decoder

BL0 A0 A0 A1 A1 BL 1 BL2 BL 3
D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches
Decoder for circular shift-register

VDD WL0 R VDD R VDD WL 1 R VDD VDD WL 2 ... VDD VDD
Memory
Prentice Hall 1995
Sense Amplifiers
t C V = ---------------p I av large make V as small as possible
small
Idea: Use Sense Amplifer small transition input

s.a. output
Prentice Hall 1995
Differential Sensing - SRAM

VDD VDD PC VDD x SE WLi y M3 M1 BL M4 M2 M5 x x SE VDD y x
BL
EQ
(b) Doubled-ended Current Mirror Amplifier VDD SRAM cell i y Diff. Sense x x Amp y y D D x SE y x
(a) SRAM sensing scheme.

(c) Cross-Coupled Amplifier

Prentice Hall 1995
Latch-Based Sense Amplifier

EQ BL VDD SE BL
SE
Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
Single-to-Differential Conversion
WL BL x Diff. S.A. x
+ _
cell
Vref
How to make good V ref?

Open bitline architecture

EQ R L1 L0 VDD SE BLL BLR R0 R1 L
CS
... CS
CS
SE
CS
... CS
CS
dummy cell
dummy cell
Memory
Prentice Hall 1995
DRAM Read Process with Dummy Cell

6.0 4.0 BL 2.0 0.00 BL 5.0 V (Volt) 1 2 3 t (nsec) (a) reading a zero 4 5 4.0 3.0 2.0 1.0 0.00 V (Volt) 4.0 BL BL 1 2 3 t (nsec) 4 5 2.0 1 2 3 4 (c) control signals 5 EQ WL SE
V (Volt)
6.0
0.00
(b) reading a one

Single-Ended Cascode Amplifier

VDD
Vcasc
WLC
WL
Memory
Prentice Hall 1995
DRAM Timing
Memory
Prentice Hall 1995
Address Transition Detection

VDD
A0
DELAY td
ATD
ATD
A1
DELAY td
... AN-1 DELAY td
Memory
Prentice Hall 1995
Reliability and Yield
Memory
Prentice Hall 1995
Open Bit-line Architecture Cross Coupling

EQ
WL1 BL CBL C
WL0 WL D CWBL
CWBL
WLD
WL 0
WL1 BL
Sense C C Amplifier C C C
CBL
Memory
Prentice Hall 1995
Folded-Bitline Architecture
WL1 BL ... CBL
WL1
WL0 WL0 CWBL
WLD
WL D y Sense C EQ Amplifier x y
x C C
BL
CBL CWBL
Memory
Prentice Hall 1995
Transposed-Bitline Architecture
BL BL BL BL" (a) Straightforward bitline routing. BL BL BL BL" (b) Transposed bitline architecture.
Ccross SA
Ccross SA
Alpha-particles
-particle WL BL n+ SiO2
VDD
1 particle ~ 1 million carriers

Yield
Yield curves at different stages of process maturity (from [Veendrick92])

Redundancy
Row Address Redundant rows : Redundant columns Memory Array Row Decoder Fuse Bank
Column Decoder
Column Address
Prentice Hall 1995
Memory
Redundancy and Error Correction
Memory
Prentice Hall 1995
Programmable Logic Array

Product Terms
AND PLANE
x0x1 x2
OR PLANE
f0 x0 x1 x2
f1
Memory
Prentice Hall 1995
Pseudo-Static PLA
GND GND GND GND VDD GND
GND
GND
VDD
x0
x0
x1
x1
x2
x2
f0
f1
AND-PLANE
OR-PLANE
Prentice Hall 1995
Dynamic PLA
AND GND VDD OR
AND V DD x0 x0 x1 x1 x2 x2
OR f0 f1 GND
AND-PLANE
OR-PLANE
Prentice Hall 1995
Clock Signal Generation for self-timed dynamic PLA

Dummy AND Row
AND
AND AND
Dummy AND Row
OR
OR
(a) Clock signals

(b) Timing generation circuitry.

Memory Prentice Hall 1995
PLA Layout
VDD And-Plane Or-Plane GND
x0 x0 x1 x1 x2 x2 Pull-up devices
Memory
f0 f1 Pull-up devices
Prentice Hall 1995
PLA versus ROM

Programmable Logic Array structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO ROM! Main difference ROM: fully populated PLA: one element per minterm Note: Importance of PLA has drastically reduced s 1. slow 2. better software techniques (mutli-level logic synthesis)
Semiconductor Memory Trends
Memory Size as a function of time: x 4 every three years

Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation
Memory
Prentice Hall 1995
Technology feature size for different SRAM generations
Memory
Prentice Hall 1995

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SEMICONDUCTOR MEMORIES

Digital Integrated Circuits

Prentice Hall 1995

Digital Integrated Circuits

Prentice Hall 1995

Semiconductor Memory Classification

Non-Random Access FIFO LIFO Shift Register CAM

EPROM E2PROM FLASH

Mask-Programmed Programmable (PROM)

Digital Integrated Circuits

Prentice Hall 1995

Memory Architecture: Decoders

Word N-2 Word N-1

N words => N select signals Too many select signals

Decoder reduces # of select signals K = log2N

Array-Structured Memory Architecture

Bit Line Storage Cell

M.2 Sense Amplifiers / Drivers A0 A K-1 Input-Output (M bits)

Amplify swing to rail-to-rail amplitude Selects appropriate word

Prentice Hall 1995

Hierarchical Memory Architecture

Memory Timing: Definitions

Digital Integrated Circuits

Prentice Hall 1995

Memory Timing: Approaches

Address Bus RAS

Row Address Colum n Address Address Bus

Address Address transition initiates memory operation

DRAM Timing Multiplexed Adressing

SRAM Timing Self-timed

MOS NOR ROM

WL[2] GND WL[3]

MOS NOR ROM Layout

MOS NOR ROM Layout

Threshold raising implants disable transistors

MOS NAND ROM

All word lines high by default with exception of selected row

MOS NAND ROM Layout

Threshold lowering implant

Equivalent Transient Model for MOS NOR ROM

Model for NOR ROM

Digital Integrated Circuits

Prentice Hall 1995

Equivalent Transient Model for MOS NAND ROM

Model for NAND ROM

Digital Integrated Circuits

Prentice Hall 1995

Propagation Delay of NOR ROM

Decreasing Word Line Delay

Metal word line

(a) Driving the word line from both sides

Polysilicon word line

(b) Using a metal bypass (c) Use silicides

Precharged MOS NOR ROM

WL[2] GND WL[3]

Floating-gate transistor (FAMOS)

(a) Device cross-section

(b) Schematic symbol

Floating-Gate Transistor Programming

Removing programming voltage leaves charge trapped.

Programming results in higher V T.

Digital Integrated Circuits