A PRACTICAL IMPLEMENTATION OF ACMC BUCK CONVERTER

BASED ON UC3825











LIM ZONG ZHENG











UNIVERSITI TEKNOLOGI MALAYSIA














Replace this page with form PSZ 19:16 (Pind. 1/07), which can be
obtained from SPS or your faculty.




























I hereby declare that I have read this report and in
my opinion this report is sufficient in terms of scope and
quality for the award of the degree of Bachelor of Electrical Engineering




Signature :
Supervisor : MR. NIK DIN MUHAMAD ,
Date : 23

APRIL 2010 ,







i

A PRACTICAL IMPLEMENTATION OF ACMC BUCK CONVERTER
BASED ON UC3825






LIM ZONG ZHENG






A report submitted in fulfillment of the
requirement for the award of the degree of
Bachelor of Electrical Engineering


Faculty of Electrical Engineering
Universiti Teknologi Malaysia


APRIL 2010


ii

I declare that this report entitled A Practical Implementation of ACMC Buck Converter
Based on UC3825 is the result of my own research except as cited in the references.
The report has not been accepted for any degree and is not concurrently submitted in
candidature of any other degree.




Signature :
Supervisor : LIM ZONG ZHENG ,
Date : April 23, 2010 ,












iii

To my beloved family.

iv

ACKNOWLEDGEMENT




I wish to express my sincere appreciations to my project supervisor, Mr. Nik
Din Muhamad, for his enthusiasm, patience, wisdom, guidance, critics and motivation.
Without his continued support and interest, this project paper would not have been the
same as presented here.


In completing this project paper, I was in contact with many people in Power
Electronics Lab, UTM. They have contributed towards my understanding and thoughts,
which are always appreciated.


Finally, a special thanks to my dearest family members for their love, care and
supports throughout these two semesters.










v

ABSTRACT




This report is a description of the project which implements an Average Current
Mode Control (ACMC) Buck Converter that capable in regulating output voltage at 5V
when input voltage varied from 10V to 18V. ACMC is a linear control scheme
implementing the feedback control method to adjust duty ratio to a required value to
provide or sustain output at desired level and ensuring the stability after some
disturbances applied. ACMC is superior among other schemes due to excellent noise
immunity and fast response to compensate changes. Besides, this project is divided into
two, which are software simulation and hardware implementation. For software part, the
ACMC buck converter is designed using PSpice software and verified by applying
disturbances. After this, hardware implementation is partitioned to power stage and
controller stage to reduce project hardness. The ACMC buck converter is
experimentally tested in both open loop and close loop condition to ensure it function
well.










vi

ABSTRAK




Kertas projek ini membincangkan projek yang mengimplimentasikan Average
Current Mode Control (ACMC) Buck Converter yang mampu mengekalkan voltan
keluaran pada 5V apabila voltan masukan diubah daripada 10V ke 18V. ACMC adalah
salah satu skema kawalan linear yang mengimplimentasikan kawalan suapbalik untuk
mengubah duty ratio ke nilai yang dikehendaki untuk mengekalkan keluaran pada tahap
yang diingini dan memastikan kestabilan selepas ganguan dikenakan. ACMC adalah
superior berbanding dengan skema lain disebabkan immunisasi hingar yang cemerlang
and sambutan yang cepat untuk memampas perubahan. Selain itu, projek ini
dibahagikan kepada dua bahagian, iaitu simulasi perisian dan implementasi perkakas.
Untuk bahagian perisian, ACMC buck converter adalah direkabentuk dengan
menggunakan perisian PSpice dan diverifikasikan dengan mengenakan gangguan.
Seterusnya, implementasi perkakas dibahagikan kepada power stage dan controller
stage untuk mengurangkan kesukaran projek ini. Selepas itu, ACMC buck converter
adalah diuji secara eksperimen dalam gelung terbuka dan gelung tertutup untuk
memastikannya berfungsi dengan baik.








vii

TABLE OF CONTENTS




CHAPTER TITLE PAGE

TITLE PAGE i
DECLARATION ii
DEDICATION iii
ACKNOWLEDGEMENT iv
ABSTRACT v
ABSTRAK vi
TABLE OF CONTENT vii
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF ABBREVIATIONS xiii
LIST OF APPENDIX xiv

1 INTRODUCTION 1
1.1 Problem Statement 1
1.2 Project Objective 2
1.3 Scope of Project 2
1.4 Report Outline 3

2 BACKGROUND OF STUDY 5
2.1 Buck Converter 6
2.2 Control Schemes 8
viii

2.2.1 Voltage Mode Control 9

2.2.2 Peak Current Mode Control 11
2.2.3 Average Current Mode Control 13

3 METHODOLOGY 15
3.1 Design Procedures for power stage 15
3.2 Design Procedures for ACMC buck converter 18
3.2.1 Design of inner current loop compensator 20
3.2.2 Design of outer voltage loop compensator 24

4 HARDWARE IMPLEMENTATION 27
4.1 Power Stage 27
4.1.1 Power Switch 28
4.1.2 Power Diode 28
4.1.3 Inductor 29
4.1.4 Output Capacitor 29
4.1.5 Load 29
4.1.6 Input filter 30
4.2 Controller Stage 30
4.2.1 Pulse Width Modulator (PWM) 30
4.2.1.1 Current Loop Compensator 31
4.2.1.2 Switching Frequency 32
4.2.1.3 Soft-start 32
4.2.1.4 PWM Output 32
4.2.2 MOSFET Driver 33
4.2.2.1 Opto-isolator 33
4.2.2.2 Driver Selection 34
4.2.2.3 Configuration of MOSFET Driver 35
4.2.3 Feedback Network 36


ix

5 RESULTS AND ANALYSIS 38

5.1 Procedure 38
5.2 Simulation Result and Discussion 39
5.2.1 Verification through input disturbances 40
5.2.2 Verification through load disturbances 42
5.3 Experimental Result and Discussion 44
5.3.1 Open Loop Laboratory Test 44
5.3.2 Open Loop Test with Power Stage 45
5.3.3 Close Loop Test 46
5.4 Approaches to Bridge Gaps between Theoretical
Principle and Hardware Implementation 49
5.4.1 Current Sense 49
5.4.2 PCB layout of power stage 51

6 CONCLUSION AND RECOMMENDATION 53
6.1 Conclusion 53
6.2 Recommendation 54

REFERENCES 55
Appendices A-D 56 - 66

LIST OF TABLES




TABLE NO. TITLE PAGE

3.1 Specification of buck converter 16
3.2 Converter transfer function for average current mode controller 19



















xi

LIST OF FIGURES




FIGURE NO. TITLE PAGE

2.1 Basic buck converter topology 6
2.2 General circuit of buck converter with voltage-mode control 9
2.3 Waveform of V
ramp
, V
error
and PWM output 10
2.4 General circuit of buck converter with PCMC 11
2.5 Waveform of V
error
, V
Rs
and CA output 12
2.6 General circuit of buck converter with ACMC 13
2.7 Waveform of V
sawtooth
, V
CA
and PWM output 14
3.1 Block diagram of ACMC of DC-DC converters 19
3.2 Current loop compensator 20
3.3 Simulation circuit used to design current loop compensator 21
3.4 Frequency response of system with current loop compensator 22
3.5 Component values in current loop compensator 23
3.6 Simulation circuit used to design voltage loop compensator 24
3.7 Frequency response of system with voltage loop compensator 25
3.8 Component values in voltage loop compensator 26
3.9 Voltage loop compensator 26
4.1 Functional diagram of UC3825 31
4.2 Schematic diagram of configuration for PWM controller UC3825 33
4.3 Schematic diagram of opto-isolator 34
4.4 Schematic diagram of MC34151 driver 35
4.5 Configuration of MOSFET driver 36
xii

4.6 Full schematic diagram of ACMC buck converter 37

5.1 Procedures in hardware implementation 39
5.2 Simulation circuit of buck converter with switch model 40
5.3 Design verification by applying input disturbance 41
5.4 Design verification by applying input disturbance 42
5.5 The designed CA gain is optimum to avoid sub-harmonic
oscillations 43
5.6 Result of open loop laboratory test on UC3825 44
5.7 Result of open loop test with power stage 45
5.8 Waveform of output voltage when input voltage is (a) 10V
(b) 12V (c) 18V 47
5.9 Waveform of voltage across diode (Ch1) and output voltage (Ch4) 48
5.10 Current Sense network with buck converter 50
5.11 Critical current loops in a buck converter 52
5.12 PCB layout of power stage 52
















xiii

LIST OF SYMBOLS / ABBREVIATIONS




D - Duty ratio
i
L
- Inductor current ripple
T - One cycle period
V
O
- Output voltage
V
O
- Output voltage ripple
f
S
- Switching frequency
V
i
- Input voltage
ACMC - Average Current-Mode Control
CA - Current Error Amplifier
CCM - Continuous Conduction Mode
CMC - Current-Mode Control
CT - Timing Capacitor
EMI - Electromagnetic Interference
ESR - Equivalent Series Resistance
GND - Ground
IC - Integrated Circuit
LPF - Low Pass Filter
PCB - Printed Circuit Board
PCMC - Peak Current-Mode Control
PWM - Pulse Width Modulator
RT - Timing Resistance
VMC - Voltage-Mode Control

xiv

LIST OF APPENDICES




APPENDIX TITLE PAGE

A1 Power Stage 56
A2 Controller Stage 57
A3 ACMC Buck Converter 57
B1 PCB Layout for Power Stage 58
B2 PCB Layout for Controller Stage 58
C UC3825 Data Sheet 59

CHAPTER 1




INTRODUCTION




This project is intended to implement an average current mode control (ACMC)
buck converter based on UC3825. A buck converter is one of the common DC-DC
converters used to regulate an output voltage at a fixed level. Besides, the ACMC
control scheme is used with feedback controllers to help in providing a perfect
regulation. This project is started with the design of ACMC buck converter, followed by
validation of designs through the PSpice simulation. After this, the designed ACMC
buck converter is implemented into hardware and the approaches to overcome the
difficulties during the implementations are highlighted as a step to bridge the gaps
between theoretical principles and practical implementations.




1.1 Problem Statement


Designing and implementing a DC Buck converter circuit involves a lot of
procedures from specifications of converter, circuit topology selection, component
2

selection, simulation to validate the design and finally hardware implementation. This
indicates that systematic design procedures are very important to ensure a well-
functional Buck converter. Besides, there are gaps between the theoretical principles
and practical accomplishments. This is because the theoretical principles always come
with assumptions which can simplify or make the analysis become easier. Thus, when
moving from the design manner (with theoretical principles) to hardware
implementation, definitely there are some limitations exist due to the failure of
assumptions applied or the limitation of components.


However, by observing on the existing project or research papers and literatures,
not as much of literatures or research papers provide or describe systematic and easy-to-
follow design procedures to design a Buck converter. Moreover, most of the literatures
or research papers rarely discuss the practical aspects of the implementation such as
appropriate approaches to cope with the limitations during circuit implementation.




1.2 Objectives


There are several objectives in this project, as listed in the following:
1. To introduce systematic design procedures in the development of an Average
Current Mode Control Buck converter based on UC3285
2. To outline the approaches to bridge the gaps between the theoretical principles and
practical implementation during circuit design
3. To validate the designed buck converter through PSpice simulation and to
implement the converter into hardware manner


3

1.3 Scope of Project

This project focuses on the practical implementation of a Buck converter using
PWM controller IC, UC3285. The Average Current Mode Control method is applied
into the Buck converter as a feedback controller. The designed converter is verified
through PSpice simulation and implemented into hardware manner. During circuit
design and implementation, the approaches to bridge the gaps between the theoretical
principles and practical limitations are highlighted as well.




1.4 Report Outlines


This project paper is organized into 6 parts:
Part 1: Introduction
This part gives a brief introduction to this project which includes problem statements,
objectives and scope of works.


Part 2: Background of Study
This part provides literature reviews which include the operation principles of Average
Current Mode Control on Buck converter.


Part 3: Methodology
This part describes the design procedures of power stage design, inner and outer loop
control loop using PSpice simulation.

4

Part 4: Hardware Implementation

This part discusses the practical considerations when selecting components for
hardware implementation.


Part 5: Results and Analysis
This part represents the simulation results on verifying designed ACMC buck converter
as well as the experimental results for ACMC buck converter on open loop and close
loop.


Part 6: Conclusion
This part concludes the overall achievement of this project.


















5

CHAPTER 2




BACKGROUND OF STUDY




In electronic engineering, the DC-DC converters are the electronic circuits
which can convert unregulated DC input to a controlled DC output with a desired
voltage level. DC-DC converters are utilized in a variety of applications, including
power supplies for electronic devices such as personal computers, office equipment,
laptop computers, and telecommunication equipments, as well as DC motor drives.


Since mostly electronic circuits operating at several different voltage levels,
hence, by using DC-DC conversion method, it is convenient to convert energy level
from single source rather than from several different supplies [1]. Practically, there are
three basic topologies commonly used in DC-DC conversion, which are the Buck,
Boost and Buck-Boost converters. Moreover, the Buck converters are also known as
step down converters, which regulating output at voltage level lower than the input
voltage level. Besides, the Boost converters or Step Up converters is used to regulate
output at voltage level higher than the input voltage level. On the other hands, the Buck-
Boost converters are the cascade connections of both the Buck and Boost converters,
which can operate as either step-down converter or step-up converters, depending on
the duty ratio of corresponding converters.
6

2.1 Buck Converter

The most common and the simplest DC converter topology is the buck converter.
The output voltage of a buck converter is always less than the input voltage in the same
polarity and is not isolated from the input. Figure 2.1 shows the basic buck converter
circuit.



Figure 2.1 Basic buck converter topology.


The following discusses the operations of buck converter and the relationship
between input and output voltage of buck converter. The general equation of voltage
across an inductor is

:
L
= I
Ji
L
Jt
= I
Ai
L
At
(2.1)

Thus, the change in inductor current can be obtained as

Ai
L
=
:
L
I
At (2.2)

7

When the switch is closed and diode is reverse-biased, there is voltage across inductor
is V
d
V
o
for duration of DT where V
d
is input voltage, V
o
is output voltage, T is
periodic switching time of switch and D is the duty ratio of switch. Thus, the change in
inductor current is

(Ai
L
)
cIoscd
=
I
d
- I
o
I
I (2.S)


When the switch is opened for duration of (1-D) T, the change in inductor current is

(Ai
L
)
opcncd
=
- I
o
I
(1 - )I (2.4)

In steady - state operation, i
L
at the end of switching cycle is the same at the beginning
of the next cycle which means that the change of inductor over one period is zero. Thus,

(Ai
L
)
cIoscd
+ (Ai
L
)
opcncd
= u (2.S)

_
I
d
- I
o
I
I] + _
- I
o
I
(1 -)I] = u (2.6)

Solving the above equation gives

I
o
= I
d
(2.7)

The Equation (2.7) is a very important relationship between output and input voltage
and duty ratio in this project, as the duty ratio D can be adjusted by controllers to fix the
output voltage at desired level when there are disturbances either at input voltage or
load current.

8

From the basic buck converter circuit, combination of both the inductor and
capacitor act as a Low Pass Filter (LPF) where the inductor is responsible for smoothing
the inductor current and capacitor is used to reduce the output voltage ripples so that a
nearly pure DC output voltage can be obtained. On the other hand, the diode is
providing a path for continuous inductor current during the switch is opened.


The output voltage ripples can be controlled by the value of capacitance C given as

C =
AI
I
o
(1 - )
8I
2
(2.8)

where AI is output voltage ripple and f is switching frequency.


The minimum value of inductance to ensure continuous conduction mode (CCM) of
buck converter is given as

I
mn
=
(1 -)R
2
(2.9)

where R is the load resistance.




2.2 Control Schemes

Usually the output of a circuit is depending on the input. With there is a change
at input, the output cannot be maintained at desired level anymore. Thus in practice, the
external controls are required to provide perfect regulation of output voltage.

9

There are two types of control scheme which are linear and non-linear. The
linear control schemes that are commonly used include Sliding-Mode Control, Voltage-
Mode Control and Current-Mode Control. These linear control schemes are
implementing the feedback control method which is serving for two purposes. Firstly, it
will adjust the duty ratio to a required value to provide or sustain a fixed output.
Secondly, it will ensure the stability where the power converter will return to the
desired operating point after some disturbances are applied.




2.2.1 Voltage Mode Control


One of the most extended control methods of dc-dc switching converters is
voltage-mode control (VMC). VMC only contains one feedback loop from the output
voltage. The Figure 2.2 shows the general circuit of buck converter with voltage-mode
control.


Figure 2.2 General circuit of buck converter with voltage-mode control.

10

In VMC, the output voltage is fed to voltage error amplifier and compared to a
DC reference voltage and any difference or voltage error is amplified by the voltage
error amplifier. The output of the voltage error amplifier is called error voltage, V
error
.
After this, this V
error
is compared to a sawtooth ramp voltage, V
ramp
at the PWM
comparator to obtain the essential duty ratio of the power switch to provide or maintain
output voltage at desired level. When V
error
is higher than V
ramp
, output of PWM will
become high and vice versa, as shown in Figure 2.3. Thus, the duty ratio is proportional
to the error voltage, the higher the error voltage, the longer the duty ratio to turn on
power switch.



Figure 2.3 Waveform of V
ramp
, V
error
and PWM output.


As stated earlier, the VMC is a simple control scheme and easy to design and
implement. Moreover, a large amplitude ramp waveform provides good noise margin
for a stable modulation process. However, VMC has some disadvantages. The feedback
loop only works when the output voltage varies. This means that any line or load
disturbance is delayed in phase by the inductor and capacitor prior to the output. In
addition, any change in input voltage will alter the gain and influence the system
dynamics behavior.


V
ramp

V
error

PWM output
11

2.2.2 Peak Current Mode Control

On the other hands, the current-mode control (CMC) is a two-loop feedback
system consists of inner current control loop and the outer voltage control loop. The
principle of the two-loop feedback arrangement is that when output voltage too low, the
converter can increase the inductor current to regulate the output voltage. Besides that,
the CMC can be divided into two, which are Peak Current Mode Control (PCMC) and
Average Current Mode Control (ACMC). PCMC exhibits several advantages, such as
eliminating both the delayed response and gain variation resulted with changes in input
voltage (which is the main problem faced by VMC).


In PCMC, the ramp waveform that used to compare with the error voltage by
error amplifier (CA) is derived from the instantaneous peak inductor current, since the
waveform of instantaneous inductor current is similar to a ramp waveform at PWM.
The general circuit of buck converter with PCMC is shown in Figure 2.4.



Figure 2.4 General circuit of buck converter with PCMC.
12

From the Figure 2.4, the output voltage is feedback and compared with a
reference at a voltage error amplifier. The output of the voltage error amplifier, V
error
represents the desired inductor current level. When the pulse sets the latch to turn on the
power switch, the inductor current will ramp up. A current sense resistor Rs can be used
to sense inductor current and converted to corresponding voltage ramp which is then
compared with the error voltage, V
error
, as shown in Figure 2.5. The current error
amplifier (CA) will test the relationship between the error voltage and the voltage
representing the instantaneous inductor current. When the instantaneous voltage reaches
the desired inductor current level represented by V
error
, the comparator resets the latch
and turns off the power switch. The inductor current will decay, until the clock initiates
the next cycle.



Figure 2.5 Waveform of V
error
, V
Rs
and CA output.


However, the main disadvantage of PCMC is poor noise immunity. The current
loop has low loop gain causing current ramp is usually small, especially when input
voltage is low. As a result, this method is extremely susceptible to noise spike generated
each time when the switch is turned on. Besides that, the disadvantages of PCMC
includes a need slope compensation and peak-to-average current errors, due to the low
loop gain in the current loop.

V
RS
V
error

CA output
13

2.2.3 Average Current Mode Control

The ACMC method can overcome problems faced by VMC and PCMC with
introducing a compensation network which can provide high gain for the inner current
loop. Thus, ACMC does not require slope compensation and it has excellent noise
immunity due to the high gain in current loop.


Figure 2.6 shows the general circuit of buck converter ACMC. From the figure,
the instantaneous inductor current is sensed by Rs and compared with V
error
, the desired
current level determined by the outer voltage loop. The current error is amplified by
current error amplifier (CA). The output of CA is compared to a sawtooth ramp at the
PWM comparator and the output is shown in Figure 2.7. In this figure, the output of
PWM is high when V
CA
, the output of CA is higher than the ramp input (V
ramp
) of PWM
and vice versa in order to produce a duty ratio that provides or maintains the output
voltage at a desired level.



Figure 2.6 General circuit of buck converter with ACMC.
14

Figure 2.7 Waveform of V
sawtooth
, V
CA
and PWM output.


The ACMC not only preserving the advantages of PCMC as mentioned earlier,
instead, ACMC is superior to PCMC in several aspects. ACMC provides excellent noise
immunity to the spike sensed in the inductor current. Moreover, slope compensation is
not required, but there is a limit to loop gain at the switching frequency in order to
achieve stability.


In fact, the ACMC can be used to sense and control the current in any circuit
branch. Thus, it can control input current accurately in the buck topology as well as to
control output current with boost and flyback topologies, providing flexibility in any
topologies. Furthermore, ACMC can function well even when the mode boundary is
crossed into the discontinuous conduction mode at low current levels.







PWM output
V
sawtooth

V
CA

15

CHAPTER 3




METHODOLOGY




This topic discusses the methods or strategies used to conduct and achieve the
objective of this project. This project is carried by preliminary study of buck converter
and a few control schemes, especially on the average current mode control. After that,
the project is started by defining the specifications of buck converter and designing of
power stage. Since this project is mainly focusing on hardware implementation of an
ACMC buck converter, the design of outer voltage loop and inner current loop in the
ACMC scheme is using the PSpice design files provided by project supervisor. All the
components values in the voltage and current loop compensators can be directly
calculated from the PSpice design files and can be used in hardware implementation.




3.1 Design Procedures for power stage


The design of a buck converter with average current mode controller is based on the
specifications listed in Table 3.1.
16

Table 3.1 Specification of buck converter.
Description Parameter Value
Input voltage V
d
10 18V, 12V nominal
Output voltage V
o
5V
Output current I
o
0 5A
Output voltage ripple V
o
1% (or 50mV at 5V output)
Switching frequency f
S
50kHz


The following discusses a few steps to design the power stage of ACMC buck converter:


Step 1: Calculation of duty ratio D
The duty ratio D is calculated as

=
I
o
I
d
(S.1)

When I
d
is 18V,
mn
=
v
c
v
d (mcx)
=
5
18
= u.2778.

When I
d
is 10V,
mux
=
v
c
v
d (min)
=
5
10
= u.Su.

Thus, the range of required duty ratio is 0.2778 D 0.50.


Step 2: Calculation of load resistance R
The load resistance R can be calculated by using

17

R =
I
o
I
o
(S.2)

When I
o
is 5 AR
mn
=
v
c
I
c (mcx)
=
5
5
= 1 0.,

When I
o
is 1 A, R
mux
=
v
c
I
c (min)
=
5
1
= S 0.

Thus, the range of required load resistance is 1 R 5 .


Step 3: Calculation of minimum inductance for ensuring CCM operation
For CCM operation, the minimum inductance in this project is

I
mn
=
(1 -
mux
) R
mux
2
s
(S.S)

I
mn
=
(1 - u.S)(S)
2(Su 1u
3
)
= 2SpE

Thus, the inductance used in this project is chosen as 47 B.


Step 4: Calculation of capacitor
For keeping output voltage small, the maximum value of equivalent series resistance,
R
esr
is calculated as
R
cs

AI
o
I
o
_

s
I
mn
1 -
mn
] (S.4)

R
cs

u.uS
S
_
(Su 1u
3
)(47 1u
-6
)
1 - u.2778
_

R
cs
S2.S4m0
18

By selecting R
esr
= 28 mu, the minimum capacitor can be calculated:

C
mn
= mox _
1 -
mn
2 R
cs

s
,

mux
2 R
cs

s
] (S.S)

C
mn
= mox _
1 - u.2778
2(u.u28)(Su 1u
3
)
,
u.Su
2(u.u28)(Su 1u
3
)
]

C
mn
= mo x(128.96pF, 89.29pF)


Thus, the capacitor of 150F is chosen.




3.2 Design Procedures for ACMC buck converter


To design the control system or compensator of an ACMC buck converter, it is
necessary to model the converter dynamic behavior. In particular, it is of interest to
determine how variations in the input voltage v
d
(t), the load current i(t), and the duty
cycle d(t) affect the output voltage. Unfortunately, understanding of converter dynamic
behavior is hampered by the nonlinear time-varying nature of the switching and pulse-
width modulation process. These difficulties can be overcome through the use of
waveform averaging and small signal modeling techniques.


The averaging technique is required so as to take the average of all circuit
quantities over one switching cycle, then followed by the linearization process so that
numerous analysis techniques (such as Laplace) available for linear system can be
applied to analyze the converter circuit. After this, the converter circuit can be modeled
into small signal model and is ready to be used for design the loop compensators.
19

The Figure 3.1 shows the block diagram of ACMC of DC-DC converters. There
are two control loops, which are inner loop for the inductor current control and outer
loop for the output voltage control.


Figure 3.1 Block diagram of ACMC of DC-DC converters.


The Table 3.2 shows the converter transfer function for average current mode
controller of buck converter, where R represent the load equivalent resistance, r is ESR
of capacitor and V
in
is the DC input voltage source.


Table 3.2 Converter transfer function for average current mode controller.

Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
outer voltage loop compensa
loop compensators is then verified by applying disturbances to buck converter.




3.2.1 Design of inner current loop compensator
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
circuit used to design current loop compensator based on average model of buck
converter.
linearization, then they are modeled and



Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
outer voltage loop compensa
loop compensators is then verified by applying disturbances to buck converter.
Design of inner current loop compensator
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
converter. The power switch and diode are
linearization, then they are modeled and
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
outer voltage loop compensator of buck converter in small
loop compensators is then verified by applying disturbances to buck converter.
Design of inner current loop compensator
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
he power switch and diode are
linearization, then they are modeled and
Figure 3.2
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
tor of buck converter in small
loop compensators is then verified by applying disturbances to buck converter.
Design of inner current loop compensator
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
he power switch and diode are
linearization, then they are modeled and repre
Figure 3.2 Current loop compensator
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
tor of buck converter in small
loop compensators is then verified by applying disturbances to buck converter.
Design of inner current loop compensator


The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
he power switch and diode are undergone averaging technique and
represented in a
Current loop compensator
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
tor of buck converter in small-signal model. The design of
loop compensators is then verified by applying disturbances to buck converter.
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
undergone averaging technique and
sented in a ccm1 block
Current loop compensator.
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
signal model. The design of
loop compensators is then verified by applying disturbances to buck converter.
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
undergone averaging technique and
block.
20
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
signal model. The design of
loop compensators is then verified by applying disturbances to buck converter.
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
undergone averaging technique and

20
Besides, the design of loop compensators can be divided into a few stages in
sequence, started from the design of inner current loop compensator and followed by
signal model. The design of
The Figure 3.2 shows the circuit of inner current loop compensator. The design
of inner current loop compensator is about to determine the component values based on
the frequency response of the designed control system. Figure 3.3 shows the simulation
uit used to design current loop compensator based on average model of buck
undergone averaging technique and
21

Figure 3.3 Simulation circuit used to design current loop compensator.


There are 4 steps in designing an inner loop compensator, as shown in the following:


Step 1: Calculation of suitable range of crossover frequency
According to Lloyd Dixon, to avoid sub-harmonic oscillations, the loop gain crossover
frequency can be selected as

co
=

s
2n
(S.6)

When duty ratio is maximum,
co
=
]
s
2n
mcx
=
(5010
3
)
2n(0.5)
= 1S.92 kEz.
When duty ratio is minimum,
co
=
]
s
2n
min
=
(10010
3
)
2n(0.2778)
= 28.6S kEz.

Thus, the loop gain crossover frequency can be selected in between 15.92 kHz and
28.65 kHz.
22

Step 2: Pole-zero placement
The transfer function of the current loop compensator is

0

(s) =
(w

) _1 +
s
2n
z
]
[ 1 +
s
1
_ 1 +
s
2n
p
]
(S.7)

From the transfer function in Equation (3.7), one system pole is placed at 1 rad/s and
another system pole
pI
can be placed at 100 kHz with the purpose as to eliminate noise
spikes riding on the current waveform and the zero
zI
is placed at 1.6 kHz.


Step 3: Selection of gain margin from frequency response
The loop gain of current compensator, wii is set to 1 and the frequency response is
shown in Figure 3.4.



Figure 3.4 Frequency response of system with current loop compensator.
Magnitude Response
Phase Response

The suitable range of phase margin is between 45 and 76. The signals in time
domain will undergo critically
into this range, while over
which leads to low transient response of signals.


From the frequency response above, gain margin of
selected wi
phase margin of 7


Step 4: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by
using the calculator in the design files, as shown in Figure 3.5.




From the interface of calculator in the Figure 3.5, the value of resistance
capacitor


The suitable range of phase margin is between 45 and 76. The signals in time
domain will undergo critically
into this range, while over
eads to low transient response of signals.
From the frequency response above, gain margin of
selected with the crossover frequency at 16
phase margin of 75 for better oscillations.
: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by
using the calculator in the design files, as shown in Figure 3.5.
Figure 3.5
From the interface of calculator in the Figure 3.5, the value of resistance
capacitor Cfpi is 58.82pF and capacitor Cfzi is 3.618
The suitable range of phase margin is between 45 and 76. The signals in time
domain will undergo critically-
into this range, while over-damped oscillation will occur if phase margin above 76
eads to low transient response of signals.
From the frequency response above, gain margin of
th the crossover frequency at 16
for better oscillations.
: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by
using the calculator in the design files, as shown in Figure 3.5.
Figure 3.5 Component values in current loop compensator
From the interface of calculator in the Figure 3.5, the value of resistance
is 58.82pF and capacitor Cfzi is 3.618
The suitable range of phase margin is between 45 and 76. The signals in time
-damped oscillation if the phase margin of system falls
damped oscillation will occur if phase margin above 76
eads to low transient response of signals.
From the frequency response above, gain margin of
th the crossover frequency at 16
for better oscillations.
: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by
using the calculator in the design files, as shown in Figure 3.5.
Component values in current loop compensator
From the interface of calculator in the Figure 3.5, the value of resistance
is 58.82pF and capacitor Cfzi is 3.618
The suitable range of phase margin is between 45 and 76. The signals in time
damped oscillation if the phase margin of system falls
damped oscillation will occur if phase margin above 76
eads to low transient response of signals.
From the frequency response above, gain margin of
th the crossover frequency at 16 kHz to avoid sub
for better oscillations.
: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by
using the calculator in the design files, as shown in Figure 3.5.
Component values in current loop compensator
From the interface of calculator in the Figure 3.5, the value of resistance
is 58.82pF and capacitor Cfzi is 3.618nF.
The suitable range of phase margin is between 45 and 76. The signals in time
damped oscillation if the phase margin of system falls
damped oscillation will occur if phase margin above 76
From the frequency response above, gain margin of 88.691
kHz to avoid sub-harmonic osc
: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by
using the calculator in the design files, as shown in Figure 3.5.
Component values in current loop compensator
From the interface of calculator in the Figure 3.5, the value of resistance
nF.
The suitable range of phase margin is between 45 and 76. The signals in time
damped oscillation if the phase margin of system falls
damped oscillation will occur if phase margin above 76
691 dB or 27.2
harmonic oscillations and
: Calculation of component values in current loop compensator
The components in the designed current loop compensator can be directly calculated by

Component values in current loop compensator.
From the interface of calculator in the Figure 3.5, the value of resistance Rfi
23
The suitable range of phase margin is between 45 and 76. The signals in time-
damped oscillation if the phase margin of system falls
damped oscillation will occur if phase margin above 76
27.2 10
3
is
illations and
The components in the designed current loop compensator can be directly calculated by

is 27.50k,
23
-
damped oscillation if the phase margin of system falls
damped oscillation will occur if phase margin above 76
is
illations and
The components in the designed current loop compensator can be directly calculated by
,
24

3.2.2 Design of outer voltage loop compensator

The Figure 3.6 shows the simulation circuit used to design the outer voltage loop
compensator. The design of outer loop is taking inner loop into considerations and there
are a few steps in designing outer loop, as described below:


Step 1: Pole-zero placement
The compensators transfer function is given as

0

(s) =
1uu (w

) _1 +
s
2n
z
]
[ 1 +
s
u.u1
_ 1 +
s
2n
p
]
(S.8)

Thus, from the Equation (3.8), there is one pole placed near origin, at 0.01 rad/s and
another pole f
pv
is placed at 40 kHz to cancel the effect of system zero f
Z
, while the zero
of the Gv(s) which is f
zv
is placed at 200 Hz to compensate the effect of system pole, f
P
.



Figure 3.6 Simulation circuit used to design voltage loop compensator.
25

Step 2: Selection of gain margin from frequency response

The loop gain of voltage loop compensator, wiv is set to 1 and the frequency response is
shown in Figure 3.7.



Figure 3.7 Frequency response of system with voltage loop compensator.


From the frequency response above, gain margin of 55.586 dB or 601.6 is
selected with the crossover frequency at 2 kHz and phase margin of 89.05.


Step 3: Calculation of component values in voltage loop compensator
By using the calculator in the design files, the components in the designed voltage loop
compensator can be directly calculated, as shown in Figure 3.8. The Figure 3.9 shows
the connection of voltage loop compensator circuit.


Magnitude Response
Phase Response

From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
capacitor Cfpv is


Thus, b
of ACMC buck converter in small signal model are verified by applyin
output disturbances as discussed
Figure 3.8
From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
capacitor Cfpv is 1.768n
Thus, both the designed inner current loop and outer voltage loop compensators
of ACMC buck converter in small signal model are verified by applyin
output disturbances as discussed
Figure 3.8 Component values in
Figure 3.9
From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
1.768nF and capacitor Cfzv is
oth the designed inner current loop and outer voltage loop compensators
of ACMC buck converter in small signal model are verified by applyin
output disturbances as discussed
Component values in
Figure 3.9 Voltage
From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
F and capacitor Cfzv is
oth the designed inner current loop and outer voltage loop compensators
of ACMC buck converter in small signal model are verified by applyin
output disturbances as discussed in the next topic.
Component values in voltage
Voltage loop compensator


From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
F and capacitor Cfzv is 351.9nF.
oth the designed inner current loop and outer voltage loop compensators
of ACMC buck converter in small signal model are verified by applyin
in the next topic.
voltage loop compensator
loop compensator.
From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
nF.
oth the designed inner current loop and outer voltage loop compensators
of ACMC buck converter in small signal model are verified by applyin

loop compensator.

From the interface of calculator in the Figure 3.8, the value of resistance Rfv is
oth the designed inner current loop and outer voltage loop compensators
of ACMC buck converter in small signal model are verified by applying input and
26
From the interface of calculator in the Figure 3.8, the value of resistance Rfv is 2.261k
oth the designed inner current loop and outer voltage loop compensators
g input and
26
,
oth the designed inner current loop and outer voltage loop compensators
g input and
27

CHAPTER 4




HARDWARE IMPLEMENTATION




The hardware implementation is divided into two stages which are power stage
and controller stage so as to group the components in the controller circuit away from
power stage where the Electromagnetic Interference (EMI) origins. First, the hardware
is implemented on the breadboard to verify the circuits, followed by transferring circuit
in two stages into the Printed Circuit Board (PCB) separately.




4.1 Power Stage


The considerations on determining the power components including power switch,
power diode, inductor, output capacitor, load and input filter capacitor are discussed.




28

4.1.1 Power Switch

The power switch in the buck converter is implemented using MOSFET due to a
few advantages. Power MOSFET has higher breakdown voltage and can be used in
higher frequency applications where the on-state-resistance has no theoretical limit,
hence switching power losses can be far lower. The MOSFET also has a body-drain
diode, which is particularly useful in dealing with limited freewheeling currents. The
desired MOSFET should have a maximum drain-to-source voltage, V
DS
, greater than
the maximum input voltage (18 V) in addition of some margin for spikes. The rating for
the maximum drain current, I
D(max)
is at least twice the maximum load current which is
5A. Therefore, 100 V, 33 A N-channel MOSFET IRF540N from International Rectifier
is chosen.




4.1.2 Power Diode


Power diode should be selected by considering fast switching, current rating,
reverse voltage and low voltage drop. The current rating must be above 5.0 A
(maximum inductor current) and the reverse voltage must greater than 18 V (maximum
input voltage). Thus, a fast soft recovery rectifier diode 10ETF06PbF from International
Rectifier is selected. The peak forward current is 10 A and the peak repetitive reverse
voltage, V
RRM
is 600 V. The forward voltage drop at 10 A forward current is low which
only 1.2 V.




29

4.1.3 Inductor


The inductor selected in this project is 47H bobbin type from C&D
Technologies. The current rating is 6.0 A, prohibiting the converter from operating at
maximum power rating for long duration to prevent overheating or saturation. As
described in its datasheet, the inductor is suitable for many power supply applications
because its DC resistance is low, at 33m.




4.1.4 Output Capacitor


A 150F (16SH150M) from the Sanyo OS-CON SH series is chosen. This series
is dedicated for high frequency power supplies and is well known for low ESR. The
digit 16 in the part number refers to its voltage rating and the tolerance on rated
capacitance is 20%. The advantages of SH series is the long life (guaranteed at 105C
for 5000h) with keeping high frequency characteristics and the high reliability.




4.1.5 Load


A 5 resistor is needed to provide maximum current of 1A. The power rating of
resistor should be at least 5 W. Hence, a 7 W 5 vitreous enameled wire wound resistor
from Welwyn Components W22 series is chosen. This device has high stability and
reliability with maximum ambient temperature up to 200C.
30

4.1.6 Input filter

Input filter is a must to attenuate the switching harmonics of the input current
and protect the converter from input voltage transients. A 220F miniature aluminum
electrolytic capacitor Rubycon ZLH series is selected as the input filter. The voltage
rating is 35 V which is greater than the maximum input voltage, 18V.




4.2 Controller Stage


The following discusses the considerations on determining the components on
controller stage including Pulse Width Modulator (PWM) controller, MOSFET driver,
current sensor and feedback network.




4.2.1 Pulse Width Modulator (PWM)


A high speed PWM controller, UC3825 from Unitrode is selected. It is
optimized for high frequency switched mode power supply applications for practical
switching frequencies up to 1 MHz. This device is compatible with current mode
control. The internal protection circuitry includes a current limit comparator with a 1V
threshold, a TTL compatible shutdown port, and a soft start pin which will double as a
maximum duty cycle clamp. Figure 4.1 shows the functional diagram of UC3825.

31

Figure 4.1 Functional diagram of UC3825.




4.2.1.1 Current Loop Compensator


In this project, the wide bandwidth error amplifier (at pin 1, 2, 3) of UC3825 is
used as a current loop compensator with the corresponding compensation network.





32

4.2.1.2 Switching Frequency

The switching frequency is determined by the oscillating frequency of sawtooth
signal. This can done generated by connecting a resistor at pin 5 (RT) and a capacitor at
pin 6 (CT). The available frequencies range of UC3825 is from 100 Hz to 1 MHz.
According to the Timing Resistance vs. Frequency graph in the datasheet, combination
of CT 10nF and RT 5k can generate switching frequency of 50 kHz. A 5 k
potentiometer is used for RT to adjust the switching frequency. For ACC application,
pin 7 (Ramp) is connected to pin 6 (CT).




4.2.1.3 Soft-start


An external 1 F electrolytic capacitor is connected at pin 8 to slowly increase
the MOSFET peak current during start up. This can prevent the large in-rush current at
external MOSFET.




4.2.1.4 PWM Output


UC3825 has totem pole outputs provided by pin 11 and pin 14. The outputs are
analogical OR by locating a diode (1N4148) at each output pin, followed by a pull-
down resistor. This output configuration gives a wider range of operating duty ratio, up
to 95%. Figure 4.2 shows the schematic diagram to configure UC3825.
33

Figure 4.2 Schematic diagram of configuration for PWM controller UC3825.




4.2.2 MOSFET Driver


4.2.2.1 Opto-isolator


An opto-isolator transfer a signal between elements of a circuit by using a short
optical transmission path while keeping them electrically isolated due to the electrical
contact along the path is broken. Thus, a super high speed photo coupler, 6N137 is
chosen. The pin connection of 6N137 is shown as Figure 4.3.



34

Figure 4.3 Schematic diagram of opto-isolator.




4.2.2.2 Driver Selection


In this project, MC34151 driver is chosen. The MC34151 is dual inverting high
speed drivers specifically designed for applications that require low current digital
circuitry to drive large capacitive loads with high slew rates. This device is intended for
switching power supplies and dc-dc converters application due to the high efficiency at
high frequency operation. The two independent high current totem pole outputs ideally
suited for driving power MOSFETs. The schematic diagram of MC34151 driver is
shown in Figure 4.4.






35

Figure 4.4 Schematic diagram of MC34151 driver.




4.2.2.3 Configuration of MOSFET Driver


Pin 2 of opto-isolator (6N137) is anode of the internal LED and is connected to
PWM output, while Pin 3 cathode of the internal LED that connected to PWM ground
(GND1). 6N137 requires 5V power supply which can be obtained by connecting a 5.1V
zener diode and a 500 resistor to the 12 V power supply (Figure 4.5).


For the MOSFET driver, only one inverting high speed driver is used with the
necessary pin at Logic Input A (Pin 2) and Driver Output A (Pin 7). The Driver Output
A is connected to the gate of MOSFET while the source of MOSFET is connected to
GND2 via jumper J1, as shown in Figure 4.5. Note that there are two grounds in the
connection, where GND1 is power ground and GND2 is signal ground.
36

Figure 4.5 Configuration of MOSFET driver.




4.2.3 Feedback Network


In controller stage, there are two feedback networks which are inner current loop
compensator and outer voltage loop compensator. The built-in error amplifier in
UC3825 is used for current loop compensator, while the voltage loop compensator and
current sense network require two operational amplifiers (op-amp). Therefore, one
TL084 with 4 op-amps is selected. TL084 requires dual polarity supply voltages, rating
from 5 V to 18 V. The ground reference is the midpoint between Vcc. The full
schematic diagram of ACMC buck converter is shown in Figure 4.6.



37

Figure 4.6 Full schematic diagram of ACMC buck converter.














38

CHAPTER 5




RESULTS AND ANALYSIS




5.1 Procedure


The project can be divided into two major parts which are simulation and
hardware. For simulation, the input disturbance and load disturbance are applied to
observe the transient response of the ACMC buck converter.


Next, hardware implementation follows the steps demonstrated in Figure 5.1.
First, perform open loop laboratory test of UC3825 and study the characteristics of
UC3825 by varying some parameters. Then, implement power stage into PCB, followed
by testing open loop buck converter power stage for verification. The duty ratio is
adjusted to observe the response of output voltage. After this, implement controller
stage into PCB and perform closed loop test and verification.

39

Figure 5.1 Procedures in hardware implementation.




5.2 Simulation Result and Discussion


The Figure 5.2 shows the simulation circuit of buck converter with switch model
to verify the design values of both the inner and outer loop compensators. Note that the
component values of each compensator are changed to real component values which
available in markets.

40

Figure 5.2 Simulation circuit of buck converter with switch model.




5.2.1 Verification through input disturbances


By applying disturbance at input with raising the input voltage from 12V to 20V
for 2ms, the results of output voltage and inductor current are shown in Figure 5.3. It
can be clearly observed that the output voltage and inductor current are able to return to
their operating points after the input disturbance is applied at t = 2ms as well as after the
input disturbance is removed at t = 4ms.





41

Figure 5.3 Design verification by applying input disturbance.










Input Disturbance
Output Voltage
Inductor current
42

5.2.2 Verification through load disturbances

Load disturbance is applying by raising the load current from 1A to 2A for 3ms,
the results of output voltage and inductor current are shown in Figure 5.4. From the
figure, it is obviously showing that the output voltage and inductor current are capable
to return to their operating points after the load disturbance is applied at t = 6ms as well
as after the load disturbance is removed at t = 9ms.




Figure 5.4 Design verification by applying input disturbance.


Load Disturbance
Output Voltage
Inductor current
43

Besides, the figure below shows the output of PWM when comparing the output
of error amplifier CA with ramp input. To avoid sub-harmonic, the slope of off-time CA
output must not exceed the slope of the ramp input. From the Figure 5.5, the slope of
off-time CA output is not exceeding the ramp input slope. Furthermore, the off-time CA
output slope is almost similar with the ramp input slope indicating that the designed CA
gain is optimum to avoid from sub-harmonic oscillations.




Figure 5.5 The designed CA gain is optimum to avoid sub-harmonic oscillations.



PWM inputs
PWM output
V
ramp

V
CA

44

5.3 Experimental Result and Discussion

5.3.1 Open Loop Laboratory Test


The open loop laboratory test is performed UC3825 to study the characteristics
of PWM controller. In Figure 5.6, Ch1, Ch2 and Ch4 represents sawtooth ramp
waveform, PWM output waveform and output voltage (by comparing inverting and
non-inverting inputs) respectively. Obviously, PWM output is high when instantaneous
output voltage higher than instantaneous sawtooth voltage and vice versa. In fact, the
PWM output is representing a duty ratio to trigger MOSFET. This result is exactly the
same as expectation. Note that there is an offset of 1.25 V at the error amplifier output.



Figure 5.6 Result of open loop laboratory test on UC3825.



45

5.3.2 Open Loop Test with Power Stage

The power stage is implemented and tested at open loop and is verified that the
power stage is function well. Figure 5.7 demonstrates the result of open loop test, where
Ch1 represents voltage across diode in power stage while Ch4 represents output voltage
of power stage. When input voltage is around 10V, output voltage is 6.6V, with duty
ratio approximately 66%. Thus, it is clearly showing that the output voltage does follow
the proper relationship with input voltage for a given duty ratio.



Figure 5.7 Result of open loop test with power stage.







46

5.3.3 Close Loop Test

After the power stage is verified function well, the controller stage is
implemented into PCB to complete the circuit of ACMC buck converter. By using the
feedback control loops, the output voltage is regulated at 5 V when changing input
voltage from 10 V to 18 V. The waveforms of output voltage with various input
voltages are show in Figure 5.8. The input voltage waveform is represented by Ch1
while the output voltage waveform is represented by Ch4.



(a)


47

(b)



(c)
Figure 5.8 Waveform of output voltage when input voltage is (a) 10V (b) 12V (c) 18V.
48

However, when looking at the voltage across diode of buck converter, it is found
that the diode is working with incorrect duty ratio. As demonstrated in Figure 5.9, the
circuit is operating at frequency lower than 50 kHz. This is due to low frequency signal
exists on input voltage and output voltage (can refer Figure 5.8). Hence, when feedback
signals that contain noises are processed by compensator, definitely incorrect duty ratio
is generated by PWM.



Figure 5.9 Waveform of voltage across diode (Ch1) and output voltage (Ch4).


Although some troubleshoots have done like adding bypass capacitors and even
re-designing and changing the component values on controller stage, the output voltage
is still degraded by low frequency noise. Thus, it is suspected that the low frequency
noise may be generated from controller stage due to improper design of PCB and cause
excessive radiations of EMI.


49

5.4 Approaches to Bridge Gaps between Theoretical Principle and Hardware

Implementation


As mentioned in problem statement of this project, there are gaps between the
theoretical principles and practical accomplishments. The following discusses the
approaches to bridge the gaps.




5.4.1 Current Sense


There are two feedback paths in ACMC buck converter: voltage feedback and
current feedback. In simulation, it is easy to feedback inductor current, as indicated in
Figure 5.2 previously. However, in hardware implementation, it is not such easy to
feedback current directly from inductor current path in buck converter. Moreover,
improper feedback technique will act as current divider, reducing the amount of current
delivered to output.


Thus, Resistive Sensing provides a practical solution by connecting a series
sense resistor along the current path, and hence giving a voltage proportional to the
current. The sense resistor must be as small as possible (about 50 m) to reduce the
power losses. However, it must not be so small until the differential voltage is very low
and easily interfered with noise.



50

A current sense network is constructed by using the classic differential amplifier

as a gain amplifier and a current sense resistor. The network of resistive sensing is
shown as Figure 5.10.



Figure 5.10 Current Sense network with buck converter.


The output voltage equation of the amplifier is given as

i
L
R
S
=
R
2
R
1
|I
+
- I
-
] (S.1)

With Rs = 0.25 (from simulation), the equation becomes

u.2S i
L
=
R
2
R
1
(i
L
R
scnsc
) (S.2)
51

Thus, a 3W rating, 50 m metal film resistor from Welwyn Components OAR

series is chosen as R
sense
= 50 m. By selecting R
1
= 15k, the resistor value for R
2
is
calculated as R
2
= 75k by using the equation above.




5.4.2 PCB layout of power stage


PCB layout for power converter circuits is important for reducing EMI effect.
The layout software utilized is Layout Plus in Orcad Family version 9.2. Two PCB have
been developed to keep the controller components away from the power stage
components. The PCB layout design is critical because if the design is improper, the
PCB could radiate excessive EMI that is even worse than the breadboard
implementation and subsequently defeat the purpose.


There are four loops in the power stage that will affect on noise generation and
operational performance which are input loop, power switch loop, rectifier loop and
output loop [7]. The most critical current loop in a buck converter is the power switch
loop which consist the input filter capacitor, power switch, rectifying diode and
inductor, as shown in Figure 5.11. It carries trapezoidal current waveforms with high
peak current and very sharp edges (di/dt) that are rich in harmonics and contributing to
EMI.



52

Figure 5.11 Critical current loops in a buck converter.


Thus, the components mentioned above must be placed as close as possible and
aligned to shorten the currents paths between them. The traces connecting them should
be as short and wide as possible. It is desirable to increase the width while shorten the
length of trace to reduce the parasitic inductance and resistance. For more detail
information can refer to [7]. Figure 5.12 shows the PCB layout of power stage.



Figure 5.12 PCB layout of power stage.
53

CHAPTER 6




CONCLUSION AND RECOMMENDATION




6.1 Conclusion


In this project, an easy-to-follow procedure is introduced. Moreover, the
approaches to cope with difficulties during hardware implementation are highlighted, as
an initiative to bridge gaps between theoretical principle and hardware implementation.
In open loop test, the open loop buck converter can function well. In close loop test,
however, ACMC buck converter is operating at frequency lower than 50 kHz due to
disruption of low frequency noise, although it is intended and designed to operate at
switching frequency of 50 kHz.


In overall, the ACMC Buck Converter is functional due to capability in
regulating 5V when input voltage is varied from 10V to 18V, as specified.




54

6.2 Recommendation


For future works, this project can be improved as the following: the drawbacks
can be overcome with a proper design of PCB layout for controller stage to reduce the
impacts of EMI radiations which can degrade the overall performance of ACMC buck
converter. Besides, another recommendation for this project is to use an IC which
integrates both the opto-isolator and driver. This can help in reducing project hardness
and interface problem that may arise when connecting opto-isolator with driver.






















55

REFERENCES




[1] Dixon, L. Average current-mode control of switching power supplies. Unitrode
Power Supply Design Seminar Handbook: SEM700, 1990.

[2] J. Sun, R. M. Bass. Modeling and Practical Design Issues for Average Current
Control. IEEE Transaction on Power Electronics. 1999: 980-986.

[3] Ridley, R. A new, continuous time model for current mode control. IEEE
Transaction on Power Electronics. Mar 1991. 6: 271-280.

[4] Daniel W. H. Introduction to Power Electronics. Prentice-Hall International,
INC. 1997 .

[5] Chin Rou Chin. Average Current Mode Control of Buck Converter Using
UC3825. University Teknologi Malaysia: Bachelor Degree Project Paper, 2009.

[6] Phoon Tuck Wing. Average Current Mode Control of Buck DC-DC Converter.
University Teknologi Malaysia: Bachelor Degree Project Paper, 2007.

[7] Marty Brown. Designing PCBs for embedded switching power supplies.
Fairchild Semiconductor. 1999.

[8] Texas Instruments. Understanding Buck Power Stages in Switchmode Power
Supplies. Texas: Application report, TI Literature Number SLVA057. 1999.
56

APPENDIX A




A1: Power Stage










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A2: Controller Stage

A3: ACMC Buck Converter

58

APPENDIX B



B1: PCB Layout for Power Stage



B2: PCB Layout for Controller Stage

59

APPENDIX C


UC3825 Data Sheet

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61

62

63

64

65

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