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SCCR
TIE RIE 3
Ld
SEL SEL SEL 2 1 0
Receiver
TDRE
BCLK
start bit
BCLK
clear Bct
Bct=9
From Page 378 Operation of UART Receiver 1. When the UART detects a start bit, it reads in the remaining bits serially and shifts them into the RSR. 2. When all of the data bits and the stop bit have been received, the RSR is loaded into the RDR, and the Receive Data Register Full flag (RDRF) in the SCSR is set. 3. The microcontroller checks the RDRF flag, and if it is set, the RDR is read and the flag is cleared.
Figure 11-6 Sampling RxD with BclkX8 start bit RxD * BclkX8 4 clocks * Read data at these points 8 clocks 8 clocks * * 1st data bit 2nd data bit
Receive Data 0
RxD
Bclkx8
1 inc1 0 1
Bclkx8
Ct1=7
Ct2=8
Ct1=3
1
RDRF
OE
0
RxD
FE
stop bit
1 load RDR
RSR
FDCE
D C CLR Q
incrementer
CT1
FDCE
D C CLR Q
D C CLR
RDR
FDCE
D C CLR Q RDR[7,0] Q PWR VDD
FDCE
FDCE
D C CLR
incrementer
Q
D C CLR
FDCE
D C CLR
FDCE
D C CLR Q
FDCE
D C CLR Q
FDCE
D C CLR Q
FDCE FDCE
D C CLR Q C CLR
FDCE
D C CLR Q
FDCE
D Q
D C CLR
FDCE
D C CLR Q
FDCE
D C CLR Q
FDCE
D C CLR Q
FDCE
D C CLR Q
GND
FDCE
D C CLR Q
GND
FDCE
D C CLR SETRDRF Q
state(0)
RXD
FDCE
D Q CLR
FDCE
D Q CLR C
FDCE
D C CLR Q
FDCE
D C CLR Q
state(1)
FDCE
D Q CLR C
FDCE
D C CLR Q
SETFE
RDRFIN
SETDE
Bclkx8-Dlyed
BclkX8
8 MHz clk
divide by 13
Clkdiv13
divide by 256
BAUD Rate (Bclk) 38462 19231 9615 4808 2404 1202 601 300.5
Select Bits 000 001 010 011 100 101 110 111
ALU
Data direction B
CPU Registers
0 0 0 0 0 1 1
Stack pointer
UART
Program counter
Port B
Port A
Rxd Txd
Half-carry flag Interrupt mask Negative flag Zero flag Carry/borrow flag
Read/Modify/Write
INHA 4 NEG INHX 5 NEG IX1M 6 NEG IXM 7 NEG
Control
INH1 8 RTI RTS INH2 9 IMM A SUB CMP SBC CPX AND BIT LDA DIR B SUB CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX
Register/Memory
EXT C SUB CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX IX2 D SUB CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX IX1 E SUB CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX IX F SUB CMP SBC CPX AND BIT LDA STA EOR ADC ORA ADD JMP JSR LDX STX
0 1 2 3 4 5 6 7 8 9 A B C D E F
BRSET0* BSET0* BRCLR0* BCLR0* BRSETI* BSETI* BRCLR1* BCLR1* BRSET2* BSET2* BRCLR2* BCLR2* BRSET3* BSET3* BRCLR3* BCLR3*
BRSET4* BSET4* BHCC* BRCLR4* BCLR4* BHCS* BRSET5* BSET5* BRCLR5* BCLR5* BRSET6* BSET6* BRCLR6* BCLR6* BRSET7* BSET7* BRCLR7* BCLR7* BPL BMI BMC BMS BIL* BIH*
inha, inherent 1 INCA inhx INCX inh1, inherent 1 RTI inh2 TAX *rr is sign-extended before addition
ADD dir
ADD ext
ADD ix2
STA ext
{writeback} mem(MAR) Md
{addx} PC MAR+ X {addr2} PCL mem(PC) PCH MARH {addr2} MARL mem(PC) PC PC + 1 {push1} mem(SP) PCL SP SP - 1 {push1} mem(SP) PCL SP SP - 1 {addx} MAR MAR+ X {addr2} MARL mem(PC) PC PC + 1 {addr2} MARL mem(PC) PC PC + 1
JMP ext
JMP ix2
{addx} PC MAR + X {push2} mem(SP) PCH SP SP - 1 PC MAR {push2} mem(SP) PCH SP SP - 1 PC MAR {push1} mem(SP) PCL SP SP - 1 {push1} mem(SP) PCL SP SP - 1 {addx} MAR MAR + X
JSR dir
JSR ix
JSR ix1
JSR ext
JSR ix2
{push2} mem(SP) PCH SP SP - 1 PC MAR {push2} mem(SP) PCH SP SP - 1 PC MAR {push1} mem(SP) PCL SP SP - 1
BRA rel
SWI
SWI continued
{push2} mem(SP) PCH SP SP - 1 (9th cycle) {cycle9} PCH mem(MAR) MAR MAR + 1 {pop4} A mem(SP) SP SP + 1
{push4} mem(SP) A SP SP - 1
RTI
6th and 7th cycles same as 3rd and 4th cycles of RTS
fetch opcode get direct address read memory data do addition, fetch next opcode get direct address store data in memory fetch next opcode
testBR pop5
pop2
writeback
pop1
From Page 400 Main Sections of Behavioral Code for CPU: 1. 2. 3. 4. 5. Signal and control declarations; Procedure ALU_OP, which performs ALU operations for register-memory instructions including all two-operand instructions; Procedure ALU_1, which performs ALU and shifting operations for read-modifywrite instructions, which have a single operand; Procedure fill_memory, which fills the memory with instructions and data for test purposes; Process cpu_cycles, which specifies the state sequence for the CPU controller and the actions which occur in each state.
0000011
SP
MARH
MARL
PCH
PCL
Md
CCR
shiftout 8 SHIFTER Opcode ALU control 9 alu9 ALU Op1 8 MUX1 A X Md 0 Op2 8 MUX2 Md 0
CC logic
Cin
process (clk, rst_b) -- this process writes to the port registers begin if (rst_b = '0') then DDRA <= "00000000"; -- set all pins to inputs elsif (rising_edge(clk)) then if (loadDDRA = '1') then DDRA <= DBUS; end if; if (loadPORTA = '1') then PORTA <= DBUS;end if; end if; end process; end port1;
begin CPU: cpu6805 port map (clk, rst_b, irq, SCint, data_bus, addr_bus, wr); PA: PORT_A port map (clk, rst_b, SelPA, addr_bus(0), wr, data_bus, PortA); PB: PORT_A port map (clk, rst_b, SelPB, addr_bus(0), wr, data_bus, PortB); Uart1: UART port map (SelSC, wr, clk, rst_b, RxD, addr_bus(1 downto 0), data_bus, SCint, TxD); LowRAM: ram32X8_io port map (addr_bus(4 downto 0), data_bus, cs1, we); HiRAM: ram32X8_io port map (addr_bus(4 downto 0), data_bus, cs2, we); -- memory interface cs1 <= SelLowRam and not clk; cs2 <= SelHiRam and not clk; we <= wr and not clk; -- select ram on 2nd half of clock cycle -- write enable on 2nd half of clock cycle
CPU
dbus_in
MUX
From Page 416: Summary of steps used to design CPU: 1. 2. 3. 4. 5. 6. 7. Define the register structure, instruction set, and addressing modes. Construct a table which shows the register transfers that take place during each clock cycle. Design the control state machine. Write behavioral VHDL code based on (1), (2), and (3). Simulate execution of the instructions to verify that specifications are met. Work out block diagrams for the major components of the CPU and determine the needed control signals. Rewrite the VHDL based on (5). Again, simulate execution of the instructions. Synthesize the CPU from the VHDL code. Make changes in the VHDL code as needed to improve the synthesis results.