REVISED COURSE OUTLINE FOR THE SUBJECT

VLSI DESIGN TECHNIQUES (CE-410)

COURSE COORDINATOR: SAQIB HUSSAIN SIDDIQUI COURSE TEACHERS: MUHAMMAD NASEEM, HASAN RAZA NAQVI, MUHAMMAD ZEESHAN AHMED KARIM

Batch 2007, Computer Engineering Department

Weeks 1 & 2: Discrete and Integrated Circuits Advantages/disadvantages of ICs IC terminology Scales of integration Moores law IC Economics Yield, Faults and Defects Weeks 3 & 4: Introduction to electronic switch MOS transistor Introduction Types Working as a switch Week #5: Introduction to CMOS logic Implementing logic circuits in CMOS logic Weeks 6 & 7: IC Design Processes Week #8: MID-TERM TEST Weeks 9, 10 & 11: Step-by-step fabrication of a CMOS inverter Week #12: Programmable Logic devices: SPLD & CPLD Programmable switch technologies Implementing logic circuits using SPLDs Week #13: Semiconductor Memories Storage cells of: ROM PROM EPROM EEPROM Flash EPROM SRAM DRAM

Weeks #14: ASICs Advantages of ASICs Types of ASICs ASIC Design cycle Week #15: Programmable Logic implementation: Multiplexer Lookup Tables Weeks #16: Physical design Placement & Routing (P&R) algorithm Future trends in VLSI technology (optional)

COURSE BOOKS:
TEXT: ASICs By: Michael John Sebastian Smith REFERENCE: VLSI DESIGN TECHNIQUES ANALOG & DIGITAL CIRCUITS By: Randall / Geiger / Strader

FOR

Sessional grading: (excluding Practical side)

Best one of two assignments: 10 marks x 1 Best two of three quizzes: 05 Marks x 2 Mid-term (regular): 10 marks Mid-term (compensation): 7.5 marks