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 R.M.D ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING

21EC503 - VLSI DESIGN (Lab Integrated)

Department :Electronics and Communication

Engineering

Batch/Year :2021-2025/III

Created by :Ms.P.Santhoshini
:Ms.S.Gayathri Priya

Date :23.09.2023

4 4
 TABLE OF CONTENTS
S.No Contents Page
Number

1 Course Objectives 7
2 Pre Requisites 8
3 Syllabus 9
4 Course outcomes 11
5 CO- PO/PSO Mapping 15
6 Unit III- Sequential Circuit Design 16
6.1 Lecture Plan 17

6.2 Activity based learning 18

6.3 Lecture Notes 19

6.3.1 Introduction 19

6.3.2 Static Latches Vs Registers 23

6.3.2.1 Multiplexer Based Latches 34
6.3.2.2 Master Slave Edge Triggered Register 36
6.3.2.3 Low-voltage Static Latches 41
6.3.3 Dynamic Latches 44
6.3.4 Pulse Registers 52
6.3.5 Pipelining 57
6.3.6 Schmitt Trigger 63
6.3.7 Mono stable Circuit 65
6.3.8 Astable Circuits 67
6.3.9 Timing Classification of Synchronous Design 69
6.3.10 Design of Sequential Circuits using verilog 73
6.4 Assignments 81
6.5 Part A Q & A 82
6.6 Part B Questions 88
6.7 Supportive online Certification courses 89
6.8 Real time Applications in day to day life and to Industry 90
6.9 Contents beyond the Syllabus 91

5 5
 Table of Contents

S.No Contents Page

Number
7 Assessment Schedule 97

8 Prescribed Text Books & Reference Books 98

9 Mini Project suggestions 99

6 6
 1. COURSE OBJECTIVE

OBJECTIVES:

❖ To study the fundamentals of CMOS circuits and its characteristics.

❖ To learn the design and realization of combinational & sequential digital

circuits.
❖ To study the Architectural choices and performance tradeoffs involved in
designing and realizing the circuits in CMOS technology are discussed.
❖ To learn the different FPGA architectures and testability of VLSI circuits.
❖ To learn Hardware Descriptive Language (Verilog / VHDL) and to
familiarize fusing of logical modules on FPGAs.

7
 2. PRE REQUISITES

1.21EC303 - DIGITAL ELECTRONICS

By learning this course,the student will have a thorough knowledge
about designing combinational and sequential circuits.

2. 21EC404 – LINEAR INTEGRATED CIRCUITS

By learning this course,the student will have deep insight in fabrication
and designing ICs

8
 3. SYLLABUS

Subject Code Subject Name L T P C

21EC503 VLSI Design (Lab 3 0 2 4

Integrated)

UNIT I INTRODUCTION TO MOS TRANSISTOR 15

MOS Transistor, CMOS logic, Inverter, Layout Design Rules, Gate Layouts, Stick
Diagrams, Long-Channel I-V Characteristics, C-V Characteristics, Non ideal I-V
Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay
Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.

LIST OF EXPERIMENTS
1. Design of inverter using LT-SPICE
2. Layout verification of CMOS inverter, NOR and NAND gates

UNIT II COMBINATIONAL MOS LOGIC CIRCUITS 15

Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic,
Dynamic Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail
Domino, CPL, DCVSPG, DPL, CMOS Power Dissipation. Design of combinational
circuits using Verilog.

LIST OF EXPERIMENTS
1. Design of adder and subtractor
2. Design of multiplexer and demultiplexer

UNIT III SEQUENTIAL CIRCUIT DESIGN 15

Static latches and Registers, Dynamic latches and Registers, Pulse Registers,
Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential
Circuits. Timing Issues: Timing Classification of Digital System, Synchronous Design,
Design of sequential circuits using Verilog.

LIST OF EXPERIMENTS
1.Design of Flipflops
2.Design of counter
3. Design of universal shift register
4. Design of Mealy and Moore State Machines
5. Design of random Access Memory

9
UNIT IV DESIGN OF ARITHMETIC BUILDING BLOCKS AND
SUBSYSTEM 15
Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, power
and speed tradeoffs, Designing Memory and Array structures: Memory Architectures
and Building Blocks, Memory Core, Memory Peripheral Circuitry.

LIST OF EXPERIMENTS
1.Design of Arithmetic Logic Unit
2.Design of Ripple Carry Adder
3.Design of Carry Select Adder
4.Design of Multiplier

UNIT V IMPLEMENTATION STRATEGIES AND TESTING 15

FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design
for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Boundary Scan.

10
 4. COURSE OUTCOMES

After successful completion of the course, the students should be

able to

Highest
Course Outcomes Cognitive
Level
Understand the fundamental principles of VLSI circuit design in
CO1 K2
digital domain

CO2 Realize the combinational circuits using different logic families K3

Understand the memory design in sequential logic circuits K3

CO3

Analyze the architectural choice and performance tradeoff

CO4 K3
involved in data path unit design

Understand the different FPGA architectures and its testing K2

CO5

Design, Simulate to verify the functionality of logic modules

CO6 using EDA tools and familiarize fusing of logical modules on K2
FPGA

11
 Program Outcomes(PO)
Program Engineering Graduates will be able to
Outcome
Engineering Apply the knowledge of mathematics,science,engineering
fundamentals, and an engineering specialization to the solution of
PO1 Knowledge
complex engineering problems.

Identify, formulate, review research literature, and analyze complex

Problem
engineering problems reaching substantiated conclusions using first
PO2 Analysis
principles of mathematics, natural sciences, and engineering sciences

Design solutions for complex engineering problems and design

Design/
system components or processes that meet the specified needs with
Development
PO3 appropriate consideration for the public health and safety, and the
of Solutions
cultural, societal, and environmental considerations.

Conduct
Use research-based knowledge and research methods including
Investigations
design of experiments, analysis and interpretation of data, and
PO4 of Complex
synthesis of the information to provide valid conclusions.
Problems

Create, select, and apply appropriate techniques, resources, and

Modern Tool modern engineering and IT tools including prediction and modeling to
PO5 Usage complex engineering activities with an understanding of the
limitations.

Apply reasoning informed by the contextual knowledge to assess

The Engineer
societal, health, safety, legal and cultural issues and the consequent
PO6 and Society
responsibilities relevant to the professional engineering practice.

Environment Understand the impact of the professional engineering solutions in

and societal and environmental contexts, and demonstrate the knowledge
PO7
Sustainability of, and need for sustainable development.

12
 Program Outcomes(PO)
Program Engineering Graduates will be able to
Outcome
Ethics Apply ethical principles and commit to professional ethics and
PO8
responsibilities and norms of the engineering practice
Individual and Function effectively as an individual, and as a member or leader in
Team Work
PO9 diverse teams, and in multidisciplinary settings

Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able
Communication
PO10 to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive
clear instructions
Project Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a
Management
PO11 member and leader in a team, to manage projects and in
and Finance
multidisciplinary environments

Lifelong Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context
PO12 Learning
of technological change.

13
 Program Specific Outcomes(PSO)

Program
Specific Electronics and Communication Engineering Graduates will be
Outcomes able to

To analyze, design and develop solutions by applying

PSO1 foundational concepts of Electronics and Communication
Engineering.

PSO2
To apply design principles and best practices for developing
quality products for scientific and business applications

To adapt to emerging information and communication

PSO3 technologies (ICT) to innovate ideas and solutions to
existing/novel problems.

14
 5. CO- PO/PSO Mapping

Program
Course Level
Outcom of Program Outcomes Specific
es CO Outcomes
K3,K5
K K4 K4 K5 A3 A2 A3 A3 A3 A3 A2 K6 K5 K3
,K6
3
P
PO-
O- PO-2 PO-3 PO-4 PO-6 PO-7 PO-8 9 PO-10 PO-11 PO-12 PSO-1 PSO-2 PSO-3
PO-5
1

CO1 K2 2 1 1 - - - - - - - - - - 1 1

CO2 K3 1 2 - - - - - - - - - - - 2 1

CO3 K3 2 1 2 - - - - - - - - - - 1 1

CO4 K3 1 2 1 - - - - - - - - - - 1 2

CO5 K3 1 2 - - - - - - - - - - - 1 2

CO6 K2 2 1 1 - - - - - - - - - - 1 1

15
 UNIT III SEQUENTIAL CIRCUIT DESIGN

Static latches and Registers, Dynamic latches and Registers,

Pulse Registers, Pipelining, Schmitt Trigger, Monostable
Sequential Circuits, Astable Sequential Circuits. Timing Issues:
Timing Classification of Digital System, Synchronous Design,
Design of sequential circuits using Verilog.

16
 LECTURE PLAN
UNIT III -SEQUENTIAL CIRCUIT DESIGN

S No. Proposed Ac Per Reaso

. of Date tu tai Taxonom Mode of n or
N Per al nin y level Delivery Devia
o Topic iods Da g tion
te CO

Static latches and K3 Chalk

1 -
1 Registers, CO3 Apply and talk

Dynamic latches K3 Chalk

1 -
2 and Registers, CO3 Apply and talk

Dynamic latches K3 Chalk

1 -
3 and Registers, CO3 Apply and talk

K3 Chalk -
1 CO3
4 Pulse Registers Apply and talk

Sense Amplifier K3 Chalk

1 -
5 Based Register, CO3 Apply and talk

Pipelining, Schmitt K3 Chalk

1 -
6 Trigger, CO3 Apply and talk

Monostable K3 Chalk
1 CO3 -
7 Sequential Circuits, Apply and talk

K2
Astable Sequential Chalk
1 CO3 Under -
8 Circuits. and talk
stand
Timing Classification
Of Digital System, Chalk -
K1
Synchronous 1 CO3 and talk
9 Remember
Design.

Total No. of Periods : 9

17 18
 6.2 Activity Based Learning

1. Virtual Simulation:

Implementation of universal shift register using a simulator.

2. Role Play: A group of 10 students are given the following topic and instructed
to demonstrate a role play.

―Difference between foreground and background memory

18 18
 6.3 Lecture Notes
Unit III-SEQUENTIAL CIRCUIT DESIGN

6.3.1 INTRODUCTION:
In Sequential circuits, the output depends not only on the latest inputs, but also
on the condition of earlier inputs.
Sequential circuits contain memory elements.

Fig 3.1 Block Diagram of Sequential Circuit Design

Sequential circuits are of three types −
Bistable
Monostable

Astable

Fig 3.2 Types of Sequential Circuits

Bistable− Bistable circuits have two stable operating points and

will be in either of the states.
Example − Memory cells, latches, flip-flops and registers.
Monostable − Monostable circuits have only one stable
operating point and even if they are temporarily perturbed to
the opposite state, they will return in time to their stable
operating point.
Example: Timers, pulse generators.
Astable − circuits have no stable operating point and oscillate
between several states.
Example − Ring oscillator.

19
 Among these three main groups of regenerative circuit types, the bistable circuits
are by far the most widely used 'and the most important class. All basic latch and
flip-flop circuits, registers, and memory elements used in digital systems fall into
this category.

Synchronous sequential systems, in which all registers are under control of a

single global clock. The outputs of the FSM are a function of the current Inputs
and the Current State. The Next State is determined based on the Current State
and the current Inputs and is fed to the inputs of registers.

On the rising edge of the clock, the Next State bits are copied to the outputs of
the registers (after some propagation delay), and a new cycle begins.

The register then ignores changes in the input signals until the next rising edge.
In general, registers can be positive edge-triggered (where the input data is
copied on the positive edge of the clock) or negative edge-triggered (where the
input data is copied on the negative edge, as is indicated by a small circle at the
clock input).

Timing Metrics for Sequential Circuits:

The set-up time (tsu) is the time that the data inputs (D input) must be
valid before the clock transition (this is, the 0 to 1 transition for a
positive edge-triggered register.

The hold time (thold) is the time the data input must remain valid after
the clock edge.

20
Assuming that the set-up and hold-times are met, the data at the D input is copied
to the Q output after a worst-case propagation delay (with reference to the clock
edge) denoted by tc-q.

Assume that the worst-case propagation delay of the logic equals tplogic, while its
minimum delay (also called the contamination delay) is tcd. The minimum clock
period T, required for proper operation of the sequential circuit is given by

T ≥ tc-q + t plogic +t su

The hold time of the register imposes an extra constraint for proper
operation,

tcdregister
+t
cdlogic
≥ t hold

where tcdregister is the minimum propagation delay (or contamination delay) of

the register

LATCHES VS REGISTERS
A latch is an essential component in the construction of an edge-triggered
register.It is level-sensitive circuit that passes the D input to the Q output
when the clock signal is high. This latch is said to be in transparent mode.

When the clock is low, the input data sampled on the falling edge of the
clock is held stable at the output for the entire phase, and the latch is in

hold mode.

The inputs must be stable for a short period around the falling edge of the
clock to meet set-up and hold requirements.A latch operating under the
above conditions is a positive latch.

Similarly, a negative latch passes the D input to the Q output when the
clock signal is low.

21
 Fig 3.3 Timing of positive and negative latches

A wide variety of static and dynamic implementations exists for the realization of
latches.Contrary to level-sensitive latches, edge-triggered registers only sample the
input on a clock transition 0-to-1 for a positive edge triggered register, and 1-to-0 for a
negative edge-triggered register. They are typically built using the latch primitives.
A most-often recurring configuration is the master-slave structure that cascades a
positive and negative latch. Registers can also be constructed using one-shot generators
of the clock signal (―glitch registers), or using other specialized structures.

22
6.3.2 STATIC LATCHES AND REGISTERS

BISTABILITY PRINCIPLE:
Static memories use positive feedback to create a bistable circuit

a circuit having two stable states that represent 0 and 1.

The basic idea is two inverters connected in cascade along with a
voltage-transfer characteristic typical of such a circuit.

There are two stable states of bistable elements as shown.If the circuit
is initially operating at one of the two stable points, it will preserve this state
unless it is forced externally to change its state.

The gain of each inverter circuit, i.e., the slope of the voltage transfer
curves, is smaller than unity at the two stable operating points.

Fig 3.4 Two cascade inverter and its

VTC.

23
 Thus, in order to change the state by moving the operating point from one
stable point to the other, a sufficiently large external voltage perturbation must
be applied so that the voltage gain of the inverter loop becomes larger than
unity.

In summary, a bistable circuit has two stable states. In absence of any

triggering, the circuit remains in a single state (assuming that the power supply
remains applied to the circuit), and hence remembers a value. A trigger pulse
must be applied to change the state of the circuit. Another common name for a
bistable circuit is flip-flop (unfortunately, an edge-triggered register is also

referred to as a flip-flop).

BASICS OF STATIC LATCHES

Latch is an electronic logic circuit with two stable states i.e. it is a bistable.Latch
has a feedback path to retain the information.Hence a latch can be a memory
device.

Latch can store one bit of information as long as the device is powered on.When
enable is asserted, latch immediately changes the stored information when the
input is changed i.e. they are level triggered devices.It continuously samples the
inputs when the enable signal is on.Latch circuits can work in two states
depending on the triggering signal being high or low:

□ Active – High

□ Active – Low.
In case of Active – High latch circuits, normally both the inputs are low. The
circuit is triggered by a momentary high on either of the inputs.

In case of Active – Low latch circuits, normally both the inputs are high. The
circuit is triggered by a momentary low on either of the inputs.

24
SR LATCH USING NOR GATE
The circuit structure of the simple CMOS SR latch, which has two such
triggering inputs, S (set) and R (reset).
The SR latch is also called an SR flip-flop, since two stable states can be
switched back and forth.
The circuit consists of two CMOS NOR gates. One of the input terminals of
each NOR gate is used to cross-couple to the output of the other NOR gate,
while the second input enables triggering of the circuit.

S R 𝑸𝒏+𝟏 𝑸̅𝒏+𝟏
Operation

0 0 𝑄𝑛 𝑄𝑛 Hold

0 1 1 0 Set

1 0 0 1 Reset

1 1 0 0 Not allowed

Fig 3.5 SR Latch using NOR Gate and its Truth table

CMOS realization of SR latch:

Fig 3.6 Static SR Latch using NOR Gate and its Truth table using CMOS
25
 If the set input (S) is equal to VOH and the reset input (R) is equal to VOL, both of
the parallel-connected transistors Ml and M2 will be on. Consequently, the voltage on
node Q will assume a logic-low level of VOL = 0.

At the same time, both M3 and M4 are turned off, which results in a logic-high
voltage VOH at node Q. If the reset input (R) is equal to VOH and the set input (S) is
equal to VOL, the situation will be reversed (Ml and M2 turned off and M3 and M4
turned on).

When both of the input voltages are equal to VOL' on the other hand, there are two
possibilities. Depending on the previous state of the SR latch, either M2 or M3 will be
on, while both of the trigger transistors MI and M4 are off. This will generate a
logic-low level of VOL = O at one of the output nodes, while the complementary
output node is at VOH.

26
SR LATCH USING NAND GATE

Fig 3.7 SR Latch using NAND Gate and its Truth table

The conclusion is that the NAND-based SR latch responds to active

low input signals, as opposed to the NOR-based SR latch, which
responds to active high inputs.
Note that if both input signals are equal to logic "0," both output
nodes assume a logic-high level, which is not allowed because it
violates the complementarity of the two outputs.
DEPLETION LOAD CIRCUITS OF SR LATCH
The operation point of view is similar to other
implementations of SR Latch but this CMOS circuit
implementation offers a better alternative in terms of static
power dissipation and noise margins.

27
 Fig 3.8 Depletion Load circuits of SR Latch

CLOCKED/EDGE-TRIGGERED LATCHES(FLIP FLOP)

Asynchronous sequential circuits, which will respond to the changes
occurring in input signals at a circuit-delay-dependent time point
during their operation.
To facilitate synchronous operation, the circuit response can be
controlled simply by adding a gating clock signal to the circuit, so that
the outputs will respond to the input levels only during the active
period of a clock pulse.

Fig 3.9 Edge Triggered Latches

It can be seen that if the clock (CK) is equal to logic "0," the
input signals have no influence upon the circuit response.
When the clock input goes to logic " 1," the logic levels applied to
the S and R inputs are permitted to reach the SR latch, and
possibly change its state.
The circuit is strictly level-sensitive during active clock phases,
i.e., any changes occurring. in the S and R input voltages when
the CK level is equal to " 1 " will be reflected onto the circuit
outputs.

28
 Fig 3.10 Clocking of SR Latch

The basic S-R Latch circuit suffers from two basic switching
problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be
avoided.
2. If Set or Reset change state while the enable (EN) input is high the
correct latching action may not occur.
Then to overcome these two fundamental design problems with the
SR Latch, the JK Latch was used.

CLOCKED JK LATCH
The sequential operation of the JK Latch is exactly the same as for
the previous SR Latch with the same Set and Reset inputs. The
difference this time is that the JK Latch has no invalid or forbidden
input states of the SR Latch even when S and R are both at logic 1.

SR
LATCH

K
Latch

Fig 3.11 Clocked J

29
 Fig 3.12 Static JK Latch
The J and K inputs in this circuit correspond to the set and
reset inputs of the basic SR latch.

J K 𝑸𝒏 𝑸’𝒏 S R 𝑸𝒏+𝟏 𝑸’𝒏+𝟏 Operation

0 0 0 1 1 1 0 1 hold
1 0 1 1 1 0
0 1 0 1 1 1 0 1 reset
1 0 1 0 0 1
1 0 0 1 0 1 1 0 set
1 0 1 1 1 0
1 1 0 1 0 1 1 0 toggle
1 0 1 0 0 1

Fig 3.13 Truth Table of JK Latch

When the clock is active, the latch can be set with the input
combination (J = '1," K = "0") & Here, Q=0, Q’=1 , and whereas it
can be reset with the input combination (J = "0," K = "1") & Here
Q=1, Q’=0

30
If both inputs are equal to logic "0," the latch preserves (holds)
its current state.
If, on the other hand, both inputs are equal to " 1 " during the active
clock phase, the latch simply switches its state due to feedback (i.e)., the
output of the circuit will oscillate (toggle) continuously until either the
clock becomes inactive (goes to zero), or one of the input signals goes to
zero.
To prevent this undesirable timing problem, the clock pulse width must
be made smaller than the input-to-output propagation delay of the JK
latch circuit.

RACE AROUND CONDITION

Clocked SR and JK flip-flop has a drawback of timing problem known as
RACE.The condition of RACE arises if the output Q changes its state
before the timing pulse of the clock input has time to go in OFF state.
The timing pulse period (T) should be kept as short as possible to avoid
the problem of timing.In logic circuits, Race condition means ―The
situation at which the two inputs of a logic circuit change at the same
time and that will make the output tentativeǁ.
The inputs are in competition to change the output. It generally happens
in the devices which have the output as the feed-back input of the circuit.
It is an unwanted situation that occurs when a device attempts to
perform two operations at the same time (i.e. changing the state of two
inputs simultaneously).
There are few ways in which we can avoid race around condition like
using a D-Latch or by Edge Triggering or by using Master Slave Flip –
flop.

31
CLOCKED D-LATCH
Data latch or Delay latch (D latch) is one of the simple
latches to store data. It is also called transparent latch.
The race around condition in SR latch that occurs when S = R
= 1 can be avoided in D latch as the R input is replaced with
inverted S which is renamed to D.
Hence there are no illegal or forbidden inputs. In a D latch,
Q is always D.

Fig 3.14 D Latch

The output Q assumes the value of the input D when the

clock is active, i.e., for CK = "1.
When the clock signal goes to zero, the output will simply
preserve its state.
Thus, the CK input acts as an enable signal which allows
data to be accepted into the D-latch.

Fig 3.15 Static D Latch using Transmission

Gates
32
The TG at the input is activated by the CK signal, whereas
the TG in the inverter loop is activated by the inverse of the
CK signal, CK.
Thus, the input signal is accepted (latched) into the circuit
when the clock is high, and this information is preserved as
the state of the inverter loop when the clock is low.
The operation of the CMOS D-latch circuit can be better
visualized by replacing the CMOS transmission gates with
simple switches.

Fig 3.16 D Latch using tri-state inverters

The first tri-state inverter acts as the input switch,

accepting the input signal when the clock is high.
At this time, the second tristate inverter is at its high-
impedance state, and the output Q is following the input
signal.
When the clock goes low, the input buffer becomes inactive,
and the second tristate inverter completes the two- inverter
loop, which preserves its state until the next clock pulse.

33
6.3.2.1 MULTIPLEXER BASED LATCHES
There are many approaches for constructing latches.
One very common technique involves the use of transmission gate
multiplexers.
Below figure shows an implementation of static positive and negative
latches based on multiplexers.

Fig 3.15 Negative and positive latches based on multiplexers.

For a negative latch, when the clock signal is low, the input 0 of the
multiplexer is selected, and the D input is passed to the output. When
the clock signal is high, the input 1 of the multiplexer, which connects
to the output of the latch, is selected. The feedback holds the output
stable while the clock signal is high. Similarly in the positive latch, the
D input is selected when clock is high, and the output is held (using
feedback) when clock is low.
A transistor level implementation of a positive latch based on
multiplexers is, When CLK is high, the bottom transmission gate is on
and the latch is transparent - that is, the D input is copied to the Q
output. During this phase, the feedback loop is open since the top
transmission gate is off. Unlike the SR latch, the feedback does not
have to be overridden to write the memory and hence sizing of
transistors is not critical for realizing correct functionality.

34
The advantage of this approach is the reduced clock load of only two
NMOS devices.

Fig 3.16 Positive latch built using transmission gates.

When CLK is high, the latch samples the D input, while a low clock-signal
enables the feedback-loop, and puts the latch in the hold mode.

While attractive for its simplicity, the use of NMOS only pass transistors
results in the passing of a degraded high voltage of VDD-VTn to the input
of the first inverter.
This impacts both noise margin and the switching performance,
especially in the case of low values of VDD and high values of VTn.

It also causes static power dissipation in first inverter.

Since the maximum input-voltage to the inverter equals VDD-VTn, the
PMOS device of the inverter is never turned off, resulting is a static
current flow.

35
6.3.2.2 MASTER SLAVE EDGE TRIGGERED REGISTER
The most common approach for constructing an edge-
triggered register is to use a master slave configuration.
The register consists of cascading a negative latch (master
stage) with a positive latch (slave stage).
A multiplexer-based latch is used in this particular
implementation, although any latch could be used.
On the low phase of the clock, the master stage is
transparent, and the D input is passed to the master stage
output QM.
During this period, the slave stage is in the hold mode,
keeping its previous value using feedback.
On the rising edge of the clock, the master slave stops
sampling the input, and the slave stage starts sampling.
During the high phase of the clock, the slave stage samples
the output of the master stage (QM), while the master stage
remains in a hold mode.
Since QM is constant during the high phase of the clock, the
output Q makes only one transition per cycle.
The value of Q is the value of D right before the rising edge
of the clock, achieving the positive edge-triggered effect.

Fig 3.18 Multiplexer-based NMOS latch using NMOS-only pass transistors

and The non-overlapping clock

36
 A negative edge-triggered register can be constructed using the same
principle by simply switching the order of the positive and negative latch
(this is, placing the positive latch first).

Fig 3.19 Positive edge-triggered register based on a master-slave configuration.

A complete transistor-level implementation of a the master-slave positive

edge-triggered register is shown in Figure and The multiplexer is
implemented using transmission gates.

Fig 3.20 Master-slave positive edge-triggered register using multiplexers.

When the clock is low (CLK = 1), T1 is on and T2 is off, and the D input is sampled
onto node QM.

During this period, T3 is off and T4 is on and the cross-coupled inverters (I5 , I6 )
holds the state of the slave latch. When the clock goes high, the master stage stops
sampling the input and goes into a hold mode.
T1 is off and T2 is on, and the cross coupled inverters I3 and I4 holds the state of
QM. Also, T3 is on and T4 is off, and QM is copied to the output Q.

37
 TIMING PROPERTIES OF MULTIPLEXER-BASED
MASTER-SLAVE REGISTER
Registers are characterized by three important timing parameters: the
set-up time, the hold time and the propagation delay.It is important to
understand the factors that affect these timing parameters, and develop
the intuition to manually estimate them.
Assume that the propagation delay of each inverter is tpd_inv, and
the propagation delay of the transmission gate is tpd_tx.Also assume that
the contamination delay is 0 and the inverter delay to derive CLK from CLK
has a delay equal to 0.
The set-up time is the time before the rising edge of the clock that the
input data D must become valid.For the transmission gate multiplexer-based
register, the input D has to propagate through I1 , T1 , I3 and I2 before
the rising edge of the clock.
This is to ensure that the node voltages on both terminals of the
transmission gate T2 are at the same value. Otherwise, it is possible for the
cross-coupled pair I2 and I3 to settle to an incorrect value.
The set-up time is therefore equal to 3 *tpd_inv + tpd_tx.The
propagation delay is the time for the value of QM to propagate to the
output Q.
Note that since we included the delay of I2 in the set-up time, the
output of I4 is valid before the rising edge of clock.
Therefore the delay t c-q is simply the delay through T3 and I6 (t c-q
= tpd_tx + tpd_inv).
The hold time represents the time that the input must be held stable
after the rising edge of the clock.

38
 In this case, the transmission gate T1 turns off when clock goes high and
therefore any changes in the D-input after clock going high are not seen
by the input. Therefore, the hold time is 0.
❖ The drawback of the transmission gate register is the high capacitive load
presented to the clock signal.
❖ The clock load per register is important, since it directly impacts the
power dissipation of the clock network.
❖ Ignoring the overhead required to invert the clock signal (since the buffer
inverter overhead can be amortized over multiple register bits), each
register has a clock load of 8 transistors.
❖ One approach to reduce the clock load at the cost of robustness is to
make the circuit ratioed. Figure below shows that the feedback
transmission gate can be eliminated by directly cross coupling the
inverters.
❖ The penalty for the reduced clock load is increased design complexity. The
transmission gate (T1 ) and its source driver must overpower the
feedback inverter (I2 ) to switch the state of the cross-coupled inverter.

Fig 3.21 Reduced load clock load static master-slave register

Another problem with this scheme is the reverse conduction this is, the second
stage can affect the state of the first latch.
When the slave stage is on, it is possible for the combination of T2 and I4 to
influence the data stored in I1 -I2 latch.
As long as I4 is a weak device, this is fortunately not a major problem.

Fig 3.22 Reverse conduction possible in the transmission gate.

39
NON-IDEAL CLOCK SIGNALS
We have assumed that CLK is a perfect inversion of CLK, or in other words,
that the delay of the generating inverter is zero. Even if this were possible,
this would still not be a good assumption. Variations can exist in the wires
used to route the two clock signals, or the load capacitances can vary
based on data stored in the connecting latches. This effect, known as clock
skew is a major problem, and causes the two clock signals to overlap.
Clock-overlap can cause two types of failures, When the clock goes high,
the slave stage should stop sampling the master stage output and go into a
hold mode. However, since CLK and CLK are both high for a short period of
time (the overlap period), both sampling pass transistors conduct and there
is a direct path from the D input to the Q output. As a result, data at the
output can change on the rising edge of the clock, which is undesired for a
negative edge triggered register. The is know as a race condition in which
the value of the output.
If there is clock overlap between CLK and CLK, node A can be driven by
both D and B, resulting in an undefined state.
Those problems can be avoided by using two non-overlapping clocks PHI1
and PHI2 instead, and by keeping the nonoverlap time tnon_overlap
between the clocks large enough such that no overlap occurs even in the
presence of clock-routing delays.
During the nonoverlap time, the FF is in the high-impedance state—the
feedback loop is open, the loop gain is zero, and the input is disconnected.
Leakage will destroy the state if this condition holds for too long a time.
Hence the name pseudo-static: the register employs a combination of
static and dynamic storage approaches depending upon the state of the
clock.

40
 Fig 3.23 Master-slave register based on NMOS-only pass transistors
and its overlapping clock pairs

6.3.2.3 LOW-VOLTAGE STATIC LATCHES

The scaling of supply voltages is critical for low power operation. Unfortunately, certain
latch structures don’t function at reduced supply voltages.

For example, without the scaling of device thresholds, NMOS only pass transistors

don’t scale well with supply voltage due to its inherent threshold drop.

Fig 3.24 Pseudo-static two-phase D register and its Two phase non-overlapping clocks.

41
At very low power supply voltages, the input to the inverter cannot be
raised above the switching threshold, resulting in incorrect evaluation.
Even with the use of transmission gates, performance degrades
significantly at reduced supply voltages Scaling to low supply voltages
hence requires the use of reduced threshold devices.
However, this has the negative effect of exponentially increasing the sub-
threshold leakage power as discussed in Chapter 6. When the registers are
constantly accessed, the leakage energy is typically insignificant compared
to the switching power.
However, with the use of conditional clocks, it is possible that registers are
idle for extended periods and the leakage energy expended by registers
can be quite significant. Many solutions are being explored to address the
problem of high leakage during idle periods.
One approach for this involves the use of Multiple Threshold devices as
shown in Figure below.Only the negative latch is shown here. The shaded
inverters and transmission gates are implemented in low-threshold
devices. The low threshold inverters are gated using high threshold
devices to eliminate leakage.
During normal mode of operation, the sleep devices are tuned on. When
clock is low, the D input is sampled and propagates to the output.When
clock is high, the latch is in the hold mode. The feedback transmission
gate conducts and the cross-coupled feedback is enabled.
Note there is an extra inverter, needed for storage of state when the latch
is in the sleep state.During idle mode, the high threshold devices in series
with the low threshold inverter are turned off (the SLEEP signal is high),
eliminating leakage.
It is assumed that clock is in the high state when the latch is in the sleep
state.

42
The feedback low-threshold transmission gate is turned on and
the cross-coupled high-threshold devices maintains the state of
the latch.

Fig 3.25 Solving the leakage problem using multiple-threshold CMOS

43
6.3.3 DYNAMIC LATCHES

Storage in a static sequential circuit relies on the concept that a cross-

coupled inverter pair produces a bistable element and can thus be
used to memorize binary values.
This approach has the useful property that a stored value remains
valid as long as the supply voltage is applied to the circuit, hence the
name static.The major disadvantage of the static gate, however, is its
complexity.
When registers are used in computational structures that are
constantly clocked such as pipelined data path, the requirement that
the memory should hold state for extended periods of time can be
significantly relaxed.
This results in a class of circuits based on temporary storage of
charge on parasitic capacitors. The principle is exactly identical to the
one used in dynamic logic — charge stored on a capacitor can be
used to represent a logic signal.
The absence of charge denotes a 0, while its presence stands for a
stored 1.
No capacitor is ideal, unfortunately, and some charge leakage is
always present.
A stored value can hence only be kept for a limited amount of time,
typically in the range of milliseconds. If one wants to preserve signal
integrity, a periodic refresh of its value is necessary. Hence the name
dynamic storage.
Reading the value of the stored signal from a capacitor without
disrupting the charge requires the availability of a device with a high
input impedance.

44
 DYNAMIC TRANSMISSION GATE
EDGE TRIGGERED REGISTER:
A fully dynamic positive edge-triggered register based on the master- slave
concept is shown in figure.
When CLK = 0, the input data is sampled on storage node 1, which has an
equivalent capacitance of C1 consisting of the gate capacitance of I1, the
junction capacitance of T1, and the overlap gate capacitance of T1.

Fig 3.26 Dynamic edge-triggered register.

During this period, the slave stage is in a hold mode, with node 2 in a
high impedance (floating) state.
On the rising edge of clock, the transmission gate T2 turns on, and
the value sampled on node 1 right before the rising edge propagates
to the output Q (note that node 1 is stable during the high phase of
the clock since the first transmission gate is turned off).Node 2 now
stores the inverted version of node 1.
This implementation of an edge triggered register is very efficient as it
requires only 8 transistors.The sampling switches can be implemented
using NMOS-only pass transistors, resulting in an even-simpler 6
transistor implementation.

45
The reduced transistor count is attractive for high-performance and
low-power systems.
The set-up time of this circuit is simply the delay of the transmission
gate , and corresponds to the time it takes node 1 to sample the
Dinput.The hold time is approximately zero, since the transmission gate
is turned off on the clock edge and further inputs changes are
ignored.
The propagation delay (tc-q) is equal to two inverter delays plus the
delay of the transmission gate T2.One important consideration for such
a dynamic register is that the storage nodes (i.e., the state) has to be
refreshed at periodic intervals to prevent a loss due to charge
leakage, due to diode leakage as well as sub-threshold currents.
In data path circuits, the refresh rate is not an issue since the
registers are periodically clocked, and the storage nodes are
constantly updated.Clock overlap is an important concern for this
register. Consider the clock waveforms shown in below figure.
During the 0-0 overlap period, the NMOS of T1 and the PMOS of T2
are simultaneously on, creating a direct path for data to flow from the
D input of the register to the Q output.This is known as race condition.
The output Q can change on the falling edge if the overlap period is
large.

Fig 3.27 Impact of non-overlapping clocks

46
𝑪𝟐MOS DYNAMIC REGISTER- A CLOCK SKEW
INSENSITIVE APPROACH:

The following shows an ingenious positive edge-triggered register

based on the master- slave concept which is insensitive to clock
overlap. This circuit is called the C2MOS (Clocked CMOS) register. The
register operates in two phases.
1. CLK = 0 (CLK = 1):
2. The roles are reversed when CLK = 1.

Fig 3.28 C 2MOS master-slave positive edge-triggered register.

It can be stated that the C2MOS latch is insensitive to clock overlaps

because those overlaps activate either the pull-up or the pull-down
networks of the latches, but never both of them simultaneously.
If the rise and fall times of the clock are sufficiently slow, however,
there exists a time slot where both the NMOS and PMOS transistors
are conducting.
This creates a path between input and output that can destroy the
state of the circuit.

47
𝑪𝟐MOS Dynamic Register Operation

CLK = 0 (CLK = 1): The first tri-state driver is turned on, and the master
stage acts as an inverter sampling the inverted version of D on the internal
node X. The master stage is in the evaluation mode. Meanwhile, the slave
section is in a high-impedance mode, or in a hold mode. Both transistors
M7 and M8 are off, decoupling the output from the input. The output Q
retains its previous value stored on the output capacitor CL2.The roles are
reversed when CLK = 1: The master stage section is in hold mode (M3- M4
off), while the second section evaluates (M7-M8 on). The value stored on
CL1 propagates to the output node through the slave stage which acts as
an inverter.
The overall circuit operates as a positive edge-triggered master-slave
register very similar to the transmission-gate based register presented
earlier. However, there is an important difference:
A C2MOS register with CLK-CLK clocking is insensitive to overlap, as long as
the rise and fall times of the clock edges are sufficiently small.
In the (0-0) overlap case, the circuit simplifies to the network shown in
Figure (a) in which both PMOS devices are on during this period. The
question is does any new data sampled during the overlap window
propagate to the output Q. This is not desirable since data should not
change on the negative edge for a positive edge-triggered register.
Indeed new data is sampled on node X through the series PMOS devices
M2-M4, and node X can make a 0-to-1 transition during the overlap period.
However, this data cannot propagate to the output since the NMOS device
M7 is turned off. At the end of the overlap period, CLK=1 and both M7 and
M8 turn off, putting the slave stage is in the hold mode.
Therefore, any new data sampled on the falling clock edge is not seen at
the slave output Q, since the slave state is off till the next rising edge of the
clock.

48
 C2MOS D-FF during overlap periods. No feasible signal path can exist between
In and D, as illustrated by the arrows.

The (1-1) overlap case (Figure b), where both NMOS devices M3 and M7
are turned on, is somewhat more contentious. The question is again if new
data sampled during the overlap period (right after clock goes high)
propagates to the Q output.

A positive edge-triggered register may only pass data that is presented at

the input before the rising edge. If the D input changes during the overlap
period, node X can make a 1-to-0 transition, but cannot propagate to the
output. However, as soon as the overlap period is over, the PMOS M8 is
turned on and the 0 propagates to output. This effect is not desirable. The
problem is fixed by imposing a hold time constraint on the input data, D, or,
in other words, the data D should be stable during the overlap period.

In summary, it can be stated that the C2MOS latch is insensitive to clock

overlaps because those overlaps activate either the pull-up or the pull-down
networks of the latches.

49
 DUAL-EDGE TRIGGERED REGISTERS:
So far, we have focused on edge-triggered registers that sample the input
data on only one of the clock edges (rising or falling).
It is also possible to design sequential circuits that sample the input on both
edges.
The advantage of this scheme is that a lower frequency clock (half of the
original rate) is distributed for the same functional throughput, resulting in
power savings in the clock distribution network. The below figure shows a
modification of the C2MOS register to enable sampling on both edges.

Fig 3.29 C 2MOS master-slave positive edge-triggered register.

3.4.4. True Single-Phase Clocked Register (TSPCR)

In the two-phase clocking schemes described above, care must be
taken in routing the two clock signals to ensure that overlap is
minimized.
While the C2MOS provides a skew- tolerant solution, it is possible to
design registers that only use a single phase clock. The basic single-
phase positive and negative latches are shown in figure.

50
For the positive latch, when CLK is high, the latch is in the
transparent mode and corresponds to two caged inverters;
the latch is non-inverting, and propagates the input to the
output. On the other hand, when C LK = 0, both inverters are
disabled, and the latch is in hold- mode.

Fig 3.30 True Single Phase Latches.

Only the pull-up networks are still active, while the pull-down circuits
are deactivated.
As a result of the dual-stage approach, no signal can ever propagate
from the input of the latch to the output in this mode.
A register can be constructed by caging positive and negative latches.
On the other hand, when CLK = 0, both inverters are disabled, and
the latch is in hold-mode. Only the pull-up networks are still active,
while the pull-down circuits are deactivated.
As a result of the dual-stage approach, no signal can ever propagate
from the input of the latch to the output in this mode. A register can
be constructed by cascading positive and negative latches. The clock
load is similar to a conventional transmission gate register, or C2MOS
register. The main advantage is the use of a single clock phase.
The disadvantage is the slight increase in the number of transistors
12 transistors are required.

51
 6.3.4 PULSE REGISTER
We use the master-slave configuration
edge-triggered register.
to create an

Pulse register is a fundamentally different approach for constructing a

register uses pulse signals.
The idea is to construct a short pulse around the rising (or falling) edge
of the clock.
This pulse acts as the clock input to a latch sampling the input only in a
short window.
Race conditions are thus avoided by keeping the opening time of the
latch very short.
The combination of the glitch generation circuitry and the latch results
in a positive edge-triggered register.

Fig 3.31 Glitch latch - timing generation and register

52
When CLK = 0, node X is charged up to VDD (MN is off since CLKG is
low).
On the rising edge of the clock, there is a short period of time when
both inputs of the AND gate are high, causing CLKG to go high.This in
turn activates MN , pulling X and eventually CLKG low.
The length of the pulse is controlled by the delay of the AND gate and
the two inverters.Note that there exists also a delay between the rising
edges of the input clock (CLK) and the glitch clock (CLKG) — also equal
to the delay of the AND gate and the two inverters.
If every register on the chip uses the same clock generation
mechanism, this sampling delay does not matter.However, process
variations and load variations may cause the delays through the glitch
clock circuitry to be different.
This must be taken into account when performing timing verification
and clock skew analysis.If set-up time and hold time are measured in
reference to the rising edge of the glitch clock, the set-up time is
essentially zero, the hold time is equal to the length of the pulse (if the
contamination delay is zero for the gates), and the propagation delay
(t c-q) equals two gate delays.The advantage of the approach is the
reduced clock load and the small number of transistors required.The
glitch-generation circuitry can be amortized over multiple register bits.
The disadvantage is a substantial increase in verification complexity.
This has prevented a wide-spread use.
Another version of the pulsed register is shown in below figure. This is
attractive, as data can arrive at the register even after the clock goes
high, which means that time is borrowed from the previous cycle.

53
 Fig 3.32 Flow-through positive edge-triggered register.

SENSE AMPLIFIER BASED REGISTER

We have presented two fundamental approaches towards building edge-

triggered registers: the master-slave concept and the glitch technique.
Figure shown below introduces another technique that uses a sense amplifier
structure to implement an edge-triggered register.

Fig 3.33 Flow-through positive edge-triggered

register.
54
Sense-amplifier circuits accept small input signals and amplify them to
generate rail-to-rail swings.
As we will see, sense amplifier circuits are used extensively in
memory cores and in low swing bus drivers to amplify small voltage
swings present in heavily loaded wires.
There are many techniques to construct these amplifiers, with the use
of feedback (e.g., cross-coupled inverters) being one common
approach.
The circuit uses a pre-charged front-end amplifier that samples the
differential input signal on the rising edge of the clock signal.The
outputs of front-end are fed into a NAND cross-coupled SR FF that
holds the data and guarantees that the differential outputs switch
only once per clock cycle.
The differential inputs in this implementation don’t have to have rail-
to-rail swing and hence this register can be used as a receiver for a
reduced swing differential bus.
The core of the front-end consists of a cross-coupled inverter (M5
-M8 ), whose outputs (L1 and L2 ) are pre-charged using devices M9
and M10 during the low phase of the clock.
As a result, PMOS transistors M7 and M8 to be turned off and the
NAND FF is holding its previous state.
Transistor M1 is similar to an evaluate switch in dynamic circuits and
is turned off ensuring that the differential inputs don’t affect the
output during the low phase of the clock.
On the rising edge of the clock, the evaluate transistor turns on and
the differential input pair (M2 and M3 ) is enabled, and the difference
between the input signals is amplified on the output nodes on L1 and
L2 .

55
 Figure 3.34 The need for the shorting transistor M4.

The cross-coupled inverter pair flips to one of its the stable states based on
the value of the inputs. For example, if IN is 1, L1 is pulled to 0, and L2
remains at VDD.

Due to the amplifying properties of the input stage, it is not necessary for the
input to swing all the way up to VDD and enables the use of low swing
signaling on the input wires.

The shorting transistor, M4 , is used to provide a DC leakage path from either

node L3 , or L4 , to ground. This is necessary to accommodate the case
where the inputs change their value after the positive edge of CLK has
occurred, resulting in either L3 or L4 being left in a high-impedance state
with a logical low voltage level stored on the node.

Without the leakage path that node would be susceptible to charging by

leakage currents. The latch could then actually change state prior to the next
rising edge of CLK.

56
6.3.5 PIPELINING
Pipelining is a popular design technique often used to accelerate the
operation of the data paths in digital processors.
The goal of the presented circuit is to compute log (|a - b|), where
both a and b represent streams of numbers, that is, the computation
must be performed on a large set of input values.
The minimal clock period Tmin necessary to ensure correct evaluation
is given as:
Tmin = tc-q + t pd,logic + t su
where tc-q and t su are the propagation delay and the set-up time of the
register, respectively.

Pipelining is a technique to improve the resource utilization, and

increase the functional throughput.
Assume that we introduce registers between the logic blocks. The
result for the data set (a1, b1) only appears at the output after three
clock periods.
Example of pipelined computations.

The combinational circuit block has been partitioned into three

sections, each of which has a smaller propagation delay than the
original function. This effectively reduces the value of the
minimum allowable clock period:

57
Figure 3.35 Datapath for the computation of log(|a + b|). (a) Reference
Circuit (b) Pipelined Version

At that time, the circuit has already performed parts of the

computations for the next data sets, (a2, b2) and (a3,b3). The
computation is performed in an assembly-line fashion, hence the
name pipeline.
The advantage of pipelined operation becomes apparent when
examining the minimum clock period of the modified circuit. The
combinational circuit block has been partitioned into three sections,
each of which has a smaller propagation delay than the original
function.
This effectively reduces the value of the minimum allowable clock
period.

58
LATCH Vs REGISTER BASED PIPELINE
Pipelined circuits can be constructed using level-sensitive latches
instead of edge triggered registers.
Consider the pipelined circuit of below figure. The pipeline system is
implemented based on pass-transistor-based positive and negative
latches instead of edge triggered registers.
That is, logic is introduced between the master and slave latches of a
Master- slave system.

Fig 3.36 Operation of two-phase pipelined circuit using dynamic registers

59
 The CLK-CLK notation to denote a two-phase clock system.
Latch-based systems give significantly more flexibility in
implementing a pipelined system, and often offer higher
performance.
When the clocks CLK and CLK are non-overlapping, correct pipeline
operation is obtained.Input data is sampled on C1 at the negative
edge of CLK and the computation of logic block F starts; the result
of the logic block F is stored on C2 on the falling edge of CLK, and
the computation of logic block G starts.
The non-overlapping of the clocks ensures correct operation.The
value stored on C2 at the end of the CLK low phase is the result of
passing the previous input (stored on the falling edge of C LK on C1)
through the logic function F.
When overlap exists between CLK and CLK, the next input is already
being applied to F, and its effect might propagate to C2 before CLK
goes low (assuming that the contamination delay of F is small).
Which value wins depends upon the logic function F , the overlap
time, and the value of the inputs since the propagation delay is
often a function of the applied inputs.

NORA CMOS- A LOGIC STYLE FOR PIPELINED

STRUCTURE
The latch-basedpipeline circuit can also be implemented
using CMOS latches, as shown in Figure. The operation is similar to
the one discussed above. This topology has one additional,
important property:

60
 Fig 3.37 Pipelined data path using C2MOS latches
A CMOS-based pipelined circuit is race-free as long as all the logic
functions F (implemented using static logic) between the latches are
non inverting.
The reasoning for the above argument is similar to the argument
made in the construction of a C2MOS register. During a (0-0) overlap
between CLK and CLK, all C2MOS latches, simplify to pure pull-up
networks .
The only way a signal can race from stage to stage under this
condition is when the logic function F is inverting, as illustrated in
below figure, where F is replaced by a single, static CMOS inverter.

Fig 3.38 Potential race condition during (0-0) overlap in C2MOS-based design.

Similar considerations are valid for the (1-1) overlap. Based on this
concept, a logic circuit style called NORA-CMOS; it combines CMOS
pipeline registers and NORA dynamic logic function blocks.

61
 Each module consists of a block of combinational logic that can
be a mixture of static and dynamic logic, followed by a CMOS
latch.Logic and latch are clocked in such a way that both are
simultaneously in either evaluation, or hold (precharge) mode.
A block that is in evaluation during CLK = 1 is called a CLK-
module, while the inverse is called a CLK- module.A NORA data path
consists of a chain of alternating CLK and CLK modules.
While one class of modules is pre-charging with its output latch
in hold mode, preserving the previous output value, the other class
is evaluating.Data is passed in a pipelined fashion from module to
module. NORA offers designers a wide range of design choices.
Dynamic and static logic can be mixed freely, and both CLKp
and CLKn dynamic blocks can be used in caged or in pipelined
form.With this freedom of design, extra inverter stages, as required
in DOMINO-CMOS, are most often avoided.
In order to ensure correct operation, two important rules
should always be followed,the dynamic-logic rule: Inputs to a
dynamic CLKn (CLKp) block are only allowed to make a single 0🡪1
(1🡪0) transition during the evaluation period.
The CMOS rule: In order to avoid races, the number of static
inversions between CMOS latches should be even.

62
 NON-BISTABLE SEQUENTIAL CIRCUITS
One of the interesting regenerative circuit is the Schmitt
trigger.
This component has the useful property of showing
hysteresis in its dc characteristics—its switching
threshold is variable and depends upon the direction of
the transition (low-to-high or high-to-low).
This peculiar feature can come in handy
in noisy environments.

6.3.5. SCHMITT TRIGGER

A.Schmitt trigger is a device with two important

properties:
2. It responds to a slowly changing input waveform with
a fast transition time at the output.
3. The voltage-transfer characteristic of the device
displays different switching thresholds for positive-
and negative- going input signals. The switching
thresholds for the low-to- high and high to-low
transitions are called VM+ and VM- , respectively. The
hysteresis voltage is defined as the difference
between the two.
One of the main uses of the Schmitt trigger is to turn a
noisy or slowly varying input signal into a clean digital
output signal. This is illustrated in Figure below. Notice
how the hysteresis suppresses the ringing on the signal.
At the same time, the fast low-to-high (and high to-low)
transitions of the output signal should be observed. For
instance, steep signal slopes are beneficial in reducing
power consumption by suppressing direct-path
currents.
The ―secretǁ behind the Schmitt trigger concept is the
6 63
3
use of positive fee d back.
 Fig 3.39 Non-inverting Schmitt trigger.

One possible CMOS implementation of the Schmitt trigger is shown in

below Figure.

Fig 3.40 CMOS Schmitt trigger

The idea behind this circuit is that the switching threshold of a

CMOS inverter is determined by the (kn /kp ) ratio between the
NMOS and PMOS Transistors.
Increasing the ratio results in a reduction of the threshold, while
decreasing it results in an increase in VM.
Adapting the ratio depending upon the direction of the transition
results in a shift in the switching threshold and a hysteresis
effect. This adaptation is achieved with the aid of feedback.
Suppose that Vin is initially equal to 0, so that Vout = 0 as well.
The feedback loop biases the PMOS transistor M4 in the
conductive mode while M3 is off.

64
 Fig 3.41 Noise suppression using a Schmitt trigger.
The input signal effectively connects to an inverter consisting of two
PMOS transistors in parallel (M2 and M4 ) as a pull-up network, and
a single NMOS transistor (M1 ) in the pull-down chain.
This modifies the effective transistor ratio of the inverter to kM1
/(kM2+kM4 ), which moves the switching threshold upwards. Once
the inverter switches, the feedback loop turns off M4 , and the
NMOS device M3 is activated.
This extra pull-down device speeds up the transition and produces a
clean output signal with steep slopes.
A similar behavior can be observed for the high-to-low transition. In
this case, the pull-down network originally consists of M1 and M3 in
parallel, while the pull-up network is formed by M2 .
This reduces the value of the switching threshold to VM–

6.3.6 MONOSTABLE CIRCUITS

A monostable element is a circuit that generates a pulse of
a predetermined width every time the quiescent circuit is
triggered by a pulse or transition event. It is called
monostable because it has only one stable state (the
quiescent one).
65
A trigger event, which is either a signal transition or a pulse, causes
the circuit to go temporarily into another quasi-stable state.
This means that it eventually returns to its original state after a time
period determined by the circuit parameters.
This circuit, also called a one-shot, is useful in generating pulses of a
known length. This functionality is required in a wide range of
applications.
One example of a one-shot in the construction of glitch registers.
Another notorious example is the address transition detection (ATD)
circuit, used for the timing generation in static memories.
This circuit detects a change in a signal, or group of signals, such as
the address or data bus, and produces a pulse to initialize the
subsequent circuitry. T
he most common approach to the implementation of one- shots is the
use of a simple delay element to control the duration of the pulse.
In the quiescent state, both inputs to the XOR are identical, and the
output is low.
A transition on the input causes the XOR inputs to differ temporarily
and the output to go high.
After a delay td (of the delay element), this disruption is removed,
and the output goes low again.
A pulse of length td is created. The delay circuit can be realized in
many different ways, such as an RC-network or a chain of basic
gates.

66
 Fig 3.42 Transition-triggered one-shot.

6.3.7 ASTABLE CIRCUITS

An astable circuit has no stable states.
The output oscillates back and forth between two quasi-
stable states with a period determined by the circuit topology
and parameters (delay, power supply, etc.).
One of the main applications of oscillators is the on-chip
generation of clock signals.
The ring oscillator is a simple, example of an astable circuit.
It consists of an odd number of inverters connected in a
circular chain.
Due to the odd number of inversions, no stable operation
point exists, and the circuit oscillates with a period equal to 2
´ tp ´ N, with N the number of inverters in the chain and tp
the propagation delay of each inverter.
The ring oscillator composed of cascaded inverters produces
a waveform with a fixed oscillating frequency determined by
the delay of an inverter in the CMOS process.
In many applications, it is necessary to control the frequency
of the oscillator. An example of such a circuit is the voltage-
controlled oscillator (VCO), whose oscillation frequency is a
function (typically non-linear) of a control voltage

67
 The standard ring oscillator can be modified into a VCO by
replacing the standard inverter with a current-starved
inverter.
The mechanism for controlling the delay of each inverter is
to limit the current available to discharge the load
capacitance of the gate.

Fig 3.43 Simulated waveforms of five-stage ring oscillator. The outputs of stages 1,
3, and 5 are shown
In this modified inverter circuit, the maximal discharge
current of the inverter is limited by adding an extra series
device.
Note that the low-to-high transition on the inverter can also
be controlled by adding a PMOS device in series with M2 .
The added NMOS transistor M3 , is controlled by an analog
control voltage Vcntl, which determines the
discharge current. Lowering Vcntl reduces available the
current and, hence, increases tpHL. discharge
The ability to alter the propagation delay per stage allows us
to control the frequency of the ring structure.The control
voltage is generally set using feedback
techniques.
Under low operating current levels, the
current-starved inverter suffers from slow fall times at its
output.

68
 This can result in significant short-circuit current.
This is resolved by feeding its output into a CMOS inverter or
better yet a Schmitt trigger.
An extra inverter is needed at the end to ensure that the
structure oscillates.

Fig 3.44 Voltage-controlled oscillator based on current-starved inverters.

6.3.8 TIMING ISSUES

1. TIMING CLASSIFICATION OF SYNCHRONOUS DESIGN
The following timing parameters characterize the timing of
the sequential circuit.
□The contamination (minimum) delay tc-q,cd, and maximum
propagation delay of the register tc-q.
□The set-up (tsu) and hold time (thold) for the registers.
□The contamination delay tlogic,cd and maximum delay tlogic of
the combinational logic.

69
 tclk1 and tclk2, corresponding to the position of the rising
edge of the clock relative to a global reference.

❖ CLOCK NON-IDEALITIES
Clock skew
Spatial variation in temporally equivalent clock edges
deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the clock
signal; modulation + random noise
Cycle-to-cycle (short-term) tJS Long term tJL
Variation of the pulse width
Important for level sensitive clocking.

❖ CLOCK SKEW AND JITTER

Both skew and jitter affect the effective cycle
time. Only skew affects the race margin.

❖ Sources of Skew and Jitter

Clock-Signal Generation- The generation of the clock signal
itself causes jitter
Manufacturing Device Variations
Interconnect Variations -One important source of
interconnect variation is the Inter-level Dielectric (ILD)
thickness variations.
Environmental Variations -Environmental variations are
probably the most significant and primarily contribute to skew
and jitter. The two major sources of environmental variations
are temperature and power supply. Power supply variations is
the major source of jitter in clock distribution networks.
70
Capacitive Coupling -The variation in capacitive load also
contributes to timing uncertainty. There are two major sources
of capacitive load variations: coupling between the clock lines
and adjacent signal wires and variation in gate capacitance.

CHOOSING A CLOCKING STRATEGY

A crucial decision that must be made in the earliest phases of
a chip design is to select the appropriate clocking
methodology.
The reliable synchronization of the various operations
occurring in a complex circuit is one of the most intriguing
challenges facing the digital designer of the next decade.
Choosing the right clocking scheme affects the functionality,
speed and power of a circuit.
The most robust and conceptually simple scheme is the two-
phase master-slave design.
The predominant approach is use the multiplexer-based
register, and to generate the two clock phases locally by
simply inverting the clock. More exotic schemes such as the
glitch register are also used in practice.
However, these schemes require significant hand tuning and
must only be used in specific situations.
An example of such is the need for a negative setup time to
cope with clock skew.
The general trend in high-performance CMOS VLSI design is
therefore to use simple clocking schemes, even at the
expense of performance.

71
Most automated design methodologies such as standard cell
employ a single-phase, edge-triggered approach, based on
static flip-flops.
But the tendency towards simpler clocking approaches is
also apparent i high-performance designs such as
microprocessors.
The use of latches between logic is also very common to
improve circuit performance.

72
6.3.9 Design of Sequential Circuits using Verilog

In the previous sections, we saw how combinational circuits are modeled. They
can be designed using SSI/MSI gates, ROM, PLA, or PAL. Ideally, the response
of a combinational circuit is immediate with changes of inputs. In reality, the res-
ponse is delayed by the propagation delays of the gates as well as the interconnect
delays. A sequential circuit is, in general, a cluster of combinational circuit con-
nected to a register, which stores the combinational circuit output prevailing at the
time of rising edge (or the falling edge) of a clock. The output of a sequential cir-
cuit is a function of the inputs as well as the state of the stored value in the regis-
ter. The output of a sequential circuit depends on the present inputs as well as on
the past inputs. The register may be a RS flip-flop, a D flip-flop, a JK flip-flop, or
a T flip-flop. These flip-flops will be described in later sub-sections. The sequen-
tial circuits are referred to as synchronous circuits as they work in tandem with the
clock. A block diagram of a sequential circuit is shown in Figure 3.45. It consists of
combinational circuits to which registers are connected, with register outputs fed
back. The storage elements are flip-flops, capable of storing binary information.

RS Flip-flop
The flip-flops are binary cells, each capable of storing one bit of information. A flip-
flop circuit can maintain a binary state ‘0’ or ‘1’ so long as power is applied to the
circuit or until directed by an input signal to change state. A common type of flip-
flop is called a RS flip-flop or a SR latch. The R and S are the two inputs that are
abbreviations for reset and set respectively. Figure3.46 shows an RS flip-flop circuit
using NOR gates. When S = 1 and R = 0, the flip-flop is set, i.e., Q is set to ‘1’ and
Q′ is reset. Similarly, when S = 0 and R = 1, the flip-flop is reset. The flip-flop is in
store mode for SR = 00 and stores whatever was the previous state as can be seen
from the truth table. It may be noted that SR = 11 is an invalid input since the
corresponding outputs Q and Q′ must be complement of each other instead of ‘0’
each. The RS flip-flop may also be realized by using NAND gates instead of NOR
gates. The logic diagram and its truth table are shown in Figure 3.47. This flip-flop
can be set and reset by applying the inputs SR = 01 and 10 respectively. SR = 11 is
the store mode, while 00 input is invalid. These circuits are asynchronous.

Outputs
Inputs
Combinational Next State Value(s)
circuits
Register(s)
Clock

Fig. 3.45 Block diagram of a sequential circuit

73
R S R Q Q’
Q
1 0 1 0 (after S =1, R = 0)
0 0 1 0
0 1 0 1
0 0 0 1 (after S =0, R = 1)
1 1 0 0
Q’
S

a Logic Circuit b Truth table

Fig. 3.46 RS flip-flop circuit using NOR gates

S S R Q Q’
Q
1 0 0 1
1 1 0 1 (after S =1, R = 0)
0 1 1 0
1 1 1 0 (after S =0, R = 1)
Q’
R 0 0 1 1

a Logic diagram b Truth table

Fig. 3.47 RS flip-flop circuit using NAND gates

Synchronous RS flip-flop can be built by providing a clock input that deter-

mines when the state of the circuit is to be changed. The RS flip-flop with a clock
input in shown in Figure 3.48a. Q(n) and Q(n + 1) stand for the state of the flip-flop
before and after the application of a clock pulse and are referred to as the present
and the next state respectively. As shown in the truth table in Figure 3.48b, for the
inputs S and R and the present state Q(n), the application of a single pulse causes
the flip-flop to go to the next state, Q(n + 1). The last two lines are indeterminate
and should not be allowed. This can be met if SR = 0. The characteristic equation
of the flip-flop is derived from the K map shown in Figure3 . 4 8 c . This specifies
the value of the next state as a function of the inputs and the present state. The
clocked RS flip-flop may be represented symbolically as shown in Figure 3.48 d.

74
 S R Q(n) Q(n+1)

0 0 0 0
S 0 0 1 1
Q 0 1 0 0
0 1 1 0
Clk 1 0 0 1
1 0 1 1
1 1 0 Indeterminate
Q’ 1 1 1 Indeterminate
R

a Logic Diagram b Characteristic Table

SR S
Q 00 01 11 10
0 0 0 X 1

1 1 0 X 1 S Q

Clk
R’Q
R Q’
Q(n+1) = S+R’Q
SR = 0

c Characteristic Equation d Symbol

Fig .3.48 Clocked RS flip-flop

JK Flip-flop
A negative edge triggered JK flip-flop in master–slave configuration is shown in
Figure 3.49. The 74LS73 is a commercially available negative triggered dual flip-
flop with individual JK inputs. In addition to the J and K inputs, the JK flip-flop has
Clock and direct Reset inputs. Positive pulse triggered JK flip-flops such as 7473
and 74H73 are also available commercially. JK information is loaded into the master
while the Clock is HIGH and transferred to the slave on the HIGH-to-LOW Clock
transition. For these devices the J and K inputs should be stable while the Clock is
HIGH for conventional operation. The J and K inputs must be stable one setup time
prior to the HIGH-to-LOW Clock transition for predictable operation. The Reset
(RD′) is an asynchronous active LOW input. When LOW, it overrides the Clock
and the data inputs forcing the Q output LOW and the Q′ output HIGH. The truth
table of JK flip-flop is shown in Table

75
 J Q

CP

K RD Q

Q Q

RD

K J

Clk

Fig. 3.49 Clocked JK flip-flop

Table Truth table of JK flip-flop

Inputs Outputs
Operating Mode
RD CP J K Q Q

Asynchronous Reset (Clear) L X X X L H

Toggle H h h q
q
Load ‘0’ (Reset) H l h L H

Load ‘1’ (Set) H h l H L

Hold ‘no change’ H l l q q

76
Notes:

H = HIGH voltage level steady state.

L = LOW voltage level steady state.
h = HIGH voltage level one setup time prior to the HIGH-to-LOWClock
transition.
l = LOW voltage level one setup time prior to the HIGH-to-LOW Clock
transition.
X = Don’t care.
q = Lower case letters indicate the state of the referenced output prior to the
HIGH-to-LOW Clock transition.
= Positive Clock pulse.

D Flip-flop
The “74LS74” is a dual positive edge triggered D type flip-flop featuring individual
data, clock, set, and reset inputs and complementary Q and Q′ outputs. Set (SD′)
and Reset (RD′) are asynchronous active low inputs and operate independently
of the clock input. Information on the data (D) input is transferred to the Q

D S Q

R Q

SD

RD Q

Q
Clk

Fig. 3.50 D flip-flop

77
Truth table of D flip-flop

Inputs Outputs
Operating Mode
SD RD CP D Q Q
Asynchronous Set L H X X H L

Asynchronous Reset (Clear) H L X X L H

Undetermined L L X X H H

Load ‘1’ (Set) H H 🠅 h H L

Load ‘0’ (Reset) H H 🠅 l L H

H = HIGH voltage level steady state.

L = LOW voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH Clock
transition.
l = LOW voltage level one setup time prior to the LOW-to-HIGH Clock
transition.
X = Don’t care.

output on the LOW-to-HIGH (rising edge) transition of the clock pulse. The D
inputs must be stable one setup time prior to the LOW-to-HIGH clock transition
for predictable operation. Although the clock input is level sensitive, the positive
transition of the clock pulse between 0.8 V and 2.0 V levels should be equal to or
less than the clock to output delay time for reliable operation. Figure 2.30 shows
the logic diagram and the circuit diagram of a D flip-flop. The truth table of D flip-
flop is presented in Table.

T Flip-flop
A toggle or T flip-flop is a single input alternative to a JK flip-flop. The T flip-
flop can be realized by using an RS flip-flop and two AND gates to gate the inputs
T and the clock as shown in the logic circuit diagram in Figure 2.31a. As the name
implies, the output can be toggled by setting the T input as shown in the character-
istic table in Figure 2.31b. On the other hand, the next state output Q(n + 1) fol-
lows the previous (state) output Q(n) if T is low. The characteristic equation may
be obtained from K map as shown in Figure 2.31c.
We have covered four types of flip-flops, RS, JK, D, and T, whose symbols are
shown in Figure 3.52. Table shows the corresponding characteristics table. These
tables may be re-arranged as what are known as excitation tables shown in Table
From these tables, we can get the desired input(s) corresponding to a set of present
state Q(n) and next state Q(n + 1) conditions. This helps in the systematic

78
design of the logic circuit diagram for an application. We will consider a number
of applications using these flip-flops in Section 2.15.

T
Q

Clk

Q’

a Logic Diagram

T
T Q(n) Q(n+1) 0 1
Q(n)
0 0 0 0 0 1
0 1 1
1 0 1 1 1 0
1 1 0
Q(n+1) = TQ(n)’+T’Q(n)

b Characteristic Table c Characteristic Equation

Fig3.51 T flip-flop

S Q J Q D Q T Q

CLK CLK CLK CLK

R Q’ K Q’ Q’
Q’

RS FF JK FF D FF T FF

Fig. 3.52 Symbols for flip-flops

79
Table Characteristic tables of flip-flops

RS flip-flop JK flip-flop

S R Q(n + 1) Condition J K Q(n + 1) Condition

0 0 Q(n) No change 0 0 Q(n) No change
0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 ? Unpredictable 1 1 Q′(n) Complement

D flip-flop T flip-flop

D Q(n + 1) Condition T Q(n + 1) Condition

0 0 Reset 0 Q(n) No change
1 1 Set 1 Q′(n) Complement

Table Excitation tables of flip-flops

RS FF JK FF

Q(n) Q(n + 1) S R Q(n) Q(n + 1) J K

0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 1 X 0 1 1 X 0

D FF T FF

Q(n) Q(n + 1) D Q(n) Q(n + 1) T

0 0 0 0 0 0
0 1 1 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0

80
 6.4 Assignment

Assignments ( For higher level learning and Evaluation -

Examples: Case study, Comprehensive design, etc.,)
UNIT III
CO BT
Q.No Questions
Level Level
Figure shows one possible implementation of the clock
generation circuitry for generating a two-phase non-
overlapping clocks. Assuming that each gate has a unit gate
delay, derive the timing relationship between the input clock
and the two output clocks. What is the nonoverlap period?
How can this period be increased if needed?

1. CO3 K3

A CMOS Schmitt trigger is shown in Figure .Discuss the

operation of the gate, and derive expressions for VM- and
VM+.

2. CO3 K3

81
 6.5 Part A Q & A
Unit-III Sequential Circuit Design

S.N Question and Answers CO K

o
1 Define sequential circuits. CO3 K1
A sequential circuit is an interconnection of flip-flops and gates. The
gates by themselves constitute a combinational circuit, but when
included with the flip flops, the overall circuit is classified as a sequential
circuit.
2 Define pipelining. CO3 K1
Pipelining is a technique of decomposing a sequential process into sub
operations with each subprocess being executed in a special dedicated
segment that operates concurrently with all other segments
3 What is latch? CO3 K1

A latch is a level sensitive circuit that passes the D input to the Q output
when the clock signal is high.

4 What is register? CO3 K1

Registers is a edge triggering device which samples the input only on
the clock transition . Depending on the transition it may positive edge
triggered register and negative edge triggered register.

5 Compare & Contrast synchronous design and CO3 K2

asynchronous design
Synchronous Sequential Circuit: Output changes at discrete interval
of time. It is a circuit based on an equal state time or a state time
defined by external means such as clock. Examples of synchronous
sequential circuit are Flip Flops, Synchronous Counter.

Asynchronous Sequential Circuit: Output can be changed at any

instant of time by changing the input. It is a circuit whose state time
depends solely upon the internal logic circuit delays. Example of
asynchronous sequential circuit is Asynchronous Counter.

82
 6.5 Part A Q & A
Unit-III Sequential Circuit Design

S.N Question and Answers CO K

o
6. Draw the schematic of dynamic edge-triggered register. CO3 K1

7. Difference between latch and flip-flop. CO3 K2

8 List out the techniques used for low power CO3 K1

logic design.

□To reduce the dynamic power, supply voltage VDD is

reduced. The transistors with minimum size can be used to
reduce the capacitances.
□The power dissipation due to short circuit current is
minimized by matching the rise time/fall times of the input
and output signals.
□Proper layout techniques are used to minimize routing
capacitances

83
 6.5 Part A Q & A
Unit-III Sequential Circuit Design

S.No Question and Answers CO K

9 Draw the switch level schematic of multiplexer based nMOS CO3 K1

latch using nMOS only pass transistors for multipliers.

10 What is clocked CMOS registers. CO3 K1

The dynamic latch can also be drawn as a clocked tristate.

Such a form is sometimes called clocked CMOS (C2MOS) the
output is driven through the nMOS and pMOS working in
parallel. C2MOS is slightly smaller because it eliminates two
contacts.
11 What is Dynamic CMOS logic ? CO3 K1
Dynamic circuits rely on the temporary storage of signal values on the
capacitance of high impedance node.
□ Requires only N+2 transistors.
□ Takes a sequence of precharge and conditional evaluation phases to
realizes logic functions.
12 What are the properties of Dynamic logic ? CO3 K1
Logic function is implemented by pull-down network only.
□ Full swing outputs (VOL= GND and VOH = VDD).
□ Non-ratioed.
□ Faster switching speeds.
□ Needs a precharge clock.
13. What is CMOS Domino logic ? CO3 K1
A static CMOS inverter placed between dynamic gates which eliminate
the monotonicity problem in dynamic circuits are called CMOS Domino
logic.

84
 6.5 Part A Q & A
Unit-III Sequential Circuit Design
S.No Question and Answers CO K

14 Define propagation delay and contamination delay? CO3 K1

Propagation delay(t pd): The amount of time needed for a change in a

logic input to result in a permanent change at an output, that is the
combinational logic will not show any further output changes in
response to an input change .

Contamination delay(tcd): The amount of time needed for a change in

a logic input to result in an initial change at an output, that is the
combinational logic is guaranteed not to show any output change in
response to an input change before fed time units have passed.

15 Define Setup time and Hold time. CO3 K1

Setup time (t setup): The amount of time before the clock edge that
data input D must be stable the rising clock edge arrives.

Hold time (t hold): This indicates the amount of time after the clock
edge arrives the data input D must be held stable in order for FF to
latch the correct value. Hold time is always measured from the rising
clock edge to a point after the clock edge.
16 What is bistability Principle? CO3 K1

Static memories use positive feedback to create a bistable circuit — a

circuit having two stable states that represent 0 and 1. The basic idea
is shown in Figure which shows two inverters connected in cascade
along with a voltage-transfer characteristic typical of such a circuit.

17 Draw the positive negative latch using transmission gates? CO3 K2

85
7
7
 6.5 Part A Q & A
Unit-III Sequential Circuit Design
S.No Question and Answers CO K

18. What is race condition ? CO3 K1

Since CLK and CLK are both high for a short period of time (the
overlap period), both sampling pass transistors conduct and there is a
direct path from the D input to the Q output. As a result, data at the
output can change on the rising edge of the clock, which is undesired
for a negative edge triggered register. The is know as a race condition.

19 What is 𝑪𝟐MOS Register? CO3 K1

The 𝐶2 MOS (Clocked CMOS) register: A C2MOS register with CLK-CLK
clocking is insensitive to overlap, as long as the rise and fall times of
the clock edges are sufficiently small.
20 What is TSPCR? CO3 K1
The True Single-Phase Clocked Register (TSPCR). For the positive
latch, when CLK is high, the latch is in the transparent mode and
corresponds to two cascaded inverters; the latch is non-inverting, and
propagates the input to the output. On the other hand, when CLK = 0,
both inverters are disabled, and the latch is in hold-mode.
21 What are pulse registers? CO3 K1
The idea is to construct a short pulse around the rising (or falling)
edge of the clock. This pulse acts as the clock input to a latch,
sampling the input only in a short window. Race conditions are thus
avoided by keeping the opening time (i.e, the transparent period) of
the latch very short. The combination of the glitch generation circuitry
and the latch results in a positive edge-triggered register.
22 What are the timing metrics of pulse registers? CO3 K1
If set-up time and hold time are measured in reference to the rising
edge of the glitch clock, the set-up time is essentially zero, the hold
time is equal to the length of the pulse (if the contamination delay is
zero for the gates), and the propagation delay (tc-q) equals two gate
delays.
23 What is meant by sense amplifier? CO3 K1
Sense-amplifier circuits accept small input signals and amplify them
to generate rail-to-rail swings. sense amplifier circuits are used
extensively in memory cores and in low swing bus drivers to amplify
small voltage swings present in heavily loaded wires.

86
 6.5 Part A Q & A
Unit-III Sequential Circuit Design
S.No Question and Answers CO K

24 What is NORA-CMOS? CO3 K1

The latch-based pipeline circuit can also be implemented using 𝑪𝟐 MOS
latches. a logic circuit style called NORA-CMOS was conceived It
combines C2MOS pipeline registers and NORA dynamic logic function
blocks. Each module consists of a block of combinational logic that can
be a mixture of static and dynamic logic, followed by a 𝑪𝟐 MOS latch.

25 What are the types of non bistabe sequential circuits? CO3 K1

Schmitt trigger, Monostable Sequential Circuits and Astable circuits.

26 What is the idea behind the implementation of schmitt CO3 K2

triggers using CMOS?
The idea behind this circuit is that the switching threshold of a CMOS
inverter is determined by the (kn/kp) ratio between the NMOS and
PMOS transistors. Increasing the ratio results in a reduction of the
threshold, while decreasing it results in an increase in VM. Adapting
the ratio depending upon the direction of the transition results in a
shift in the switching threshold and a hysteresis effect. This adaptation
is achieved with the aid of feedback.

87
 6.6 Part B Questions

S.No Questions CO K
1 CO3 K2
Discuss in detail about
(i) Master-Slave Edge-Triggered Register.
(ii)Timing properties of Multiplexer-Based Master-Slave
registers.

2 CO3 K2
Write short notes on:
(i) Multiplexer-Based Latches
(ii) Low-Voltage Static Latches.
3 Explain the working of C2MOS Register with CLK-CLK clocking CO3 K2
approach.
4 Draw and explain about True Single-Phase Clocked CO3 K2
Register (TSPCR) and TSPC Edge-Triggered register
5 Illustrate the following Alternative Register styles. CO3 K2
(i) Pulse Registers. (ii) Sense-Amplifier-Based Registers.
6 Discuss in detail about various Pipelining techniques and CO3 K2
explain in detail.
7 Illustrate the following. CO3 K2
(i) Latch versus Register based pipeline
(i i) NORA-CMOS logic style for pipelined structures.
8 (i)Write about Schmitt trigger and its properties. CO3 K2
(ii)Describe Schmitt trigger and its CMOS implementation
with neat diagram
9 Analyse the basics of synchronous timing, clock skew, clock CO3 K4
jitter and combined impact of skew and jitter.

10 Draw and explain about Master-Slave Edge-Triggered CO3 K2

register with its timing properties and Non-ideal clock
signals
11 Design the following circuits and illustrate its working: CO3 K2
(i)Dynamic transmission-gate edge-triggered registers.
(ii)C2MOS -A clock-skew insensitive approach.
(iii)True single-phase clocked register
12 Implement the following Non bistable sequential circuits and CO3 K2
explain in detail.
(i) Schmitt Trigger
(ii)Monostable Sequential Circuits
(iii)Astable Circuits

88
6.7 Supportive online Certification courses (NPTEL, Swayam, Coursera,
Udemy, etc.,) for EC8095 VLSI DESIGN

S.nO Name of the Course Name of the Duration Link

online platform
1 MOS Transistor Coursera 18 hours https://www.cours
era.org/learn/mosf
et
2 CMOS Digital VLSI NPTEL 8 weeks https://onlinecours
Design es.nptel.ac.in/noc2
1_ee09/preview
3 VSD Custom Layout Udemy 4.5 https://www.udem
hours y.com/course/vlsi-
academy-custom-
layout/
4 VSD Physical Design Udemy 5 hours https://www.udem
Flow y.com/course/vlsi-
academy-physical-
design-flow/

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 Supportive Link to Videos
UNIT III

S.No Topic Link

Sequential logic circuit-Part 1 https://www.youtube.com/watch?v=

1 yndN_m9L5qI
Sequential logic circuit-Part 2 https://www.youtube.com/watch?v=
2 o8TyiMEWCk0
https://nptel.ac.in/courses/108/107
Sequential Logic Design -I
3 /108107129/

Sequential Logic Design -II https://nptel.ac.in/courses/108/107

4 /108107129/

Sequential Logic Design -III https://nptel.ac.in/courses/108/107

5 /108107129/

https://www.youtube.com/watch?v
6 Schmitt Trigger using CMOS
=p8GGUzIo1e8

Dynamic CMOS, Transmission https://www.youtube.com/watch?v

7 Gates; Realization Of MUX,
Decoder, D-F/F =q8adOpQx7tc

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6.8 Real time Applications in day to day life and to
Industry

1. MAS: Maximum Energy-Aware Sense Amplifier Link for Asynchronous

Network on Chip
2.Sense Amplifiers for flash memories

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 6.9 Contents beyond the Syllabus
Unit III- Sequential Circuit Design

SRAM Design and Working

Objectives: In this section you will learn the following

• SRAM Basics
• CMOS SRAM Cell
• CMOS SRAM Cell Design
• READ Operation
• WRITE Operation
SRAM Basics:
The memory circuit is said to be static if the stored data can be retained indefinitely,
as long as the power supply is on, without any need for periodic refresh operation.
The data storage cell, i.e., the one-bit memory cell in the static RAM arrays,
invariably consists of a simple latch circuit with two stable operating points.
Depending on the preserved state of the two inverter latch circuit, the data being
held in the memory cell will be interpreted either as logic '0' or as logic '1'. To access
the data contained in the memory cell via a bit line, we need atleast one switch,
which is controlled by the corresponding word line as shown in Figure 1.

Figure 1. SRAM Celll

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CMOS SRAM Cell:
A low power SRAM cell may be designed by using cross-coupled CMOS inverters.
The most important advantage of this circuit topology is that the static power
dissipation is very small; essentially, it is limited by small leakage current. Other
advantages of this design are high noise immunity due to larger noise margins,
and the ability to operate at lower power supply voltage. The major disadvantage
of this topology is larger cell size. The circuit structure of the full CMOS static RAM
cell is shown in Figure 2. The memory cell consists of simple CMOS inverters
connected back to back, and two access transistors. The access transistors are
turned on whenever a word line is activated for read or write operation,
connecting the cell to the complementary bit line columns.

Fig 2: Full CMOS SRAM cell

CMOS SRAM Cell Design :

To determine W/L ratios of the transistors, a number of design criteria must be
taken into consideration. The two basic requirements, which dictate W/L ratios,
are that the data read operation should not destroy the stored information in the
cell. The cell should allow stored information modification during write operation.

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 Figure3. CMOS SRAM cell with precharge transistors

READ Operation:
Consider a data read operation, shown in Figure 4, assuming that
logic '0' is stored in the cell. The transistors M2 and M5 are turned
off, while the transistors M1 and M6 operate in linear mode. Thus
internal node voltages are V1 = 0 and V2 = VDD before the cell access
transistors are turned on. The active transistors at the beginning of
data read operation are shown in Figure 4.

Figure 4.Read Operation

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After the pass transistors M3 and M4 are turned on by the row selection circuitry,
the voltage CBb of will not change any significant variation since no current flows
through M4. On the other hand M1 and M3 will conduct a nonzero current and the
voltage level of CB will begin to drop slightly. The node voltage V1 will increase from
its initial value of '0'V. The node voltage V1 may exceed the threshold voltage of M2
during this process, forcing an unintended change of the stored state. Therefore
voltage must not exceed the threshold voltage of M2, so the transistor M2 remains
turned off during read phase

WRITE Operation:
Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell
initially. Figure 5. shows the voltage levels in the CMOS SRAM cell at the beginning
of the data write operation. The transistors M1 and M6 are turned off, while M2 and
M5 are operating in the linear mode. Thus the internal node voltage V1 = VDD and
V2 = 0 before the access transistors are turned on. The column voltage Vb is forced
to '0' by the write circuitry. Once M3 and M4 are turned on, we expect the nodal
voltage V2 to remain below the threshold voltage of M1, since M2 and M4 are
designed .

Figure 5 SRAM start of write '0'

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Comparison of various types of SRAM Cell based on the features

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 7. ASSESSMENT SCHEDULE

ASSESSMENT PROPOSED DATE ACTUAL DATE

Unit 1 Assignment
Assessment
Unit Test 1

Unit 2 Assignment
Assessment
Internal Assessment 1 27.02.2023
Retest for IA 1

Unit 3 Assignment
Assessment
Unit Test 2

Unit 4 Assignment
Assessment
Internal Assessment 2 18.04.2023
Retest for IA 2

Unit 5 Assignment
Assessment
Revision Test 1

Revision Test 2

Model Exam 11.05.2023

Remodel Exam

University Exam

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71
 8.Prescribed Text Books & Reference Books

TEXT BOOKS:
1. Neil H.E. Weste, David Money Harris ―CMOS VLSI Design: A
Circuits and Systems Perspectiveǁ, 4th Edition, Pearson , 2017
(UNIT I,II,V)
2. Jan M. Rabaey ,Anantha Chandrakasan, Borivoje. Nikolic, ǁDigital
Integrated Circuits:A Design perspectiveǁ, Second Edition , Pearson ,
2016.(UNIT III,IV)

REFERENCES :
1. M.J. Smith, ―Application Specific Integrated Circuitsǁ, Addisson
Wesley, 1997
2. Sung-Mo kang, Yusuf leblebici, Chulwoo Kim ―CMOS Digital
Integrated Circuits: Analysis & Designǁ,4th edition McGraw Hill
Education,2013
3. Wayne Wolf, ―Modern VLSI Design: System On Chipǁ, Pearson
Education, 2007
4. R.Jacob Baker, Harry W.LI., David E.Boyee, ―CMOS Circuit Design,
Layout and Simulationǁ, Prentice Hall of India 2005.

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9. Mini Project suggestions

S.no Name of The Mini Project

1. Design of 6T SRAM.

2. Design of SRAM using transmission gates and compare the

performance with 6T SRAM.
3. Low power CMOS counter using clock gated flip – flop

4. Differential static ultra low-voltage CMOS flip – flop for

high speed applications
5. True Single Phase Clocking Flip – Flop Design using
Multi Threshold CMOS Technique

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 Thank
you

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