VISVESVARAYA TECHNOLOGICAL UNIVERSITY,

BELAGAVI– 590014

An Internship Seminar on
“VLSI Design”

Department of Electronics & Communication Engineering

S.D.M Institute of Technology, Ujire. 

Presented by Internship Guide

Saikiran B Mr.Prajwal Shetty
4SU18EC062 Director of Evo-Trix technologies
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 CONTENTS
Company Profile
Objective
Work completed and learning
VLSI Design Flow
CMOS Inverter
Fingers and Multiplier
CMOS Schematic and Symbol
DC Analysis and Test bench for Transient Analysis
Transient Analysis and Output Response
Inverter Layout Creation
Schematic, Test bench, Output waveform, Layout of assigned project
Conclusion
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 Company Profile

 EVO-TRIX TECHNOLOGIES PRIVATE LIMITED is a Quantum

computing and training company founded on 7 July 2021

 Conducts training programs in the domains of VLSI, Machine learning

Its goal is to be a leader in quantum computing solutions

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 Overall Objective
•To learn and implement circuit design, icon and test bench for inverter,
NAND , NOR ,Latch and Flip-Flops like JK, T, D in 45nm technology
•Verifying the workings of the same using simulations in applications like
Symica, Electric VLSI and LT spice
•Basic commands in LINUX and performing operation on CDL net list using
python programming language
Specific Objective
•Layout design for inverter and OR gate in 300nm technology and verifying
it through simulation using spice code and carrying out DRC and LVS
verifications 4
 Work Completed

Week Duration Work carried out

Week 1 01/09/2021 – 07/09/2021 1. Introduction to Symica tool
2. CMOS inverter schematic and simulation
3. CMOS NAND gate schematic and simulation
Week 2 08/09/2021 – 14/09/2021 1. CMOS NOR gate schematic and simulation
2. Using fingers and multipliers to change output
parameters
Week 3 15/09/2021 – 21/09/2021 1. 3 Input and 4 Input NAND gate implementation
2. Flip-Flop schematic and simulation
3. 4:1 MUX schematic and simulation
Week 4 22/09/2021 – 28/09/2021 1. Working on LINUX environment
2. Inverter layout, DRC and LVS error check

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 Learning from week 1 and week 2
• VLSI design flow and operation regions of MOSFET.
• Introduction to Symica tool and implementation of CMOS Inverter
using the same
• DC and transient analysis of CMOS inverter
• CMOS NAND and NOR gate schematic and simulation using Symica
tool
• About active and passive electronic components
• Use of fingers and multipliers in changing the output to get specified
result
• CMOS fabrication technology
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 Learning from week 3 and week 4

• 3 Input and 4 Input NAND gate schematic and simulation using tool
• Design of latches and flip-flops using the NAND gates
• Flip-flops schematic implementation and simulation using tool
• 4:1 MUX schematic and simulation
• Basics of drawing stick diagram and layout rules to be followed during
layout design
• Introduction to LINUX operating system, LT spice and Electric VLSI tools
• Inverter layout implementation and DRC, LVS verification

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 VLSI Design Flow
SYSTEM SPECIFICATION

ARCHITECTURAL DESIGN

FUNCTIONAL DESIGN PACKAGING AND TESTING

LOGIC DESIGN FABRICATION

CIRCUIT DESIGN PHYSICAL DESIGN

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 CMOS Inverter

CMOS is a combination of PMOS and NMOS

The output of CMOS will be inversion of input

Supply voltage Vdd is connected at source

 
of PMOS,

GND is connected at source of NMOS

Vin is connected at gate terminals

Output is taken at drain terminal

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 Fingers
• Every metal has sheet resistance and depending upon value of sheet
resistance , voltage drop occurs.
• We are reducing Gate resistance area , this concept is called Fingers
Concept.
• In here we are dividing the width of transistor. As shown in below
figure:

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 Multipliers

• Multipliers plays an important role in many computation systems.

Multipliers in VLSI require more hardware resources and more
processing time and are used in digital processing systems.
• Below figure shows a demonstration of how multipliers work

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 CMOS Schematic and Symbol

CMOS Inverter Schematic CMOS Inverter Symbol

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 DC Analysis and Test bench for Transient Analysis

DC Analysis
To plot the transfer characteristics and to calculate the operating point (Q-
point) of a circuit DC analysis is used.

DC Analysis of CMOS Inverter Waveform of DC Analysis of CMOS 13

Transient Analysis
In the circuit simulation, during transient analysis circuit’s response as a function of
time is computed. To calculate rise time, fall time, propagation delay from low to
high and high to low signal transient analysis is used.

Transient Analysis of CMOS Inverter Output Waveform of CMOS Inverter14

 Transient Analysis and Output Response

In Circuit simulation , during Transient analysis circuit' s response as a function of time is

computed. To calculate rise time, fall time, propagation delay from low to high and high to low
signal transient analysis is used.
• Rise time
The time required for a pulse to rise from 10 per cent to 90 per cent of its steady value
• Fall time
The time required for a pulse to fall from 90 per cent to 10 per cent of its steady value
• Rise delay
Time difference between input transition(50%) and 50% of the output level during the
transition from low to high
• Fall delay
Time difference between input transition(50%) and 50% of the output level during the
transition from high to low

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 Inverter Layout Creation

Schematic of CMOS inverter Layout of CMOS inverter

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 Assigned Project : OR gate

Schematic of OR gate Test bench of OR gate 17

 Assigned Project: OR gate

Spice code
vdd vdd 0 DC 5
va a 0 pulse 5 0 0 1n 1n 4u 8u
vb b 0 pulse 5 0 0 1n 1n 2u 4u
Output waveform of OR gate .tran 30u
.include/home/codebind/Desktop/electric/models.txt
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Assigned Project: OR gate

Layout of OR gate
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 Conclusion
• In this internship I learnt about Circuit design. Creation of icon, test bench of
CMOS inverter, NAND and NOR gate using 45nm technology and verified the
results through simulation
• The simulation were carried out using SYMICA tool which is used to plot
schematic
• I also learnt basic commands and working on LINUX environment where we went
on to create layout using 300nm technology with the help of tools: LT spice and
Electric VLSI .I learnt how DRC and LVS verification is done

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Thank You

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